1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <linux/list.h> 13 #include <linux/ioport.h> 14 #include <asm/io.h> 15 #include <asm/hardware.h> 16 #include <dm/device.h> 17 #include <dm/read.h> 18 #include <dm/ofnode.h> 19 #include <syscon.h> 20 #include <asm/arch-rockchip/clock.h> 21 #include <asm/gpio.h> 22 23 #include "rockchip_display.h" 24 #include "rockchip_crtc.h" 25 #include "rockchip_connector.h" 26 #include "rockchip_lvds.h" 27 28 enum rockchip_lvds_sub_devtype { 29 PX30_LVDS, 30 RK3126_LVDS, 31 RK3288_LVDS, 32 RK3368_LVDS, 33 }; 34 35 struct rockchip_lvds_chip_data { 36 u32 chip_type; 37 bool has_vop_sel; 38 u32 grf_soc_con5; 39 u32 grf_soc_con6; 40 u32 grf_soc_con7; 41 u32 grf_soc_con15; 42 u32 grf_gpio1d_iomux; 43 }; 44 45 struct rockchip_lvds_device { 46 void *regbase; 47 void *grf; 48 void *ctrl_reg; 49 u32 channel; 50 u32 output; 51 u32 format; 52 struct drm_display_mode *mode; 53 const struct rockchip_lvds_chip_data *pdata; 54 }; 55 56 static inline int lvds_name_to_format(const char *s) 57 { 58 if (!s) 59 return -EINVAL; 60 61 if (strncmp(s, "jeida", 6) == 0) 62 return LVDS_FORMAT_JEIDA; 63 else if (strncmp(s, "vesa", 5) == 0) 64 return LVDS_FORMAT_VESA; 65 66 return -EINVAL; 67 } 68 69 static inline int lvds_name_to_output(const char *s) 70 { 71 if (!s) 72 return -EINVAL; 73 74 if (strncmp(s, "rgb", 3) == 0) 75 return DISPLAY_OUTPUT_RGB; 76 else if (strncmp(s, "lvds", 4) == 0) 77 return DISPLAY_OUTPUT_LVDS; 78 else if (strncmp(s, "duallvds", 8) == 0) 79 return DISPLAY_OUTPUT_DUAL_LVDS; 80 81 return -EINVAL; 82 } 83 84 static inline void lvds_writel(struct rockchip_lvds_device *lvds, 85 u32 offset, u32 val) 86 { 87 writel(val, lvds->regbase + offset); 88 89 if ((lvds->pdata->chip_type == RK3288_LVDS) && 90 (lvds->output == DISPLAY_OUTPUT_DUAL_LVDS)) 91 writel(val, lvds->regbase + offset + 0x100); 92 } 93 94 static inline void lvds_msk_reg(struct rockchip_lvds_device *lvds, u32 offset, 95 u32 msk, u32 val) 96 { 97 u32 temp; 98 99 temp = readl(lvds->regbase + offset) & (0xFF - (msk)); 100 writel(temp | ((val) & (msk)), lvds->regbase + offset); 101 } 102 103 static inline u32 lvds_readl(struct rockchip_lvds_device *lvds, u32 offset) 104 { 105 return readl(lvds->regbase + offset); 106 } 107 108 static inline void lvds_ctrl_writel(struct rockchip_lvds_device *lvds, 109 u32 offset, u32 val) 110 { 111 writel(val, lvds->ctrl_reg + offset); 112 } 113 114 static inline u32 lvds_pmugrf_readl(u32 offset) 115 { 116 return readl((void *)LVDS_PMUGRF_BASE + offset); 117 } 118 119 static inline void lvds_pmugrf_writel(u32 offset, u32 val) 120 { 121 writel(val, (void *)LVDS_PMUGRF_BASE + offset); 122 } 123 124 static inline u32 lvds_phy_lock(struct rockchip_lvds_device *lvds) 125 { 126 u32 val = 0; 127 val = readl(lvds->ctrl_reg + MIPIC_PHY_STATUS); 128 return (val & m_PHY_LOCK_STATUS) ? 1 : 0; 129 } 130 131 static int rockchip_lvds_clk_enable(struct rockchip_lvds_device *lvds) 132 { 133 return 0; 134 } 135 136 static int rk336x_lvds_pwr_off(struct display_state *state) 137 { 138 struct connector_state *conn_state = &state->conn_state; 139 struct rockchip_lvds_device *lvds = conn_state->private; 140 141 /* disable lvds lane and power off pll */ 142 lvds_writel(lvds, MIPIPHY_REGEB, 143 v_LANE0_EN(0) | v_LANE1_EN(0) | v_LANE2_EN(0) | 144 v_LANE3_EN(0) | v_LANECLK_EN(0) | v_PLL_PWR_OFF(1)); 145 146 /* power down lvds pll and bandgap */ 147 lvds_msk_reg(lvds, MIPIPHY_REG1, 148 m_SYNC_RST | m_LDO_PWR_DOWN | m_PLL_PWR_DOWN, 149 v_SYNC_RST(1) | v_LDO_PWR_DOWN(1) | v_PLL_PWR_DOWN(1)); 150 151 /* disable lvds */ 152 lvds_msk_reg(lvds, MIPIPHY_REGE3, m_LVDS_EN | m_TTL_EN, 153 v_LVDS_EN(0) | v_TTL_EN(0)); 154 155 return 0; 156 } 157 158 static int rk3288_lvds_pwr_off(struct display_state *state) 159 { 160 struct connector_state *conn_state = &state->conn_state; 161 struct rockchip_lvds_device *lvds = conn_state->private; 162 163 lvds_writel(lvds, RK3288_LVDS_CFG_REG21, RK3288_LVDS_CFG_REG21_TX_DISABLE); 164 lvds_writel(lvds, RK3288_LVDS_CFG_REGC, RK3288_LVDS_CFG_REGC_PLL_DISABLE); 165 166 writel(0xffff8000, lvds->grf + lvds->pdata->grf_soc_con7); 167 168 return 0; 169 } 170 171 static int rk336x_lvds_pwr_on(struct display_state *state) 172 { 173 struct connector_state *conn_state = &state->conn_state; 174 struct rockchip_lvds_device *lvds = conn_state->private; 175 u32 delay_times = 20; 176 177 if (lvds->output == DISPLAY_OUTPUT_LVDS) { 178 /* set VOCM 900 mv and V-DIFF 350 mv */ 179 lvds_msk_reg(lvds, MIPIPHY_REGE4, m_VOCM | m_DIFF_V, 180 v_VOCM(0) | v_DIFF_V(2)); 181 /* power up lvds pll and ldo */ 182 lvds_msk_reg(lvds, MIPIPHY_REG1, 183 m_SYNC_RST | m_LDO_PWR_DOWN | m_PLL_PWR_DOWN, 184 v_SYNC_RST(0) | v_LDO_PWR_DOWN(0) | 185 v_PLL_PWR_DOWN(0)); 186 /* enable lvds lane and power on pll */ 187 lvds_writel(lvds, MIPIPHY_REGEB, 188 v_LANE0_EN(1) | v_LANE1_EN(1) | v_LANE2_EN(1) | 189 v_LANE3_EN(1) | v_LANECLK_EN(1) | v_PLL_PWR_OFF(0)); 190 191 /* enable lvds */ 192 lvds_msk_reg(lvds, MIPIPHY_REGE3, 193 m_MIPI_EN | m_LVDS_EN | m_TTL_EN, 194 v_MIPI_EN(0) | v_LVDS_EN(1) | v_TTL_EN(0)); 195 } else { 196 lvds_msk_reg(lvds, MIPIPHY_REGE3, 197 m_MIPI_EN | m_LVDS_EN | m_TTL_EN, 198 v_MIPI_EN(0) | v_LVDS_EN(0) | v_TTL_EN(1)); 199 } 200 /* delay for waitting pll lock on */ 201 while (delay_times--) { 202 if (lvds_phy_lock(lvds)) 203 break; 204 udelay(100); 205 } 206 207 if (delay_times <= 0) 208 printf("wait lvds phy lock failed, please check the hardware!\n"); 209 210 return 0; 211 } 212 213 static void px30_output_ttl(struct display_state *state) 214 { 215 struct connector_state *conn_state = &state->conn_state; 216 struct rockchip_lvds_device *lvds = conn_state->private; 217 u32 val = 0; 218 219 /* enable lvds mode */ 220 val = PX30_LVDS_PHY_MODE(0) | PX30_DPHY_FORCERXMODE(1); 221 writel(val, lvds->grf + PX30_GRF_PD_VO_CON1); 222 223 /* enable lane */ 224 lvds_writel(lvds, MIPIPHY_REG0, 0x7f); 225 val = v_LANE0_EN(1) | v_LANE1_EN(1) | v_LANE2_EN(1) | v_LANE3_EN(1) | 226 v_LANECLK_EN(1) | v_PLL_PWR_OFF(1); 227 lvds_writel(lvds, MIPIPHY_REGEB, val); 228 /* set ttl mode and reset phy config */ 229 val = v_LVDS_MODE_EN(0) | v_TTL_MODE_EN(1) | v_MIPI_MODE_EN(0) | 230 v_MSB_SEL(1) | v_DIG_INTER_RST(1); 231 lvds_writel(lvds, MIPIPHY_REGE0, val); 232 rk336x_lvds_pwr_on(state); 233 } 234 235 static void rk3126_output_ttl(struct display_state *state) 236 { 237 struct connector_state *conn_state = &state->conn_state; 238 struct rockchip_lvds_device *lvds = conn_state->private; 239 u32 val = 0; 240 241 /* enable lvds mode */ 242 val = v_RK3126_LVDSMODE_EN(0) | 243 v_RK3126_MIPIPHY_TTL_EN(1) | 244 v_RK3126_MIPIPHY_LANE0_EN(1) | 245 v_RK3126_MIPIDPI_FORCEX_EN(1); 246 writel(val, lvds->grf + lvds->pdata->grf_soc_con7); 247 val = v_RK3126_MIPITTL_CLK_EN(1) | 248 v_RK3126_MIPITTL_LANE0_EN(1) | 249 v_RK3126_MIPITTL_LANE1_EN(1) | 250 v_RK3126_MIPITTL_LANE2_EN(1) | 251 v_RK3126_MIPITTL_LANE3_EN(1); 252 writel(val, lvds->grf + lvds->pdata->grf_soc_con15); 253 /* enable lane */ 254 lvds_writel(lvds, MIPIPHY_REG0, 0x7f); 255 val = v_LANE0_EN(1) | v_LANE1_EN(1) | v_LANE2_EN(1) | v_LANE3_EN(1) | 256 v_LANECLK_EN(1) | v_PLL_PWR_OFF(1); 257 lvds_writel(lvds, MIPIPHY_REGEB, val); 258 /* set ttl mode and reset phy config */ 259 val = v_LVDS_MODE_EN(0) | v_TTL_MODE_EN(1) | v_MIPI_MODE_EN(0) | 260 v_MSB_SEL(1) | v_DIG_INTER_RST(1); 261 lvds_writel(lvds, MIPIPHY_REGE0, val); 262 rk336x_lvds_pwr_on(state); 263 } 264 265 static void rk336x_output_ttl(struct display_state *state) 266 { 267 struct connector_state *conn_state = &state->conn_state; 268 struct rockchip_lvds_device *lvds = conn_state->private; 269 u32 val = 0; 270 271 /* enable lvds mode */ 272 val = v_RK336X_LVDSMODE_EN(0) | v_RK336X_MIPIPHY_TTL_EN(1) | 273 v_RK336X_MIPIPHY_LANE0_EN(1) | 274 v_RK336X_MIPIDPI_FORCEX_EN(1); 275 writel(val, lvds->grf + lvds->pdata->grf_soc_con7); 276 val = v_RK336X_FORCE_JETAG(0); 277 writel(val, lvds->grf + lvds->pdata->grf_soc_con15); 278 279 /* enable lane */ 280 lvds_writel(lvds, MIPIPHY_REG0, 0x7f); 281 val = v_LANE0_EN(1) | v_LANE1_EN(1) | v_LANE2_EN(1) | v_LANE3_EN(1) | 282 v_LANECLK_EN(1) | v_PLL_PWR_OFF(1); 283 lvds_writel(lvds, MIPIPHY_REGEB, val); 284 285 /* set ttl mode and reset phy config */ 286 val = v_LVDS_MODE_EN(0) | v_TTL_MODE_EN(1) | v_MIPI_MODE_EN(0) | 287 v_MSB_SEL(1) | v_DIG_INTER_RST(1); 288 lvds_writel(lvds, MIPIPHY_REGE0, val); 289 290 rk336x_lvds_pwr_on(state); 291 } 292 293 static void px30_output_lvds(struct display_state *state) 294 { 295 struct connector_state *conn_state = &state->conn_state; 296 struct rockchip_lvds_device *lvds = conn_state->private; 297 u32 val = 0; 298 299 /* enable lvds mode */ 300 val = PX30_LVDS_PHY_MODE(1) | PX30_DPHY_FORCERXMODE(1); 301 /* config lvds_format */ 302 val |= PX30_LVDS_OUTPUT_FORMAT(lvds->format); 303 /* LSB receive mode */ 304 val |= PX30_LVDS_MSBSEL(LVDS_MSB_D7); 305 writel(val, lvds->grf + PX30_GRF_PD_VO_CON1); 306 307 /* digital internal disable */ 308 lvds_msk_reg(lvds, MIPIPHY_REGE1, m_DIG_INTER_EN, v_DIG_INTER_EN(0)); 309 310 /* set pll prediv and fbdiv */ 311 lvds_writel(lvds, MIPIPHY_REG3, v_PREDIV(2) | v_FBDIV_MSB(0)); 312 lvds_writel(lvds, MIPIPHY_REG4, v_FBDIV_LSB(28)); 313 314 lvds_writel(lvds, MIPIPHY_REGE8, 0xfc); 315 316 /* set lvds mode and reset phy config */ 317 lvds_msk_reg(lvds, MIPIPHY_REGE0, 318 m_MSB_SEL | m_DIG_INTER_RST, 319 v_MSB_SEL(1) | v_DIG_INTER_RST(1)); 320 321 rk336x_lvds_pwr_on(state); 322 lvds_msk_reg(lvds, MIPIPHY_REGE1, m_DIG_INTER_EN, v_DIG_INTER_EN(1)); 323 } 324 325 static void rk3126_output_lvds(struct display_state *state) 326 { 327 struct connector_state *conn_state = &state->conn_state; 328 struct rockchip_lvds_device *lvds = conn_state->private; 329 u32 val = 0; 330 331 /* enable lvds mode */ 332 val = v_RK3126_LVDSMODE_EN(1) | 333 v_RK3126_MIPIPHY_TTL_EN(0); 334 /* config lvds_format */ 335 val |= v_RK3126_LVDS_OUTPUT_FORMAT(lvds->format); 336 /* LSB receive mode */ 337 val |= v_RK3126_LVDS_MSBSEL(LVDS_MSB_D7); 338 val |= v_RK3126_MIPIPHY_LANE0_EN(1) | 339 v_RK3126_MIPIDPI_FORCEX_EN(1); 340 writel(val, lvds->grf + lvds->pdata->grf_soc_con7); 341 342 /* digital internal disable */ 343 lvds_msk_reg(lvds, MIPIPHY_REGE1, m_DIG_INTER_EN, v_DIG_INTER_EN(0)); 344 345 /* set pll prediv and fbdiv */ 346 lvds_writel(lvds, MIPIPHY_REG3, v_PREDIV(2) | v_FBDIV_MSB(0)); 347 lvds_writel(lvds, MIPIPHY_REG4, v_FBDIV_LSB(28)); 348 349 lvds_writel(lvds, MIPIPHY_REGE8, 0xfc); 350 351 /* set lvds mode and reset phy config */ 352 lvds_msk_reg(lvds, MIPIPHY_REGE0, 353 m_MSB_SEL | m_DIG_INTER_RST, 354 v_MSB_SEL(1) | v_DIG_INTER_RST(1)); 355 356 rk336x_lvds_pwr_on(state); 357 lvds_msk_reg(lvds, MIPIPHY_REGE1, m_DIG_INTER_EN, v_DIG_INTER_EN(1)); 358 } 359 360 static void rk336x_output_lvds(struct display_state *state) 361 { 362 struct connector_state *conn_state = &state->conn_state; 363 struct rockchip_lvds_device *lvds = conn_state->private; 364 u32 val = 0; 365 366 /* enable lvds mode */ 367 val |= v_RK336X_LVDSMODE_EN(1) | v_RK336X_MIPIPHY_TTL_EN(0); 368 /* config lvds_format */ 369 val |= v_RK336X_LVDS_OUTPUT_FORMAT(lvds->format); 370 /* LSB receive mode */ 371 val |= v_RK336X_LVDS_MSBSEL(LVDS_MSB_D7); 372 val |= v_RK336X_MIPIPHY_LANE0_EN(1) | 373 v_RK336X_MIPIDPI_FORCEX_EN(1); 374 writel(val, lvds->grf + lvds->pdata->grf_soc_con7); 375 /* digital internal disable */ 376 lvds_msk_reg(lvds, MIPIPHY_REGE1, m_DIG_INTER_EN, v_DIG_INTER_EN(0)); 377 378 /* set pll prediv and fbdiv */ 379 lvds_writel(lvds, MIPIPHY_REG3, v_PREDIV(2) | v_FBDIV_MSB(0)); 380 lvds_writel(lvds, MIPIPHY_REG4, v_FBDIV_LSB(28)); 381 382 lvds_writel(lvds, MIPIPHY_REGE8, 0xfc); 383 384 /* set lvds mode and reset phy config */ 385 lvds_msk_reg(lvds, MIPIPHY_REGE0, 386 m_MSB_SEL | m_DIG_INTER_RST, 387 v_MSB_SEL(1) | v_DIG_INTER_RST(1)); 388 389 rk336x_lvds_pwr_on(state); 390 lvds_msk_reg(lvds, MIPIPHY_REGE1, m_DIG_INTER_EN, v_DIG_INTER_EN(1)); 391 } 392 393 static int rk3288_lvds_pwr_on(struct display_state *state) 394 { 395 struct connector_state *conn_state = &state->conn_state; 396 struct rockchip_lvds_device *lvds = conn_state->private; 397 struct drm_display_mode *mode = &conn_state->mode; 398 u32 val; 399 u32 h_bp = mode->htotal - mode->hsync_start; 400 u8 pin_hsync = (mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1 : 0; 401 u8 pin_dclk = (mode->flags & DRM_MODE_FLAG_PCSYNC) ? 1 : 0; 402 403 val = lvds->format; 404 if (lvds->output == DISPLAY_OUTPUT_DUAL_LVDS) 405 val |= LVDS_DUAL | LVDS_CH0_EN | LVDS_CH1_EN; 406 else if (lvds->output == DISPLAY_OUTPUT_LVDS) 407 val |= LVDS_CH0_EN; 408 else if (lvds->output == DISPLAY_OUTPUT_RGB) 409 val |= LVDS_TTL_EN | LVDS_CH0_EN | LVDS_CH1_EN; 410 411 if (h_bp & 0x01) 412 val |= LVDS_START_PHASE_RST_1; 413 414 val |= (pin_dclk << 8) | (pin_hsync << 9); 415 val |= (0xffff << 16); 416 writel(val, lvds->grf + lvds->pdata->grf_soc_con7); 417 418 return 0; 419 } 420 421 static void rk3288_output_ttl(struct display_state *state) 422 { 423 struct connector_state *conn_state = &state->conn_state; 424 struct rockchip_lvds_device *lvds = conn_state->private; 425 426 rk3288_lvds_pwr_on(state); 427 lvds_writel(lvds, RK3288_LVDS_CH0_REG0, 428 RK3288_LVDS_CH0_REG0_TTL_EN | 429 RK3288_LVDS_CH0_REG0_LANECK_EN | 430 RK3288_LVDS_CH0_REG0_LANE4_EN | 431 RK3288_LVDS_CH0_REG0_LANE3_EN | 432 RK3288_LVDS_CH0_REG0_LANE2_EN | 433 RK3288_LVDS_CH0_REG0_LANE1_EN | 434 RK3288_LVDS_CH0_REG0_LANE0_EN); 435 lvds_writel(lvds, RK3288_LVDS_CH0_REG2, 436 RK3288_LVDS_PLL_FBDIV_REG2(0x46)); 437 438 lvds_writel(lvds, RK3288_LVDS_CH0_REG3, 439 RK3288_LVDS_PLL_FBDIV_REG3(0x46)); 440 lvds_writel(lvds, RK3288_LVDS_CH0_REG4, 441 RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE | 442 RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE | 443 RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE | 444 RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE | 445 RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE | 446 RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE); 447 lvds_writel(lvds, RK3288_LVDS_CH0_REG5, 448 RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA | 449 RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA | 450 RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA | 451 RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA | 452 RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA | 453 RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA); 454 lvds_writel(lvds, RK3288_LVDS_CH0_REGD, 455 RK3288_LVDS_PLL_PREDIV_REGD(0x0a)); 456 lvds_writel(lvds, RK3288_LVDS_CH0_REG20, 457 RK3288_LVDS_CH0_REG20_LSB); 458 459 lvds_writel(lvds, RK3288_LVDS_CFG_REGC, RK3288_LVDS_CFG_REGC_PLL_ENABLE); 460 lvds_writel(lvds, RK3288_LVDS_CFG_REG21, RK3288_LVDS_CFG_REG21_TX_ENABLE); 461 } 462 463 static void rk3288_output_lvds(struct display_state *state) 464 { 465 struct connector_state *conn_state = &state->conn_state; 466 struct rockchip_lvds_device *lvds = conn_state->private; 467 468 rk3288_lvds_pwr_on(state); 469 470 lvds_writel(lvds, RK3288_LVDS_CH0_REG0, 471 RK3288_LVDS_CH0_REG0_LVDS_EN | 472 RK3288_LVDS_CH0_REG0_LANECK_EN | 473 RK3288_LVDS_CH0_REG0_LANE4_EN | 474 RK3288_LVDS_CH0_REG0_LANE3_EN | 475 RK3288_LVDS_CH0_REG0_LANE2_EN | 476 RK3288_LVDS_CH0_REG0_LANE1_EN | 477 RK3288_LVDS_CH0_REG0_LANE0_EN); 478 lvds_writel(lvds, RK3288_LVDS_CH0_REG1, 479 RK3288_LVDS_CH0_REG1_LANECK_BIAS | 480 RK3288_LVDS_CH0_REG1_LANE4_BIAS | 481 RK3288_LVDS_CH0_REG1_LANE3_BIAS | 482 RK3288_LVDS_CH0_REG1_LANE2_BIAS | 483 RK3288_LVDS_CH0_REG1_LANE1_BIAS | 484 RK3288_LVDS_CH0_REG1_LANE0_BIAS); 485 lvds_writel(lvds, RK3288_LVDS_CH0_REG2, 486 RK3288_LVDS_CH0_REG2_RESERVE_ON | 487 RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE | 488 RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE | 489 RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE | 490 RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE | 491 RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE | 492 RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE | 493 RK3288_LVDS_PLL_FBDIV_REG2(0x46)); 494 lvds_writel(lvds, RK3288_LVDS_CH0_REG3, 495 RK3288_LVDS_PLL_FBDIV_REG3(0x46)); 496 lvds_writel(lvds, RK3288_LVDS_CH0_REG4, 0x00); 497 lvds_writel(lvds, RK3288_LVDS_CH0_REG5, 0x00); 498 lvds_writel(lvds, RK3288_LVDS_CH0_REGD, 499 RK3288_LVDS_PLL_PREDIV_REGD(0x0a)); 500 lvds_writel(lvds, RK3288_LVDS_CH0_REG20, 501 RK3288_LVDS_CH0_REG20_LSB); 502 503 lvds_writel(lvds, RK3288_LVDS_CFG_REGC, RK3288_LVDS_CFG_REGC_PLL_ENABLE); 504 lvds_writel(lvds, RK3288_LVDS_CFG_REG21, RK3288_LVDS_CFG_REG21_TX_ENABLE); 505 } 506 507 static int rockchip_lvds_init(struct display_state *state) 508 { 509 struct connector_state *conn_state = &state->conn_state; 510 const struct rockchip_connector *connector = conn_state->connector; 511 const struct rockchip_lvds_chip_data *pdata = connector->data; 512 struct rockchip_lvds_device *lvds; 513 const char *name; 514 int i, width; 515 struct resource lvds_phy, lvds_ctrl; 516 struct panel_state *panel_state = &state->panel_state; 517 ofnode panel_node = panel_state->node; 518 int ret; 519 520 lvds = malloc(sizeof(*lvds)); 521 if (!lvds) 522 return -ENOMEM; 523 lvds->pdata = pdata; 524 525 if (pdata->chip_type == RK3288_LVDS) { 526 lvds->regbase = dev_read_addr_ptr(conn_state->dev); 527 } else { 528 i = dev_read_resource(conn_state->dev, 0, &lvds_phy); 529 if (i) { 530 printf("can't get regs lvds_phy addresses!\n"); 531 free(lvds); 532 return -ENOMEM; 533 } 534 535 i = dev_read_resource(conn_state->dev, 1, &lvds_ctrl); 536 if (i) { 537 printf("can't get regs lvds_ctrl addresses!\n"); 538 free(lvds); 539 return -ENOMEM; 540 } 541 542 lvds->regbase = (void *)lvds_phy.start; 543 lvds->ctrl_reg = (void *)lvds_ctrl.start; 544 } 545 546 lvds->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 547 if (lvds->grf <= 0) { 548 printf("%s: Get syscon grf failed (ret=%p)\n", 549 __func__, lvds->grf); 550 return -ENXIO; 551 } 552 553 ret = dev_read_string_index(panel_state->dev, "rockchip,output", 0, &name); 554 if (ret) 555 /* default set it as output rgb */ 556 lvds->output = DISPLAY_OUTPUT_RGB; 557 else 558 lvds->output = lvds_name_to_output(name); 559 if (lvds->output < 0) { 560 printf("invalid output type [%s]\n", name); 561 free(lvds); 562 return lvds->output; 563 } 564 ret = dev_read_string_index(panel_state->dev, "rockchip,data-mapping", 0, &name); 565 if (ret) 566 /* default set it as format jeida */ 567 lvds->format = LVDS_FORMAT_JEIDA; 568 else 569 lvds->format = lvds_name_to_format(name); 570 571 if (lvds->format < 0) { 572 printf("invalid data-mapping format [%s]\n", name); 573 free(lvds); 574 return lvds->format; 575 } 576 width = ofnode_read_u32_default(panel_node, "rockchip,data-width", 24); 577 if (width == 24) { 578 lvds->format |= LVDS_24BIT; 579 } else if (width == 18) { 580 lvds->format |= LVDS_18BIT; 581 } else { 582 printf("rockchip-lvds unsupport data-width[%d]\n", width); 583 free(lvds); 584 return -EINVAL; 585 } 586 587 printf("LVDS: data mapping: %s, data-width:%d, format:%d,\n", 588 name, width, lvds->format); 589 conn_state->private = lvds; 590 conn_state->type = DRM_MODE_CONNECTOR_LVDS; 591 592 if ((lvds->output == DISPLAY_OUTPUT_RGB) && (width == 18)) 593 conn_state->output_mode = ROCKCHIP_OUT_MODE_P666; 594 else 595 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 596 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 597 598 return 0; 599 } 600 601 static void rockchip_lvds_deinit(struct display_state *state) 602 { 603 struct connector_state *conn_state = &state->conn_state; 604 struct rockchip_lvds_device *lvds = conn_state->private; 605 606 free(lvds); 607 } 608 609 static int rockchip_lvds_prepare(struct display_state *state) 610 { 611 struct connector_state *conn_state = &state->conn_state; 612 struct rockchip_lvds_device *lvds = conn_state->private; 613 lvds->mode = &conn_state->mode; 614 615 rockchip_lvds_clk_enable(lvds); 616 617 return 0; 618 } 619 620 static void rockchip_lvds_vop_routing(struct rockchip_lvds_device *lvds, int pipe) 621 { 622 u32 val; 623 624 if (lvds->pdata->chip_type == RK3288_LVDS) { 625 if (pipe) 626 val = RK3288_LVDS_SOC_CON6_SEL_VOP_LIT | 627 (RK3288_LVDS_SOC_CON6_SEL_VOP_LIT << 16); 628 else 629 val = RK3288_LVDS_SOC_CON6_SEL_VOP_LIT << 16; 630 writel(val, lvds->grf + lvds->pdata->grf_soc_con6); 631 } else if (lvds->pdata->chip_type == PX30_LVDS) { 632 if (lvds->output == DISPLAY_OUTPUT_RGB) 633 writel(PX30_RGB_VOP_SEL(pipe), 634 lvds->grf + PX30_GRF_PD_VO_CON1); 635 else if (lvds->output == DISPLAY_OUTPUT_LVDS) 636 writel(PX30_LVDS_VOP_SEL(pipe), 637 lvds->grf + PX30_GRF_PD_VO_CON1); 638 } 639 } 640 641 static int rockchip_lvds_enable(struct display_state *state) 642 { 643 struct connector_state *conn_state = &state->conn_state; 644 struct rockchip_lvds_device *lvds = conn_state->private; 645 struct crtc_state *crtc_state = &state->crtc_state; 646 647 if (lvds->pdata->has_vop_sel) 648 rockchip_lvds_vop_routing(lvds, crtc_state->crtc_id); 649 650 if ((lvds->output == DISPLAY_OUTPUT_LVDS) || 651 (lvds->output == DISPLAY_OUTPUT_DUAL_LVDS)) { 652 if (lvds->pdata->chip_type == RK3288_LVDS) 653 rk3288_output_lvds(state); 654 else if (lvds->pdata->chip_type == RK3126_LVDS) 655 rk3126_output_lvds(state); 656 else if (lvds->pdata->chip_type == PX30_LVDS) 657 px30_output_lvds(state); 658 else 659 rk336x_output_lvds(state); 660 } else { 661 if (lvds->pdata->chip_type == RK3288_LVDS) 662 rk3288_output_ttl(state); 663 else if (lvds->pdata->chip_type == RK3126_LVDS) 664 rk3126_output_ttl(state); 665 else if (lvds->pdata->chip_type == PX30_LVDS) 666 px30_output_ttl(state); 667 else 668 rk336x_output_ttl(state); 669 } 670 671 return 0; 672 } 673 674 static int rockchip_lvds_disable(struct display_state *state) 675 { 676 struct connector_state *conn_state = &state->conn_state; 677 struct rockchip_lvds_device *lvds = conn_state->private; 678 679 if (lvds->pdata->chip_type == RK3288_LVDS) 680 rk3288_lvds_pwr_off(state); 681 else 682 rk336x_lvds_pwr_off(state); 683 684 return 0; 685 } 686 687 const struct rockchip_connector_funcs rockchip_lvds_funcs = { 688 .init = rockchip_lvds_init, 689 .deinit = rockchip_lvds_deinit, 690 .prepare = rockchip_lvds_prepare, 691 .enable = rockchip_lvds_enable, 692 .disable = rockchip_lvds_disable, 693 }; 694 695 static const struct rockchip_lvds_chip_data px30_lvds_drv_data = { 696 .chip_type = PX30_LVDS, 697 .has_vop_sel = true, 698 }; 699 700 static const struct rockchip_connector px30_lvds_data = { 701 .funcs = &rockchip_lvds_funcs, 702 .data = &px30_lvds_drv_data, 703 }; 704 705 static const struct rockchip_lvds_chip_data rk3126_lvds_drv_data = { 706 .chip_type = RK3126_LVDS, 707 .grf_soc_con7 = RK3126_GRF_LVDS_CON0, 708 .grf_soc_con15 = RK3126_GRF_CON1, 709 .has_vop_sel = true, 710 }; 711 712 static const struct rockchip_connector rk3126_lvds_data = { 713 .funcs = &rockchip_lvds_funcs, 714 .data = &rk3126_lvds_drv_data, 715 }; 716 717 static const struct rockchip_lvds_chip_data rk3288_lvds_drv_data = { 718 .chip_type = RK3288_LVDS, 719 .has_vop_sel = true, 720 .grf_soc_con6 = 0x025c, 721 .grf_soc_con7 = 0x0260, 722 .grf_gpio1d_iomux = 0x000c, 723 }; 724 725 static const struct rockchip_connector rk3288_lvds_data = { 726 .funcs = &rockchip_lvds_funcs, 727 .data = &rk3288_lvds_drv_data, 728 }; 729 730 static const struct rockchip_lvds_chip_data rk3368_lvds_drv_data = { 731 .chip_type = RK3368_LVDS, 732 .grf_soc_con7 = RK3368_GRF_SOC_CON7, 733 .grf_soc_con15 = RK3368_GRF_SOC_CON15, 734 .has_vop_sel = false, 735 }; 736 737 static const struct rockchip_connector rk3368_lvds_data = { 738 .funcs = &rockchip_lvds_funcs, 739 .data = &rk3368_lvds_drv_data, 740 }; 741 742 static const struct udevice_id rockchip_lvds_ids[] = { 743 { 744 .compatible = "rockchip,px30-lvds", 745 .data = (ulong)&px30_lvds_data, 746 }, 747 { 748 .compatible = "rockchip,rk3126-lvds", 749 .data = (ulong)&rk3126_lvds_data, 750 }, 751 { 752 .compatible = "rockchip,rk3288-lvds", 753 .data = (ulong)&rk3288_lvds_data, 754 }, 755 { 756 .compatible = "rockchip,rk3368-lvds", 757 .data = (ulong)&rk3368_lvds_data, 758 }, 759 {} 760 }; 761 762 U_BOOT_DRIVER(rockchip_lvds) = { 763 .name = "rockchip_lvds", 764 .id = UCLASS_DISPLAY, 765 .of_match = rockchip_lvds_ids, 766 }; 767