1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <linux/list.h> 13 #include <linux/ioport.h> 14 #include <asm/io.h> 15 #include <asm/hardware.h> 16 #include <dm/device.h> 17 #include <dm/read.h> 18 #include <dm/ofnode.h> 19 #include <syscon.h> 20 #include <asm/arch-rockchip/clock.h> 21 #include <asm/gpio.h> 22 23 #include "rockchip_display.h" 24 #include "rockchip_crtc.h" 25 #include "rockchip_connector.h" 26 #include "rockchip_lvds.h" 27 28 enum rockchip_lvds_sub_devtype { 29 PX30_LVDS, 30 RK3126_LVDS, 31 RK3288_LVDS, 32 RK3368_LVDS, 33 }; 34 35 struct rockchip_lvds_chip_data { 36 u32 chip_type; 37 bool has_vop_sel; 38 u32 grf_soc_con5; 39 u32 grf_soc_con6; 40 u32 grf_soc_con7; 41 u32 grf_soc_con15; 42 u32 grf_gpio1d_iomux; 43 }; 44 45 struct rockchip_lvds_device { 46 void *regbase; 47 void *grf; 48 void *ctrl_reg; 49 u32 channel; 50 u32 output; 51 u32 format; 52 struct drm_display_mode *mode; 53 const struct rockchip_lvds_chip_data *pdata; 54 }; 55 56 static inline int lvds_name_to_format(const char *s) 57 { 58 if (!s) 59 return -EINVAL; 60 61 if (strncmp(s, "jeida", 6) == 0) 62 return LVDS_FORMAT_JEIDA; 63 else if (strncmp(s, "vesa", 5) == 0) 64 return LVDS_FORMAT_VESA; 65 66 return -EINVAL; 67 } 68 69 static inline int lvds_name_to_output(const char *s) 70 { 71 if (!s) 72 return -EINVAL; 73 74 if (strncmp(s, "rgb", 3) == 0) 75 return DISPLAY_OUTPUT_RGB; 76 else if (strncmp(s, "lvds", 4) == 0) 77 return DISPLAY_OUTPUT_LVDS; 78 else if (strncmp(s, "duallvds", 8) == 0) 79 return DISPLAY_OUTPUT_DUAL_LVDS; 80 81 return -EINVAL; 82 } 83 84 static inline void lvds_writel(struct rockchip_lvds_device *lvds, 85 u32 offset, u32 val) 86 { 87 writel(val, lvds->regbase + offset); 88 89 if ((lvds->pdata->chip_type == RK3288_LVDS) && 90 (lvds->output == DISPLAY_OUTPUT_DUAL_LVDS)) 91 writel(val, lvds->regbase + offset + 0x100); 92 } 93 94 static inline void lvds_msk_reg(struct rockchip_lvds_device *lvds, u32 offset, 95 u32 msk, u32 val) 96 { 97 u32 temp; 98 99 temp = readl(lvds->regbase + offset) & (0xFF - (msk)); 100 writel(temp | ((val) & (msk)), lvds->regbase + offset); 101 } 102 103 static inline u32 lvds_readl(struct rockchip_lvds_device *lvds, u32 offset) 104 { 105 return readl(lvds->regbase + offset); 106 } 107 108 static inline void lvds_ctrl_writel(struct rockchip_lvds_device *lvds, 109 u32 offset, u32 val) 110 { 111 writel(val, lvds->ctrl_reg + offset); 112 } 113 114 static inline u32 lvds_pmugrf_readl(u32 offset) 115 { 116 return readl((void *)LVDS_PMUGRF_BASE + offset); 117 } 118 119 static inline void lvds_pmugrf_writel(u32 offset, u32 val) 120 { 121 writel(val, (void *)LVDS_PMUGRF_BASE + offset); 122 } 123 124 static inline u32 lvds_phy_lock(struct rockchip_lvds_device *lvds) 125 { 126 u32 val = 0; 127 val = readl(lvds->ctrl_reg + MIPIC_PHY_STATUS); 128 return (val & m_PHY_LOCK_STATUS) ? 1 : 0; 129 } 130 131 static int rockchip_lvds_clk_enable(struct rockchip_lvds_device *lvds) 132 { 133 return 0; 134 } 135 136 static int rk336x_lvds_pwr_off(struct display_state *state) 137 { 138 struct connector_state *conn_state = &state->conn_state; 139 struct rockchip_lvds_device *lvds = conn_state->private; 140 141 /* disable lvds lane and power off pll */ 142 lvds_writel(lvds, MIPIPHY_REGEB, 143 v_LANE0_EN(0) | v_LANE1_EN(0) | v_LANE2_EN(0) | 144 v_LANE3_EN(0) | v_LANECLK_EN(0) | v_PLL_PWR_OFF(1)); 145 146 /* power down lvds pll and bandgap */ 147 lvds_msk_reg(lvds, MIPIPHY_REG1, 148 m_SYNC_RST | m_LDO_PWR_DOWN | m_PLL_PWR_DOWN, 149 v_SYNC_RST(1) | v_LDO_PWR_DOWN(1) | v_PLL_PWR_DOWN(1)); 150 151 /* disable lvds */ 152 lvds_msk_reg(lvds, MIPIPHY_REGE3, m_LVDS_EN | m_TTL_EN, 153 v_LVDS_EN(0) | v_TTL_EN(0)); 154 155 return 0; 156 } 157 158 static int rk3288_lvds_pwr_off(struct display_state *state) 159 { 160 struct connector_state *conn_state = &state->conn_state; 161 struct rockchip_lvds_device *lvds = conn_state->private; 162 163 lvds_writel(lvds, RK3288_LVDS_CFG_REG21, RK3288_LVDS_CFG_REG21_TX_DISABLE); 164 lvds_writel(lvds, RK3288_LVDS_CFG_REGC, RK3288_LVDS_CFG_REGC_PLL_DISABLE); 165 166 writel(0xffff8000, lvds->grf + lvds->pdata->grf_soc_con7); 167 168 return 0; 169 } 170 171 static int rk336x_lvds_pwr_on(struct display_state *state) 172 { 173 struct connector_state *conn_state = &state->conn_state; 174 struct rockchip_lvds_device *lvds = conn_state->private; 175 u32 delay_times = 20; 176 177 if (lvds->output == DISPLAY_OUTPUT_LVDS) { 178 /* set VOCM 900 mv and V-DIFF 350 mv */ 179 lvds_msk_reg(lvds, MIPIPHY_REGE4, m_VOCM | m_DIFF_V, 180 v_VOCM(0) | v_DIFF_V(2)); 181 /* power up lvds pll and ldo */ 182 lvds_msk_reg(lvds, MIPIPHY_REG1, 183 m_SYNC_RST | m_LDO_PWR_DOWN | m_PLL_PWR_DOWN, 184 v_SYNC_RST(0) | v_LDO_PWR_DOWN(0) | 185 v_PLL_PWR_DOWN(0)); 186 /* enable lvds lane and power on pll */ 187 lvds_writel(lvds, MIPIPHY_REGEB, 188 v_LANE0_EN(1) | v_LANE1_EN(1) | v_LANE2_EN(1) | 189 v_LANE3_EN(1) | v_LANECLK_EN(1) | v_PLL_PWR_OFF(0)); 190 191 /* enable lvds */ 192 lvds_msk_reg(lvds, MIPIPHY_REGE3, 193 m_MIPI_EN | m_LVDS_EN | m_TTL_EN, 194 v_MIPI_EN(0) | v_LVDS_EN(1) | v_TTL_EN(0)); 195 } else { 196 lvds_msk_reg(lvds, MIPIPHY_REGE3, 197 m_MIPI_EN | m_LVDS_EN | m_TTL_EN, 198 v_MIPI_EN(0) | v_LVDS_EN(0) | v_TTL_EN(1)); 199 200 /* set clock lane enable */ 201 lvds_ctrl_writel(lvds, 0xa0, 0x4); 202 } 203 /* delay for waitting pll lock on */ 204 while (delay_times--) { 205 if (lvds_phy_lock(lvds)) 206 break; 207 udelay(100); 208 } 209 210 if (delay_times <= 0) 211 printf("wait lvds phy lock failed, please check the hardware!\n"); 212 213 return 0; 214 } 215 216 static void px30_output_ttl(struct display_state *state) 217 { 218 struct connector_state *conn_state = &state->conn_state; 219 struct rockchip_lvds_device *lvds = conn_state->private; 220 u32 val = 0; 221 222 /* enable lvds mode */ 223 val = PX30_RGB_SYNC_BYPASS(1) | PX30_DPHY_FORCERXMODE(1); 224 writel(val, lvds->grf + PX30_GRF_PD_VO_CON1); 225 226 /* enable lane */ 227 lvds_writel(lvds, MIPIPHY_REG0, 0x7f); 228 val = v_LANE0_EN(1) | v_LANE1_EN(1) | v_LANE2_EN(1) | v_LANE3_EN(1) | 229 v_LANECLK_EN(1) | v_PLL_PWR_OFF(1); 230 lvds_writel(lvds, MIPIPHY_REGEB, val); 231 /* set ttl mode and reset phy config */ 232 val = v_LVDS_MODE_EN(0) | v_TTL_MODE_EN(1) | v_MIPI_MODE_EN(0) | 233 v_MSB_SEL(1) | v_DIG_INTER_RST(1); 234 lvds_writel(lvds, MIPIPHY_REGE0, val); 235 rk336x_lvds_pwr_on(state); 236 } 237 238 static void rk3126_output_ttl(struct display_state *state) 239 { 240 struct connector_state *conn_state = &state->conn_state; 241 struct rockchip_lvds_device *lvds = conn_state->private; 242 u32 val = 0; 243 244 /* enable lvds mode */ 245 val = v_RK3126_LVDSMODE_EN(0) | 246 v_RK3126_MIPIPHY_TTL_EN(1) | 247 v_RK3126_MIPIPHY_LANE0_EN(1) | 248 v_RK3126_MIPIDPI_FORCEX_EN(1); 249 writel(val, lvds->grf + lvds->pdata->grf_soc_con7); 250 val = v_RK3126_MIPITTL_CLK_EN(1) | 251 v_RK3126_MIPITTL_LANE0_EN(1) | 252 v_RK3126_MIPITTL_LANE1_EN(1) | 253 v_RK3126_MIPITTL_LANE2_EN(1) | 254 v_RK3126_MIPITTL_LANE3_EN(1); 255 writel(val, lvds->grf + lvds->pdata->grf_soc_con15); 256 /* enable lane */ 257 lvds_writel(lvds, MIPIPHY_REG0, 0x7f); 258 val = v_LANE0_EN(1) | v_LANE1_EN(1) | v_LANE2_EN(1) | v_LANE3_EN(1) | 259 v_LANECLK_EN(1) | v_PLL_PWR_OFF(1); 260 lvds_writel(lvds, MIPIPHY_REGEB, val); 261 /* set ttl mode and reset phy config */ 262 val = v_LVDS_MODE_EN(0) | v_TTL_MODE_EN(1) | v_MIPI_MODE_EN(0) | 263 v_MSB_SEL(1) | v_DIG_INTER_RST(1); 264 lvds_writel(lvds, MIPIPHY_REGE0, val); 265 rk336x_lvds_pwr_on(state); 266 } 267 268 static void rk336x_output_ttl(struct display_state *state) 269 { 270 struct connector_state *conn_state = &state->conn_state; 271 struct rockchip_lvds_device *lvds = conn_state->private; 272 u32 val = 0; 273 274 /* enable lvds mode */ 275 val = v_RK336X_LVDSMODE_EN(0) | v_RK336X_MIPIPHY_TTL_EN(1) | 276 v_RK336X_MIPIPHY_LANE0_EN(1) | 277 v_RK336X_MIPIDPI_FORCEX_EN(1); 278 writel(val, lvds->grf + lvds->pdata->grf_soc_con7); 279 val = v_RK336X_FORCE_JETAG(0); 280 writel(val, lvds->grf + lvds->pdata->grf_soc_con15); 281 282 /* enable lane */ 283 lvds_writel(lvds, MIPIPHY_REG0, 0x7f); 284 val = v_LANE0_EN(1) | v_LANE1_EN(1) | v_LANE2_EN(1) | v_LANE3_EN(1) | 285 v_LANECLK_EN(1) | v_PLL_PWR_OFF(1); 286 lvds_writel(lvds, MIPIPHY_REGEB, val); 287 288 /* set ttl mode and reset phy config */ 289 val = v_LVDS_MODE_EN(0) | v_TTL_MODE_EN(1) | v_MIPI_MODE_EN(0) | 290 v_MSB_SEL(1) | v_DIG_INTER_RST(1); 291 lvds_writel(lvds, MIPIPHY_REGE0, val); 292 293 rk336x_lvds_pwr_on(state); 294 } 295 296 static void px30_output_lvds(struct display_state *state) 297 { 298 struct connector_state *conn_state = &state->conn_state; 299 struct rockchip_lvds_device *lvds = conn_state->private; 300 u32 val = 0; 301 302 /* enable lvds mode */ 303 val = PX30_LVDS_PHY_MODE(1) | PX30_DPHY_FORCERXMODE(1); 304 /* config lvds_format */ 305 val |= PX30_LVDS_OUTPUT_FORMAT(lvds->format); 306 /* LSB receive mode */ 307 val |= PX30_LVDS_MSBSEL(LVDS_MSB_D7); 308 writel(val, lvds->grf + PX30_GRF_PD_VO_CON1); 309 310 /* digital internal disable */ 311 lvds_msk_reg(lvds, MIPIPHY_REGE1, m_DIG_INTER_EN, v_DIG_INTER_EN(0)); 312 313 /* set pll prediv and fbdiv */ 314 lvds_writel(lvds, MIPIPHY_REG3, v_PREDIV(2) | v_FBDIV_MSB(0)); 315 lvds_writel(lvds, MIPIPHY_REG4, v_FBDIV_LSB(28)); 316 317 lvds_writel(lvds, MIPIPHY_REGE8, 0xfc); 318 319 /* set lvds mode and reset phy config */ 320 lvds_msk_reg(lvds, MIPIPHY_REGE0, 321 m_MSB_SEL | m_DIG_INTER_RST, 322 v_MSB_SEL(1) | v_DIG_INTER_RST(1)); 323 324 rk336x_lvds_pwr_on(state); 325 lvds_msk_reg(lvds, MIPIPHY_REGE1, m_DIG_INTER_EN, v_DIG_INTER_EN(1)); 326 } 327 328 static void rk3126_output_lvds(struct display_state *state) 329 { 330 struct connector_state *conn_state = &state->conn_state; 331 struct rockchip_lvds_device *lvds = conn_state->private; 332 u32 val = 0; 333 334 /* enable lvds mode */ 335 val = v_RK3126_LVDSMODE_EN(1) | 336 v_RK3126_MIPIPHY_TTL_EN(0); 337 /* config lvds_format */ 338 val |= v_RK3126_LVDS_OUTPUT_FORMAT(lvds->format); 339 /* LSB receive mode */ 340 val |= v_RK3126_LVDS_MSBSEL(LVDS_MSB_D7); 341 val |= v_RK3126_MIPIPHY_LANE0_EN(1) | 342 v_RK3126_MIPIDPI_FORCEX_EN(1); 343 writel(val, lvds->grf + lvds->pdata->grf_soc_con7); 344 345 /* digital internal disable */ 346 lvds_msk_reg(lvds, MIPIPHY_REGE1, m_DIG_INTER_EN, v_DIG_INTER_EN(0)); 347 348 /* set pll prediv and fbdiv */ 349 lvds_writel(lvds, MIPIPHY_REG3, v_PREDIV(2) | v_FBDIV_MSB(0)); 350 lvds_writel(lvds, MIPIPHY_REG4, v_FBDIV_LSB(28)); 351 352 lvds_writel(lvds, MIPIPHY_REGE8, 0xfc); 353 354 /* set lvds mode and reset phy config */ 355 lvds_msk_reg(lvds, MIPIPHY_REGE0, 356 m_MSB_SEL | m_DIG_INTER_RST, 357 v_MSB_SEL(1) | v_DIG_INTER_RST(1)); 358 359 rk336x_lvds_pwr_on(state); 360 lvds_msk_reg(lvds, MIPIPHY_REGE1, m_DIG_INTER_EN, v_DIG_INTER_EN(1)); 361 } 362 363 static void rk336x_output_lvds(struct display_state *state) 364 { 365 struct connector_state *conn_state = &state->conn_state; 366 struct rockchip_lvds_device *lvds = conn_state->private; 367 u32 val = 0; 368 369 /* enable lvds mode */ 370 val |= v_RK336X_LVDSMODE_EN(1) | v_RK336X_MIPIPHY_TTL_EN(0); 371 /* config lvds_format */ 372 val |= v_RK336X_LVDS_OUTPUT_FORMAT(lvds->format); 373 /* LSB receive mode */ 374 val |= v_RK336X_LVDS_MSBSEL(LVDS_MSB_D7); 375 val |= v_RK336X_MIPIPHY_LANE0_EN(1) | 376 v_RK336X_MIPIDPI_FORCEX_EN(1); 377 writel(val, lvds->grf + lvds->pdata->grf_soc_con7); 378 /* digital internal disable */ 379 lvds_msk_reg(lvds, MIPIPHY_REGE1, m_DIG_INTER_EN, v_DIG_INTER_EN(0)); 380 381 /* set pll prediv and fbdiv */ 382 lvds_writel(lvds, MIPIPHY_REG3, v_PREDIV(2) | v_FBDIV_MSB(0)); 383 lvds_writel(lvds, MIPIPHY_REG4, v_FBDIV_LSB(28)); 384 385 lvds_writel(lvds, MIPIPHY_REGE8, 0xfc); 386 387 /* set lvds mode and reset phy config */ 388 lvds_msk_reg(lvds, MIPIPHY_REGE0, 389 m_MSB_SEL | m_DIG_INTER_RST, 390 v_MSB_SEL(1) | v_DIG_INTER_RST(1)); 391 392 rk336x_lvds_pwr_on(state); 393 lvds_msk_reg(lvds, MIPIPHY_REGE1, m_DIG_INTER_EN, v_DIG_INTER_EN(1)); 394 } 395 396 static int rk3288_lvds_pwr_on(struct display_state *state) 397 { 398 struct connector_state *conn_state = &state->conn_state; 399 struct rockchip_lvds_device *lvds = conn_state->private; 400 struct drm_display_mode *mode = &conn_state->mode; 401 u32 val; 402 u32 h_bp = mode->htotal - mode->hsync_start; 403 u8 pin_hsync = (mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1 : 0; 404 u8 pin_dclk = (mode->flags & DRM_MODE_FLAG_PCSYNC) ? 1 : 0; 405 406 val = lvds->format; 407 if (lvds->output == DISPLAY_OUTPUT_DUAL_LVDS) 408 val |= LVDS_DUAL | LVDS_CH0_EN | LVDS_CH1_EN; 409 else if (lvds->output == DISPLAY_OUTPUT_LVDS) 410 val |= LVDS_CH0_EN; 411 else if (lvds->output == DISPLAY_OUTPUT_RGB) 412 val |= LVDS_TTL_EN | LVDS_CH0_EN | LVDS_CH1_EN; 413 414 if (h_bp & 0x01) 415 val |= LVDS_START_PHASE_RST_1; 416 417 val |= (pin_dclk << 8) | (pin_hsync << 9); 418 val |= (0xffff << 16); 419 writel(val, lvds->grf + lvds->pdata->grf_soc_con7); 420 421 return 0; 422 } 423 424 static void rk3288_output_ttl(struct display_state *state) 425 { 426 struct connector_state *conn_state = &state->conn_state; 427 struct rockchip_lvds_device *lvds = conn_state->private; 428 429 rk3288_lvds_pwr_on(state); 430 lvds_writel(lvds, RK3288_LVDS_CH0_REG0, 431 RK3288_LVDS_CH0_REG0_TTL_EN | 432 RK3288_LVDS_CH0_REG0_LANECK_EN | 433 RK3288_LVDS_CH0_REG0_LANE4_EN | 434 RK3288_LVDS_CH0_REG0_LANE3_EN | 435 RK3288_LVDS_CH0_REG0_LANE2_EN | 436 RK3288_LVDS_CH0_REG0_LANE1_EN | 437 RK3288_LVDS_CH0_REG0_LANE0_EN); 438 lvds_writel(lvds, RK3288_LVDS_CH0_REG2, 439 RK3288_LVDS_PLL_FBDIV_REG2(0x46)); 440 441 lvds_writel(lvds, RK3288_LVDS_CH0_REG3, 442 RK3288_LVDS_PLL_FBDIV_REG3(0x46)); 443 lvds_writel(lvds, RK3288_LVDS_CH0_REG4, 444 RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE | 445 RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE | 446 RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE | 447 RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE | 448 RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE | 449 RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE); 450 lvds_writel(lvds, RK3288_LVDS_CH0_REG5, 451 RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA | 452 RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA | 453 RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA | 454 RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA | 455 RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA | 456 RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA); 457 lvds_writel(lvds, RK3288_LVDS_CH0_REGD, 458 RK3288_LVDS_PLL_PREDIV_REGD(0x0a)); 459 lvds_writel(lvds, RK3288_LVDS_CH0_REG20, 460 RK3288_LVDS_CH0_REG20_LSB); 461 462 lvds_writel(lvds, RK3288_LVDS_CFG_REGC, RK3288_LVDS_CFG_REGC_PLL_ENABLE); 463 lvds_writel(lvds, RK3288_LVDS_CFG_REG21, RK3288_LVDS_CFG_REG21_TX_ENABLE); 464 } 465 466 static void rk3288_output_lvds(struct display_state *state) 467 { 468 struct connector_state *conn_state = &state->conn_state; 469 struct rockchip_lvds_device *lvds = conn_state->private; 470 471 rk3288_lvds_pwr_on(state); 472 473 lvds_writel(lvds, RK3288_LVDS_CH0_REG0, 474 RK3288_LVDS_CH0_REG0_LVDS_EN | 475 RK3288_LVDS_CH0_REG0_LANECK_EN | 476 RK3288_LVDS_CH0_REG0_LANE4_EN | 477 RK3288_LVDS_CH0_REG0_LANE3_EN | 478 RK3288_LVDS_CH0_REG0_LANE2_EN | 479 RK3288_LVDS_CH0_REG0_LANE1_EN | 480 RK3288_LVDS_CH0_REG0_LANE0_EN); 481 lvds_writel(lvds, RK3288_LVDS_CH0_REG1, 482 RK3288_LVDS_CH0_REG1_LANECK_BIAS | 483 RK3288_LVDS_CH0_REG1_LANE4_BIAS | 484 RK3288_LVDS_CH0_REG1_LANE3_BIAS | 485 RK3288_LVDS_CH0_REG1_LANE2_BIAS | 486 RK3288_LVDS_CH0_REG1_LANE1_BIAS | 487 RK3288_LVDS_CH0_REG1_LANE0_BIAS); 488 lvds_writel(lvds, RK3288_LVDS_CH0_REG2, 489 RK3288_LVDS_CH0_REG2_RESERVE_ON | 490 RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE | 491 RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE | 492 RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE | 493 RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE | 494 RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE | 495 RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE | 496 RK3288_LVDS_PLL_FBDIV_REG2(0x46)); 497 lvds_writel(lvds, RK3288_LVDS_CH0_REG3, 498 RK3288_LVDS_PLL_FBDIV_REG3(0x46)); 499 lvds_writel(lvds, RK3288_LVDS_CH0_REG4, 0x00); 500 lvds_writel(lvds, RK3288_LVDS_CH0_REG5, 0x00); 501 lvds_writel(lvds, RK3288_LVDS_CH0_REGD, 502 RK3288_LVDS_PLL_PREDIV_REGD(0x0a)); 503 lvds_writel(lvds, RK3288_LVDS_CH0_REG20, 504 RK3288_LVDS_CH0_REG20_LSB); 505 506 lvds_writel(lvds, RK3288_LVDS_CFG_REGC, RK3288_LVDS_CFG_REGC_PLL_ENABLE); 507 lvds_writel(lvds, RK3288_LVDS_CFG_REG21, RK3288_LVDS_CFG_REG21_TX_ENABLE); 508 } 509 510 static int rockchip_lvds_init(struct display_state *state) 511 { 512 struct connector_state *conn_state = &state->conn_state; 513 const struct rockchip_connector *connector = conn_state->connector; 514 const struct rockchip_lvds_chip_data *pdata = connector->data; 515 struct rockchip_lvds_device *lvds; 516 const char *name; 517 int i, width; 518 struct resource lvds_phy, lvds_ctrl; 519 struct panel_state *panel_state = &state->panel_state; 520 ofnode panel_node = panel_state->node; 521 int ret; 522 523 lvds = malloc(sizeof(*lvds)); 524 if (!lvds) 525 return -ENOMEM; 526 lvds->pdata = pdata; 527 528 if (pdata->chip_type == RK3288_LVDS) { 529 lvds->regbase = dev_read_addr_ptr(conn_state->dev); 530 } else { 531 i = dev_read_resource(conn_state->dev, 0, &lvds_phy); 532 if (i) { 533 printf("can't get regs lvds_phy addresses!\n"); 534 free(lvds); 535 return -ENOMEM; 536 } 537 538 i = dev_read_resource(conn_state->dev, 1, &lvds_ctrl); 539 if (i) { 540 printf("can't get regs lvds_ctrl addresses!\n"); 541 free(lvds); 542 return -ENOMEM; 543 } 544 545 lvds->regbase = (void *)lvds_phy.start; 546 lvds->ctrl_reg = (void *)lvds_ctrl.start; 547 } 548 549 lvds->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 550 if (lvds->grf <= 0) { 551 printf("%s: Get syscon grf failed (ret=%p)\n", 552 __func__, lvds->grf); 553 return -ENXIO; 554 } 555 556 ret = dev_read_string_index(panel_state->dev, "rockchip,output", 0, &name); 557 if (ret) 558 /* default set it as output rgb */ 559 lvds->output = DISPLAY_OUTPUT_RGB; 560 else 561 lvds->output = lvds_name_to_output(name); 562 if (lvds->output < 0) { 563 printf("invalid output type [%s]\n", name); 564 free(lvds); 565 return lvds->output; 566 } 567 ret = dev_read_string_index(panel_state->dev, "rockchip,data-mapping", 0, &name); 568 if (ret) 569 /* default set it as format jeida */ 570 lvds->format = LVDS_FORMAT_JEIDA; 571 else 572 lvds->format = lvds_name_to_format(name); 573 574 if (lvds->format < 0) { 575 printf("invalid data-mapping format [%s]\n", name); 576 free(lvds); 577 return lvds->format; 578 } 579 width = ofnode_read_u32_default(panel_node, "rockchip,data-width", 24); 580 if (width == 24) { 581 lvds->format |= LVDS_24BIT; 582 } else if (width == 18) { 583 lvds->format |= LVDS_18BIT; 584 } else { 585 printf("rockchip-lvds unsupport data-width[%d]\n", width); 586 free(lvds); 587 return -EINVAL; 588 } 589 590 printf("LVDS: data mapping: %s, data-width:%d, format:%d,\n", 591 name, width, lvds->format); 592 conn_state->private = lvds; 593 conn_state->type = DRM_MODE_CONNECTOR_LVDS; 594 595 if ((lvds->output == DISPLAY_OUTPUT_RGB) && (width == 18)) 596 conn_state->output_mode = ROCKCHIP_OUT_MODE_P666; 597 else 598 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 599 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 600 601 return 0; 602 } 603 604 static void rockchip_lvds_deinit(struct display_state *state) 605 { 606 struct connector_state *conn_state = &state->conn_state; 607 struct rockchip_lvds_device *lvds = conn_state->private; 608 609 free(lvds); 610 } 611 612 static int rockchip_lvds_prepare(struct display_state *state) 613 { 614 struct connector_state *conn_state = &state->conn_state; 615 struct rockchip_lvds_device *lvds = conn_state->private; 616 lvds->mode = &conn_state->mode; 617 618 rockchip_lvds_clk_enable(lvds); 619 620 return 0; 621 } 622 623 static void rockchip_lvds_vop_routing(struct rockchip_lvds_device *lvds, int pipe) 624 { 625 u32 val; 626 627 if (lvds->pdata->chip_type == RK3288_LVDS) { 628 if (pipe) 629 val = RK3288_LVDS_SOC_CON6_SEL_VOP_LIT | 630 (RK3288_LVDS_SOC_CON6_SEL_VOP_LIT << 16); 631 else 632 val = RK3288_LVDS_SOC_CON6_SEL_VOP_LIT << 16; 633 writel(val, lvds->grf + lvds->pdata->grf_soc_con6); 634 } else if (lvds->pdata->chip_type == PX30_LVDS) { 635 if (lvds->output == DISPLAY_OUTPUT_RGB) 636 writel(PX30_RGB_VOP_SEL(pipe), 637 lvds->grf + PX30_GRF_PD_VO_CON1); 638 else if (lvds->output == DISPLAY_OUTPUT_LVDS) 639 writel(PX30_LVDS_VOP_SEL(pipe), 640 lvds->grf + PX30_GRF_PD_VO_CON1); 641 } 642 } 643 644 static int rockchip_lvds_enable(struct display_state *state) 645 { 646 struct connector_state *conn_state = &state->conn_state; 647 struct rockchip_lvds_device *lvds = conn_state->private; 648 struct crtc_state *crtc_state = &state->crtc_state; 649 650 if (lvds->pdata->has_vop_sel) 651 rockchip_lvds_vop_routing(lvds, crtc_state->crtc_id); 652 653 if ((lvds->output == DISPLAY_OUTPUT_LVDS) || 654 (lvds->output == DISPLAY_OUTPUT_DUAL_LVDS)) { 655 if (lvds->pdata->chip_type == RK3288_LVDS) 656 rk3288_output_lvds(state); 657 else if (lvds->pdata->chip_type == RK3126_LVDS) 658 rk3126_output_lvds(state); 659 else if (lvds->pdata->chip_type == PX30_LVDS) 660 px30_output_lvds(state); 661 else 662 rk336x_output_lvds(state); 663 } else { 664 if (lvds->pdata->chip_type == RK3288_LVDS) 665 rk3288_output_ttl(state); 666 else if (lvds->pdata->chip_type == RK3126_LVDS) 667 rk3126_output_ttl(state); 668 else if (lvds->pdata->chip_type == PX30_LVDS) 669 px30_output_ttl(state); 670 else 671 rk336x_output_ttl(state); 672 } 673 674 return 0; 675 } 676 677 static int rockchip_lvds_disable(struct display_state *state) 678 { 679 struct connector_state *conn_state = &state->conn_state; 680 struct rockchip_lvds_device *lvds = conn_state->private; 681 682 if (lvds->pdata->chip_type == RK3288_LVDS) 683 rk3288_lvds_pwr_off(state); 684 else 685 rk336x_lvds_pwr_off(state); 686 687 return 0; 688 } 689 690 const struct rockchip_connector_funcs rockchip_lvds_funcs = { 691 .init = rockchip_lvds_init, 692 .deinit = rockchip_lvds_deinit, 693 .prepare = rockchip_lvds_prepare, 694 .enable = rockchip_lvds_enable, 695 .disable = rockchip_lvds_disable, 696 }; 697 698 static const struct rockchip_lvds_chip_data px30_lvds_drv_data = { 699 .chip_type = PX30_LVDS, 700 .has_vop_sel = true, 701 }; 702 703 static const struct rockchip_connector px30_lvds_data = { 704 .funcs = &rockchip_lvds_funcs, 705 .data = &px30_lvds_drv_data, 706 }; 707 708 static const struct rockchip_lvds_chip_data rk3126_lvds_drv_data = { 709 .chip_type = RK3126_LVDS, 710 .grf_soc_con7 = RK3126_GRF_LVDS_CON0, 711 .grf_soc_con15 = RK3126_GRF_CON1, 712 .has_vop_sel = true, 713 }; 714 715 static const struct rockchip_connector rk3126_lvds_data = { 716 .funcs = &rockchip_lvds_funcs, 717 .data = &rk3126_lvds_drv_data, 718 }; 719 720 static const struct rockchip_lvds_chip_data rk3288_lvds_drv_data = { 721 .chip_type = RK3288_LVDS, 722 .has_vop_sel = true, 723 .grf_soc_con6 = 0x025c, 724 .grf_soc_con7 = 0x0260, 725 .grf_gpio1d_iomux = 0x000c, 726 }; 727 728 static const struct rockchip_connector rk3288_lvds_data = { 729 .funcs = &rockchip_lvds_funcs, 730 .data = &rk3288_lvds_drv_data, 731 }; 732 733 static const struct rockchip_lvds_chip_data rk3368_lvds_drv_data = { 734 .chip_type = RK3368_LVDS, 735 .grf_soc_con7 = RK3368_GRF_SOC_CON7, 736 .grf_soc_con15 = RK3368_GRF_SOC_CON15, 737 .has_vop_sel = false, 738 }; 739 740 static const struct rockchip_connector rk3368_lvds_data = { 741 .funcs = &rockchip_lvds_funcs, 742 .data = &rk3368_lvds_drv_data, 743 }; 744 745 static const struct udevice_id rockchip_lvds_ids[] = { 746 { 747 .compatible = "rockchip,px30-lvds", 748 .data = (ulong)&px30_lvds_data, 749 }, 750 { 751 .compatible = "rockchip,rk3126-lvds", 752 .data = (ulong)&rk3126_lvds_data, 753 }, 754 { 755 .compatible = "rockchip,rk3288-lvds", 756 .data = (ulong)&rk3288_lvds_data, 757 }, 758 { 759 .compatible = "rockchip,rk3368-lvds", 760 .data = (ulong)&rk3368_lvds_data, 761 }, 762 {} 763 }; 764 765 U_BOOT_DRIVER(rockchip_lvds) = { 766 .name = "rockchip_lvds", 767 .id = UCLASS_DISPLAY, 768 .of_match = rockchip_lvds_ids, 769 }; 770