1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <linux/list.h> 13 #include <linux/ioport.h> 14 #include <asm/io.h> 15 #include <asm/hardware.h> 16 #include <dm/device.h> 17 #include <dm/read.h> 18 #include <dm/ofnode.h> 19 #include <syscon.h> 20 #include <asm/arch-rockchip/clock.h> 21 #include <asm/gpio.h> 22 23 #include "rockchip_display.h" 24 #include "rockchip_crtc.h" 25 #include "rockchip_connector.h" 26 #include "rockchip_lvds.h" 27 28 enum rockchip_lvds_sub_devtype { 29 PX30_LVDS, 30 RK3126_LVDS, 31 RK3288_LVDS, 32 RK3368_LVDS, 33 }; 34 35 struct rockchip_lvds_chip_data { 36 u32 chip_type; 37 bool has_vop_sel; 38 u32 grf_soc_con5; 39 u32 grf_soc_con6; 40 u32 grf_soc_con7; 41 u32 grf_soc_con15; 42 u32 grf_gpio1d_iomux; 43 }; 44 45 struct rockchip_lvds_device { 46 void *regbase; 47 void *grf; 48 void *ctrl_reg; 49 u32 channel; 50 u32 output; 51 u32 format; 52 struct drm_display_mode *mode; 53 const struct rockchip_lvds_chip_data *pdata; 54 }; 55 56 static inline int lvds_name_to_format(const char *s) 57 { 58 if (!s) 59 return -EINVAL; 60 61 if (strncmp(s, "jeida", 6) == 0) 62 return LVDS_FORMAT_JEIDA; 63 else if (strncmp(s, "vesa", 5) == 0) 64 return LVDS_FORMAT_VESA; 65 66 return -EINVAL; 67 } 68 69 static inline int lvds_name_to_output(const char *s) 70 { 71 if (!s) 72 return -EINVAL; 73 74 if (strncmp(s, "rgb", 3) == 0) 75 return DISPLAY_OUTPUT_RGB; 76 else if (strncmp(s, "lvds", 4) == 0) 77 return DISPLAY_OUTPUT_LVDS; 78 else if (strncmp(s, "duallvds", 8) == 0) 79 return DISPLAY_OUTPUT_DUAL_LVDS; 80 81 return -EINVAL; 82 } 83 84 static inline void lvds_writel(struct rockchip_lvds_device *lvds, 85 u32 offset, u32 val) 86 { 87 writel(val, lvds->regbase + offset); 88 89 if ((lvds->pdata->chip_type == RK3288_LVDS) && 90 ((lvds->output == DISPLAY_OUTPUT_DUAL_LVDS) || 91 (lvds->output == DISPLAY_OUTPUT_RGB))) 92 writel(val, lvds->regbase + offset + 0x100); 93 } 94 95 static inline void lvds_msk_reg(struct rockchip_lvds_device *lvds, u32 offset, 96 u32 msk, u32 val) 97 { 98 u32 temp; 99 100 temp = readl(lvds->regbase + offset) & (0xFF - (msk)); 101 writel(temp | ((val) & (msk)), lvds->regbase + offset); 102 } 103 104 static inline u32 lvds_readl(struct rockchip_lvds_device *lvds, u32 offset) 105 { 106 return readl(lvds->regbase + offset); 107 } 108 109 static inline void lvds_ctrl_writel(struct rockchip_lvds_device *lvds, 110 u32 offset, u32 val) 111 { 112 writel(val, lvds->ctrl_reg + offset); 113 } 114 115 static inline u32 lvds_pmugrf_readl(u32 offset) 116 { 117 return readl((void *)LVDS_PMUGRF_BASE + offset); 118 } 119 120 static inline void lvds_pmugrf_writel(u32 offset, u32 val) 121 { 122 writel(val, (void *)LVDS_PMUGRF_BASE + offset); 123 } 124 125 static inline u32 lvds_phy_lock(struct rockchip_lvds_device *lvds) 126 { 127 u32 val = 0; 128 val = readl(lvds->ctrl_reg + MIPIC_PHY_STATUS); 129 return (val & m_PHY_LOCK_STATUS) ? 1 : 0; 130 } 131 132 static int rockchip_lvds_clk_enable(struct rockchip_lvds_device *lvds) 133 { 134 return 0; 135 } 136 137 static int rk336x_lvds_pwr_off(struct display_state *state) 138 { 139 struct connector_state *conn_state = &state->conn_state; 140 struct rockchip_lvds_device *lvds = conn_state->private; 141 142 /* disable lvds lane and power off pll */ 143 lvds_writel(lvds, MIPIPHY_REGEB, 144 v_LANE0_EN(0) | v_LANE1_EN(0) | v_LANE2_EN(0) | 145 v_LANE3_EN(0) | v_LANECLK_EN(0) | v_PLL_PWR_OFF(1) | 146 v_LVDS_BGPD(1)); 147 148 /* power down lvds pll and bandgap */ 149 lvds_msk_reg(lvds, MIPIPHY_REG1, 150 m_SYNC_RST | m_LDO_PWR_DOWN | m_PLL_PWR_DOWN, 151 v_SYNC_RST(1) | v_LDO_PWR_DOWN(1) | v_PLL_PWR_DOWN(1)); 152 153 /* disable lvds */ 154 lvds_msk_reg(lvds, MIPIPHY_REGE3, m_LVDS_EN | m_TTL_EN, 155 v_LVDS_EN(0) | v_TTL_EN(0)); 156 157 return 0; 158 } 159 160 static int rk3288_lvds_pwr_off(struct display_state *state) 161 { 162 struct connector_state *conn_state = &state->conn_state; 163 struct rockchip_lvds_device *lvds = conn_state->private; 164 165 lvds_writel(lvds, RK3288_LVDS_CFG_REG21, RK3288_LVDS_CFG_REG21_TX_DISABLE); 166 lvds_writel(lvds, RK3288_LVDS_CFG_REGC, RK3288_LVDS_CFG_REGC_PLL_DISABLE); 167 168 writel(0xffff8000, lvds->grf + lvds->pdata->grf_soc_con7); 169 170 return 0; 171 } 172 173 static int rk336x_lvds_pwr_on(struct display_state *state) 174 { 175 struct connector_state *conn_state = &state->conn_state; 176 struct rockchip_lvds_device *lvds = conn_state->private; 177 u32 delay_times = 20; 178 179 if (lvds->output == DISPLAY_OUTPUT_LVDS) { 180 /* set VOCM 900 mv and V-DIFF 350 mv */ 181 lvds_msk_reg(lvds, MIPIPHY_REGE4, m_VOCM | m_DIFF_V, 182 v_VOCM(0) | v_DIFF_V(2)); 183 /* power up lvds pll and ldo */ 184 lvds_msk_reg(lvds, MIPIPHY_REG1, 185 m_SYNC_RST | m_LDO_PWR_DOWN | m_PLL_PWR_DOWN, 186 v_SYNC_RST(0) | v_LDO_PWR_DOWN(0) | 187 v_PLL_PWR_DOWN(0)); 188 /* enable lvds lane and power on pll */ 189 lvds_writel(lvds, MIPIPHY_REGEB, 190 v_LANE0_EN(1) | v_LANE1_EN(1) | v_LANE2_EN(1) | 191 v_LANE3_EN(1) | v_LANECLK_EN(1) | v_PLL_PWR_OFF(0) | 192 v_LVDS_BGPD(0)); 193 194 /* enable lvds */ 195 lvds_msk_reg(lvds, MIPIPHY_REGE3, 196 m_MIPI_EN | m_LVDS_EN | m_TTL_EN, 197 v_MIPI_EN(0) | v_LVDS_EN(1) | v_TTL_EN(0)); 198 } else { 199 lvds_msk_reg(lvds, MIPIPHY_REGE3, 200 m_MIPI_EN | m_LVDS_EN | m_TTL_EN, 201 v_MIPI_EN(0) | v_LVDS_EN(0) | v_TTL_EN(1)); 202 203 /* set clock lane enable */ 204 lvds_ctrl_writel(lvds, 0xa0, 0x4); 205 } 206 /* delay for waitting pll lock on */ 207 while (delay_times--) { 208 if (lvds_phy_lock(lvds)) 209 break; 210 udelay(100); 211 } 212 213 if (delay_times <= 0) 214 printf("wait lvds phy lock failed, please check the hardware!\n"); 215 216 return 0; 217 } 218 219 static void px30_output_ttl(struct display_state *state) 220 { 221 struct connector_state *conn_state = &state->conn_state; 222 struct rockchip_lvds_device *lvds = conn_state->private; 223 u32 val = 0; 224 225 /* enable lvds mode */ 226 val = PX30_RGB_SYNC_BYPASS(1) | PX30_DPHY_FORCERXMODE(1); 227 writel(val, lvds->grf + PX30_GRF_PD_VO_CON1); 228 229 /* enable lane */ 230 lvds_msk_reg(lvds, MIPIPHY_REG0, 0x7c, 0x7c); 231 val = v_LANE0_EN(1) | v_LANE1_EN(1) | v_LANE2_EN(1) | v_LANE3_EN(1) | 232 v_LANECLK_EN(1) | v_PLL_PWR_OFF(1) | v_LVDS_BGPD(0); 233 lvds_writel(lvds, MIPIPHY_REGEB, val); 234 /* set ttl mode and reset phy config */ 235 val = v_LVDS_MODE_EN(0) | v_TTL_MODE_EN(1) | v_MIPI_MODE_EN(0) | 236 v_MSB_SEL(1) | v_DIG_INTER_RST(1); 237 lvds_writel(lvds, MIPIPHY_REGE0, val); 238 rk336x_lvds_pwr_on(state); 239 } 240 241 static void rk3126_output_ttl(struct display_state *state) 242 { 243 struct connector_state *conn_state = &state->conn_state; 244 struct rockchip_lvds_device *lvds = conn_state->private; 245 u32 val = 0; 246 247 /* enable lvds mode */ 248 val = v_RK3126_LVDSMODE_EN(0) | 249 v_RK3126_MIPIPHY_TTL_EN(1) | 250 v_RK3126_MIPIPHY_LANE0_EN(1) | 251 v_RK3126_MIPIDPI_FORCEX_EN(1); 252 writel(val, lvds->grf + lvds->pdata->grf_soc_con7); 253 val = v_RK3126_MIPITTL_CLK_EN(1) | 254 v_RK3126_MIPITTL_LANE0_EN(1) | 255 v_RK3126_MIPITTL_LANE1_EN(1) | 256 v_RK3126_MIPITTL_LANE2_EN(1) | 257 v_RK3126_MIPITTL_LANE3_EN(1); 258 writel(val, lvds->grf + lvds->pdata->grf_soc_con15); 259 /* enable lane */ 260 lvds_msk_reg(lvds, MIPIPHY_REG0, 0x7c, 0x7c); 261 val = v_LANE0_EN(1) | v_LANE1_EN(1) | v_LANE2_EN(1) | v_LANE3_EN(1) | 262 v_LANECLK_EN(1) | v_PLL_PWR_OFF(1) | v_LVDS_BGPD(0); 263 lvds_writel(lvds, MIPIPHY_REGEB, val); 264 /* set ttl mode and reset phy config */ 265 val = v_LVDS_MODE_EN(0) | v_TTL_MODE_EN(1) | v_MIPI_MODE_EN(0) | 266 v_MSB_SEL(1) | v_DIG_INTER_RST(1); 267 lvds_writel(lvds, MIPIPHY_REGE0, val); 268 rk336x_lvds_pwr_on(state); 269 } 270 271 static void rk336x_output_ttl(struct display_state *state) 272 { 273 struct connector_state *conn_state = &state->conn_state; 274 struct rockchip_lvds_device *lvds = conn_state->private; 275 u32 val = 0; 276 277 /* enable lvds mode */ 278 val = v_RK336X_LVDSMODE_EN(0) | v_RK336X_MIPIPHY_TTL_EN(1) | 279 v_RK336X_MIPIPHY_LANE0_EN(1) | 280 v_RK336X_MIPIDPI_FORCEX_EN(1); 281 writel(val, lvds->grf + lvds->pdata->grf_soc_con7); 282 val = v_RK336X_FORCE_JETAG(0); 283 writel(val, lvds->grf + lvds->pdata->grf_soc_con15); 284 285 /* enable lane */ 286 lvds_msk_reg(lvds, MIPIPHY_REG0, 0x7c, 0x7c); 287 val = v_LANE0_EN(1) | v_LANE1_EN(1) | v_LANE2_EN(1) | v_LANE3_EN(1) | 288 v_LANECLK_EN(1) | v_PLL_PWR_OFF(1) | v_LVDS_BGPD(0); 289 lvds_writel(lvds, MIPIPHY_REGEB, val); 290 291 /* set ttl mode and reset phy config */ 292 val = v_LVDS_MODE_EN(0) | v_TTL_MODE_EN(1) | v_MIPI_MODE_EN(0) | 293 v_MSB_SEL(1) | v_DIG_INTER_RST(1); 294 lvds_writel(lvds, MIPIPHY_REGE0, val); 295 296 rk336x_lvds_pwr_on(state); 297 } 298 299 static void px30_output_lvds(struct display_state *state) 300 { 301 struct connector_state *conn_state = &state->conn_state; 302 struct rockchip_lvds_device *lvds = conn_state->private; 303 u32 val = 0; 304 305 /* enable lvds mode */ 306 val = PX30_LVDS_PHY_MODE(1) | PX30_DPHY_FORCERXMODE(1); 307 /* config lvds_format */ 308 val |= PX30_LVDS_OUTPUT_FORMAT(lvds->format); 309 /* LSB receive mode */ 310 val |= PX30_LVDS_MSBSEL(LVDS_MSB_D7); 311 writel(val, lvds->grf + PX30_GRF_PD_VO_CON1); 312 313 /* digital internal disable */ 314 lvds_msk_reg(lvds, MIPIPHY_REGE1, m_DIG_INTER_EN, v_DIG_INTER_EN(0)); 315 316 /* set pll prediv and fbdiv */ 317 lvds_writel(lvds, MIPIPHY_REG3, v_PREDIV(2) | v_FBDIV_MSB(0)); 318 lvds_writel(lvds, MIPIPHY_REG4, v_FBDIV_LSB(28)); 319 320 lvds_writel(lvds, MIPIPHY_REGE8, 0xfc); 321 322 lvds_msk_reg(lvds, MIPIPHY_REG8, 323 m_SAMPLE_CLK_DIR, v_SAMPLE_CLK_DIR_REVERSE); 324 325 /* set lvds mode and reset phy config */ 326 lvds_msk_reg(lvds, MIPIPHY_REGE0, 327 m_MSB_SEL | m_DIG_INTER_RST, 328 v_MSB_SEL(1) | v_DIG_INTER_RST(1)); 329 330 rk336x_lvds_pwr_on(state); 331 lvds_msk_reg(lvds, MIPIPHY_REGE1, m_DIG_INTER_EN, v_DIG_INTER_EN(1)); 332 } 333 334 static void rk3126_output_lvds(struct display_state *state) 335 { 336 struct connector_state *conn_state = &state->conn_state; 337 struct rockchip_lvds_device *lvds = conn_state->private; 338 u32 val = 0; 339 340 /* enable lvds mode */ 341 val = v_RK3126_LVDSMODE_EN(1) | 342 v_RK3126_MIPIPHY_TTL_EN(0); 343 /* config lvds_format */ 344 val |= v_RK3126_LVDS_OUTPUT_FORMAT(lvds->format); 345 /* LSB receive mode */ 346 val |= v_RK3126_LVDS_MSBSEL(LVDS_MSB_D7); 347 val |= v_RK3126_MIPIPHY_LANE0_EN(1) | 348 v_RK3126_MIPIDPI_FORCEX_EN(1); 349 writel(val, lvds->grf + lvds->pdata->grf_soc_con7); 350 351 /* digital internal disable */ 352 lvds_msk_reg(lvds, MIPIPHY_REGE1, m_DIG_INTER_EN, v_DIG_INTER_EN(0)); 353 354 /* set pll prediv and fbdiv */ 355 lvds_writel(lvds, MIPIPHY_REG3, v_PREDIV(2) | v_FBDIV_MSB(0)); 356 lvds_writel(lvds, MIPIPHY_REG4, v_FBDIV_LSB(28)); 357 358 lvds_writel(lvds, MIPIPHY_REGE8, 0xfc); 359 360 /* set lvds mode and reset phy config */ 361 lvds_msk_reg(lvds, MIPIPHY_REGE0, 362 m_MSB_SEL | m_DIG_INTER_RST, 363 v_MSB_SEL(1) | v_DIG_INTER_RST(1)); 364 365 rk336x_lvds_pwr_on(state); 366 lvds_msk_reg(lvds, MIPIPHY_REGE1, m_DIG_INTER_EN, v_DIG_INTER_EN(1)); 367 } 368 369 static void rk336x_output_lvds(struct display_state *state) 370 { 371 struct connector_state *conn_state = &state->conn_state; 372 struct rockchip_lvds_device *lvds = conn_state->private; 373 u32 val = 0; 374 375 /* enable lvds mode */ 376 val |= v_RK336X_LVDSMODE_EN(1) | v_RK336X_MIPIPHY_TTL_EN(0); 377 /* config lvds_format */ 378 val |= v_RK336X_LVDS_OUTPUT_FORMAT(lvds->format); 379 /* LSB receive mode */ 380 val |= v_RK336X_LVDS_MSBSEL(LVDS_MSB_D7); 381 val |= v_RK336X_MIPIPHY_LANE0_EN(1) | 382 v_RK336X_MIPIDPI_FORCEX_EN(1); 383 writel(val, lvds->grf + lvds->pdata->grf_soc_con7); 384 /* digital internal disable */ 385 lvds_msk_reg(lvds, MIPIPHY_REGE1, m_DIG_INTER_EN, v_DIG_INTER_EN(0)); 386 387 /* set pll prediv and fbdiv */ 388 lvds_writel(lvds, MIPIPHY_REG3, v_PREDIV(2) | v_FBDIV_MSB(0)); 389 lvds_writel(lvds, MIPIPHY_REG4, v_FBDIV_LSB(28)); 390 391 lvds_writel(lvds, MIPIPHY_REGE8, 0xfc); 392 393 /* set lvds mode and reset phy config */ 394 lvds_msk_reg(lvds, MIPIPHY_REGE0, 395 m_MSB_SEL | m_DIG_INTER_RST, 396 v_MSB_SEL(1) | v_DIG_INTER_RST(1)); 397 398 rk336x_lvds_pwr_on(state); 399 lvds_msk_reg(lvds, MIPIPHY_REGE1, m_DIG_INTER_EN, v_DIG_INTER_EN(1)); 400 } 401 402 static int rk3288_lvds_pwr_on(struct display_state *state) 403 { 404 struct connector_state *conn_state = &state->conn_state; 405 struct rockchip_lvds_device *lvds = conn_state->private; 406 struct drm_display_mode *mode = &conn_state->mode; 407 u32 val; 408 u32 h_bp = mode->htotal - mode->hsync_start; 409 u8 pin_hsync = (mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1 : 0; 410 u8 pin_dclk = (mode->flags & DRM_MODE_FLAG_PCSYNC) ? 1 : 0; 411 412 val = lvds->format; 413 if (lvds->output == DISPLAY_OUTPUT_DUAL_LVDS) 414 val |= LVDS_DUAL | LVDS_CH0_EN | LVDS_CH1_EN; 415 else if (lvds->output == DISPLAY_OUTPUT_LVDS) 416 val |= LVDS_CH0_EN; 417 else if (lvds->output == DISPLAY_OUTPUT_RGB) 418 val |= LVDS_TTL_EN | LVDS_CH0_EN | LVDS_CH1_EN; 419 420 if (h_bp & 0x01) 421 val |= LVDS_START_PHASE_RST_1; 422 423 val |= (pin_dclk << 8) | (pin_hsync << 9); 424 val |= (0xffff << 16); 425 writel(val, lvds->grf + lvds->pdata->grf_soc_con7); 426 427 return 0; 428 } 429 430 static void rk3288_output_ttl(struct display_state *state) 431 { 432 struct connector_state *conn_state = &state->conn_state; 433 struct rockchip_lvds_device *lvds = conn_state->private; 434 435 rk3288_lvds_pwr_on(state); 436 lvds_writel(lvds, RK3288_LVDS_CH0_REG0, 437 RK3288_LVDS_CH0_REG0_TTL_EN | 438 RK3288_LVDS_CH0_REG0_LANECK_EN | 439 RK3288_LVDS_CH0_REG0_LANE4_EN | 440 RK3288_LVDS_CH0_REG0_LANE3_EN | 441 RK3288_LVDS_CH0_REG0_LANE2_EN | 442 RK3288_LVDS_CH0_REG0_LANE1_EN | 443 RK3288_LVDS_CH0_REG0_LANE0_EN); 444 lvds_writel(lvds, RK3288_LVDS_CH0_REG2, 445 RK3288_LVDS_PLL_FBDIV_REG2(0x46)); 446 447 lvds_writel(lvds, RK3288_LVDS_CH0_REG3, 448 RK3288_LVDS_PLL_FBDIV_REG3(0x46)); 449 lvds_writel(lvds, RK3288_LVDS_CH0_REG4, 450 RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE | 451 RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE | 452 RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE | 453 RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE | 454 RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE | 455 RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE); 456 lvds_writel(lvds, RK3288_LVDS_CH0_REG5, 457 RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA | 458 RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA | 459 RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA | 460 RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA | 461 RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA | 462 RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA); 463 lvds_writel(lvds, RK3288_LVDS_CH0_REGD, 464 RK3288_LVDS_PLL_PREDIV_REGD(0x0a)); 465 lvds_writel(lvds, RK3288_LVDS_CH0_REG20, 466 RK3288_LVDS_CH0_REG20_LSB); 467 468 lvds_writel(lvds, RK3288_LVDS_CFG_REGC, RK3288_LVDS_CFG_REGC_PLL_ENABLE); 469 lvds_writel(lvds, RK3288_LVDS_CFG_REG21, RK3288_LVDS_CFG_REG21_TX_ENABLE); 470 } 471 472 static void rk3288_output_lvds(struct display_state *state) 473 { 474 struct connector_state *conn_state = &state->conn_state; 475 struct rockchip_lvds_device *lvds = conn_state->private; 476 477 rk3288_lvds_pwr_on(state); 478 479 lvds_writel(lvds, RK3288_LVDS_CH0_REG0, 480 RK3288_LVDS_CH0_REG0_LVDS_EN | 481 RK3288_LVDS_CH0_REG0_LANECK_EN | 482 RK3288_LVDS_CH0_REG0_LANE4_EN | 483 RK3288_LVDS_CH0_REG0_LANE3_EN | 484 RK3288_LVDS_CH0_REG0_LANE2_EN | 485 RK3288_LVDS_CH0_REG0_LANE1_EN | 486 RK3288_LVDS_CH0_REG0_LANE0_EN); 487 lvds_writel(lvds, RK3288_LVDS_CH0_REG1, 488 RK3288_LVDS_CH0_REG1_LANECK_BIAS | 489 RK3288_LVDS_CH0_REG1_LANE4_BIAS | 490 RK3288_LVDS_CH0_REG1_LANE3_BIAS | 491 RK3288_LVDS_CH0_REG1_LANE2_BIAS | 492 RK3288_LVDS_CH0_REG1_LANE1_BIAS | 493 RK3288_LVDS_CH0_REG1_LANE0_BIAS); 494 lvds_writel(lvds, RK3288_LVDS_CH0_REG2, 495 RK3288_LVDS_CH0_REG2_RESERVE_ON | 496 RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE | 497 RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE | 498 RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE | 499 RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE | 500 RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE | 501 RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE | 502 RK3288_LVDS_PLL_FBDIV_REG2(0x46)); 503 lvds_writel(lvds, RK3288_LVDS_CH0_REG3, 504 RK3288_LVDS_PLL_FBDIV_REG3(0x46)); 505 lvds_writel(lvds, RK3288_LVDS_CH0_REG4, 0x00); 506 lvds_writel(lvds, RK3288_LVDS_CH0_REG5, 0x00); 507 lvds_writel(lvds, RK3288_LVDS_CH0_REGD, 508 RK3288_LVDS_PLL_PREDIV_REGD(0x0a)); 509 lvds_writel(lvds, RK3288_LVDS_CH0_REG20, 510 RK3288_LVDS_CH0_REG20_LSB); 511 512 lvds_writel(lvds, RK3288_LVDS_CFG_REGC, RK3288_LVDS_CFG_REGC_PLL_ENABLE); 513 lvds_writel(lvds, RK3288_LVDS_CFG_REG21, RK3288_LVDS_CFG_REG21_TX_ENABLE); 514 } 515 516 static int rockchip_lvds_init(struct display_state *state) 517 { 518 struct connector_state *conn_state = &state->conn_state; 519 const struct rockchip_connector *connector = conn_state->connector; 520 const struct rockchip_lvds_chip_data *pdata = connector->data; 521 struct rockchip_lvds_device *lvds; 522 const char *name; 523 int i, width; 524 struct resource lvds_phy, lvds_ctrl; 525 struct panel_state *panel_state = &state->panel_state; 526 ofnode panel_node = panel_state->node; 527 int ret; 528 529 lvds = malloc(sizeof(*lvds)); 530 if (!lvds) 531 return -ENOMEM; 532 lvds->pdata = pdata; 533 534 if (pdata->chip_type == RK3288_LVDS) { 535 lvds->regbase = dev_read_addr_ptr(conn_state->dev); 536 } else { 537 i = dev_read_resource(conn_state->dev, 0, &lvds_phy); 538 if (i) { 539 printf("can't get regs lvds_phy addresses!\n"); 540 free(lvds); 541 return -ENOMEM; 542 } 543 544 i = dev_read_resource(conn_state->dev, 1, &lvds_ctrl); 545 if (i) { 546 printf("can't get regs lvds_ctrl addresses!\n"); 547 free(lvds); 548 return -ENOMEM; 549 } 550 551 lvds->regbase = (void *)lvds_phy.start; 552 lvds->ctrl_reg = (void *)lvds_ctrl.start; 553 } 554 555 lvds->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 556 if (lvds->grf <= 0) { 557 printf("%s: Get syscon grf failed (ret=%p)\n", 558 __func__, lvds->grf); 559 return -ENXIO; 560 } 561 562 ret = dev_read_string_index(panel_state->dev, "rockchip,output", 0, &name); 563 if (ret) 564 /* default set it as output rgb */ 565 lvds->output = DISPLAY_OUTPUT_RGB; 566 else 567 lvds->output = lvds_name_to_output(name); 568 if (lvds->output < 0) { 569 printf("invalid output type [%s]\n", name); 570 free(lvds); 571 return lvds->output; 572 } 573 ret = dev_read_string_index(panel_state->dev, "rockchip,data-mapping", 0, &name); 574 if (ret) 575 /* default set it as format jeida */ 576 lvds->format = LVDS_FORMAT_JEIDA; 577 else 578 lvds->format = lvds_name_to_format(name); 579 580 if (lvds->format < 0) { 581 printf("invalid data-mapping format [%s]\n", name); 582 free(lvds); 583 return lvds->format; 584 } 585 width = ofnode_read_u32_default(panel_node, "rockchip,data-width", 24); 586 if (width == 24) { 587 lvds->format |= LVDS_24BIT; 588 } else if (width == 18) { 589 lvds->format |= LVDS_18BIT; 590 } else { 591 printf("rockchip-lvds unsupport data-width[%d]\n", width); 592 free(lvds); 593 return -EINVAL; 594 } 595 596 printf("LVDS: data mapping: %s, data-width:%d, format:%d,\n", 597 name, width, lvds->format); 598 conn_state->private = lvds; 599 conn_state->type = DRM_MODE_CONNECTOR_LVDS; 600 601 if ((lvds->output == DISPLAY_OUTPUT_RGB) && (width == 18)) 602 conn_state->output_mode = ROCKCHIP_OUT_MODE_P666; 603 else 604 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 605 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 606 607 return 0; 608 } 609 610 static void rockchip_lvds_deinit(struct display_state *state) 611 { 612 struct connector_state *conn_state = &state->conn_state; 613 struct rockchip_lvds_device *lvds = conn_state->private; 614 615 free(lvds); 616 } 617 618 static int rockchip_lvds_prepare(struct display_state *state) 619 { 620 struct connector_state *conn_state = &state->conn_state; 621 struct rockchip_lvds_device *lvds = conn_state->private; 622 lvds->mode = &conn_state->mode; 623 624 rockchip_lvds_clk_enable(lvds); 625 626 return 0; 627 } 628 629 static void rockchip_lvds_vop_routing(struct rockchip_lvds_device *lvds, int pipe) 630 { 631 u32 val; 632 633 if (lvds->pdata->chip_type == RK3288_LVDS) { 634 if (pipe) 635 val = RK3288_LVDS_SOC_CON6_SEL_VOP_LIT | 636 (RK3288_LVDS_SOC_CON6_SEL_VOP_LIT << 16); 637 else 638 val = RK3288_LVDS_SOC_CON6_SEL_VOP_LIT << 16; 639 writel(val, lvds->grf + lvds->pdata->grf_soc_con6); 640 } else if (lvds->pdata->chip_type == PX30_LVDS) { 641 if (lvds->output == DISPLAY_OUTPUT_RGB) 642 writel(PX30_RGB_VOP_SEL(pipe), 643 lvds->grf + PX30_GRF_PD_VO_CON1); 644 else if (lvds->output == DISPLAY_OUTPUT_LVDS) 645 writel(PX30_LVDS_VOP_SEL(pipe), 646 lvds->grf + PX30_GRF_PD_VO_CON1); 647 } 648 } 649 650 static int rockchip_lvds_enable(struct display_state *state) 651 { 652 struct connector_state *conn_state = &state->conn_state; 653 struct rockchip_lvds_device *lvds = conn_state->private; 654 struct crtc_state *crtc_state = &state->crtc_state; 655 656 if (lvds->pdata->has_vop_sel) 657 rockchip_lvds_vop_routing(lvds, crtc_state->crtc_id); 658 659 if ((lvds->output == DISPLAY_OUTPUT_LVDS) || 660 (lvds->output == DISPLAY_OUTPUT_DUAL_LVDS)) { 661 if (lvds->pdata->chip_type == RK3288_LVDS) 662 rk3288_output_lvds(state); 663 else if (lvds->pdata->chip_type == RK3126_LVDS) 664 rk3126_output_lvds(state); 665 else if (lvds->pdata->chip_type == PX30_LVDS) 666 px30_output_lvds(state); 667 else 668 rk336x_output_lvds(state); 669 } else { 670 if (lvds->pdata->chip_type == RK3288_LVDS) 671 rk3288_output_ttl(state); 672 else if (lvds->pdata->chip_type == RK3126_LVDS) 673 rk3126_output_ttl(state); 674 else if (lvds->pdata->chip_type == PX30_LVDS) 675 px30_output_ttl(state); 676 else 677 rk336x_output_ttl(state); 678 } 679 680 return 0; 681 } 682 683 static int rockchip_lvds_disable(struct display_state *state) 684 { 685 struct connector_state *conn_state = &state->conn_state; 686 struct rockchip_lvds_device *lvds = conn_state->private; 687 688 if (lvds->pdata->chip_type == RK3288_LVDS) 689 rk3288_lvds_pwr_off(state); 690 else 691 rk336x_lvds_pwr_off(state); 692 693 return 0; 694 } 695 696 const struct rockchip_connector_funcs rockchip_lvds_funcs = { 697 .init = rockchip_lvds_init, 698 .deinit = rockchip_lvds_deinit, 699 .prepare = rockchip_lvds_prepare, 700 .enable = rockchip_lvds_enable, 701 .disable = rockchip_lvds_disable, 702 }; 703 704 static const struct rockchip_lvds_chip_data px30_lvds_drv_data = { 705 .chip_type = PX30_LVDS, 706 .has_vop_sel = true, 707 }; 708 709 static const struct rockchip_connector px30_lvds_data = { 710 .funcs = &rockchip_lvds_funcs, 711 .data = &px30_lvds_drv_data, 712 }; 713 714 static const struct rockchip_lvds_chip_data rk3126_lvds_drv_data = { 715 .chip_type = RK3126_LVDS, 716 .grf_soc_con7 = RK3126_GRF_LVDS_CON0, 717 .grf_soc_con15 = RK3126_GRF_CON1, 718 .has_vop_sel = true, 719 }; 720 721 static const struct rockchip_connector rk3126_lvds_data = { 722 .funcs = &rockchip_lvds_funcs, 723 .data = &rk3126_lvds_drv_data, 724 }; 725 726 static const struct rockchip_lvds_chip_data rk3288_lvds_drv_data = { 727 .chip_type = RK3288_LVDS, 728 .has_vop_sel = true, 729 .grf_soc_con6 = 0x025c, 730 .grf_soc_con7 = 0x0260, 731 .grf_gpio1d_iomux = 0x000c, 732 }; 733 734 static const struct rockchip_connector rk3288_lvds_data = { 735 .funcs = &rockchip_lvds_funcs, 736 .data = &rk3288_lvds_drv_data, 737 }; 738 739 static const struct rockchip_lvds_chip_data rk3368_lvds_drv_data = { 740 .chip_type = RK3368_LVDS, 741 .grf_soc_con7 = RK3368_GRF_SOC_CON7, 742 .grf_soc_con15 = RK3368_GRF_SOC_CON15, 743 .has_vop_sel = false, 744 }; 745 746 static const struct rockchip_connector rk3368_lvds_data = { 747 .funcs = &rockchip_lvds_funcs, 748 .data = &rk3368_lvds_drv_data, 749 }; 750 751 static const struct udevice_id rockchip_lvds_ids[] = { 752 { 753 .compatible = "rockchip,px30-lvds", 754 .data = (ulong)&px30_lvds_data, 755 }, 756 { 757 .compatible = "rockchip,rk3126-lvds", 758 .data = (ulong)&rk3126_lvds_data, 759 }, 760 { 761 .compatible = "rockchip,rk3288-lvds", 762 .data = (ulong)&rk3288_lvds_data, 763 }, 764 { 765 .compatible = "rockchip,rk3368-lvds", 766 .data = (ulong)&rk3368_lvds_data, 767 }, 768 {} 769 }; 770 771 U_BOOT_DRIVER(rockchip_lvds) = { 772 .name = "rockchip_lvds", 773 .id = UCLASS_DISPLAY, 774 .of_match = rockchip_lvds_ids, 775 }; 776