1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <boot_rkimg.h> 9 #include <asm/io.h> 10 #include <dm/device.h> 11 #include <linux/dw_hdmi.h> 12 #include <linux/hdmi.h> 13 #include <linux/media-bus-format.h> 14 #include "rockchip_display.h" 15 #include "rockchip_crtc.h" 16 #include "rockchip_connector.h" 17 #include "dw_hdmi.h" 18 #include "rockchip_dw_hdmi.h" 19 20 #define HDMI_SEL_LCDC(x, bit) ((((x) & 1) << bit) | (1 << (16 + bit))) 21 #define RK3288_GRF_SOC_CON6 0x025C 22 #define RK3288_HDMI_LCDC_SEL BIT(4) 23 #define RK3399_GRF_SOC_CON20 0x6250 24 #define RK3399_HDMI_LCDC_SEL BIT(6) 25 26 #define RK3228_IO_3V_DOMAIN ((7 << 4) | (7 << (4 + 16))) 27 #define RK3328_IO_3V_DOMAIN (7 << (9 + 16)) 28 #define RK3328_IO_5V_DOMAIN ((7 << 9) | (3 << (9 + 16))) 29 #define RK3328_IO_CTRL_BY_HDMI ((1 << 13) | (1 << (13 + 16))) 30 #define RK3328_IO_DDC_IN_MSK ((3 << 10) | (3 << (10 + 16))) 31 #define RK3228_IO_DDC_IN_MSK ((3 << 13) | (3 << (13 + 16))) 32 #define RK3228_GRF_SOC_CON2 0x0408 33 #define RK3228_GRF_SOC_CON6 0x0418 34 #define RK3328_GRF_SOC_CON2 0x0408 35 #define RK3328_GRF_SOC_CON3 0x040c 36 #define RK3328_GRF_SOC_CON4 0x0410 37 38 #define RK3568_GRF_VO_CON1 0x0364 39 #define RK3568_HDMI_SDAIN_MSK ((1 << 15) | (1 << (15 + 16))) 40 #define RK3568_HDMI_SCLIN_MSK ((1 << 14) | (1 << (14 + 16))) 41 42 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { 43 { 44 30666000, { 45 { 0x00b3, 0x0000 }, 46 { 0x2153, 0x0000 }, 47 { 0x40f3, 0x0000 }, 48 }, 49 }, { 50 36800000, { 51 { 0x00b3, 0x0000 }, 52 { 0x2153, 0x0000 }, 53 { 0x40a2, 0x0001 }, 54 }, 55 }, { 56 46000000, { 57 { 0x00b3, 0x0000 }, 58 { 0x2142, 0x0001 }, 59 { 0x40a2, 0x0001 }, 60 }, 61 }, { 62 61333000, { 63 { 0x0072, 0x0001 }, 64 { 0x2142, 0x0001 }, 65 { 0x40a2, 0x0001 }, 66 }, 67 }, { 68 73600000, { 69 { 0x0072, 0x0001 }, 70 { 0x2142, 0x0001 }, 71 { 0x4061, 0x0002 }, 72 }, 73 }, { 74 92000000, { 75 { 0x0072, 0x0001 }, 76 { 0x2145, 0x0002 }, 77 { 0x4061, 0x0002 }, 78 }, 79 }, { 80 122666000, { 81 { 0x0051, 0x0002 }, 82 { 0x2145, 0x0002 }, 83 { 0x4061, 0x0002 }, 84 }, 85 }, { 86 147200000, { 87 { 0x0051, 0x0002 }, 88 { 0x2145, 0x0002 }, 89 { 0x4064, 0x0003 }, 90 }, 91 }, { 92 184000000, { 93 { 0x0051, 0x0002 }, 94 { 0x214c, 0x0003 }, 95 { 0x4064, 0x0003 }, 96 }, 97 }, { 98 226666000, { 99 { 0x0040, 0x0003 }, 100 { 0x214c, 0x0003 }, 101 { 0x4064, 0x0003 }, 102 }, 103 }, { 104 272000000, { 105 { 0x0040, 0x0003 }, 106 { 0x214c, 0x0003 }, 107 { 0x5a64, 0x0003 }, 108 }, 109 }, { 110 340000000, { 111 { 0x0040, 0x0003 }, 112 { 0x3b4c, 0x0003 }, 113 { 0x5a64, 0x0003 }, 114 }, 115 }, { 116 600000000, { 117 { 0x1a40, 0x0003 }, 118 { 0x3b4c, 0x0003 }, 119 { 0x5a64, 0x0003 }, 120 }, 121 }, { 122 ~0UL, { 123 { 0x0000, 0x0000 }, 124 { 0x0000, 0x0000 }, 125 { 0x0000, 0x0000 }, 126 }, 127 } 128 }; 129 130 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg_420[] = { 131 { 132 30666000, { 133 { 0x00b7, 0x0000 }, 134 { 0x2157, 0x0000 }, 135 { 0x40f7, 0x0000 }, 136 }, 137 }, { 138 92000000, { 139 { 0x00b7, 0x0000 }, 140 { 0x2143, 0x0001 }, 141 { 0x40a3, 0x0001 }, 142 }, 143 }, { 144 184000000, { 145 { 0x0073, 0x0001 }, 146 { 0x2146, 0x0002 }, 147 { 0x4062, 0x0002 }, 148 }, 149 }, { 150 340000000, { 151 { 0x0052, 0x0003 }, 152 { 0x214d, 0x0003 }, 153 { 0x4065, 0x0003 }, 154 }, 155 }, { 156 600000000, { 157 { 0x0041, 0x0003 }, 158 { 0x3b4d, 0x0003 }, 159 { 0x5a65, 0x0003 }, 160 }, 161 }, { 162 ~0UL, { 163 { 0x0000, 0x0000 }, 164 { 0x0000, 0x0000 }, 165 { 0x0000, 0x0000 }, 166 }, 167 } 168 }; 169 170 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { 171 /* pixelclk bpp8 bpp10 bpp12 */ 172 { 173 600000000, { 0x0000, 0x0000, 0x0000 }, 174 }, { 175 ~0UL, { 0x0000, 0x0000, 0x0000}, 176 } 177 }; 178 179 static const struct dw_hdmi_phy_config rockchip_phy_config[] = { 180 /*pixelclk symbol term vlev*/ 181 { 74250000, 0x8009, 0x0004, 0x0272}, 182 { 165000000, 0x802b, 0x0004, 0x0209}, 183 { 297000000, 0x8039, 0x0005, 0x028d}, 184 { 594000000, 0x8039, 0x0000, 0x019d}, 185 { ~0UL, 0x0000, 0x0000, 0x0000}, 186 { ~0UL, 0x0000, 0x0000, 0x0000} 187 }; 188 189 static unsigned int drm_rk_select_color(struct hdmi_edid_data *edid_data, 190 struct base_screen_info *screen_info, 191 enum dw_hdmi_devtype dev_type, 192 bool output_bus_format_rgb) 193 { 194 struct drm_display_info *info = &edid_data->display_info; 195 struct drm_display_mode *mode = edid_data->preferred_mode; 196 int max_tmds_clock = info->max_tmds_clock; 197 bool support_dc = false; 198 bool mode_420 = drm_mode_is_420(info, mode); 199 unsigned int color_depth = 8; 200 unsigned int base_color = DRM_HDMI_OUTPUT_YCBCR444; 201 unsigned int color_format = DRM_HDMI_OUTPUT_DEFAULT_RGB; 202 unsigned long tmdsclock, pixclock = mode->clock; 203 204 if (screen_info) 205 base_color = screen_info->format; 206 207 switch (base_color) { 208 case DRM_HDMI_OUTPUT_YCBCR_HQ: 209 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) 210 color_format = DRM_HDMI_OUTPUT_YCBCR444; 211 else if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) 212 color_format = DRM_HDMI_OUTPUT_YCBCR422; 213 else if (mode_420) 214 color_format = DRM_HDMI_OUTPUT_YCBCR420; 215 break; 216 case DRM_HDMI_OUTPUT_YCBCR_LQ: 217 if (mode_420) 218 color_format = DRM_HDMI_OUTPUT_YCBCR420; 219 else if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) 220 color_format = DRM_HDMI_OUTPUT_YCBCR422; 221 else if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) 222 color_format = DRM_HDMI_OUTPUT_YCBCR444; 223 break; 224 case DRM_HDMI_OUTPUT_YCBCR420: 225 if (mode_420) 226 color_format = DRM_HDMI_OUTPUT_YCBCR420; 227 break; 228 case DRM_HDMI_OUTPUT_YCBCR422: 229 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) 230 color_format = DRM_HDMI_OUTPUT_YCBCR422; 231 break; 232 case DRM_HDMI_OUTPUT_YCBCR444: 233 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) 234 color_format = DRM_HDMI_OUTPUT_YCBCR444; 235 break; 236 case DRM_HDMI_OUTPUT_DEFAULT_RGB: 237 default: 238 break; 239 } 240 241 if (output_bus_format_rgb) 242 color_format = DRM_HDMI_OUTPUT_DEFAULT_RGB; 243 244 if (color_format == DRM_HDMI_OUTPUT_DEFAULT_RGB && 245 info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) 246 support_dc = true; 247 if (color_format == DRM_HDMI_OUTPUT_YCBCR444 && 248 (info->edid_hdmi_dc_modes & 249 (DRM_EDID_HDMI_DC_Y444 | DRM_EDID_HDMI_DC_30))) 250 support_dc = true; 251 if (color_format == DRM_HDMI_OUTPUT_YCBCR422) 252 support_dc = true; 253 if (color_format == DRM_HDMI_OUTPUT_YCBCR420 && 254 info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) 255 support_dc = true; 256 257 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 258 pixclock *= 2; 259 260 if (screen_info && screen_info->depth == 10) 261 color_depth = screen_info->depth; 262 263 if (color_format == DRM_HDMI_OUTPUT_YCBCR422 || color_depth == 8) 264 tmdsclock = pixclock; 265 else 266 tmdsclock = pixclock * color_depth / 8; 267 268 if (color_format == DRM_HDMI_OUTPUT_YCBCR420) 269 tmdsclock /= 2; 270 271 if (!max_tmds_clock) 272 max_tmds_clock = 340000; 273 274 switch (dev_type) { 275 case RK3368_HDMI: 276 max_tmds_clock = min(max_tmds_clock, 340000); 277 break; 278 case RK3328_HDMI: 279 case RK3228_HDMI: 280 max_tmds_clock = min(max_tmds_clock, 371250); 281 break; 282 default: 283 max_tmds_clock = min(max_tmds_clock, 594000); 284 break; 285 } 286 287 if (tmdsclock > max_tmds_clock) { 288 if (max_tmds_clock >= 594000) { 289 color_depth = 8; 290 } else if (max_tmds_clock > 340000) { 291 if (drm_mode_is_420(info, mode)) 292 color_format = DRM_HDMI_OUTPUT_YCBCR420; 293 } else { 294 color_depth = 8; 295 if (drm_mode_is_420(info, mode)) 296 color_format = DRM_HDMI_OUTPUT_YCBCR420; 297 } 298 } 299 300 if (color_depth > 8 && support_dc) { 301 if (dev_type == RK3288_HDMI) 302 return MEDIA_BUS_FMT_RGB101010_1X30; 303 switch (color_format) { 304 case DRM_HDMI_OUTPUT_YCBCR444: 305 return MEDIA_BUS_FMT_YUV10_1X30; 306 case DRM_HDMI_OUTPUT_YCBCR422: 307 return MEDIA_BUS_FMT_UYVY10_1X20; 308 case DRM_HDMI_OUTPUT_YCBCR420: 309 return MEDIA_BUS_FMT_UYYVYY10_0_5X30; 310 default: 311 return MEDIA_BUS_FMT_RGB101010_1X30; 312 } 313 } else { 314 if (dev_type == RK3288_HDMI) 315 return MEDIA_BUS_FMT_RGB888_1X24; 316 switch (color_format) { 317 case DRM_HDMI_OUTPUT_YCBCR444: 318 return MEDIA_BUS_FMT_YUV8_1X24; 319 case DRM_HDMI_OUTPUT_YCBCR422: 320 return MEDIA_BUS_FMT_UYVY8_1X16; 321 case DRM_HDMI_OUTPUT_YCBCR420: 322 return MEDIA_BUS_FMT_UYYVYY8_0_5X24; 323 default: 324 return MEDIA_BUS_FMT_RGB888_1X24; 325 } 326 } 327 } 328 329 void drm_rk_selete_output(struct hdmi_edid_data *edid_data, 330 struct connector_state *conn_state, 331 unsigned int *bus_format, 332 struct overscan *overscan, 333 enum dw_hdmi_devtype dev_type, 334 bool output_bus_format_rgb) 335 { 336 int ret, i, screen_size; 337 struct base_disp_info base_parameter; 338 struct base2_disp_info *base2_parameter = conn_state->disp_info; 339 const struct base_overscan *scan; 340 struct base_screen_info *screen_info = NULL; 341 struct base2_screen_info *screen_info2 = NULL; 342 int max_scan = 100; 343 int min_scan = 51; 344 int offset = 0; 345 bool found = false; 346 struct blk_desc *dev_desc; 347 disk_partition_t part_info; 348 char baseparameter_buf[8 * RK_BLK_SIZE] __aligned(ARCH_DMA_MINALIGN); 349 350 overscan->left_margin = max_scan; 351 overscan->right_margin = max_scan; 352 overscan->top_margin = max_scan; 353 overscan->bottom_margin = max_scan; 354 355 if (dev_type == RK3288_HDMI || output_bus_format_rgb) 356 *bus_format = MEDIA_BUS_FMT_RGB888_1X24; 357 else 358 *bus_format = MEDIA_BUS_FMT_YUV8_1X24; 359 360 if (!base2_parameter) { 361 dev_desc = rockchip_get_bootdev(); 362 if (!dev_desc) { 363 printf("%s: Could not find device\n", __func__); 364 goto null_basep; 365 } 366 367 ret = part_get_info_by_name(dev_desc, "baseparameter", 368 &part_info); 369 if (ret < 0) { 370 printf("Could not find baseparameter partition\n"); 371 goto null_basep; 372 } 373 374 read_aux: 375 ret = blk_dread(dev_desc, part_info.start + offset, 1, 376 (void *)baseparameter_buf); 377 if (ret < 0) { 378 printf("read baseparameter failed\n"); 379 goto null_basep; 380 } 381 382 memcpy(&base_parameter, baseparameter_buf, 383 sizeof(base_parameter)); 384 scan = &base_parameter.scan; 385 386 screen_size = sizeof(base_parameter.screen_list) / 387 sizeof(base_parameter.screen_list[0]); 388 389 for (i = 0; i < screen_size; i++) { 390 if (base_parameter.screen_list[i].type == 391 DRM_MODE_CONNECTOR_HDMIA) { 392 found = true; 393 screen_info = &base_parameter.screen_list[i]; 394 break; 395 } 396 } 397 398 if (!found && !offset) { 399 printf("hdmi info isn't saved in main block\n"); 400 offset += 16; 401 goto read_aux; 402 } 403 } else { 404 scan = &base2_parameter->overscan_info; 405 screen_size = sizeof(base2_parameter->screen_info) / 406 sizeof(base2_parameter->screen_info[0]); 407 408 for (i = 0; i < screen_size; i++) { 409 if (base2_parameter->screen_info[i].type == 410 DRM_MODE_CONNECTOR_HDMIA) { 411 screen_info2 = 412 &base2_parameter->screen_info[i]; 413 break; 414 } 415 } 416 screen_info = malloc(sizeof(*screen_info)); 417 418 screen_info->type = screen_info2->type; 419 screen_info->mode = screen_info2->resolution; 420 screen_info->format = screen_info2->format; 421 screen_info->depth = screen_info2->depthc; 422 screen_info->feature = screen_info2->feature; 423 } 424 425 if (scan->leftscale < min_scan && scan->leftscale > 0) 426 overscan->left_margin = min_scan; 427 else if (scan->leftscale < max_scan && scan->leftscale > 0) 428 overscan->left_margin = scan->leftscale; 429 430 if (scan->rightscale < min_scan && scan->rightscale > 0) 431 overscan->right_margin = min_scan; 432 else if (scan->rightscale < max_scan && scan->rightscale > 0) 433 overscan->right_margin = scan->rightscale; 434 435 if (scan->topscale < min_scan && scan->topscale > 0) 436 overscan->top_margin = min_scan; 437 else if (scan->topscale < max_scan && scan->topscale > 0) 438 overscan->top_margin = scan->topscale; 439 440 if (scan->bottomscale < min_scan && scan->bottomscale > 0) 441 overscan->bottom_margin = min_scan; 442 else if (scan->bottomscale < max_scan && scan->bottomscale > 0) 443 overscan->bottom_margin = scan->bottomscale; 444 445 null_basep: 446 447 if (screen_info) 448 printf("base_parameter.mode:%dx%d\n", 449 screen_info->mode.hdisplay, 450 screen_info->mode.vdisplay); 451 drm_rk_select_mode(edid_data, screen_info); 452 453 *bus_format = drm_rk_select_color(edid_data, screen_info, 454 dev_type, output_bus_format_rgb); 455 } 456 457 void inno_dw_hdmi_set_domain(void *grf, int status) 458 { 459 if (status) 460 writel(RK3328_IO_5V_DOMAIN, grf + RK3328_GRF_SOC_CON4); 461 else 462 writel(RK3328_IO_3V_DOMAIN, grf + RK3328_GRF_SOC_CON4); 463 } 464 465 void dw_hdmi_set_iomux(void *grf, int dev_type) 466 { 467 switch (dev_type) { 468 case RK3328_HDMI: 469 writel(RK3328_IO_DDC_IN_MSK, grf + RK3328_GRF_SOC_CON2); 470 writel(RK3328_IO_CTRL_BY_HDMI, grf + RK3328_GRF_SOC_CON3); 471 break; 472 case RK3228_HDMI: 473 writel(RK3228_IO_3V_DOMAIN, grf + RK3228_GRF_SOC_CON6); 474 writel(RK3228_IO_DDC_IN_MSK, grf + RK3228_GRF_SOC_CON2); 475 break; 476 case RK3568_HDMI: 477 writel(RK3568_HDMI_SDAIN_MSK | RK3568_HDMI_SCLIN_MSK, 478 grf + RK3568_GRF_VO_CON1); 479 break; 480 default: 481 break; 482 } 483 } 484 485 static const struct dw_hdmi_phy_ops inno_dw_hdmi_phy_ops = { 486 .init = inno_dw_hdmi_phy_init, 487 .disable = inno_dw_hdmi_phy_disable, 488 .read_hpd = inno_dw_hdmi_phy_read_hpd, 489 .mode_valid = inno_dw_hdmi_mode_valid, 490 }; 491 492 static const struct rockchip_connector_funcs rockchip_dw_hdmi_funcs = { 493 .pre_init = rockchip_dw_hdmi_pre_init, 494 .init = rockchip_dw_hdmi_init, 495 .deinit = rockchip_dw_hdmi_deinit, 496 .prepare = rockchip_dw_hdmi_prepare, 497 .enable = rockchip_dw_hdmi_enable, 498 .disable = rockchip_dw_hdmi_disable, 499 .get_timing = rockchip_dw_hdmi_get_timing, 500 .detect = rockchip_dw_hdmi_detect, 501 .get_edid = rockchip_dw_hdmi_get_edid, 502 }; 503 504 const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = { 505 .vop_sel_bit = 4, 506 .grf_vop_sel_reg = RK3288_GRF_SOC_CON6, 507 .mpll_cfg = rockchip_mpll_cfg, 508 .cur_ctr = rockchip_cur_ctr, 509 .phy_config = rockchip_phy_config, 510 .dev_type = RK3288_HDMI, 511 }; 512 513 const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { 514 .vop_sel_bit = 0, 515 .grf_vop_sel_reg = 0, 516 .phy_ops = &inno_dw_hdmi_phy_ops, 517 .phy_name = "inno_dw_hdmi_phy2", 518 .dev_type = RK3328_HDMI, 519 }; 520 521 const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { 522 .vop_sel_bit = 0, 523 .grf_vop_sel_reg = 0, 524 .phy_ops = &inno_dw_hdmi_phy_ops, 525 .phy_name = "inno_dw_hdmi_phy", 526 .dev_type = RK3228_HDMI, 527 }; 528 529 const struct dw_hdmi_plat_data rk3368_hdmi_drv_data = { 530 .mpll_cfg = rockchip_mpll_cfg, 531 .cur_ctr = rockchip_cur_ctr, 532 .phy_config = rockchip_phy_config, 533 .mpll_cfg_420 = rockchip_mpll_cfg_420, 534 .dev_type = RK3368_HDMI, 535 }; 536 537 const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { 538 .vop_sel_bit = 6, 539 .grf_vop_sel_reg = RK3399_GRF_SOC_CON20, 540 .mpll_cfg = rockchip_mpll_cfg, 541 .cur_ctr = rockchip_cur_ctr, 542 .phy_config = rockchip_phy_config, 543 .mpll_cfg_420 = rockchip_mpll_cfg_420, 544 .dev_type = RK3399_HDMI, 545 }; 546 547 const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = { 548 .vop_sel_bit = 0, 549 .grf_vop_sel_reg = 0, 550 .mpll_cfg = rockchip_mpll_cfg, 551 .cur_ctr = rockchip_cur_ctr, 552 .phy_config = rockchip_phy_config, 553 .mpll_cfg_420 = rockchip_mpll_cfg_420, 554 .dev_type = RK3568_HDMI, 555 }; 556 557 static int rockchip_dw_hdmi_probe(struct udevice *dev) 558 { 559 return 0; 560 } 561 562 static const struct rockchip_connector rk3568_dw_hdmi_data = { 563 .funcs = &rockchip_dw_hdmi_funcs, 564 .data = &rk3568_hdmi_drv_data, 565 }; 566 567 static const struct rockchip_connector rk3399_dw_hdmi_data = { 568 .funcs = &rockchip_dw_hdmi_funcs, 569 .data = &rk3399_hdmi_drv_data, 570 }; 571 572 static const struct rockchip_connector rk3368_dw_hdmi_data = { 573 .funcs = &rockchip_dw_hdmi_funcs, 574 .data = &rk3368_hdmi_drv_data, 575 }; 576 577 static const struct rockchip_connector rk3288_dw_hdmi_data = { 578 .funcs = &rockchip_dw_hdmi_funcs, 579 .data = &rk3288_hdmi_drv_data, 580 }; 581 582 static const struct rockchip_connector rk3328_dw_hdmi_data = { 583 .funcs = &rockchip_dw_hdmi_funcs, 584 .data = &rk3328_hdmi_drv_data, 585 }; 586 587 static const struct rockchip_connector rk3228_dw_hdmi_data = { 588 .funcs = &rockchip_dw_hdmi_funcs, 589 .data = &rk3228_hdmi_drv_data, 590 }; 591 592 static const struct udevice_id rockchip_dw_hdmi_ids[] = { 593 { 594 .compatible = "rockchip,rk3568-dw-hdmi", 595 .data = (ulong)&rk3568_dw_hdmi_data, 596 }, { 597 .compatible = "rockchip,rk3399-dw-hdmi", 598 .data = (ulong)&rk3399_dw_hdmi_data, 599 }, { 600 .compatible = "rockchip,rk3368-dw-hdmi", 601 .data = (ulong)&rk3368_dw_hdmi_data, 602 }, { 603 .compatible = "rockchip,rk3288-dw-hdmi", 604 .data = (ulong)&rk3288_dw_hdmi_data, 605 }, { 606 .compatible = "rockchip,rk3328-dw-hdmi", 607 .data = (ulong)&rk3328_dw_hdmi_data, 608 }, { 609 .compatible = "rockchip,rk3128-inno-hdmi", 610 .data = (ulong)&rk3228_dw_hdmi_data, 611 }, { 612 .compatible = "rockchip,rk3228-dw-hdmi", 613 .data = (ulong)&rk3228_dw_hdmi_data, 614 }, {} 615 }; 616 617 U_BOOT_DRIVER(rockchip_dw_hdmi) = { 618 .name = "rockchip_dw_hdmi", 619 .id = UCLASS_DISPLAY, 620 .of_match = rockchip_dw_hdmi_ids, 621 .probe = rockchip_dw_hdmi_probe, 622 }; 623