xref: /rk3399_rockchip-uboot/drivers/video/drm/rockchip_dw_hdmi.c (revision 5ec685037a799ecdc53ecb1a12a9ed5a9cecb4f4) 
1 /*
2  * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <dm/device.h>
9 #include <linux/dw_hdmi.h>
10 #include "rockchip_display.h"
11 #include "rockchip_crtc.h"
12 #include "rockchip_connector.h"
13 #include "dw_hdmi.h"
14 #include "rockchip_dw_hdmi.h"
15 
16 #define HDMI_SEL_LCDC(x, bit)  ((((x) & 1) << bit) | (1 << (16 + bit)))
17 #define RK3288_GRF_SOC_CON6		0x025C
18 #define RK3288_HDMI_LCDC_SEL		BIT(4)
19 #define RK3399_GRF_SOC_CON20		0x6250
20 #define RK3399_HDMI_LCDC_SEL		BIT(6)
21 
22 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
23 	{
24 		30666000, {
25 			{ 0x00b3, 0x0000 },
26 			{ 0x2153, 0x0000 },
27 			{ 0x40f3, 0x0000 },
28 		},
29 	},  {
30 		36800000, {
31 			{ 0x00b3, 0x0000 },
32 			{ 0x2153, 0x0000 },
33 			{ 0x40a2, 0x0001 },
34 		},
35 	},  {
36 		46000000, {
37 			{ 0x00b3, 0x0000 },
38 			{ 0x2142, 0x0001 },
39 			{ 0x40a2, 0x0001 },
40 		},
41 	},  {
42 		61333000, {
43 			{ 0x0072, 0x0001 },
44 			{ 0x2142, 0x0001 },
45 			{ 0x40a2, 0x0001 },
46 		},
47 	},  {
48 		73600000, {
49 			{ 0x0072, 0x0001 },
50 			{ 0x2142, 0x0001 },
51 			{ 0x4061, 0x0002 },
52 		},
53 	},  {
54 		92000000, {
55 			{ 0x0072, 0x0001 },
56 			{ 0x2145, 0x0002 },
57 			{ 0x4061, 0x0002 },
58 		},
59 	},  {
60 		122666000, {
61 			{ 0x0051, 0x0002 },
62 			{ 0x2145, 0x0002 },
63 			{ 0x4061, 0x0002 },
64 		},
65 	},  {
66 		147200000, {
67 			{ 0x0051, 0x0002 },
68 			{ 0x2145, 0x0002 },
69 			{ 0x4064, 0x0003 },
70 		},
71 	},  {
72 		184000000, {
73 			{ 0x0051, 0x0002 },
74 			{ 0x214c, 0x0003 },
75 			{ 0x4064, 0x0003 },
76 		},
77 	},  {
78 		226666000, {
79 			{ 0x0040, 0x0003 },
80 			{ 0x214c, 0x0003 },
81 			{ 0x4064, 0x0003 },
82 		},
83 	},  {
84 		272000000, {
85 			{ 0x0040, 0x0003 },
86 			{ 0x214c, 0x0003 },
87 			{ 0x5a64, 0x0003 },
88 		},
89 	},  {
90 		340000000, {
91 			{ 0x0040, 0x0003 },
92 			{ 0x3b4c, 0x0003 },
93 			{ 0x5a64, 0x0003 },
94 		},
95 	},  {
96 		600000000, {
97 			{ 0x1a40, 0x0003 },
98 			{ 0x3b4c, 0x0003 },
99 			{ 0x5a64, 0x0003 },
100 		},
101 	},  {
102 		~0UL, {
103 			{ 0x0000, 0x0000 },
104 			{ 0x0000, 0x0000 },
105 			{ 0x0000, 0x0000 },
106 		},
107 	}
108 };
109 
110 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
111 	/*      pixelclk    bpp8    bpp10   bpp12 */
112 	{
113 		600000000, { 0x0000, 0x0000, 0x0000 },
114 	},  {
115 		~0UL,      { 0x0000, 0x0000, 0x0000},
116 	}
117 };
118 
119 static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
120 	/*pixelclk   symbol   term   vlev*/
121 	{ 74250000,  0x8009, 0x0004, 0x0272},
122 	{ 165000000, 0x802b, 0x0004, 0x0209},
123 	{ 297000000, 0x8039, 0x0005, 0x028d},
124 	{ 594000000, 0x8039, 0x0000, 0x019d},
125 	{ ~0UL,	     0x0000, 0x0000, 0x0000}
126 };
127 
128 static const struct rockchip_connector_funcs rockchip_dw_hdmi_funcs = {
129 	.init = rockchip_dw_hdmi_init,
130 	.deinit = rockchip_dw_hdmi_deinit,
131 	.prepare = rockchip_dw_hdmi_prepare,
132 	.enable = rockchip_dw_hdmi_enable,
133 	.disable = rockchip_dw_hdmi_disable,
134 	.get_timing = rockchip_dw_hdmi_get_timing,
135 	.detect = rockchip_dw_hdmi_detect,
136 	.get_edid = rockchip_dw_hdmi_get_edid,
137 };
138 
139 static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
140 	.vop_sel_bit = 4,
141 	.grf_vop_sel_reg = RK3288_GRF_SOC_CON6,
142 	.dev_type   = RK3288_HDMI,
143 };
144 
145 static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
146 	.vop_sel_bit = 6,
147 	.grf_vop_sel_reg = RK3399_GRF_SOC_CON20,
148 	.mpll_cfg   = rockchip_mpll_cfg,
149 	.cur_ctr    = rockchip_cur_ctr,
150 	.phy_config = rockchip_phy_config,
151 	.dev_type   = RK3399_HDMI,
152 };
153 
154 static const struct rockchip_connector rk3399_dw_hdmi_data = {
155 	.funcs = &rockchip_dw_hdmi_funcs,
156 	.data = &rk3399_hdmi_drv_data,
157 };
158 
159 static const struct rockchip_connector rk3288_dw_hdmi_data = {
160 	.funcs = &rockchip_dw_hdmi_funcs,
161 	.data = &rk3288_hdmi_drv_data,
162 };
163 
164 static int rockchip_dw_hdmi_probe(struct udevice *dev)
165 {
166 	return 0;
167 }
168 
169 static const struct udevice_id rockchip_dw_hdmi_ids[] = {
170 	{
171 	 .compatible = "rockchip,rk3399-dw-hdmi",
172 	 .data = (ulong)&rk3399_dw_hdmi_data,
173 	}, {
174 	 .compatible = "rockchip,rk3288-dw-hdmi",
175 	 .data = (ulong)&rk3288_dw_hdmi_data,
176 	}, {}
177 };
178 
179 U_BOOT_DRIVER(rockchip_dw_hdmi) = {
180 	.name = "rockchip_dw_hdmi",
181 	.id = UCLASS_DISPLAY,
182 	.of_match = rockchip_dw_hdmi_ids,
183 	.probe	= rockchip_dw_hdmi_probe,
184 };
185