1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ROCKCHIP_DISPLAY_H 8 #define _ROCKCHIP_DISPLAY_H 9 10 #include <bmp_layout.h> 11 #include <drm_modes.h> 12 #include <edid.h> 13 #include <dm/ofnode.h> 14 15 /* 16 * major: IP major vertion, used for IP structure 17 * minor: big feature change under same structure 18 */ 19 #define VOP_VERSION(major, minor) ((major) << 8 | (minor)) 20 #define VOP_MAJOR(version) ((version) >> 8) 21 #define VOP_MINOR(version) ((version) & 0xff) 22 23 #define VOP_VERSION_RK3568 VOP_VERSION(0x40, 0x15) 24 #define VOP_VERSION_RK3588 VOP_VERSION(0x40, 0x17) 25 26 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0) 27 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1) 28 #define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2) 29 #define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3) 30 31 #define ROCKCHIP_DSC_PPS_SIZE_BYTE 88 32 33 enum data_format { 34 ROCKCHIP_FMT_ARGB8888 = 0, 35 ROCKCHIP_FMT_RGB888, 36 ROCKCHIP_FMT_RGB565, 37 ROCKCHIP_FMT_YUV420SP = 4, 38 ROCKCHIP_FMT_YUV422SP, 39 ROCKCHIP_FMT_YUV444SP, 40 }; 41 42 enum display_mode { 43 ROCKCHIP_DISPLAY_FULLSCREEN, 44 ROCKCHIP_DISPLAY_CENTER, 45 }; 46 47 enum rockchip_cmd_type { 48 CMD_TYPE_DEFAULT, 49 CMD_TYPE_SPI, 50 CMD_TYPE_MCU 51 }; 52 53 enum rockchip_mcu_cmd { 54 MCU_WRCMD = 0, 55 MCU_WRDATA, 56 MCU_SETBYPASS, 57 }; 58 59 /* 60 * display output interface supported by rockchip lcdc 61 */ 62 #define ROCKCHIP_OUT_MODE_P888 0 63 #define ROCKCHIP_OUT_MODE_BT1120 0 64 #define ROCKCHIP_OUT_MODE_P666 1 65 #define ROCKCHIP_OUT_MODE_P565 2 66 #define ROCKCHIP_OUT_MODE_BT656 5 67 #define ROCKCHIP_OUT_MODE_S888 8 68 #define ROCKCHIP_OUT_MODE_S888_DUMMY 12 69 #define ROCKCHIP_OUT_MODE_YUV420 14 70 /* for use special outface */ 71 #define ROCKCHIP_OUT_MODE_AAAA 15 72 73 #define VOP_OUTPUT_IF_RGB BIT(0) 74 #define VOP_OUTPUT_IF_BT1120 BIT(1) 75 #define VOP_OUTPUT_IF_BT656 BIT(2) 76 #define VOP_OUTPUT_IF_LVDS0 BIT(3) 77 #define VOP_OUTPUT_IF_LVDS1 BIT(4) 78 #define VOP_OUTPUT_IF_MIPI0 BIT(5) 79 #define VOP_OUTPUT_IF_MIPI1 BIT(6) 80 #define VOP_OUTPUT_IF_eDP0 BIT(7) 81 #define VOP_OUTPUT_IF_eDP1 BIT(8) 82 #define VOP_OUTPUT_IF_DP0 BIT(9) 83 #define VOP_OUTPUT_IF_DP1 BIT(10) 84 #define VOP_OUTPUT_IF_HDMI0 BIT(11) 85 #define VOP_OUTPUT_IF_HDMI1 BIT(12) 86 87 struct rockchip_mcu_timing { 88 int mcu_pix_total; 89 int mcu_cs_pst; 90 int mcu_cs_pend; 91 int mcu_rw_pst; 92 int mcu_rw_pend; 93 int mcu_hold_mode; 94 }; 95 96 struct vop_rect { 97 int width; 98 int height; 99 }; 100 101 struct rockchip_dsc_sink_cap { 102 /** 103 * @slice_width: the number of pixel columns that comprise the slice width 104 * @slice_height: the number of pixel rows that comprise the slice height 105 * @block_pred: Does block prediction 106 * @native_420: Does sink support DSC with 4:2:0 compression 107 * @bpc_supported: compressed bpc supported by sink : 10, 12 or 16 bpc 108 * @version_major: DSC major version 109 * @version_minor: DSC minor version 110 * @target_bits_per_pixel_x16: bits num after compress and multiply 16 111 */ 112 u16 slice_width; 113 u16 slice_height; 114 bool block_pred; 115 bool native_420; 116 u8 bpc_supported; 117 u8 version_major; 118 u8 version_minor; 119 u16 target_bits_per_pixel_x16; 120 }; 121 122 struct crtc_state { 123 struct udevice *dev; 124 struct rockchip_crtc *crtc; 125 void *private; 126 ofnode node; 127 struct device_node *ports_node; /* if (ports_node) it's vop2; */ 128 int crtc_id; 129 130 int format; 131 u32 dma_addr; 132 int ymirror; 133 int rb_swap; 134 int xvir; 135 int src_x; 136 int src_y; 137 int src_w; 138 int src_h; 139 int crtc_x; 140 int crtc_y; 141 int crtc_w; 142 int crtc_h; 143 bool yuv_overlay; 144 struct rockchip_mcu_timing mcu_timing; 145 u32 dual_channel_swap; 146 u32 feature; 147 struct vop_rect max_output; 148 }; 149 150 struct panel_state { 151 struct rockchip_panel *panel; 152 153 ofnode dsp_lut_node; 154 }; 155 156 struct overscan { 157 int left_margin; 158 int right_margin; 159 int top_margin; 160 int bottom_margin; 161 }; 162 163 struct connector_state { 164 struct udevice *dev; 165 const struct rockchip_connector *connector; 166 struct rockchip_bridge *bridge; 167 struct rockchip_phy *phy; 168 ofnode node; 169 170 void *private; 171 172 struct drm_display_mode mode; 173 struct overscan overscan; 174 u8 edid[EDID_SIZE * 4]; 175 int bus_format; 176 int output_mode; 177 int type; 178 int output_if; 179 int output_flags; 180 int color_space; 181 int dsc_enable; 182 unsigned int bpc; 183 184 /** 185 * @hold_mode: enabled when it's: 186 * (1) mcu hold mode 187 * (2) mipi dsi cmd mode 188 * (3) edp psr mode 189 */ 190 bool hold_mode; 191 192 struct base2_disp_info *disp_info; /* disp_info from baseparameter 2.0 */ 193 194 u8 dsc_id; 195 u8 dsc_slice_num; 196 u8 dsc_pixel_num; 197 u64 dsc_txp_clk; 198 u64 dsc_pxl_clk; 199 u64 dsc_cds_clk; 200 struct rockchip_dsc_sink_cap dsc_sink_cap; 201 202 struct { 203 u32 *lut; 204 int size; 205 } gamma; 206 }; 207 208 struct logo_info { 209 int mode; 210 char *mem; 211 bool ymirror; 212 u32 offset; 213 u32 width; 214 int height; 215 u32 bpp; 216 }; 217 218 struct rockchip_logo_cache { 219 struct list_head head; 220 char name[20]; 221 struct logo_info logo; 222 }; 223 224 struct display_state { 225 struct list_head head; 226 227 const void *blob; 228 ofnode node; 229 230 struct crtc_state crtc_state; 231 struct connector_state conn_state; 232 struct panel_state panel_state; 233 234 char ulogo_name[30]; 235 char klogo_name[30]; 236 237 struct logo_info logo; 238 int logo_mode; 239 int charge_logo_mode; 240 void *mem_base; 241 int mem_size; 242 243 int enable; 244 int is_init; 245 int is_enable; 246 bool force_output; 247 struct drm_display_mode force_mode; 248 u32 force_bus_format; 249 }; 250 251 static inline struct rockchip_panel *state_get_panel(struct display_state *s) 252 { 253 struct panel_state *panel_state = &s->panel_state; 254 255 return panel_state->panel; 256 } 257 258 int drm_mode_vrefresh(const struct drm_display_mode *mode); 259 int display_send_mcu_cmd(struct display_state *state, u32 type, u32 val); 260 bool drm_mode_is_420(const struct drm_display_info *display, 261 struct drm_display_mode *mode); 262 struct base2_disp_info *rockchip_get_disp_info(int type, int id); 263 264 void drm_mode_max_resolution_filter(struct hdmi_edid_data *edid_data, 265 struct vop_rect *max_output); 266 unsigned long get_cubic_lut_buffer(int crtc_id); 267 268 #endif 269