1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ROCKCHIP_DISPLAY_H 8 #define _ROCKCHIP_DISPLAY_H 9 10 #ifdef CONFIG_SPL_BUILD 11 #include <linux/hdmi.h> 12 #include <linux/media-bus-format.h> 13 #else 14 #include <bmp_layout.h> 15 #include <edid.h> 16 #endif 17 #include <drm_modes.h> 18 #include <dm/ofnode.h> 19 #include <drm/drm_dsc.h> 20 #include <reset.h> 21 #include <spl_display.h> 22 #include <clk.h> 23 #include <drm/drm_color_mgmt.h> 24 25 /* 26 * major: IP major version, used for IP structure 27 * minor: big feature change under same structure 28 * build: RTL current SVN number 29 */ 30 #define VOP_VERSION(major, minor) ((major) << 8 | (minor)) 31 #define VOP_MAJOR(version) ((version) >> 8) 32 #define VOP_MINOR(version) ((version) & 0xff) 33 34 #define VOP2_VERSION(major, minor, build) ((major) << 24 | (minor) << 16 | (build)) 35 #define VOP2_MAJOR(version) (((version) >> 24) & 0xff) 36 #define VOP2_MINOR(version) (((version) >> 16) & 0xff) 37 #define VOP2_BUILD(version) ((version) & 0xffff) 38 39 #define VOP_VERSION_RK3066 VOP_VERSION(2, 1) 40 #define VOP_VERSION_RK3036 VOP_VERSION(2, 2) 41 #define VOP_VERSION_RK3126 VOP_VERSION(2, 4) 42 #define VOP_VERSION_PX30_LITE VOP_VERSION(2, 5) 43 #define VOP_VERSION_PX30_BIG VOP_VERSION(2, 6) 44 #define VOP_VERSION_RK3308 VOP_VERSION(2, 7) 45 #define VOP_VERSION_RV1126 VOP_VERSION(2, 0xb) 46 #define VOP_VERSION_RV1106 VOP_VERSION(2, 0xc) 47 #define VOP_VERSION_RK3576_LITE VOP_VERSION(2, 0xd) 48 #define VOP_VERSION_RK3506 VOP_VERSION(2, 0xe) 49 #define VOP_VERSION_RV1126B VOP_VERSION(2, 0xf) 50 #define VOP_VERSION_RK3288 VOP_VERSION(3, 0) 51 #define VOP_VERSION_RK3288W VOP_VERSION(3, 1) 52 #define VOP_VERSION_RK3368 VOP_VERSION(3, 2) 53 #define VOP_VERSION_RK3366 VOP_VERSION(3, 4) 54 #define VOP_VERSION_RK3399_BIG VOP_VERSION(3, 5) 55 #define VOP_VERSION_RK3399_LITE VOP_VERSION(3, 6) 56 #define VOP_VERSION_RK3228 VOP_VERSION(3, 7) 57 #define VOP_VERSION_RK3328 VOP_VERSION(3, 8) 58 59 #define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263) 60 #define VOP_VERSION_RK3562 VOP2_VERSION(0x50, 0x17, 0x4350) 61 #define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023) 62 #define VOP_VERSION_RK3576 VOP2_VERSION(0x50, 0x19, 0x9765) 63 #define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786) 64 65 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0) 66 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1) 67 #define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2) 68 #define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3) 69 70 #define ROCKCHIP_DSC_PPS_SIZE_BYTE 88 71 72 enum data_format { 73 ROCKCHIP_FMT_ARGB8888 = 0, 74 ROCKCHIP_FMT_RGB888, 75 ROCKCHIP_FMT_RGB565, 76 ROCKCHIP_FMT_YUV420SP = 4, 77 ROCKCHIP_FMT_YUV422SP, 78 ROCKCHIP_FMT_YUV444SP, 79 }; 80 81 enum display_mode { 82 ROCKCHIP_DISPLAY_FULLSCREEN, 83 ROCKCHIP_DISPLAY_CENTER, 84 }; 85 86 enum rockchip_cmd_type { 87 CMD_TYPE_DEFAULT, 88 CMD_TYPE_SPI, 89 CMD_TYPE_MCU 90 }; 91 92 enum rockchip_mcu_cmd { 93 MCU_WRCMD = 0, 94 MCU_WRDATA, 95 MCU_SETBYPASS, 96 }; 97 98 /* 99 * display output interface supported by rockchip lcdc 100 */ 101 #define ROCKCHIP_OUT_MODE_P888 0 102 #define ROCKCHIP_OUT_MODE_BT1120 0 103 #define ROCKCHIP_OUT_MODE_P666 1 104 #define ROCKCHIP_OUT_MODE_P565 2 105 #define RK3588_EDP_OUTPUT_MODE_YUV422 3 106 #define ROCKCHIP_OUT_MODE_BT656 5 107 #define ROCKCHIP_OUT_MODE_S666 9 108 #define ROCKCHIP_OUT_MODE_S888 8 109 #define ROCKCHIP_OUT_MODE_YUV422 9 110 #define ROCKCHIP_OUT_MODE_S565 10 111 #define ROCKCHIP_OUT_MODE_S888_DUMMY 12 112 #define RK3588_DP_OUT_MODE_YUV422 12 113 #define RK3576_EDP_OUT_MODE_YUV422 12 114 #define RK3588_DP_OUT_MODE_YUV420 13 115 #define RK3576_HDMI_OUT_MODE_YUV422 13 116 #define ROCKCHIP_OUT_MODE_YUV420 14 117 /* for use special outface */ 118 #define ROCKCHIP_OUT_MODE_AAAA 15 119 120 #define VOP_OUTPUT_IF_RGB BIT(0) 121 #define VOP_OUTPUT_IF_BT1120 BIT(1) 122 #define VOP_OUTPUT_IF_BT656 BIT(2) 123 #define VOP_OUTPUT_IF_LVDS0 BIT(3) 124 #define VOP_OUTPUT_IF_LVDS1 BIT(4) 125 #define VOP_OUTPUT_IF_MIPI0 BIT(5) 126 #define VOP_OUTPUT_IF_MIPI1 BIT(6) 127 #define VOP_OUTPUT_IF_eDP0 BIT(7) 128 #define VOP_OUTPUT_IF_eDP1 BIT(8) 129 #define VOP_OUTPUT_IF_DP0 BIT(9) 130 #define VOP_OUTPUT_IF_DP1 BIT(10) 131 #define VOP_OUTPUT_IF_HDMI0 BIT(11) 132 #define VOP_OUTPUT_IF_HDMI1 BIT(12) 133 #define VOP_OUTPUT_IF_DP2 BIT(13) 134 135 struct rockchip_mcu_timing { 136 int mcu_pix_total; 137 int mcu_cs_pst; 138 int mcu_cs_pend; 139 int mcu_rw_pst; 140 int mcu_rw_pend; 141 int mcu_hold_mode; 142 }; 143 144 struct vop_rect { 145 int width; 146 int height; 147 }; 148 149 struct vop_urgency { 150 u8 urgen_thl; 151 u8 urgen_thh; 152 }; 153 154 struct rockchip_dsc_sink_cap { 155 /** 156 * @slice_width: the number of pixel columns that comprise the slice width 157 * @slice_height: the number of pixel rows that comprise the slice height 158 * @block_pred: Does block prediction 159 * @native_420: Does sink support DSC with 4:2:0 compression 160 * @bpc_supported: compressed bpc supported by sink : 10, 12 or 16 bpc 161 * @version_major: DSC major version 162 * @version_minor: DSC minor version 163 * @target_bits_per_pixel_x16: bits num after compress and multiply 16 164 */ 165 u16 slice_width; 166 u16 slice_height; 167 bool block_pred; 168 bool native_420; 169 u8 bpc_supported; 170 u8 version_major; 171 u8 version_minor; 172 u16 target_bits_per_pixel_x16; 173 }; 174 175 struct display_rect { 176 int x; 177 int y; 178 int w; 179 int h; 180 }; 181 182 struct bcsh_state { 183 int brightness; 184 int contrast; 185 int saturation; 186 int sin_hue; 187 int cos_hue; 188 }; 189 190 struct crtc_state { 191 struct udevice *dev; 192 struct rockchip_crtc *crtc; 193 void *private; 194 ofnode node; 195 struct device_node *ports_node; /* if (ports_node) it's vop2; */ 196 struct device_node *port_node; 197 struct reset_ctl dclk_rst; 198 struct clk dclk; 199 int crtc_id; 200 201 int format; 202 u32 dma_addr; 203 int ymirror; 204 int rb_swap; 205 int xvir; 206 int post_csc_mode; 207 int dclk_core_div; 208 int dclk_out_div; 209 struct display_rect src_rect; 210 struct display_rect crtc_rect; 211 struct display_rect right_src_rect; 212 struct display_rect right_crtc_rect; 213 bool yuv_overlay; 214 bool post_r2y_en; 215 bool post_y2r_en; 216 bool bcsh_en; 217 bool splice_mode; 218 bool soft_te; 219 bool overscan_by_win_scale; 220 u8 splice_crtc_id; 221 u8 dsc_id; 222 u8 dsc_enable; 223 u8 dsc_slice_num; 224 u8 dsc_pixel_num; 225 struct rockchip_mcu_timing mcu_timing; 226 u32 dual_channel_swap; 227 u32 feature; 228 struct vop_rect max_output; 229 230 u64 dsc_txp_clk_rate; 231 u64 dsc_pxl_clk_rate; 232 u64 dsc_cds_clk_rate; 233 struct drm_dsc_picture_parameter_set pps; 234 struct rockchip_dsc_sink_cap dsc_sink_cap; 235 236 u32 *lut_val; 237 }; 238 239 struct panel_state { 240 struct rockchip_panel *panel; 241 242 ofnode dsp_lut_node; 243 }; 244 245 struct overscan { 246 int left_margin; 247 int right_margin; 248 int top_margin; 249 int bottom_margin; 250 }; 251 252 struct connector_state { 253 struct rockchip_connector *connector; 254 struct rockchip_connector *secondary; 255 256 struct drm_display_mode mode; 257 struct overscan overscan; 258 u8 *edid; 259 int bus_format; 260 u32 bus_flags; 261 int output_mode; 262 int type; 263 int output_if; 264 int output_flags; 265 enum drm_color_encoding color_encoding; 266 enum drm_color_range color_range; 267 unsigned int bpc; 268 269 /** 270 * @hold_mode: enabled when it's: 271 * (1) mcu hold mode 272 * (2) mipi dsi cmd mode 273 * (3) edp psr mode 274 */ 275 bool hold_mode; 276 277 struct base2_disp_info *disp_info; /* disp_info from baseparameter 2.0 */ 278 279 u8 dsc_id; 280 u8 dsc_slice_num; 281 u8 dsc_pixel_num; 282 u64 dsc_txp_clk; 283 u64 dsc_pxl_clk; 284 u64 dsc_cds_clk; 285 struct rockchip_dsc_sink_cap dsc_sink_cap; 286 struct drm_dsc_picture_parameter_set pps; 287 288 struct gpio_desc *te_gpio; 289 290 struct { 291 u32 *lut; 292 int size; 293 } gamma; 294 }; 295 296 struct logo_info { 297 int mode; 298 int rotate; 299 char *mem; 300 bool ymirror; 301 u32 offset; 302 u32 width; 303 int height; 304 u32 bpp; 305 }; 306 307 struct rockchip_logo_cache { 308 struct list_head head; 309 char name[20]; 310 struct logo_info logo; 311 int logo_rotate; 312 }; 313 314 struct display_state { 315 struct list_head head; 316 317 const void *blob; 318 ofnode node; 319 320 struct crtc_state crtc_state; 321 struct connector_state conn_state; 322 struct panel_state panel_state; 323 324 char ulogo_name[30]; 325 char klogo_name[30]; 326 327 struct logo_info logo; 328 int logo_mode; 329 int charge_logo_mode; 330 int logo_rotate; 331 void *mem_base; 332 int mem_size; 333 334 int enable; 335 int is_init; 336 int is_enable; 337 bool is_klogo_valid; 338 bool force_output; 339 bool enabled_at_spl; 340 struct drm_display_mode force_mode; 341 u32 force_bus_format; 342 343 ulong vidcon_fb_addr; 344 }; 345 346 int drm_mode_vrefresh(const struct drm_display_mode *mode); 347 int display_send_mcu_cmd(struct display_state *state, u32 type, u32 val); 348 bool drm_mode_is_420_only(const struct drm_display_info *display, 349 struct drm_display_mode *mode); 350 bool drm_mode_is_420_also(const struct drm_display_info *display, 351 struct drm_display_mode *mode); 352 bool drm_mode_is_420(const struct drm_display_info *display, 353 struct drm_display_mode *mode); 354 struct base2_disp_info *rockchip_get_disp_info(int type, int id); 355 356 void drm_mode_max_resolution_filter(struct hdmi_edid_data *edid_data, 357 struct vop_rect *max_output); 358 unsigned long get_cubic_lut_buffer(int crtc_id); 359 int rockchip_ofnode_get_display_mode(ofnode node, struct drm_display_mode *mode, 360 u32 *bus_flags); 361 void rockchip_display_make_crc32_table(void); 362 uint32_t rockchip_display_crc32c_cal(unsigned char *data, int length); 363 void drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags); 364 void drm_mode_convert_to_origin_mode(struct drm_display_mode *mode); 365 void drm_mode_convert_to_split_mode(struct drm_display_mode *mode); 366 367 int display_rect_calc_hscale(struct display_rect *src, struct display_rect *dst, 368 int min_hscale, int max_hscale); 369 int display_rect_calc_vscale(struct display_rect *src, struct display_rect *dst, 370 int min_vscale, int max_vscale); 371 const struct device_node * 372 rockchip_of_graph_get_endpoint_by_regs(ofnode node, int port, int endpoint); 373 const struct device_node * 374 rockchip_of_graph_get_port_by_id(ofnode node, int id); 375 uint32_t rockchip_drm_get_cycles_per_pixel(uint32_t bus_format); 376 char* rockchip_get_output_if_name(u32 output_if, char *name); 377 378 #ifdef CONFIG_SPL_BUILD 379 int rockchip_spl_vop_probe(struct crtc_state *crtc_state); 380 int rockchip_spl_dw_hdmi_probe(struct connector_state *conn_state); 381 int inno_spl_hdmi_phy_probe(struct display_state *state); 382 #endif 383 #endif 384