1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ROCKCHIP_DISPLAY_H 8 #define _ROCKCHIP_DISPLAY_H 9 10 #ifdef CONFIG_SPL_BUILD 11 #include <linux/hdmi.h> 12 #include <linux/media-bus-format.h> 13 #else 14 #include <bmp_layout.h> 15 #include <edid.h> 16 #endif 17 #include <drm_modes.h> 18 #include <dm/ofnode.h> 19 #include <drm/drm_dsc.h> 20 #include <spl_display.h> 21 #include <clk.h> 22 #include <drm/drm_color_mgmt.h> 23 24 /* 25 * major: IP major version, used for IP structure 26 * minor: big feature change under same structure 27 * build: RTL current SVN number 28 */ 29 #define VOP_VERSION(major, minor) ((major) << 8 | (minor)) 30 #define VOP_MAJOR(version) ((version) >> 8) 31 #define VOP_MINOR(version) ((version) & 0xff) 32 33 #define VOP2_VERSION(major, minor, build) ((major) << 24 | (minor) << 16 | (build)) 34 #define VOP2_MAJOR(version) (((version) >> 24) & 0xff) 35 #define VOP2_MINOR(version) (((version) >> 16) & 0xff) 36 #define VOP2_BUILD(version) ((version) & 0xffff) 37 38 #define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263) 39 #define VOP_VERSION_RK3562 VOP2_VERSION(0x50, 0x17, 0x4350) 40 #define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023) 41 #define VOP_VERSION_RK3576 VOP2_VERSION(0x50, 0x19, 0x9765) 42 #define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786) 43 44 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0) 45 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1) 46 #define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2) 47 #define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3) 48 49 #define ROCKCHIP_DSC_PPS_SIZE_BYTE 88 50 51 enum data_format { 52 ROCKCHIP_FMT_ARGB8888 = 0, 53 ROCKCHIP_FMT_RGB888, 54 ROCKCHIP_FMT_RGB565, 55 ROCKCHIP_FMT_YUV420SP = 4, 56 ROCKCHIP_FMT_YUV422SP, 57 ROCKCHIP_FMT_YUV444SP, 58 }; 59 60 enum display_mode { 61 ROCKCHIP_DISPLAY_FULLSCREEN, 62 ROCKCHIP_DISPLAY_CENTER, 63 }; 64 65 enum rockchip_cmd_type { 66 CMD_TYPE_DEFAULT, 67 CMD_TYPE_SPI, 68 CMD_TYPE_MCU 69 }; 70 71 enum rockchip_mcu_cmd { 72 MCU_WRCMD = 0, 73 MCU_WRDATA, 74 MCU_SETBYPASS, 75 }; 76 77 /* 78 * display output interface supported by rockchip lcdc 79 */ 80 #define ROCKCHIP_OUT_MODE_P888 0 81 #define ROCKCHIP_OUT_MODE_BT1120 0 82 #define ROCKCHIP_OUT_MODE_P666 1 83 #define ROCKCHIP_OUT_MODE_P565 2 84 #define ROCKCHIP_OUT_MODE_BT656 5 85 #define ROCKCHIP_OUT_MODE_S666 9 86 #define ROCKCHIP_OUT_MODE_S888 8 87 #define ROCKCHIP_OUT_MODE_YUV422 9 88 #define ROCKCHIP_OUT_MODE_S565 10 89 #define ROCKCHIP_OUT_MODE_S888_DUMMY 12 90 #define ROCKCHIP_OUT_MODE_YUV420 14 91 /* for use special outface */ 92 #define ROCKCHIP_OUT_MODE_AAAA 15 93 94 #define VOP_OUTPUT_IF_RGB BIT(0) 95 #define VOP_OUTPUT_IF_BT1120 BIT(1) 96 #define VOP_OUTPUT_IF_BT656 BIT(2) 97 #define VOP_OUTPUT_IF_LVDS0 BIT(3) 98 #define VOP_OUTPUT_IF_LVDS1 BIT(4) 99 #define VOP_OUTPUT_IF_MIPI0 BIT(5) 100 #define VOP_OUTPUT_IF_MIPI1 BIT(6) 101 #define VOP_OUTPUT_IF_eDP0 BIT(7) 102 #define VOP_OUTPUT_IF_eDP1 BIT(8) 103 #define VOP_OUTPUT_IF_DP0 BIT(9) 104 #define VOP_OUTPUT_IF_DP1 BIT(10) 105 #define VOP_OUTPUT_IF_HDMI0 BIT(11) 106 #define VOP_OUTPUT_IF_HDMI1 BIT(12) 107 #define VOP_OUTPUT_IF_DP2 BIT(13) 108 109 struct rockchip_mcu_timing { 110 int mcu_pix_total; 111 int mcu_cs_pst; 112 int mcu_cs_pend; 113 int mcu_rw_pst; 114 int mcu_rw_pend; 115 int mcu_hold_mode; 116 }; 117 118 struct vop_rect { 119 int width; 120 int height; 121 }; 122 123 struct rockchip_dsc_sink_cap { 124 /** 125 * @slice_width: the number of pixel columns that comprise the slice width 126 * @slice_height: the number of pixel rows that comprise the slice height 127 * @block_pred: Does block prediction 128 * @native_420: Does sink support DSC with 4:2:0 compression 129 * @bpc_supported: compressed bpc supported by sink : 10, 12 or 16 bpc 130 * @version_major: DSC major version 131 * @version_minor: DSC minor version 132 * @target_bits_per_pixel_x16: bits num after compress and multiply 16 133 */ 134 u16 slice_width; 135 u16 slice_height; 136 bool block_pred; 137 bool native_420; 138 u8 bpc_supported; 139 u8 version_major; 140 u8 version_minor; 141 u16 target_bits_per_pixel_x16; 142 }; 143 144 struct display_rect { 145 int x; 146 int y; 147 int w; 148 int h; 149 }; 150 151 struct bcsh_state { 152 int brightness; 153 int contrast; 154 int saturation; 155 int sin_hue; 156 int cos_hue; 157 }; 158 159 struct crtc_state { 160 struct udevice *dev; 161 struct rockchip_crtc *crtc; 162 void *private; 163 ofnode node; 164 struct device_node *ports_node; /* if (ports_node) it's vop2; */ 165 struct clk dclk; 166 int crtc_id; 167 168 int format; 169 u32 dma_addr; 170 int ymirror; 171 int rb_swap; 172 int xvir; 173 int post_csc_mode; 174 int dclk_core_div; 175 int dclk_out_div; 176 struct display_rect src_rect; 177 struct display_rect crtc_rect; 178 struct display_rect right_src_rect; 179 struct display_rect right_crtc_rect; 180 bool yuv_overlay; 181 bool post_r2y_en; 182 bool post_y2r_en; 183 bool bcsh_en; 184 bool splice_mode; 185 bool soft_te; 186 u8 splice_crtc_id; 187 u8 dsc_id; 188 u8 dsc_enable; 189 u8 dsc_slice_num; 190 u8 dsc_pixel_num; 191 struct rockchip_mcu_timing mcu_timing; 192 u32 dual_channel_swap; 193 u32 feature; 194 struct vop_rect max_output; 195 196 u64 dsc_txp_clk_rate; 197 u64 dsc_pxl_clk_rate; 198 u64 dsc_cds_clk_rate; 199 struct drm_dsc_picture_parameter_set pps; 200 struct rockchip_dsc_sink_cap dsc_sink_cap; 201 }; 202 203 struct panel_state { 204 struct rockchip_panel *panel; 205 206 ofnode dsp_lut_node; 207 }; 208 209 struct overscan { 210 int left_margin; 211 int right_margin; 212 int top_margin; 213 int bottom_margin; 214 }; 215 216 struct connector_state { 217 struct rockchip_connector *connector; 218 struct rockchip_connector *secondary; 219 220 struct drm_display_mode mode; 221 struct overscan overscan; 222 u8 edid[EDID_SIZE * 4]; 223 int bus_format; 224 u32 bus_flags; 225 int output_mode; 226 int type; 227 int output_if; 228 int output_flags; 229 enum drm_color_encoding color_encoding; 230 enum drm_color_range color_range; 231 unsigned int bpc; 232 233 /** 234 * @hold_mode: enabled when it's: 235 * (1) mcu hold mode 236 * (2) mipi dsi cmd mode 237 * (3) edp psr mode 238 */ 239 bool hold_mode; 240 241 struct base2_disp_info *disp_info; /* disp_info from baseparameter 2.0 */ 242 243 u8 dsc_id; 244 u8 dsc_slice_num; 245 u8 dsc_pixel_num; 246 u64 dsc_txp_clk; 247 u64 dsc_pxl_clk; 248 u64 dsc_cds_clk; 249 struct rockchip_dsc_sink_cap dsc_sink_cap; 250 struct drm_dsc_picture_parameter_set pps; 251 252 struct gpio_desc *te_gpio; 253 254 struct { 255 u32 *lut; 256 int size; 257 } gamma; 258 }; 259 260 struct logo_info { 261 int mode; 262 int rotate; 263 char *mem; 264 bool ymirror; 265 u32 offset; 266 u32 width; 267 int height; 268 u32 bpp; 269 }; 270 271 struct rockchip_logo_cache { 272 struct list_head head; 273 char name[20]; 274 struct logo_info logo; 275 int logo_rotate; 276 }; 277 278 struct display_state { 279 struct list_head head; 280 281 const void *blob; 282 ofnode node; 283 284 struct crtc_state crtc_state; 285 struct connector_state conn_state; 286 struct panel_state panel_state; 287 288 char ulogo_name[30]; 289 char klogo_name[30]; 290 291 struct logo_info logo; 292 int logo_mode; 293 int charge_logo_mode; 294 int logo_rotate; 295 void *mem_base; 296 int mem_size; 297 298 int enable; 299 int is_init; 300 int is_enable; 301 bool is_klogo_valid; 302 bool force_output; 303 bool enabled_at_spl; 304 struct drm_display_mode force_mode; 305 u32 force_bus_format; 306 }; 307 308 int drm_mode_vrefresh(const struct drm_display_mode *mode); 309 int display_send_mcu_cmd(struct display_state *state, u32 type, u32 val); 310 bool drm_mode_is_420(const struct drm_display_info *display, 311 struct drm_display_mode *mode); 312 struct base2_disp_info *rockchip_get_disp_info(int type, int id); 313 314 void drm_mode_max_resolution_filter(struct hdmi_edid_data *edid_data, 315 struct vop_rect *max_output); 316 unsigned long get_cubic_lut_buffer(int crtc_id); 317 int rockchip_ofnode_get_display_mode(ofnode node, struct drm_display_mode *mode, 318 u32 *bus_flags); 319 void rockchip_display_make_crc32_table(void); 320 uint32_t rockchip_display_crc32c_cal(unsigned char *data, int length); 321 void drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags); 322 323 int display_rect_calc_hscale(struct display_rect *src, struct display_rect *dst, 324 int min_hscale, int max_hscale); 325 int display_rect_calc_vscale(struct display_rect *src, struct display_rect *dst, 326 int min_vscale, int max_vscale); 327 const struct device_node * 328 rockchip_of_graph_get_endpoint_by_regs(ofnode node, int port, int endpoint); 329 const struct device_node * 330 rockchip_of_graph_get_port_by_id(ofnode node, int id); 331 uint32_t rockchip_drm_get_cycles_per_pixel(uint32_t bus_format); 332 char* rockchip_get_output_if_name(u32 output_if, char *name); 333 334 #ifdef CONFIG_SPL_BUILD 335 int rockchip_spl_vop_probe(struct crtc_state *crtc_state); 336 int rockchip_spl_dw_hdmi_probe(struct connector_state *conn_state); 337 int inno_spl_hdmi_phy_probe(struct display_state *state); 338 #endif 339 #endif 340