1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ROCKCHIP_DISPLAY_H 8 #define _ROCKCHIP_DISPLAY_H 9 10 #include <bmp_layout.h> 11 #include <drm_modes.h> 12 #include <edid.h> 13 #include <dm/ofnode.h> 14 #include <drm/drm_dsc.h> 15 16 /* 17 * major: IP major vertion, used for IP structure 18 * minor: big feature change under same structure 19 */ 20 #define VOP_VERSION(major, minor) ((major) << 8 | (minor)) 21 #define VOP_MAJOR(version) ((version) >> 8) 22 #define VOP_MINOR(version) ((version) & 0xff) 23 24 #define VOP_VERSION_RK3528 VOP_VERSION(0x50, 0x17) 25 #define VOP_VERSION_RK3568 VOP_VERSION(0x40, 0x15) 26 #define VOP_VERSION_RK3588 VOP_VERSION(0x40, 0x17) 27 28 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0) 29 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1) 30 #define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2) 31 #define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3) 32 33 #define ROCKCHIP_DSC_PPS_SIZE_BYTE 88 34 35 enum data_format { 36 ROCKCHIP_FMT_ARGB8888 = 0, 37 ROCKCHIP_FMT_RGB888, 38 ROCKCHIP_FMT_RGB565, 39 ROCKCHIP_FMT_YUV420SP = 4, 40 ROCKCHIP_FMT_YUV422SP, 41 ROCKCHIP_FMT_YUV444SP, 42 }; 43 44 enum display_mode { 45 ROCKCHIP_DISPLAY_FULLSCREEN, 46 ROCKCHIP_DISPLAY_CENTER, 47 }; 48 49 enum rockchip_cmd_type { 50 CMD_TYPE_DEFAULT, 51 CMD_TYPE_SPI, 52 CMD_TYPE_MCU 53 }; 54 55 enum rockchip_mcu_cmd { 56 MCU_WRCMD = 0, 57 MCU_WRDATA, 58 MCU_SETBYPASS, 59 }; 60 61 /* 62 * display output interface supported by rockchip lcdc 63 */ 64 #define ROCKCHIP_OUT_MODE_P888 0 65 #define ROCKCHIP_OUT_MODE_BT1120 0 66 #define ROCKCHIP_OUT_MODE_P666 1 67 #define ROCKCHIP_OUT_MODE_P565 2 68 #define ROCKCHIP_OUT_MODE_BT656 5 69 #define ROCKCHIP_OUT_MODE_S888 8 70 #define ROCKCHIP_OUT_MODE_S888_DUMMY 12 71 #define ROCKCHIP_OUT_MODE_YUV420 14 72 /* for use special outface */ 73 #define ROCKCHIP_OUT_MODE_AAAA 15 74 75 #define VOP_OUTPUT_IF_RGB BIT(0) 76 #define VOP_OUTPUT_IF_BT1120 BIT(1) 77 #define VOP_OUTPUT_IF_BT656 BIT(2) 78 #define VOP_OUTPUT_IF_LVDS0 BIT(3) 79 #define VOP_OUTPUT_IF_LVDS1 BIT(4) 80 #define VOP_OUTPUT_IF_MIPI0 BIT(5) 81 #define VOP_OUTPUT_IF_MIPI1 BIT(6) 82 #define VOP_OUTPUT_IF_eDP0 BIT(7) 83 #define VOP_OUTPUT_IF_eDP1 BIT(8) 84 #define VOP_OUTPUT_IF_DP0 BIT(9) 85 #define VOP_OUTPUT_IF_DP1 BIT(10) 86 #define VOP_OUTPUT_IF_HDMI0 BIT(11) 87 #define VOP_OUTPUT_IF_HDMI1 BIT(12) 88 89 struct rockchip_mcu_timing { 90 int mcu_pix_total; 91 int mcu_cs_pst; 92 int mcu_cs_pend; 93 int mcu_rw_pst; 94 int mcu_rw_pend; 95 int mcu_hold_mode; 96 }; 97 98 struct vop_rect { 99 int width; 100 int height; 101 }; 102 103 struct rockchip_dsc_sink_cap { 104 /** 105 * @slice_width: the number of pixel columns that comprise the slice width 106 * @slice_height: the number of pixel rows that comprise the slice height 107 * @block_pred: Does block prediction 108 * @native_420: Does sink support DSC with 4:2:0 compression 109 * @bpc_supported: compressed bpc supported by sink : 10, 12 or 16 bpc 110 * @version_major: DSC major version 111 * @version_minor: DSC minor version 112 * @target_bits_per_pixel_x16: bits num after compress and multiply 16 113 */ 114 u16 slice_width; 115 u16 slice_height; 116 bool block_pred; 117 bool native_420; 118 u8 bpc_supported; 119 u8 version_major; 120 u8 version_minor; 121 u16 target_bits_per_pixel_x16; 122 }; 123 124 struct display_rect { 125 int x; 126 int y; 127 int w; 128 int h; 129 }; 130 131 struct bcsh_state { 132 int brightness; 133 int contrast; 134 int saturation; 135 int sin_hue; 136 int cos_hue; 137 }; 138 139 struct crtc_state { 140 struct udevice *dev; 141 struct rockchip_crtc *crtc; 142 void *private; 143 ofnode node; 144 struct device_node *ports_node; /* if (ports_node) it's vop2; */ 145 int crtc_id; 146 147 int format; 148 u32 dma_addr; 149 int ymirror; 150 int rb_swap; 151 int xvir; 152 int post_csc_mode; 153 int dclk_core_div; 154 int dclk_out_div; 155 struct display_rect src_rect; 156 struct display_rect crtc_rect; 157 struct display_rect right_src_rect; 158 struct display_rect right_crtc_rect; 159 bool yuv_overlay; 160 bool post_r2y_en; 161 bool post_y2r_en; 162 bool bcsh_en; 163 bool splice_mode; 164 u8 splice_crtc_id; 165 u8 dsc_id; 166 u8 dsc_enable; 167 u8 dsc_slice_num; 168 u8 dsc_pixel_num; 169 struct rockchip_mcu_timing mcu_timing; 170 u32 dual_channel_swap; 171 u32 feature; 172 struct vop_rect max_output; 173 174 u64 dsc_txp_clk_rate; 175 u64 dsc_pxl_clk_rate; 176 u64 dsc_cds_clk_rate; 177 struct drm_dsc_picture_parameter_set pps; 178 struct rockchip_dsc_sink_cap dsc_sink_cap; 179 }; 180 181 struct panel_state { 182 struct rockchip_panel *panel; 183 184 ofnode dsp_lut_node; 185 }; 186 187 struct overscan { 188 int left_margin; 189 int right_margin; 190 int top_margin; 191 int bottom_margin; 192 }; 193 194 struct connector_state { 195 struct rockchip_connector *connector; 196 struct rockchip_connector *secondary; 197 198 struct drm_display_mode mode; 199 struct overscan overscan; 200 u8 edid[EDID_SIZE * 4]; 201 int bus_format; 202 int output_mode; 203 int type; 204 int output_if; 205 int output_flags; 206 int color_space; 207 unsigned int bpc; 208 209 /** 210 * @hold_mode: enabled when it's: 211 * (1) mcu hold mode 212 * (2) mipi dsi cmd mode 213 * (3) edp psr mode 214 */ 215 bool hold_mode; 216 217 struct base2_disp_info *disp_info; /* disp_info from baseparameter 2.0 */ 218 219 u8 dsc_id; 220 u8 dsc_slice_num; 221 u8 dsc_pixel_num; 222 u64 dsc_txp_clk; 223 u64 dsc_pxl_clk; 224 u64 dsc_cds_clk; 225 struct rockchip_dsc_sink_cap dsc_sink_cap; 226 struct drm_dsc_picture_parameter_set pps; 227 228 struct { 229 u32 *lut; 230 int size; 231 } gamma; 232 }; 233 234 struct logo_info { 235 int mode; 236 char *mem; 237 bool ymirror; 238 u32 offset; 239 u32 width; 240 int height; 241 u32 bpp; 242 }; 243 244 struct rockchip_logo_cache { 245 struct list_head head; 246 char name[20]; 247 struct logo_info logo; 248 }; 249 250 struct display_state { 251 struct list_head head; 252 253 const void *blob; 254 ofnode node; 255 256 struct crtc_state crtc_state; 257 struct connector_state conn_state; 258 struct panel_state panel_state; 259 260 char ulogo_name[30]; 261 char klogo_name[30]; 262 263 struct logo_info logo; 264 int logo_mode; 265 int charge_logo_mode; 266 void *mem_base; 267 int mem_size; 268 269 int enable; 270 int is_init; 271 int is_enable; 272 bool is_klogo_valid; 273 bool force_output; 274 struct drm_display_mode force_mode; 275 u32 force_bus_format; 276 }; 277 278 int drm_mode_vrefresh(const struct drm_display_mode *mode); 279 int display_send_mcu_cmd(struct display_state *state, u32 type, u32 val); 280 bool drm_mode_is_420(const struct drm_display_info *display, 281 struct drm_display_mode *mode); 282 struct base2_disp_info *rockchip_get_disp_info(int type, int id); 283 284 void drm_mode_max_resolution_filter(struct hdmi_edid_data *edid_data, 285 struct vop_rect *max_output); 286 unsigned long get_cubic_lut_buffer(int crtc_id); 287 int rockchip_ofnode_get_display_mode(ofnode node, struct drm_display_mode *mode); 288 289 int display_rect_calc_hscale(struct display_rect *src, struct display_rect *dst, 290 int min_hscale, int max_hscale); 291 int display_rect_calc_vscale(struct display_rect *src, struct display_rect *dst, 292 int min_vscale, int max_vscale); 293 294 #endif 295