1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ROCKCHIP_DISPLAY_H 8 #define _ROCKCHIP_DISPLAY_H 9 10 #ifdef CONFIG_SPL_BUILD 11 #include <linux/hdmi.h> 12 #include <linux/media-bus-format.h> 13 #else 14 #include <bmp_layout.h> 15 #include <edid.h> 16 #endif 17 #include <drm_modes.h> 18 #include <dm/ofnode.h> 19 #include <drm/drm_dsc.h> 20 #include <spl_display.h> 21 22 /* 23 * major: IP major version, used for IP structure 24 * minor: big feature change under same structure 25 * build: RTL current SVN number 26 */ 27 #define VOP_VERSION(major, minor) ((major) << 8 | (minor)) 28 #define VOP_MAJOR(version) ((version) >> 8) 29 #define VOP_MINOR(version) ((version) & 0xff) 30 31 #define VOP2_VERSION(major, minor, build) ((major) << 24 | (minor) << 16 | (build)) 32 #define VOP2_MAJOR(version) (((version) >> 24) & 0xff) 33 #define VOP2_MINOR(version) (((version) >> 16) & 0xff) 34 #define VOP2_BUILD(version) ((version) & 0xffff) 35 36 #define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263) 37 #define VOP_VERSION_RK3562 VOP2_VERSION(0x50, 0x17, 0x4350) 38 #define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023) 39 #define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786) 40 41 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0) 42 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1) 43 #define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2) 44 #define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3) 45 46 #define ROCKCHIP_DSC_PPS_SIZE_BYTE 88 47 48 enum data_format { 49 ROCKCHIP_FMT_ARGB8888 = 0, 50 ROCKCHIP_FMT_RGB888, 51 ROCKCHIP_FMT_RGB565, 52 ROCKCHIP_FMT_YUV420SP = 4, 53 ROCKCHIP_FMT_YUV422SP, 54 ROCKCHIP_FMT_YUV444SP, 55 }; 56 57 enum display_mode { 58 ROCKCHIP_DISPLAY_FULLSCREEN, 59 ROCKCHIP_DISPLAY_CENTER, 60 }; 61 62 enum rockchip_cmd_type { 63 CMD_TYPE_DEFAULT, 64 CMD_TYPE_SPI, 65 CMD_TYPE_MCU 66 }; 67 68 enum rockchip_mcu_cmd { 69 MCU_WRCMD = 0, 70 MCU_WRDATA, 71 MCU_SETBYPASS, 72 }; 73 74 /* 75 * display output interface supported by rockchip lcdc 76 */ 77 #define ROCKCHIP_OUT_MODE_P888 0 78 #define ROCKCHIP_OUT_MODE_BT1120 0 79 #define ROCKCHIP_OUT_MODE_P666 1 80 #define ROCKCHIP_OUT_MODE_P565 2 81 #define ROCKCHIP_OUT_MODE_BT656 5 82 #define ROCKCHIP_OUT_MODE_S888 8 83 #define ROCKCHIP_OUT_MODE_YUV422 9 84 #define ROCKCHIP_OUT_MODE_S888_DUMMY 12 85 #define ROCKCHIP_OUT_MODE_YUV420 14 86 /* for use special outface */ 87 #define ROCKCHIP_OUT_MODE_AAAA 15 88 89 #define VOP_OUTPUT_IF_RGB BIT(0) 90 #define VOP_OUTPUT_IF_BT1120 BIT(1) 91 #define VOP_OUTPUT_IF_BT656 BIT(2) 92 #define VOP_OUTPUT_IF_LVDS0 BIT(3) 93 #define VOP_OUTPUT_IF_LVDS1 BIT(4) 94 #define VOP_OUTPUT_IF_MIPI0 BIT(5) 95 #define VOP_OUTPUT_IF_MIPI1 BIT(6) 96 #define VOP_OUTPUT_IF_eDP0 BIT(7) 97 #define VOP_OUTPUT_IF_eDP1 BIT(8) 98 #define VOP_OUTPUT_IF_DP0 BIT(9) 99 #define VOP_OUTPUT_IF_DP1 BIT(10) 100 #define VOP_OUTPUT_IF_HDMI0 BIT(11) 101 #define VOP_OUTPUT_IF_HDMI1 BIT(12) 102 103 struct rockchip_mcu_timing { 104 int mcu_pix_total; 105 int mcu_cs_pst; 106 int mcu_cs_pend; 107 int mcu_rw_pst; 108 int mcu_rw_pend; 109 int mcu_hold_mode; 110 }; 111 112 struct vop_rect { 113 int width; 114 int height; 115 }; 116 117 struct rockchip_dsc_sink_cap { 118 /** 119 * @slice_width: the number of pixel columns that comprise the slice width 120 * @slice_height: the number of pixel rows that comprise the slice height 121 * @block_pred: Does block prediction 122 * @native_420: Does sink support DSC with 4:2:0 compression 123 * @bpc_supported: compressed bpc supported by sink : 10, 12 or 16 bpc 124 * @version_major: DSC major version 125 * @version_minor: DSC minor version 126 * @target_bits_per_pixel_x16: bits num after compress and multiply 16 127 */ 128 u16 slice_width; 129 u16 slice_height; 130 bool block_pred; 131 bool native_420; 132 u8 bpc_supported; 133 u8 version_major; 134 u8 version_minor; 135 u16 target_bits_per_pixel_x16; 136 }; 137 138 struct display_rect { 139 int x; 140 int y; 141 int w; 142 int h; 143 }; 144 145 struct bcsh_state { 146 int brightness; 147 int contrast; 148 int saturation; 149 int sin_hue; 150 int cos_hue; 151 }; 152 153 struct crtc_state { 154 struct udevice *dev; 155 struct rockchip_crtc *crtc; 156 void *private; 157 ofnode node; 158 struct device_node *ports_node; /* if (ports_node) it's vop2; */ 159 int crtc_id; 160 161 int format; 162 u32 dma_addr; 163 int ymirror; 164 int rb_swap; 165 int xvir; 166 int post_csc_mode; 167 int dclk_core_div; 168 int dclk_out_div; 169 struct display_rect src_rect; 170 struct display_rect crtc_rect; 171 struct display_rect right_src_rect; 172 struct display_rect right_crtc_rect; 173 bool yuv_overlay; 174 bool post_r2y_en; 175 bool post_y2r_en; 176 bool bcsh_en; 177 bool splice_mode; 178 bool soft_te; 179 u8 splice_crtc_id; 180 u8 dsc_id; 181 u8 dsc_enable; 182 u8 dsc_slice_num; 183 u8 dsc_pixel_num; 184 struct rockchip_mcu_timing mcu_timing; 185 u32 dual_channel_swap; 186 u32 feature; 187 struct vop_rect max_output; 188 189 u64 dsc_txp_clk_rate; 190 u64 dsc_pxl_clk_rate; 191 u64 dsc_cds_clk_rate; 192 struct drm_dsc_picture_parameter_set pps; 193 struct rockchip_dsc_sink_cap dsc_sink_cap; 194 }; 195 196 struct panel_state { 197 struct rockchip_panel *panel; 198 199 ofnode dsp_lut_node; 200 }; 201 202 struct overscan { 203 int left_margin; 204 int right_margin; 205 int top_margin; 206 int bottom_margin; 207 }; 208 209 struct connector_state { 210 struct rockchip_connector *connector; 211 struct rockchip_connector *secondary; 212 213 struct drm_display_mode mode; 214 struct overscan overscan; 215 u8 edid[EDID_SIZE * 4]; 216 int bus_format; 217 u32 bus_flags; 218 int output_mode; 219 int type; 220 int output_if; 221 int output_flags; 222 int color_space; 223 unsigned int bpc; 224 225 /** 226 * @hold_mode: enabled when it's: 227 * (1) mcu hold mode 228 * (2) mipi dsi cmd mode 229 * (3) edp psr mode 230 */ 231 bool hold_mode; 232 233 struct base2_disp_info *disp_info; /* disp_info from baseparameter 2.0 */ 234 235 u8 dsc_id; 236 u8 dsc_slice_num; 237 u8 dsc_pixel_num; 238 u64 dsc_txp_clk; 239 u64 dsc_pxl_clk; 240 u64 dsc_cds_clk; 241 struct rockchip_dsc_sink_cap dsc_sink_cap; 242 struct drm_dsc_picture_parameter_set pps; 243 244 struct gpio_desc *te_gpio; 245 246 struct { 247 u32 *lut; 248 int size; 249 } gamma; 250 }; 251 252 struct logo_info { 253 int mode; 254 char *mem; 255 bool ymirror; 256 u32 offset; 257 u32 width; 258 int height; 259 u32 bpp; 260 }; 261 262 struct rockchip_logo_cache { 263 struct list_head head; 264 char name[20]; 265 struct logo_info logo; 266 }; 267 268 struct display_state { 269 struct list_head head; 270 271 const void *blob; 272 ofnode node; 273 274 struct crtc_state crtc_state; 275 struct connector_state conn_state; 276 struct panel_state panel_state; 277 278 char ulogo_name[30]; 279 char klogo_name[30]; 280 281 struct logo_info logo; 282 int logo_mode; 283 int charge_logo_mode; 284 void *mem_base; 285 int mem_size; 286 287 int enable; 288 int is_init; 289 int is_enable; 290 bool is_klogo_valid; 291 bool force_output; 292 bool enabled_at_spl; 293 struct drm_display_mode force_mode; 294 u32 force_bus_format; 295 }; 296 297 int drm_mode_vrefresh(const struct drm_display_mode *mode); 298 int display_send_mcu_cmd(struct display_state *state, u32 type, u32 val); 299 bool drm_mode_is_420(const struct drm_display_info *display, 300 struct drm_display_mode *mode); 301 struct base2_disp_info *rockchip_get_disp_info(int type, int id); 302 303 void drm_mode_max_resolution_filter(struct hdmi_edid_data *edid_data, 304 struct vop_rect *max_output); 305 unsigned long get_cubic_lut_buffer(int crtc_id); 306 int rockchip_ofnode_get_display_mode(ofnode node, struct drm_display_mode *mode, 307 u32 *bus_flags); 308 void rockchip_display_make_crc32_table(void); 309 uint32_t rockchip_display_crc32c_cal(unsigned char *data, int length); 310 void drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags); 311 312 int display_rect_calc_hscale(struct display_rect *src, struct display_rect *dst, 313 int min_hscale, int max_hscale); 314 int display_rect_calc_vscale(struct display_rect *src, struct display_rect *dst, 315 int min_vscale, int max_vscale); 316 const struct device_node * 317 rockchip_of_graph_get_endpoint_by_regs(ofnode node, int port, int endpoint); 318 void drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags); 319 320 #ifdef CONFIG_SPL_BUILD 321 int rockchip_spl_vop_probe(struct crtc_state *crtc_state); 322 int rockchip_spl_dw_hdmi_probe(struct connector_state *conn_state); 323 int inno_spl_hdmi_phy_probe(struct display_state *state); 324 #endif 325 #endif 326