1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ROCKCHIP_DISPLAY_H 8 #define _ROCKCHIP_DISPLAY_H 9 10 #ifdef CONFIG_SPL_BUILD 11 #include <linux/hdmi.h> 12 #include <linux/media-bus-format.h> 13 #else 14 #include <bmp_layout.h> 15 #include <edid.h> 16 #endif 17 #include <drm_modes.h> 18 #include <dm/ofnode.h> 19 #include <drm/drm_dsc.h> 20 #include <spl_display.h> 21 #include <clk.h> 22 #include <drm/drm_color_mgmt.h> 23 24 /* 25 * major: IP major version, used for IP structure 26 * minor: big feature change under same structure 27 * build: RTL current SVN number 28 */ 29 #define VOP_VERSION(major, minor) ((major) << 8 | (minor)) 30 #define VOP_MAJOR(version) ((version) >> 8) 31 #define VOP_MINOR(version) ((version) & 0xff) 32 33 #define VOP2_VERSION(major, minor, build) ((major) << 24 | (minor) << 16 | (build)) 34 #define VOP2_MAJOR(version) (((version) >> 24) & 0xff) 35 #define VOP2_MINOR(version) (((version) >> 16) & 0xff) 36 #define VOP2_BUILD(version) ((version) & 0xffff) 37 38 #define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263) 39 #define VOP_VERSION_RK3562 VOP2_VERSION(0x50, 0x17, 0x4350) 40 #define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023) 41 #define VOP_VERSION_RK3576 VOP2_VERSION(0x50, 0x19, 0x9765) 42 #define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786) 43 44 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0) 45 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1) 46 #define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2) 47 #define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3) 48 49 #define ROCKCHIP_DSC_PPS_SIZE_BYTE 88 50 51 enum data_format { 52 ROCKCHIP_FMT_ARGB8888 = 0, 53 ROCKCHIP_FMT_RGB888, 54 ROCKCHIP_FMT_RGB565, 55 ROCKCHIP_FMT_YUV420SP = 4, 56 ROCKCHIP_FMT_YUV422SP, 57 ROCKCHIP_FMT_YUV444SP, 58 }; 59 60 enum display_mode { 61 ROCKCHIP_DISPLAY_FULLSCREEN, 62 ROCKCHIP_DISPLAY_CENTER, 63 }; 64 65 enum rockchip_cmd_type { 66 CMD_TYPE_DEFAULT, 67 CMD_TYPE_SPI, 68 CMD_TYPE_MCU 69 }; 70 71 enum rockchip_mcu_cmd { 72 MCU_WRCMD = 0, 73 MCU_WRDATA, 74 MCU_SETBYPASS, 75 }; 76 77 /* 78 * display output interface supported by rockchip lcdc 79 */ 80 #define ROCKCHIP_OUT_MODE_P888 0 81 #define ROCKCHIP_OUT_MODE_BT1120 0 82 #define ROCKCHIP_OUT_MODE_P666 1 83 #define ROCKCHIP_OUT_MODE_P565 2 84 #define ROCKCHIP_OUT_MODE_BT656 5 85 #define ROCKCHIP_OUT_MODE_S666 9 86 #define ROCKCHIP_OUT_MODE_S888 8 87 #define ROCKCHIP_OUT_MODE_YUV422 9 88 #define ROCKCHIP_OUT_MODE_S565 10 89 #define ROCKCHIP_OUT_MODE_S888_DUMMY 12 90 #define ROCKCHIP_OUT_MODE_YUV420 14 91 /* for use special outface */ 92 #define ROCKCHIP_OUT_MODE_AAAA 15 93 94 #define VOP_OUTPUT_IF_RGB BIT(0) 95 #define VOP_OUTPUT_IF_BT1120 BIT(1) 96 #define VOP_OUTPUT_IF_BT656 BIT(2) 97 #define VOP_OUTPUT_IF_LVDS0 BIT(3) 98 #define VOP_OUTPUT_IF_LVDS1 BIT(4) 99 #define VOP_OUTPUT_IF_MIPI0 BIT(5) 100 #define VOP_OUTPUT_IF_MIPI1 BIT(6) 101 #define VOP_OUTPUT_IF_eDP0 BIT(7) 102 #define VOP_OUTPUT_IF_eDP1 BIT(8) 103 #define VOP_OUTPUT_IF_DP0 BIT(9) 104 #define VOP_OUTPUT_IF_DP1 BIT(10) 105 #define VOP_OUTPUT_IF_HDMI0 BIT(11) 106 #define VOP_OUTPUT_IF_HDMI1 BIT(12) 107 #define VOP_OUTPUT_IF_DP2 BIT(13) 108 109 struct rockchip_mcu_timing { 110 int mcu_pix_total; 111 int mcu_cs_pst; 112 int mcu_cs_pend; 113 int mcu_rw_pst; 114 int mcu_rw_pend; 115 int mcu_hold_mode; 116 }; 117 118 struct vop_rect { 119 int width; 120 int height; 121 }; 122 123 struct vop_urgency { 124 u8 urgen_thl; 125 u8 urgen_thh; 126 }; 127 128 struct rockchip_dsc_sink_cap { 129 /** 130 * @slice_width: the number of pixel columns that comprise the slice width 131 * @slice_height: the number of pixel rows that comprise the slice height 132 * @block_pred: Does block prediction 133 * @native_420: Does sink support DSC with 4:2:0 compression 134 * @bpc_supported: compressed bpc supported by sink : 10, 12 or 16 bpc 135 * @version_major: DSC major version 136 * @version_minor: DSC minor version 137 * @target_bits_per_pixel_x16: bits num after compress and multiply 16 138 */ 139 u16 slice_width; 140 u16 slice_height; 141 bool block_pred; 142 bool native_420; 143 u8 bpc_supported; 144 u8 version_major; 145 u8 version_minor; 146 u16 target_bits_per_pixel_x16; 147 }; 148 149 struct display_rect { 150 int x; 151 int y; 152 int w; 153 int h; 154 }; 155 156 struct bcsh_state { 157 int brightness; 158 int contrast; 159 int saturation; 160 int sin_hue; 161 int cos_hue; 162 }; 163 164 struct crtc_state { 165 struct udevice *dev; 166 struct rockchip_crtc *crtc; 167 void *private; 168 ofnode node; 169 struct device_node *ports_node; /* if (ports_node) it's vop2; */ 170 struct device_node *port_node; 171 struct clk dclk; 172 int crtc_id; 173 174 int format; 175 u32 dma_addr; 176 int ymirror; 177 int rb_swap; 178 int xvir; 179 int post_csc_mode; 180 int dclk_core_div; 181 int dclk_out_div; 182 struct display_rect src_rect; 183 struct display_rect crtc_rect; 184 struct display_rect right_src_rect; 185 struct display_rect right_crtc_rect; 186 bool yuv_overlay; 187 bool post_r2y_en; 188 bool post_y2r_en; 189 bool bcsh_en; 190 bool splice_mode; 191 bool soft_te; 192 u8 splice_crtc_id; 193 u8 dsc_id; 194 u8 dsc_enable; 195 u8 dsc_slice_num; 196 u8 dsc_pixel_num; 197 struct rockchip_mcu_timing mcu_timing; 198 u32 dual_channel_swap; 199 u32 feature; 200 struct vop_rect max_output; 201 202 u64 dsc_txp_clk_rate; 203 u64 dsc_pxl_clk_rate; 204 u64 dsc_cds_clk_rate; 205 struct drm_dsc_picture_parameter_set pps; 206 struct rockchip_dsc_sink_cap dsc_sink_cap; 207 208 u32 *lut_val; 209 }; 210 211 struct panel_state { 212 struct rockchip_panel *panel; 213 214 ofnode dsp_lut_node; 215 }; 216 217 struct overscan { 218 int left_margin; 219 int right_margin; 220 int top_margin; 221 int bottom_margin; 222 }; 223 224 struct connector_state { 225 struct rockchip_connector *connector; 226 struct rockchip_connector *secondary; 227 228 struct drm_display_mode mode; 229 struct overscan overscan; 230 u8 edid[EDID_SIZE * 4]; 231 int bus_format; 232 u32 bus_flags; 233 int output_mode; 234 int type; 235 int output_if; 236 int output_flags; 237 enum drm_color_encoding color_encoding; 238 enum drm_color_range color_range; 239 unsigned int bpc; 240 241 /** 242 * @hold_mode: enabled when it's: 243 * (1) mcu hold mode 244 * (2) mipi dsi cmd mode 245 * (3) edp psr mode 246 */ 247 bool hold_mode; 248 249 struct base2_disp_info *disp_info; /* disp_info from baseparameter 2.0 */ 250 251 u8 dsc_id; 252 u8 dsc_slice_num; 253 u8 dsc_pixel_num; 254 u64 dsc_txp_clk; 255 u64 dsc_pxl_clk; 256 u64 dsc_cds_clk; 257 struct rockchip_dsc_sink_cap dsc_sink_cap; 258 struct drm_dsc_picture_parameter_set pps; 259 260 struct gpio_desc *te_gpio; 261 262 struct { 263 u32 *lut; 264 int size; 265 } gamma; 266 }; 267 268 struct logo_info { 269 int mode; 270 int rotate; 271 char *mem; 272 bool ymirror; 273 u32 offset; 274 u32 width; 275 int height; 276 u32 bpp; 277 }; 278 279 struct rockchip_logo_cache { 280 struct list_head head; 281 char name[20]; 282 struct logo_info logo; 283 int logo_rotate; 284 }; 285 286 struct display_state { 287 struct list_head head; 288 289 const void *blob; 290 ofnode node; 291 292 struct crtc_state crtc_state; 293 struct connector_state conn_state; 294 struct panel_state panel_state; 295 296 char ulogo_name[30]; 297 char klogo_name[30]; 298 299 struct logo_info logo; 300 int logo_mode; 301 int charge_logo_mode; 302 int logo_rotate; 303 void *mem_base; 304 int mem_size; 305 306 int enable; 307 int is_init; 308 int is_enable; 309 bool is_klogo_valid; 310 bool force_output; 311 bool enabled_at_spl; 312 struct drm_display_mode force_mode; 313 u32 force_bus_format; 314 }; 315 316 int drm_mode_vrefresh(const struct drm_display_mode *mode); 317 int display_send_mcu_cmd(struct display_state *state, u32 type, u32 val); 318 bool drm_mode_is_420(const struct drm_display_info *display, 319 struct drm_display_mode *mode); 320 struct base2_disp_info *rockchip_get_disp_info(int type, int id); 321 322 void drm_mode_max_resolution_filter(struct hdmi_edid_data *edid_data, 323 struct vop_rect *max_output); 324 unsigned long get_cubic_lut_buffer(int crtc_id); 325 int rockchip_ofnode_get_display_mode(ofnode node, struct drm_display_mode *mode, 326 u32 *bus_flags); 327 void rockchip_display_make_crc32_table(void); 328 uint32_t rockchip_display_crc32c_cal(unsigned char *data, int length); 329 void drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags); 330 331 int display_rect_calc_hscale(struct display_rect *src, struct display_rect *dst, 332 int min_hscale, int max_hscale); 333 int display_rect_calc_vscale(struct display_rect *src, struct display_rect *dst, 334 int min_vscale, int max_vscale); 335 const struct device_node * 336 rockchip_of_graph_get_endpoint_by_regs(ofnode node, int port, int endpoint); 337 const struct device_node * 338 rockchip_of_graph_get_port_by_id(ofnode node, int id); 339 uint32_t rockchip_drm_get_cycles_per_pixel(uint32_t bus_format); 340 char* rockchip_get_output_if_name(u32 output_if, char *name); 341 342 #ifdef CONFIG_SPL_BUILD 343 int rockchip_spl_vop_probe(struct crtc_state *crtc_state); 344 int rockchip_spl_dw_hdmi_probe(struct connector_state *conn_state); 345 int inno_spl_hdmi_phy_probe(struct display_state *state); 346 #endif 347 #endif 348