1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ROCKCHIP_DISPLAY_H 8 #define _ROCKCHIP_DISPLAY_H 9 10 #ifdef CONFIG_SPL_BUILD 11 #include <linux/hdmi.h> 12 #include <linux/media-bus-format.h> 13 #else 14 #include <bmp_layout.h> 15 #include <edid.h> 16 #endif 17 #include <drm_modes.h> 18 #include <dm/ofnode.h> 19 #include <drm/drm_dsc.h> 20 #include <reset.h> 21 #include <spl_display.h> 22 #include <clk.h> 23 #include <drm/drm_color_mgmt.h> 24 25 /* 26 * major: IP major version, used for IP structure 27 * minor: big feature change under same structure 28 * build: RTL current SVN number 29 */ 30 #define VOP_VERSION(major, minor) ((major) << 8 | (minor)) 31 #define VOP_MAJOR(version) ((version) >> 8) 32 #define VOP_MINOR(version) ((version) & 0xff) 33 34 #define VOP2_VERSION(major, minor, build) ((major) << 24 | (minor) << 16 | (build)) 35 #define VOP2_MAJOR(version) (((version) >> 24) & 0xff) 36 #define VOP2_MINOR(version) (((version) >> 16) & 0xff) 37 #define VOP2_BUILD(version) ((version) & 0xffff) 38 39 #define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263) 40 #define VOP_VERSION_RK3562 VOP2_VERSION(0x50, 0x17, 0x4350) 41 #define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023) 42 #define VOP_VERSION_RK3576 VOP2_VERSION(0x50, 0x19, 0x9765) 43 #define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786) 44 45 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0) 46 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1) 47 #define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2) 48 #define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3) 49 50 #define ROCKCHIP_DSC_PPS_SIZE_BYTE 88 51 52 enum data_format { 53 ROCKCHIP_FMT_ARGB8888 = 0, 54 ROCKCHIP_FMT_RGB888, 55 ROCKCHIP_FMT_RGB565, 56 ROCKCHIP_FMT_YUV420SP = 4, 57 ROCKCHIP_FMT_YUV422SP, 58 ROCKCHIP_FMT_YUV444SP, 59 }; 60 61 enum display_mode { 62 ROCKCHIP_DISPLAY_FULLSCREEN, 63 ROCKCHIP_DISPLAY_CENTER, 64 }; 65 66 enum rockchip_cmd_type { 67 CMD_TYPE_DEFAULT, 68 CMD_TYPE_SPI, 69 CMD_TYPE_MCU 70 }; 71 72 enum rockchip_mcu_cmd { 73 MCU_WRCMD = 0, 74 MCU_WRDATA, 75 MCU_SETBYPASS, 76 }; 77 78 /* 79 * display output interface supported by rockchip lcdc 80 */ 81 #define ROCKCHIP_OUT_MODE_P888 0 82 #define ROCKCHIP_OUT_MODE_BT1120 0 83 #define ROCKCHIP_OUT_MODE_P666 1 84 #define ROCKCHIP_OUT_MODE_P565 2 85 #define ROCKCHIP_OUT_MODE_BT656 5 86 #define ROCKCHIP_OUT_MODE_S666 9 87 #define ROCKCHIP_OUT_MODE_S888 8 88 #define ROCKCHIP_OUT_MODE_YUV422 9 89 #define ROCKCHIP_OUT_MODE_S565 10 90 #define ROCKCHIP_OUT_MODE_S888_DUMMY 12 91 #define ROCKCHIP_OUT_MODE_YUV420 14 92 /* for use special outface */ 93 #define ROCKCHIP_OUT_MODE_AAAA 15 94 95 #define VOP_OUTPUT_IF_RGB BIT(0) 96 #define VOP_OUTPUT_IF_BT1120 BIT(1) 97 #define VOP_OUTPUT_IF_BT656 BIT(2) 98 #define VOP_OUTPUT_IF_LVDS0 BIT(3) 99 #define VOP_OUTPUT_IF_LVDS1 BIT(4) 100 #define VOP_OUTPUT_IF_MIPI0 BIT(5) 101 #define VOP_OUTPUT_IF_MIPI1 BIT(6) 102 #define VOP_OUTPUT_IF_eDP0 BIT(7) 103 #define VOP_OUTPUT_IF_eDP1 BIT(8) 104 #define VOP_OUTPUT_IF_DP0 BIT(9) 105 #define VOP_OUTPUT_IF_DP1 BIT(10) 106 #define VOP_OUTPUT_IF_HDMI0 BIT(11) 107 #define VOP_OUTPUT_IF_HDMI1 BIT(12) 108 #define VOP_OUTPUT_IF_DP2 BIT(13) 109 110 struct rockchip_mcu_timing { 111 int mcu_pix_total; 112 int mcu_cs_pst; 113 int mcu_cs_pend; 114 int mcu_rw_pst; 115 int mcu_rw_pend; 116 int mcu_hold_mode; 117 }; 118 119 struct vop_rect { 120 int width; 121 int height; 122 }; 123 124 struct vop_urgency { 125 u8 urgen_thl; 126 u8 urgen_thh; 127 }; 128 129 struct rockchip_dsc_sink_cap { 130 /** 131 * @slice_width: the number of pixel columns that comprise the slice width 132 * @slice_height: the number of pixel rows that comprise the slice height 133 * @block_pred: Does block prediction 134 * @native_420: Does sink support DSC with 4:2:0 compression 135 * @bpc_supported: compressed bpc supported by sink : 10, 12 or 16 bpc 136 * @version_major: DSC major version 137 * @version_minor: DSC minor version 138 * @target_bits_per_pixel_x16: bits num after compress and multiply 16 139 */ 140 u16 slice_width; 141 u16 slice_height; 142 bool block_pred; 143 bool native_420; 144 u8 bpc_supported; 145 u8 version_major; 146 u8 version_minor; 147 u16 target_bits_per_pixel_x16; 148 }; 149 150 struct display_rect { 151 int x; 152 int y; 153 int w; 154 int h; 155 }; 156 157 struct bcsh_state { 158 int brightness; 159 int contrast; 160 int saturation; 161 int sin_hue; 162 int cos_hue; 163 }; 164 165 struct crtc_state { 166 struct udevice *dev; 167 struct rockchip_crtc *crtc; 168 void *private; 169 ofnode node; 170 struct device_node *ports_node; /* if (ports_node) it's vop2; */ 171 struct device_node *port_node; 172 struct reset_ctl dclk_rst; 173 struct clk dclk; 174 int crtc_id; 175 176 int format; 177 u32 dma_addr; 178 int ymirror; 179 int rb_swap; 180 int xvir; 181 int post_csc_mode; 182 int dclk_core_div; 183 int dclk_out_div; 184 struct display_rect src_rect; 185 struct display_rect crtc_rect; 186 struct display_rect right_src_rect; 187 struct display_rect right_crtc_rect; 188 bool yuv_overlay; 189 bool post_r2y_en; 190 bool post_y2r_en; 191 bool bcsh_en; 192 bool splice_mode; 193 bool soft_te; 194 u8 splice_crtc_id; 195 u8 dsc_id; 196 u8 dsc_enable; 197 u8 dsc_slice_num; 198 u8 dsc_pixel_num; 199 struct rockchip_mcu_timing mcu_timing; 200 u32 dual_channel_swap; 201 u32 feature; 202 struct vop_rect max_output; 203 204 u64 dsc_txp_clk_rate; 205 u64 dsc_pxl_clk_rate; 206 u64 dsc_cds_clk_rate; 207 struct drm_dsc_picture_parameter_set pps; 208 struct rockchip_dsc_sink_cap dsc_sink_cap; 209 210 u32 *lut_val; 211 }; 212 213 struct panel_state { 214 struct rockchip_panel *panel; 215 216 ofnode dsp_lut_node; 217 }; 218 219 struct overscan { 220 int left_margin; 221 int right_margin; 222 int top_margin; 223 int bottom_margin; 224 }; 225 226 struct connector_state { 227 struct rockchip_connector *connector; 228 struct rockchip_connector *secondary; 229 230 struct drm_display_mode mode; 231 struct overscan overscan; 232 u8 edid[EDID_SIZE * 4]; 233 int bus_format; 234 u32 bus_flags; 235 int output_mode; 236 int type; 237 int output_if; 238 int output_flags; 239 enum drm_color_encoding color_encoding; 240 enum drm_color_range color_range; 241 unsigned int bpc; 242 243 /** 244 * @hold_mode: enabled when it's: 245 * (1) mcu hold mode 246 * (2) mipi dsi cmd mode 247 * (3) edp psr mode 248 */ 249 bool hold_mode; 250 251 struct base2_disp_info *disp_info; /* disp_info from baseparameter 2.0 */ 252 253 u8 dsc_id; 254 u8 dsc_slice_num; 255 u8 dsc_pixel_num; 256 u64 dsc_txp_clk; 257 u64 dsc_pxl_clk; 258 u64 dsc_cds_clk; 259 struct rockchip_dsc_sink_cap dsc_sink_cap; 260 struct drm_dsc_picture_parameter_set pps; 261 262 struct gpio_desc *te_gpio; 263 264 struct { 265 u32 *lut; 266 int size; 267 } gamma; 268 }; 269 270 struct logo_info { 271 int mode; 272 int rotate; 273 char *mem; 274 bool ymirror; 275 u32 offset; 276 u32 width; 277 int height; 278 u32 bpp; 279 }; 280 281 struct rockchip_logo_cache { 282 struct list_head head; 283 char name[20]; 284 struct logo_info logo; 285 int logo_rotate; 286 }; 287 288 struct display_state { 289 struct list_head head; 290 291 const void *blob; 292 ofnode node; 293 294 struct crtc_state crtc_state; 295 struct connector_state conn_state; 296 struct panel_state panel_state; 297 298 char ulogo_name[30]; 299 char klogo_name[30]; 300 301 struct logo_info logo; 302 int logo_mode; 303 int charge_logo_mode; 304 int logo_rotate; 305 void *mem_base; 306 int mem_size; 307 308 int enable; 309 int is_init; 310 int is_enable; 311 bool is_klogo_valid; 312 bool force_output; 313 bool enabled_at_spl; 314 struct drm_display_mode force_mode; 315 u32 force_bus_format; 316 }; 317 318 int drm_mode_vrefresh(const struct drm_display_mode *mode); 319 int display_send_mcu_cmd(struct display_state *state, u32 type, u32 val); 320 bool drm_mode_is_420(const struct drm_display_info *display, 321 struct drm_display_mode *mode); 322 struct base2_disp_info *rockchip_get_disp_info(int type, int id); 323 324 void drm_mode_max_resolution_filter(struct hdmi_edid_data *edid_data, 325 struct vop_rect *max_output); 326 unsigned long get_cubic_lut_buffer(int crtc_id); 327 int rockchip_ofnode_get_display_mode(ofnode node, struct drm_display_mode *mode, 328 u32 *bus_flags); 329 void rockchip_display_make_crc32_table(void); 330 uint32_t rockchip_display_crc32c_cal(unsigned char *data, int length); 331 void drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags); 332 void drm_mode_convert_to_origin_mode(struct drm_display_mode *mode); 333 void drm_mode_convert_to_split_mode(struct drm_display_mode *mode); 334 335 int display_rect_calc_hscale(struct display_rect *src, struct display_rect *dst, 336 int min_hscale, int max_hscale); 337 int display_rect_calc_vscale(struct display_rect *src, struct display_rect *dst, 338 int min_vscale, int max_vscale); 339 const struct device_node * 340 rockchip_of_graph_get_endpoint_by_regs(ofnode node, int port, int endpoint); 341 const struct device_node * 342 rockchip_of_graph_get_port_by_id(ofnode node, int id); 343 uint32_t rockchip_drm_get_cycles_per_pixel(uint32_t bus_format); 344 char* rockchip_get_output_if_name(u32 output_if, char *name); 345 346 #ifdef CONFIG_SPL_BUILD 347 int rockchip_spl_vop_probe(struct crtc_state *crtc_state); 348 int rockchip_spl_dw_hdmi_probe(struct connector_state *conn_state); 349 int inno_spl_hdmi_phy_probe(struct display_state *state); 350 #endif 351 #endif 352