1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ROCKCHIP_DISPLAY_H 8 #define _ROCKCHIP_DISPLAY_H 9 10 #include <bmp_layout.h> 11 #include <drm_modes.h> 12 #include <edid.h> 13 #include <dm/ofnode.h> 14 #include <drm/drm_dsc.h> 15 16 /* 17 * major: IP major version, used for IP structure 18 * minor: big feature change under same structure 19 * build: RTL current SVN number 20 */ 21 #define VOP_VERSION(major, minor) ((major) << 8 | (minor)) 22 #define VOP_MAJOR(version) ((version) >> 8) 23 #define VOP_MINOR(version) ((version) & 0xff) 24 25 #define VOP2_VERSION(major, minor, build) ((major) << 24 | (minor) << 16 | (build)) 26 #define VOP2_MAJOR(version) (((version) >> 24) & 0xff) 27 #define VOP2_MINOR(version) (((version) >> 16) & 0xff) 28 #define VOP2_BUILD(version) ((version) & 0xffff) 29 30 #define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263) 31 #define VOP_VERSION_RK3562 VOP2_VERSION(0x50, 0x17, 0x4350) 32 #define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023) 33 #define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786) 34 35 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0) 36 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1) 37 #define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2) 38 #define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3) 39 40 #define ROCKCHIP_DSC_PPS_SIZE_BYTE 88 41 42 enum data_format { 43 ROCKCHIP_FMT_ARGB8888 = 0, 44 ROCKCHIP_FMT_RGB888, 45 ROCKCHIP_FMT_RGB565, 46 ROCKCHIP_FMT_YUV420SP = 4, 47 ROCKCHIP_FMT_YUV422SP, 48 ROCKCHIP_FMT_YUV444SP, 49 }; 50 51 enum display_mode { 52 ROCKCHIP_DISPLAY_FULLSCREEN, 53 ROCKCHIP_DISPLAY_CENTER, 54 }; 55 56 enum rockchip_cmd_type { 57 CMD_TYPE_DEFAULT, 58 CMD_TYPE_SPI, 59 CMD_TYPE_MCU 60 }; 61 62 enum rockchip_mcu_cmd { 63 MCU_WRCMD = 0, 64 MCU_WRDATA, 65 MCU_SETBYPASS, 66 }; 67 68 /* 69 * display output interface supported by rockchip lcdc 70 */ 71 #define ROCKCHIP_OUT_MODE_P888 0 72 #define ROCKCHIP_OUT_MODE_BT1120 0 73 #define ROCKCHIP_OUT_MODE_P666 1 74 #define ROCKCHIP_OUT_MODE_P565 2 75 #define ROCKCHIP_OUT_MODE_BT656 5 76 #define ROCKCHIP_OUT_MODE_S888 8 77 #define ROCKCHIP_OUT_MODE_YUV422 9 78 #define ROCKCHIP_OUT_MODE_S888_DUMMY 12 79 #define ROCKCHIP_OUT_MODE_YUV420 14 80 /* for use special outface */ 81 #define ROCKCHIP_OUT_MODE_AAAA 15 82 83 #define VOP_OUTPUT_IF_RGB BIT(0) 84 #define VOP_OUTPUT_IF_BT1120 BIT(1) 85 #define VOP_OUTPUT_IF_BT656 BIT(2) 86 #define VOP_OUTPUT_IF_LVDS0 BIT(3) 87 #define VOP_OUTPUT_IF_LVDS1 BIT(4) 88 #define VOP_OUTPUT_IF_MIPI0 BIT(5) 89 #define VOP_OUTPUT_IF_MIPI1 BIT(6) 90 #define VOP_OUTPUT_IF_eDP0 BIT(7) 91 #define VOP_OUTPUT_IF_eDP1 BIT(8) 92 #define VOP_OUTPUT_IF_DP0 BIT(9) 93 #define VOP_OUTPUT_IF_DP1 BIT(10) 94 #define VOP_OUTPUT_IF_HDMI0 BIT(11) 95 #define VOP_OUTPUT_IF_HDMI1 BIT(12) 96 97 struct rockchip_mcu_timing { 98 int mcu_pix_total; 99 int mcu_cs_pst; 100 int mcu_cs_pend; 101 int mcu_rw_pst; 102 int mcu_rw_pend; 103 int mcu_hold_mode; 104 }; 105 106 struct vop_rect { 107 int width; 108 int height; 109 }; 110 111 struct rockchip_dsc_sink_cap { 112 /** 113 * @slice_width: the number of pixel columns that comprise the slice width 114 * @slice_height: the number of pixel rows that comprise the slice height 115 * @block_pred: Does block prediction 116 * @native_420: Does sink support DSC with 4:2:0 compression 117 * @bpc_supported: compressed bpc supported by sink : 10, 12 or 16 bpc 118 * @version_major: DSC major version 119 * @version_minor: DSC minor version 120 * @target_bits_per_pixel_x16: bits num after compress and multiply 16 121 */ 122 u16 slice_width; 123 u16 slice_height; 124 bool block_pred; 125 bool native_420; 126 u8 bpc_supported; 127 u8 version_major; 128 u8 version_minor; 129 u16 target_bits_per_pixel_x16; 130 }; 131 132 struct display_rect { 133 int x; 134 int y; 135 int w; 136 int h; 137 }; 138 139 struct bcsh_state { 140 int brightness; 141 int contrast; 142 int saturation; 143 int sin_hue; 144 int cos_hue; 145 }; 146 147 struct crtc_state { 148 struct udevice *dev; 149 struct rockchip_crtc *crtc; 150 void *private; 151 ofnode node; 152 struct device_node *ports_node; /* if (ports_node) it's vop2; */ 153 int crtc_id; 154 155 int format; 156 u32 dma_addr; 157 int ymirror; 158 int rb_swap; 159 int xvir; 160 int post_csc_mode; 161 int dclk_core_div; 162 int dclk_out_div; 163 struct display_rect src_rect; 164 struct display_rect crtc_rect; 165 struct display_rect right_src_rect; 166 struct display_rect right_crtc_rect; 167 bool yuv_overlay; 168 bool post_r2y_en; 169 bool post_y2r_en; 170 bool bcsh_en; 171 bool splice_mode; 172 u8 splice_crtc_id; 173 u8 dsc_id; 174 u8 dsc_enable; 175 u8 dsc_slice_num; 176 u8 dsc_pixel_num; 177 struct rockchip_mcu_timing mcu_timing; 178 u32 dual_channel_swap; 179 u32 feature; 180 struct vop_rect max_output; 181 182 u64 dsc_txp_clk_rate; 183 u64 dsc_pxl_clk_rate; 184 u64 dsc_cds_clk_rate; 185 struct drm_dsc_picture_parameter_set pps; 186 struct rockchip_dsc_sink_cap dsc_sink_cap; 187 }; 188 189 struct panel_state { 190 struct rockchip_panel *panel; 191 192 ofnode dsp_lut_node; 193 }; 194 195 struct overscan { 196 int left_margin; 197 int right_margin; 198 int top_margin; 199 int bottom_margin; 200 }; 201 202 struct connector_state { 203 struct rockchip_connector *connector; 204 struct rockchip_connector *secondary; 205 206 struct drm_display_mode mode; 207 struct overscan overscan; 208 u8 edid[EDID_SIZE * 4]; 209 int bus_format; 210 int output_mode; 211 int type; 212 int output_if; 213 int output_flags; 214 int color_space; 215 unsigned int bpc; 216 217 /** 218 * @hold_mode: enabled when it's: 219 * (1) mcu hold mode 220 * (2) mipi dsi cmd mode 221 * (3) edp psr mode 222 */ 223 bool hold_mode; 224 225 struct base2_disp_info *disp_info; /* disp_info from baseparameter 2.0 */ 226 227 u8 dsc_id; 228 u8 dsc_slice_num; 229 u8 dsc_pixel_num; 230 u64 dsc_txp_clk; 231 u64 dsc_pxl_clk; 232 u64 dsc_cds_clk; 233 struct rockchip_dsc_sink_cap dsc_sink_cap; 234 struct drm_dsc_picture_parameter_set pps; 235 236 struct { 237 u32 *lut; 238 int size; 239 } gamma; 240 }; 241 242 struct logo_info { 243 int mode; 244 char *mem; 245 bool ymirror; 246 u32 offset; 247 u32 width; 248 int height; 249 u32 bpp; 250 }; 251 252 struct rockchip_logo_cache { 253 struct list_head head; 254 char name[20]; 255 struct logo_info logo; 256 }; 257 258 struct display_state { 259 struct list_head head; 260 261 const void *blob; 262 ofnode node; 263 264 struct crtc_state crtc_state; 265 struct connector_state conn_state; 266 struct panel_state panel_state; 267 268 char ulogo_name[30]; 269 char klogo_name[30]; 270 271 struct logo_info logo; 272 int logo_mode; 273 int charge_logo_mode; 274 void *mem_base; 275 int mem_size; 276 277 int enable; 278 int is_init; 279 int is_enable; 280 bool is_klogo_valid; 281 bool force_output; 282 struct drm_display_mode force_mode; 283 u32 force_bus_format; 284 }; 285 286 int drm_mode_vrefresh(const struct drm_display_mode *mode); 287 int display_send_mcu_cmd(struct display_state *state, u32 type, u32 val); 288 bool drm_mode_is_420(const struct drm_display_info *display, 289 struct drm_display_mode *mode); 290 struct base2_disp_info *rockchip_get_disp_info(int type, int id); 291 292 void drm_mode_max_resolution_filter(struct hdmi_edid_data *edid_data, 293 struct vop_rect *max_output); 294 unsigned long get_cubic_lut_buffer(int crtc_id); 295 int rockchip_ofnode_get_display_mode(ofnode node, struct drm_display_mode *mode); 296 297 int display_rect_calc_hscale(struct display_rect *src, struct display_rect *dst, 298 int min_hscale, int max_hscale); 299 int display_rect_calc_vscale(struct display_rect *src, struct display_rect *dst, 300 int min_vscale, int max_vscale); 301 const struct device_node * 302 rockchip_of_graph_get_endpoint_by_regs(ofnode node, int port, int endpoint); 303 304 #endif 305