1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ROCKCHIP_DISPLAY_H 8 #define _ROCKCHIP_DISPLAY_H 9 10 #ifdef CONFIG_SPL_BUILD 11 #include <linux/hdmi.h> 12 #include <linux/media-bus-format.h> 13 #else 14 #include <bmp_layout.h> 15 #include <edid.h> 16 #endif 17 #include <drm_modes.h> 18 #include <dm/ofnode.h> 19 #include <drm/drm_dsc.h> 20 #include <reset.h> 21 #include <spl_display.h> 22 #include <clk.h> 23 #include <drm/drm_color_mgmt.h> 24 25 /* 26 * major: IP major version, used for IP structure 27 * minor: big feature change under same structure 28 * build: RTL current SVN number 29 */ 30 #define VOP_VERSION(major, minor) ((major) << 8 | (minor)) 31 #define VOP_MAJOR(version) ((version) >> 8) 32 #define VOP_MINOR(version) ((version) & 0xff) 33 34 #define VOP2_VERSION(major, minor, build) ((major) << 24 | (minor) << 16 | (build)) 35 #define VOP2_MAJOR(version) (((version) >> 24) & 0xff) 36 #define VOP2_MINOR(version) (((version) >> 16) & 0xff) 37 #define VOP2_BUILD(version) ((version) & 0xffff) 38 39 #define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263) 40 #define VOP_VERSION_RK3562 VOP2_VERSION(0x50, 0x17, 0x4350) 41 #define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023) 42 #define VOP_VERSION_RK3576 VOP2_VERSION(0x50, 0x19, 0x9765) 43 #define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786) 44 45 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0) 46 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1) 47 #define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2) 48 #define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3) 49 50 #define ROCKCHIP_DSC_PPS_SIZE_BYTE 88 51 52 enum data_format { 53 ROCKCHIP_FMT_ARGB8888 = 0, 54 ROCKCHIP_FMT_RGB888, 55 ROCKCHIP_FMT_RGB565, 56 ROCKCHIP_FMT_YUV420SP = 4, 57 ROCKCHIP_FMT_YUV422SP, 58 ROCKCHIP_FMT_YUV444SP, 59 }; 60 61 enum display_mode { 62 ROCKCHIP_DISPLAY_FULLSCREEN, 63 ROCKCHIP_DISPLAY_CENTER, 64 }; 65 66 enum rockchip_cmd_type { 67 CMD_TYPE_DEFAULT, 68 CMD_TYPE_SPI, 69 CMD_TYPE_MCU 70 }; 71 72 enum rockchip_mcu_cmd { 73 MCU_WRCMD = 0, 74 MCU_WRDATA, 75 MCU_SETBYPASS, 76 }; 77 78 /* 79 * display output interface supported by rockchip lcdc 80 */ 81 #define ROCKCHIP_OUT_MODE_P888 0 82 #define ROCKCHIP_OUT_MODE_BT1120 0 83 #define ROCKCHIP_OUT_MODE_P666 1 84 #define ROCKCHIP_OUT_MODE_P565 2 85 #define RK3588_EDP_OUTPUT_MODE_YUV422 3 86 #define ROCKCHIP_OUT_MODE_BT656 5 87 #define ROCKCHIP_OUT_MODE_S666 9 88 #define ROCKCHIP_OUT_MODE_S888 8 89 #define ROCKCHIP_OUT_MODE_YUV422 9 90 #define ROCKCHIP_OUT_MODE_S565 10 91 #define ROCKCHIP_OUT_MODE_S888_DUMMY 12 92 #define RK3588_DP_OUT_MODE_YUV422 12 93 #define RK3576_EDP_OUT_MODE_YUV422 12 94 #define RK3588_DP_OUT_MODE_YUV420 13 95 #define RK3576_HDMI_OUT_MODE_YUV422 13 96 #define ROCKCHIP_OUT_MODE_YUV420 14 97 /* for use special outface */ 98 #define ROCKCHIP_OUT_MODE_AAAA 15 99 100 #define VOP_OUTPUT_IF_RGB BIT(0) 101 #define VOP_OUTPUT_IF_BT1120 BIT(1) 102 #define VOP_OUTPUT_IF_BT656 BIT(2) 103 #define VOP_OUTPUT_IF_LVDS0 BIT(3) 104 #define VOP_OUTPUT_IF_LVDS1 BIT(4) 105 #define VOP_OUTPUT_IF_MIPI0 BIT(5) 106 #define VOP_OUTPUT_IF_MIPI1 BIT(6) 107 #define VOP_OUTPUT_IF_eDP0 BIT(7) 108 #define VOP_OUTPUT_IF_eDP1 BIT(8) 109 #define VOP_OUTPUT_IF_DP0 BIT(9) 110 #define VOP_OUTPUT_IF_DP1 BIT(10) 111 #define VOP_OUTPUT_IF_HDMI0 BIT(11) 112 #define VOP_OUTPUT_IF_HDMI1 BIT(12) 113 #define VOP_OUTPUT_IF_DP2 BIT(13) 114 115 struct rockchip_mcu_timing { 116 int mcu_pix_total; 117 int mcu_cs_pst; 118 int mcu_cs_pend; 119 int mcu_rw_pst; 120 int mcu_rw_pend; 121 int mcu_hold_mode; 122 }; 123 124 struct vop_rect { 125 int width; 126 int height; 127 }; 128 129 struct vop_urgency { 130 u8 urgen_thl; 131 u8 urgen_thh; 132 }; 133 134 struct rockchip_dsc_sink_cap { 135 /** 136 * @slice_width: the number of pixel columns that comprise the slice width 137 * @slice_height: the number of pixel rows that comprise the slice height 138 * @block_pred: Does block prediction 139 * @native_420: Does sink support DSC with 4:2:0 compression 140 * @bpc_supported: compressed bpc supported by sink : 10, 12 or 16 bpc 141 * @version_major: DSC major version 142 * @version_minor: DSC minor version 143 * @target_bits_per_pixel_x16: bits num after compress and multiply 16 144 */ 145 u16 slice_width; 146 u16 slice_height; 147 bool block_pred; 148 bool native_420; 149 u8 bpc_supported; 150 u8 version_major; 151 u8 version_minor; 152 u16 target_bits_per_pixel_x16; 153 }; 154 155 struct display_rect { 156 int x; 157 int y; 158 int w; 159 int h; 160 }; 161 162 struct bcsh_state { 163 int brightness; 164 int contrast; 165 int saturation; 166 int sin_hue; 167 int cos_hue; 168 }; 169 170 struct crtc_state { 171 struct udevice *dev; 172 struct rockchip_crtc *crtc; 173 void *private; 174 ofnode node; 175 struct device_node *ports_node; /* if (ports_node) it's vop2; */ 176 struct device_node *port_node; 177 struct reset_ctl dclk_rst; 178 struct clk dclk; 179 int crtc_id; 180 181 int format; 182 u32 dma_addr; 183 int ymirror; 184 int rb_swap; 185 int xvir; 186 int post_csc_mode; 187 int dclk_core_div; 188 int dclk_out_div; 189 struct display_rect src_rect; 190 struct display_rect crtc_rect; 191 struct display_rect right_src_rect; 192 struct display_rect right_crtc_rect; 193 bool yuv_overlay; 194 bool post_r2y_en; 195 bool post_y2r_en; 196 bool bcsh_en; 197 bool splice_mode; 198 bool soft_te; 199 u8 splice_crtc_id; 200 u8 dsc_id; 201 u8 dsc_enable; 202 u8 dsc_slice_num; 203 u8 dsc_pixel_num; 204 struct rockchip_mcu_timing mcu_timing; 205 u32 dual_channel_swap; 206 u32 feature; 207 struct vop_rect max_output; 208 209 u64 dsc_txp_clk_rate; 210 u64 dsc_pxl_clk_rate; 211 u64 dsc_cds_clk_rate; 212 struct drm_dsc_picture_parameter_set pps; 213 struct rockchip_dsc_sink_cap dsc_sink_cap; 214 215 u32 *lut_val; 216 }; 217 218 struct panel_state { 219 struct rockchip_panel *panel; 220 221 ofnode dsp_lut_node; 222 }; 223 224 struct overscan { 225 int left_margin; 226 int right_margin; 227 int top_margin; 228 int bottom_margin; 229 }; 230 231 struct connector_state { 232 struct rockchip_connector *connector; 233 struct rockchip_connector *secondary; 234 235 struct drm_display_mode mode; 236 struct overscan overscan; 237 u8 edid[EDID_SIZE * 4]; 238 int bus_format; 239 u32 bus_flags; 240 int output_mode; 241 int type; 242 int output_if; 243 int output_flags; 244 enum drm_color_encoding color_encoding; 245 enum drm_color_range color_range; 246 unsigned int bpc; 247 248 /** 249 * @hold_mode: enabled when it's: 250 * (1) mcu hold mode 251 * (2) mipi dsi cmd mode 252 * (3) edp psr mode 253 */ 254 bool hold_mode; 255 256 struct base2_disp_info *disp_info; /* disp_info from baseparameter 2.0 */ 257 258 u8 dsc_id; 259 u8 dsc_slice_num; 260 u8 dsc_pixel_num; 261 u64 dsc_txp_clk; 262 u64 dsc_pxl_clk; 263 u64 dsc_cds_clk; 264 struct rockchip_dsc_sink_cap dsc_sink_cap; 265 struct drm_dsc_picture_parameter_set pps; 266 267 struct gpio_desc *te_gpio; 268 269 struct { 270 u32 *lut; 271 int size; 272 } gamma; 273 }; 274 275 struct logo_info { 276 int mode; 277 int rotate; 278 char *mem; 279 bool ymirror; 280 u32 offset; 281 u32 width; 282 int height; 283 u32 bpp; 284 }; 285 286 struct rockchip_logo_cache { 287 struct list_head head; 288 char name[20]; 289 struct logo_info logo; 290 int logo_rotate; 291 }; 292 293 struct display_state { 294 struct list_head head; 295 296 const void *blob; 297 ofnode node; 298 299 struct crtc_state crtc_state; 300 struct connector_state conn_state; 301 struct panel_state panel_state; 302 303 char ulogo_name[30]; 304 char klogo_name[30]; 305 306 struct logo_info logo; 307 int logo_mode; 308 int charge_logo_mode; 309 int logo_rotate; 310 void *mem_base; 311 int mem_size; 312 313 int enable; 314 int is_init; 315 int is_enable; 316 bool is_klogo_valid; 317 bool force_output; 318 bool enabled_at_spl; 319 struct drm_display_mode force_mode; 320 u32 force_bus_format; 321 }; 322 323 int drm_mode_vrefresh(const struct drm_display_mode *mode); 324 int display_send_mcu_cmd(struct display_state *state, u32 type, u32 val); 325 bool drm_mode_is_420(const struct drm_display_info *display, 326 struct drm_display_mode *mode); 327 struct base2_disp_info *rockchip_get_disp_info(int type, int id); 328 329 void drm_mode_max_resolution_filter(struct hdmi_edid_data *edid_data, 330 struct vop_rect *max_output); 331 unsigned long get_cubic_lut_buffer(int crtc_id); 332 int rockchip_ofnode_get_display_mode(ofnode node, struct drm_display_mode *mode, 333 u32 *bus_flags); 334 void rockchip_display_make_crc32_table(void); 335 uint32_t rockchip_display_crc32c_cal(unsigned char *data, int length); 336 void drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags); 337 void drm_mode_convert_to_origin_mode(struct drm_display_mode *mode); 338 void drm_mode_convert_to_split_mode(struct drm_display_mode *mode); 339 340 int display_rect_calc_hscale(struct display_rect *src, struct display_rect *dst, 341 int min_hscale, int max_hscale); 342 int display_rect_calc_vscale(struct display_rect *src, struct display_rect *dst, 343 int min_vscale, int max_vscale); 344 const struct device_node * 345 rockchip_of_graph_get_endpoint_by_regs(ofnode node, int port, int endpoint); 346 const struct device_node * 347 rockchip_of_graph_get_port_by_id(ofnode node, int id); 348 uint32_t rockchip_drm_get_cycles_per_pixel(uint32_t bus_format); 349 char* rockchip_get_output_if_name(u32 output_if, char *name); 350 351 #ifdef CONFIG_SPL_BUILD 352 int rockchip_spl_vop_probe(struct crtc_state *crtc_state); 353 int rockchip_spl_dw_hdmi_probe(struct connector_state *conn_state); 354 int inno_spl_hdmi_phy_probe(struct display_state *state); 355 #endif 356 #endif 357