1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ROCKCHIP_DISPLAY_H 8 #define _ROCKCHIP_DISPLAY_H 9 10 #include <bmp_layout.h> 11 #include <drm_modes.h> 12 #include <edid.h> 13 #include <dm/ofnode.h> 14 #include <drm/drm_dsc.h> 15 16 /* 17 * major: IP major vertion, used for IP structure 18 * minor: big feature change under same structure 19 */ 20 #define VOP_VERSION(major, minor) ((major) << 8 | (minor)) 21 #define VOP_MAJOR(version) ((version) >> 8) 22 #define VOP_MINOR(version) ((version) & 0xff) 23 24 #define VOP_VERSION_RK3568 VOP_VERSION(0x40, 0x15) 25 #define VOP_VERSION_RK3588 VOP_VERSION(0x40, 0x17) 26 27 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0) 28 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1) 29 #define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2) 30 #define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3) 31 32 #define ROCKCHIP_DSC_PPS_SIZE_BYTE 88 33 34 enum data_format { 35 ROCKCHIP_FMT_ARGB8888 = 0, 36 ROCKCHIP_FMT_RGB888, 37 ROCKCHIP_FMT_RGB565, 38 ROCKCHIP_FMT_YUV420SP = 4, 39 ROCKCHIP_FMT_YUV422SP, 40 ROCKCHIP_FMT_YUV444SP, 41 }; 42 43 enum display_mode { 44 ROCKCHIP_DISPLAY_FULLSCREEN, 45 ROCKCHIP_DISPLAY_CENTER, 46 }; 47 48 enum rockchip_cmd_type { 49 CMD_TYPE_DEFAULT, 50 CMD_TYPE_SPI, 51 CMD_TYPE_MCU 52 }; 53 54 enum rockchip_mcu_cmd { 55 MCU_WRCMD = 0, 56 MCU_WRDATA, 57 MCU_SETBYPASS, 58 }; 59 60 /* 61 * display output interface supported by rockchip lcdc 62 */ 63 #define ROCKCHIP_OUT_MODE_P888 0 64 #define ROCKCHIP_OUT_MODE_BT1120 0 65 #define ROCKCHIP_OUT_MODE_P666 1 66 #define ROCKCHIP_OUT_MODE_P565 2 67 #define ROCKCHIP_OUT_MODE_BT656 5 68 #define ROCKCHIP_OUT_MODE_S888 8 69 #define ROCKCHIP_OUT_MODE_S888_DUMMY 12 70 #define ROCKCHIP_OUT_MODE_YUV420 14 71 /* for use special outface */ 72 #define ROCKCHIP_OUT_MODE_AAAA 15 73 74 #define VOP_OUTPUT_IF_RGB BIT(0) 75 #define VOP_OUTPUT_IF_BT1120 BIT(1) 76 #define VOP_OUTPUT_IF_BT656 BIT(2) 77 #define VOP_OUTPUT_IF_LVDS0 BIT(3) 78 #define VOP_OUTPUT_IF_LVDS1 BIT(4) 79 #define VOP_OUTPUT_IF_MIPI0 BIT(5) 80 #define VOP_OUTPUT_IF_MIPI1 BIT(6) 81 #define VOP_OUTPUT_IF_eDP0 BIT(7) 82 #define VOP_OUTPUT_IF_eDP1 BIT(8) 83 #define VOP_OUTPUT_IF_DP0 BIT(9) 84 #define VOP_OUTPUT_IF_DP1 BIT(10) 85 #define VOP_OUTPUT_IF_HDMI0 BIT(11) 86 #define VOP_OUTPUT_IF_HDMI1 BIT(12) 87 88 struct rockchip_mcu_timing { 89 int mcu_pix_total; 90 int mcu_cs_pst; 91 int mcu_cs_pend; 92 int mcu_rw_pst; 93 int mcu_rw_pend; 94 int mcu_hold_mode; 95 }; 96 97 struct vop_rect { 98 int width; 99 int height; 100 }; 101 102 struct rockchip_dsc_sink_cap { 103 /** 104 * @slice_width: the number of pixel columns that comprise the slice width 105 * @slice_height: the number of pixel rows that comprise the slice height 106 * @block_pred: Does block prediction 107 * @native_420: Does sink support DSC with 4:2:0 compression 108 * @bpc_supported: compressed bpc supported by sink : 10, 12 or 16 bpc 109 * @version_major: DSC major version 110 * @version_minor: DSC minor version 111 * @target_bits_per_pixel_x16: bits num after compress and multiply 16 112 */ 113 u16 slice_width; 114 u16 slice_height; 115 bool block_pred; 116 bool native_420; 117 u8 bpc_supported; 118 u8 version_major; 119 u8 version_minor; 120 u16 target_bits_per_pixel_x16; 121 }; 122 123 struct display_rect { 124 int x; 125 int y; 126 int w; 127 int h; 128 }; 129 130 struct bcsh_state { 131 int brightness; 132 int contrast; 133 int saturation; 134 int sin_hue; 135 int cos_hue; 136 }; 137 138 struct crtc_state { 139 struct udevice *dev; 140 struct rockchip_crtc *crtc; 141 void *private; 142 ofnode node; 143 struct device_node *ports_node; /* if (ports_node) it's vop2; */ 144 int crtc_id; 145 146 int format; 147 u32 dma_addr; 148 int ymirror; 149 int rb_swap; 150 int xvir; 151 int post_csc_mode; 152 int dclk_core_div; 153 int dclk_out_div; 154 struct display_rect src_rect; 155 struct display_rect crtc_rect; 156 struct display_rect right_src_rect; 157 struct display_rect right_crtc_rect; 158 bool yuv_overlay; 159 bool post_r2y_en; 160 bool post_y2r_en; 161 bool bcsh_en; 162 bool splice_mode; 163 u8 splice_crtc_id; 164 u8 dsc_id; 165 u8 dsc_enable; 166 u8 dsc_slice_num; 167 u8 dsc_pixel_num; 168 struct rockchip_mcu_timing mcu_timing; 169 u32 dual_channel_swap; 170 u32 feature; 171 struct vop_rect max_output; 172 173 u64 dsc_txp_clk_rate; 174 u64 dsc_pxl_clk_rate; 175 u64 dsc_cds_clk_rate; 176 struct drm_dsc_picture_parameter_set pps; 177 struct rockchip_dsc_sink_cap dsc_sink_cap; 178 }; 179 180 struct panel_state { 181 struct rockchip_panel *panel; 182 183 ofnode dsp_lut_node; 184 }; 185 186 struct overscan { 187 int left_margin; 188 int right_margin; 189 int top_margin; 190 int bottom_margin; 191 }; 192 193 struct connector_state { 194 struct rockchip_connector *connector; 195 struct rockchip_connector *secondary; 196 197 struct drm_display_mode mode; 198 struct overscan overscan; 199 u8 edid[EDID_SIZE * 4]; 200 int bus_format; 201 int output_mode; 202 int type; 203 int output_if; 204 int output_flags; 205 int color_space; 206 unsigned int bpc; 207 208 /** 209 * @hold_mode: enabled when it's: 210 * (1) mcu hold mode 211 * (2) mipi dsi cmd mode 212 * (3) edp psr mode 213 */ 214 bool hold_mode; 215 216 struct base2_disp_info *disp_info; /* disp_info from baseparameter 2.0 */ 217 218 u8 dsc_id; 219 u8 dsc_slice_num; 220 u8 dsc_pixel_num; 221 u64 dsc_txp_clk; 222 u64 dsc_pxl_clk; 223 u64 dsc_cds_clk; 224 struct rockchip_dsc_sink_cap dsc_sink_cap; 225 struct drm_dsc_picture_parameter_set pps; 226 227 struct { 228 u32 *lut; 229 int size; 230 } gamma; 231 }; 232 233 struct logo_info { 234 int mode; 235 char *mem; 236 bool ymirror; 237 u32 offset; 238 u32 width; 239 int height; 240 u32 bpp; 241 }; 242 243 struct rockchip_logo_cache { 244 struct list_head head; 245 char name[20]; 246 struct logo_info logo; 247 }; 248 249 struct display_state { 250 struct list_head head; 251 252 const void *blob; 253 ofnode node; 254 255 struct crtc_state crtc_state; 256 struct connector_state conn_state; 257 struct panel_state panel_state; 258 259 char ulogo_name[30]; 260 char klogo_name[30]; 261 262 struct logo_info logo; 263 int logo_mode; 264 int charge_logo_mode; 265 void *mem_base; 266 int mem_size; 267 268 int enable; 269 int is_init; 270 int is_enable; 271 bool force_output; 272 struct drm_display_mode force_mode; 273 u32 force_bus_format; 274 }; 275 276 int drm_mode_vrefresh(const struct drm_display_mode *mode); 277 int display_send_mcu_cmd(struct display_state *state, u32 type, u32 val); 278 bool drm_mode_is_420(const struct drm_display_info *display, 279 struct drm_display_mode *mode); 280 struct base2_disp_info *rockchip_get_disp_info(int type, int id); 281 282 void drm_mode_max_resolution_filter(struct hdmi_edid_data *edid_data, 283 struct vop_rect *max_output); 284 unsigned long get_cubic_lut_buffer(int crtc_id); 285 int rockchip_ofnode_get_display_mode(ofnode node, struct drm_display_mode *mode); 286 287 int display_rect_calc_hscale(struct display_rect *src, struct display_rect *dst, 288 int min_hscale, int max_hscale); 289 int display_rect_calc_vscale(struct display_rect *src, struct display_rect *dst, 290 int min_vscale, int max_vscale); 291 292 #endif 293