1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ROCKCHIP_DISPLAY_H 8 #define _ROCKCHIP_DISPLAY_H 9 10 #ifdef CONFIG_SPL_BUILD 11 #include <linux/hdmi.h> 12 #include <linux/media-bus-format.h> 13 #else 14 #include <bmp_layout.h> 15 #include <edid.h> 16 #endif 17 #include <drm_modes.h> 18 #include <dm/ofnode.h> 19 #include <drm/drm_dsc.h> 20 #include <reset.h> 21 #include <spl_display.h> 22 #include <clk.h> 23 #include <drm/drm_color_mgmt.h> 24 25 /* 26 * major: IP major version, used for IP structure 27 * minor: big feature change under same structure 28 * build: RTL current SVN number 29 */ 30 #define VOP_VERSION(major, minor) ((major) << 8 | (minor)) 31 #define VOP_MAJOR(version) ((version) >> 8) 32 #define VOP_MINOR(version) ((version) & 0xff) 33 34 #define VOP2_VERSION(major, minor, build) ((major) << 24 | (minor) << 16 | (build)) 35 #define VOP2_MAJOR(version) (((version) >> 24) & 0xff) 36 #define VOP2_MINOR(version) (((version) >> 16) & 0xff) 37 #define VOP2_BUILD(version) ((version) & 0xffff) 38 39 #define VOP_VERSION_RK3066 VOP_VERSION(2, 1) 40 #define VOP_VERSION_RK3036 VOP_VERSION(2, 2) 41 #define VOP_VERSION_RK3126 VOP_VERSION(2, 4) 42 #define VOP_VERSION_PX30_LITE VOP_VERSION(2, 5) 43 #define VOP_VERSION_PX30_BIG VOP_VERSION(2, 6) 44 #define VOP_VERSION_RK3308 VOP_VERSION(2, 7) 45 #define VOP_VERSION_RV1126 VOP_VERSION(2, 0xb) 46 #define VOP_VERSION_RV1106 VOP_VERSION(2, 0xc) 47 #define VOP_VERSION_RK3576_LITE VOP_VERSION(2, 0xd) 48 #define VOP_VERSION_RK3506 VOP_VERSION(2, 0xe) 49 #define VOP_VERSION_RV1126B VOP_VERSION(2, 0xf) 50 #define VOP_VERSION_RK3288 VOP_VERSION(3, 0) 51 #define VOP_VERSION_RK3288W VOP_VERSION(3, 1) 52 #define VOP_VERSION_RK3368 VOP_VERSION(3, 2) 53 #define VOP_VERSION_RK3366 VOP_VERSION(3, 4) 54 #define VOP_VERSION_RK3399_BIG VOP_VERSION(3, 5) 55 #define VOP_VERSION_RK3399_LITE VOP_VERSION(3, 6) 56 #define VOP_VERSION_RK3228 VOP_VERSION(3, 7) 57 #define VOP_VERSION_RK3328 VOP_VERSION(3, 8) 58 59 #define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263) 60 #define VOP_VERSION_RK3562 VOP2_VERSION(0x50, 0x17, 0x4350) 61 #define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023) 62 #define VOP_VERSION_RK3576 VOP2_VERSION(0x50, 0x19, 0x9765) 63 #define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786) 64 65 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0) 66 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1) 67 #define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2) 68 #define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3) 69 70 #define ROCKCHIP_DSC_PPS_SIZE_BYTE 88 71 72 #define ROCKCHIP_VOP2_SHARE_MODE_PRIMARY 1 73 #define ROCKCHIP_VOP2_SHARE_MODE_SECONDARY 2 74 75 enum data_format { 76 ROCKCHIP_FMT_ARGB8888 = 0, 77 ROCKCHIP_FMT_RGB888, 78 ROCKCHIP_FMT_RGB565, 79 ROCKCHIP_FMT_YUV420SP = 4, 80 ROCKCHIP_FMT_YUV422SP, 81 ROCKCHIP_FMT_YUV444SP, 82 }; 83 84 enum display_mode { 85 ROCKCHIP_DISPLAY_FULLSCREEN, 86 ROCKCHIP_DISPLAY_CENTER, 87 }; 88 89 enum rockchip_cmd_type { 90 CMD_TYPE_DEFAULT, 91 CMD_TYPE_SPI, 92 CMD_TYPE_MCU 93 }; 94 95 enum rockchip_mcu_cmd { 96 MCU_WRCMD = 0, 97 MCU_WRDATA, 98 MCU_SETBYPASS, 99 }; 100 101 /* 102 * display output interface supported by rockchip lcdc 103 */ 104 #define ROCKCHIP_OUT_MODE_P888 0 105 #define ROCKCHIP_OUT_MODE_BT1120 0 106 #define ROCKCHIP_OUT_MODE_P666 1 107 #define ROCKCHIP_OUT_MODE_P565 2 108 #define RK3588_EDP_OUTPUT_MODE_YUV422 3 109 #define ROCKCHIP_OUT_MODE_BT656 5 110 #define ROCKCHIP_OUT_MODE_S666 9 111 #define ROCKCHIP_OUT_MODE_S888 8 112 #define ROCKCHIP_OUT_MODE_YUV422 9 113 #define ROCKCHIP_OUT_MODE_S565 10 114 #define ROCKCHIP_OUT_MODE_S888_DUMMY 12 115 #define RK3588_DP_OUT_MODE_YUV422 12 116 #define RK3576_EDP_OUT_MODE_YUV422 12 117 #define RK3588_DP_OUT_MODE_YUV420 13 118 #define RK3576_HDMI_OUT_MODE_YUV422 13 119 #define ROCKCHIP_OUT_MODE_YUV420 14 120 /* for use special outface */ 121 #define ROCKCHIP_OUT_MODE_AAAA 15 122 123 #define VOP_OUTPUT_IF_RGB BIT(0) 124 #define VOP_OUTPUT_IF_BT1120 BIT(1) 125 #define VOP_OUTPUT_IF_BT656 BIT(2) 126 #define VOP_OUTPUT_IF_LVDS0 BIT(3) 127 #define VOP_OUTPUT_IF_LVDS1 BIT(4) 128 #define VOP_OUTPUT_IF_MIPI0 BIT(5) 129 #define VOP_OUTPUT_IF_MIPI1 BIT(6) 130 #define VOP_OUTPUT_IF_eDP0 BIT(7) 131 #define VOP_OUTPUT_IF_eDP1 BIT(8) 132 #define VOP_OUTPUT_IF_DP0 BIT(9) 133 #define VOP_OUTPUT_IF_DP1 BIT(10) 134 #define VOP_OUTPUT_IF_HDMI0 BIT(11) 135 #define VOP_OUTPUT_IF_HDMI1 BIT(12) 136 #define VOP_OUTPUT_IF_DP2 BIT(13) 137 138 struct rockchip_mcu_timing { 139 int mcu_pix_total; 140 int mcu_cs_pst; 141 int mcu_cs_pend; 142 int mcu_rw_pst; 143 int mcu_rw_pend; 144 int mcu_hold_mode; 145 }; 146 147 struct vop_rect { 148 int width; 149 int height; 150 }; 151 152 struct vop_urgency { 153 u8 urgen_thl; 154 u8 urgen_thh; 155 }; 156 157 struct rockchip_dsc_sink_cap { 158 /** 159 * @slice_width: the number of pixel columns that comprise the slice width 160 * @slice_height: the number of pixel rows that comprise the slice height 161 * @block_pred: Does block prediction 162 * @native_420: Does sink support DSC with 4:2:0 compression 163 * @bpc_supported: compressed bpc supported by sink : 10, 12 or 16 bpc 164 * @version_major: DSC major version 165 * @version_minor: DSC minor version 166 * @target_bits_per_pixel_x16: bits num after compress and multiply 16 167 */ 168 u16 slice_width; 169 u16 slice_height; 170 bool block_pred; 171 bool native_420; 172 u8 bpc_supported; 173 u8 version_major; 174 u8 version_minor; 175 u16 target_bits_per_pixel_x16; 176 }; 177 178 struct display_rect { 179 int x; 180 int y; 181 int w; 182 int h; 183 }; 184 185 struct bcsh_state { 186 int brightness; 187 int contrast; 188 int saturation; 189 int sin_hue; 190 int cos_hue; 191 }; 192 193 struct crtc_state { 194 struct udevice *dev; 195 struct rockchip_crtc *crtc; 196 void *private; 197 ofnode node; 198 struct device_node *ports_node; /* if (ports_node) it's vop2; */ 199 struct device_node *port_node; 200 struct reset_ctl dclk_rst; 201 struct clk dclk; 202 int crtc_id; 203 204 int format; 205 u32 dma_addr; 206 int ymirror; 207 int rb_swap; 208 int xvir; 209 int post_csc_mode; 210 int dclk_core_div; 211 int dclk_out_div; 212 struct display_rect src_rect; 213 struct display_rect crtc_rect; 214 struct display_rect right_src_rect; 215 struct display_rect right_crtc_rect; 216 bool yuv_overlay; 217 bool post_r2y_en; 218 bool post_y2r_en; 219 bool bcsh_en; 220 bool splice_mode; 221 bool soft_te; 222 bool overscan_by_win_scale; 223 u8 splice_crtc_id; 224 u8 dsc_id; 225 u8 dsc_enable; 226 u8 dsc_slice_num; 227 u8 dsc_pixel_num; 228 struct rockchip_mcu_timing mcu_timing; 229 u32 dual_channel_swap; 230 u32 feature; 231 struct vop_rect max_output; 232 233 u64 dsc_txp_clk_rate; 234 u64 dsc_pxl_clk_rate; 235 u64 dsc_cds_clk_rate; 236 struct drm_dsc_picture_parameter_set pps; 237 struct rockchip_dsc_sink_cap dsc_sink_cap; 238 239 u32 *lut_val; 240 }; 241 242 struct panel_state { 243 struct rockchip_panel *panel; 244 245 ofnode dsp_lut_node; 246 }; 247 248 struct overscan { 249 int left_margin; 250 int right_margin; 251 int top_margin; 252 int bottom_margin; 253 }; 254 255 struct connector_state { 256 struct rockchip_connector *connector; 257 struct rockchip_connector *secondary; 258 259 struct drm_display_mode mode; 260 struct overscan overscan; 261 u8 *edid; 262 int bus_format; 263 u32 bus_flags; 264 int output_mode; 265 int type; 266 int output_if; 267 int output_flags; 268 enum drm_color_encoding color_encoding; 269 enum drm_color_range color_range; 270 unsigned int bpc; 271 272 /** 273 * @hold_mode: enabled when it's: 274 * (1) mcu hold mode 275 * (2) mipi dsi cmd mode 276 * (3) edp psr mode 277 */ 278 bool hold_mode; 279 280 struct base2_disp_info *disp_info; /* disp_info from baseparameter 2.0 */ 281 282 u8 dsc_id; 283 u8 dsc_slice_num; 284 u8 dsc_pixel_num; 285 u64 dsc_txp_clk; 286 u64 dsc_pxl_clk; 287 u64 dsc_cds_clk; 288 struct rockchip_dsc_sink_cap dsc_sink_cap; 289 struct drm_dsc_picture_parameter_set pps; 290 291 struct gpio_desc *te_gpio; 292 293 struct { 294 u32 *lut; 295 int size; 296 } gamma; 297 }; 298 299 struct logo_info { 300 int mode; 301 int rotate; 302 char *mem; 303 bool ymirror; 304 u32 offset; 305 u32 width; 306 int height; 307 u32 bpp; 308 }; 309 310 struct rockchip_logo_cache { 311 struct list_head head; 312 char name[20]; 313 struct logo_info logo; 314 int logo_rotate; 315 }; 316 317 struct display_state { 318 struct list_head head; 319 320 const void *blob; 321 ofnode node; 322 323 struct crtc_state crtc_state; 324 struct connector_state conn_state; 325 struct panel_state panel_state; 326 327 char ulogo_name[30]; 328 char klogo_name[30]; 329 330 struct logo_info logo; 331 int logo_mode; 332 int charge_logo_mode; 333 int logo_rotate; 334 void *mem_base; 335 int mem_size; 336 337 int enable; 338 int is_init; 339 int is_enable; 340 bool is_klogo_valid; 341 bool force_output; 342 bool enabled_at_spl; 343 struct drm_display_mode force_mode; 344 u32 force_bus_format; 345 346 ulong vidcon_fb_addr; 347 }; 348 349 int drm_mode_vrefresh(const struct drm_display_mode *mode); 350 int display_send_mcu_cmd(struct display_state *state, u32 type, u32 val); 351 bool drm_mode_is_420_only(const struct drm_display_info *display, 352 struct drm_display_mode *mode); 353 bool drm_mode_is_420_also(const struct drm_display_info *display, 354 struct drm_display_mode *mode); 355 bool drm_mode_is_420(const struct drm_display_info *display, 356 struct drm_display_mode *mode); 357 struct base2_disp_info *rockchip_get_disp_info(int type, int id); 358 359 void drm_mode_max_resolution_filter(struct hdmi_edid_data *edid_data, 360 struct vop_rect *max_output); 361 unsigned long get_cubic_lut_buffer(int crtc_id); 362 int rockchip_ofnode_get_display_mode(ofnode node, struct drm_display_mode *mode, 363 u32 *bus_flags); 364 void rockchip_display_make_crc32_table(void); 365 uint32_t rockchip_display_crc32c_cal(unsigned char *data, int length); 366 void drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags); 367 void drm_mode_convert_to_origin_mode(struct drm_display_mode *mode); 368 void drm_mode_convert_to_split_mode(struct drm_display_mode *mode); 369 370 int display_rect_calc_hscale(struct display_rect *src, struct display_rect *dst, 371 int min_hscale, int max_hscale); 372 int display_rect_calc_vscale(struct display_rect *src, struct display_rect *dst, 373 int min_vscale, int max_vscale); 374 const struct device_node * 375 rockchip_of_graph_get_endpoint_by_regs(ofnode node, int port, int endpoint); 376 const struct device_node * 377 rockchip_of_graph_get_port_by_id(ofnode node, int id); 378 uint32_t rockchip_drm_get_cycles_per_pixel(uint32_t bus_format); 379 char* rockchip_get_output_if_name(u32 output_if, char *name); 380 381 #ifdef CONFIG_SPL_BUILD 382 int rockchip_spl_vop_probe(struct crtc_state *crtc_state); 383 int rockchip_spl_dw_hdmi_probe(struct connector_state *conn_state); 384 int inno_spl_hdmi_phy_probe(struct display_state *state); 385 #endif 386 #endif 387