xref: /rk3399_rockchip-uboot/drivers/video/drm/rockchip_display.h (revision 6414e3bc8687dbcc585b804d5c0bdfdb2d979c4b)
1186f8572SMark Yao /*
2186f8572SMark Yao  * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
3186f8572SMark Yao  *
4186f8572SMark Yao  * SPDX-License-Identifier:	GPL-2.0+
5186f8572SMark Yao  */
6186f8572SMark Yao 
7186f8572SMark Yao #ifndef _ROCKCHIP_DISPLAY_H
8186f8572SMark Yao #define _ROCKCHIP_DISPLAY_H
9186f8572SMark Yao 
10186f8572SMark Yao #include <bmp_layout.h>
11186f8572SMark Yao #include <drm_modes.h>
12186f8572SMark Yao #include <edid.h>
13e2bce6e4SKever Yang #include <dm/ofnode.h>
14186f8572SMark Yao 
15d0408543SAndy Yan #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE	BIT(0)
16d0408543SAndy Yan #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE	BIT(1)
17d0408543SAndy Yan #define ROCKCHIP_OUTPUT_DATA_SWAP			BIT(2)
18d0408543SAndy Yan 
19186f8572SMark Yao enum data_format {
20186f8572SMark Yao 	ROCKCHIP_FMT_ARGB8888 = 0,
21186f8572SMark Yao 	ROCKCHIP_FMT_RGB888,
22186f8572SMark Yao 	ROCKCHIP_FMT_RGB565,
23186f8572SMark Yao 	ROCKCHIP_FMT_YUV420SP = 4,
24186f8572SMark Yao 	ROCKCHIP_FMT_YUV422SP,
25186f8572SMark Yao 	ROCKCHIP_FMT_YUV444SP,
26186f8572SMark Yao };
27186f8572SMark Yao 
28186f8572SMark Yao enum display_mode {
29186f8572SMark Yao 	ROCKCHIP_DISPLAY_FULLSCREEN,
30186f8572SMark Yao 	ROCKCHIP_DISPLAY_CENTER,
31186f8572SMark Yao };
32186f8572SMark Yao 
3345fa51f3SSandy Huang enum rockchip_cmd_type {
3445fa51f3SSandy Huang 	CMD_TYPE_DEFAULT,
3545fa51f3SSandy Huang 	CMD_TYPE_SPI,
3645fa51f3SSandy Huang 	CMD_TYPE_MCU
3745fa51f3SSandy Huang };
3845fa51f3SSandy Huang 
3967b9012cSSandy Huang enum rockchip_mcu_cmd {
4067b9012cSSandy Huang 	MCU_WRCMD = 0,
4167b9012cSSandy Huang 	MCU_WRDATA,
4267b9012cSSandy Huang 	MCU_SETBYPASS,
4367b9012cSSandy Huang };
4467b9012cSSandy Huang 
45186f8572SMark Yao /*
46186f8572SMark Yao  * display output interface supported by rockchip lcdc
47186f8572SMark Yao  */
48186f8572SMark Yao #define ROCKCHIP_OUT_MODE_P888	0
49186f8572SMark Yao #define ROCKCHIP_OUT_MODE_P666	1
50186f8572SMark Yao #define ROCKCHIP_OUT_MODE_P565	2
5179feefb1SSandy Huang #define ROCKCHIP_OUT_MODE_S888		8
5279feefb1SSandy Huang #define ROCKCHIP_OUT_MODE_S888_DUMMY	12
5379feefb1SSandy Huang #define ROCKCHIP_OUT_MODE_YUV420	14
54186f8572SMark Yao /* for use special outface */
55186f8572SMark Yao #define ROCKCHIP_OUT_MODE_AAAA	15
56186f8572SMark Yao 
57d0408543SAndy Yan #define VOP_OUTPUT_IF_RGB	BIT(0)
58d0408543SAndy Yan #define VOP_OUTPUT_IF_BT1120	BIT(1)
59d0408543SAndy Yan #define VOP_OUTPUT_IF_BT656	BIT(2)
60d0408543SAndy Yan #define VOP_OUTPUT_IF_LVDS0	BIT(3)
61d0408543SAndy Yan #define VOP_OUTPUT_IF_LVDS1	BIT(4)
62d0408543SAndy Yan #define VOP_OUTPUT_IF_MIPI0	BIT(5)
63d0408543SAndy Yan #define VOP_OUTPUT_IF_MIPI1	BIT(6)
64d0408543SAndy Yan #define VOP_OUTPUT_IF_eDP0	BIT(7)
65d0408543SAndy Yan #define VOP_OUTPUT_IF_eDP1	BIT(8)
66d0408543SAndy Yan #define VOP_OUTPUT_IF_DP0	BIT(9)
67d0408543SAndy Yan #define VOP_OUTPUT_IF_DP1	BIT(10)
68d0408543SAndy Yan #define VOP_OUTPUT_IF_HDMI0	BIT(11)
69d0408543SAndy Yan #define VOP_OUTPUT_IF_HDMI1	BIT(12)
70d0408543SAndy Yan 
7167b9012cSSandy Huang struct rockchip_mcu_timing {
7267b9012cSSandy Huang 	int mcu_pix_total;
7367b9012cSSandy Huang 	int mcu_cs_pst;
7467b9012cSSandy Huang 	int mcu_cs_pend;
7567b9012cSSandy Huang 	int mcu_rw_pst;
7667b9012cSSandy Huang 	int mcu_rw_pend;
7767b9012cSSandy Huang 	int mcu_hold_mode;
7867b9012cSSandy Huang };
7967b9012cSSandy Huang 
80cf53642aSSandy Huang struct vop_rect {
81cf53642aSSandy Huang 	int width;
82cf53642aSSandy Huang 	int height;
83cf53642aSSandy Huang };
84cf53642aSSandy Huang 
85186f8572SMark Yao struct crtc_state {
86186f8572SMark Yao 	struct udevice *dev;
872a48727aSAlgea Cao 	struct rockchip_crtc *crtc;
88186f8572SMark Yao 	void *private;
89e2bce6e4SKever Yang 	ofnode node;
906eff7620SSandy Huang 	struct device_node *ports_node; /* if (ports_node) it's vop2; */
91186f8572SMark Yao 	int crtc_id;
92186f8572SMark Yao 
93186f8572SMark Yao 	int format;
94186f8572SMark Yao 	u32 dma_addr;
95186f8572SMark Yao 	int ymirror;
96186f8572SMark Yao 	int rb_swap;
97186f8572SMark Yao 	int xvir;
98186f8572SMark Yao 	int src_x;
99186f8572SMark Yao 	int src_y;
100186f8572SMark Yao 	int src_w;
101186f8572SMark Yao 	int src_h;
102186f8572SMark Yao 	int crtc_x;
103186f8572SMark Yao 	int crtc_y;
104186f8572SMark Yao 	int crtc_w;
105186f8572SMark Yao 	int crtc_h;
106b7618fd3SSandy Huang 	bool yuv_overlay;
10767b9012cSSandy Huang 	struct rockchip_mcu_timing mcu_timing;
108289af5f4SSandy Huang 	u32 dual_channel_swap;
10963cb669fSSandy Huang 	u32 feature;
110cf53642aSSandy Huang 	struct vop_rect max_output;
111186f8572SMark Yao };
112186f8572SMark Yao 
113186f8572SMark Yao struct panel_state {
1141a8d717cSWyon Bi 	struct rockchip_panel *panel;
115186f8572SMark Yao 
1161a8d717cSWyon Bi 	ofnode dsp_lut_node;
117186f8572SMark Yao };
118186f8572SMark Yao 
119b014f335SSandy Huang struct overscan {
120b014f335SSandy Huang 	int left_margin;
121b014f335SSandy Huang 	int right_margin;
122b014f335SSandy Huang 	int top_margin;
123b014f335SSandy Huang 	int bottom_margin;
124b014f335SSandy Huang };
125b014f335SSandy Huang 
126186f8572SMark Yao struct connector_state {
127186f8572SMark Yao 	struct udevice *dev;
128186f8572SMark Yao 	const struct rockchip_connector *connector;
1291a8d717cSWyon Bi 	struct rockchip_bridge *bridge;
13015081c50SWyon Bi 	struct rockchip_phy *phy;
131e2bce6e4SKever Yang 	ofnode node;
132186f8572SMark Yao 
133186f8572SMark Yao 	void *private;
134186f8572SMark Yao 
135186f8572SMark Yao 	struct drm_display_mode mode;
136b014f335SSandy Huang 	struct overscan overscan;
137186f8572SMark Yao 	u8 edid[EDID_SIZE * 4];
138186f8572SMark Yao 	int bus_format;
139186f8572SMark Yao 	int output_mode;
140186f8572SMark Yao 	int type;
141d0408543SAndy Yan 	int output_if;
142d0408543SAndy Yan 	int output_flags;
14379feefb1SSandy Huang 	int color_space;
1442a74799bSJianqun Xu 	unsigned int bpc;
145186f8572SMark Yao 
14650a9508eSSandy Huang 	struct base2_disp_info *disp_info; /* disp_info from baseparameter 2.0 */
14750a9508eSSandy Huang 
148186f8572SMark Yao 	struct {
149186f8572SMark Yao 		u32 *lut;
150186f8572SMark Yao 		int size;
151186f8572SMark Yao 	} gamma;
152186f8572SMark Yao };
153186f8572SMark Yao 
154186f8572SMark Yao struct logo_info {
155186f8572SMark Yao 	int mode;
156186f8572SMark Yao 	char *mem;
157186f8572SMark Yao 	bool ymirror;
158186f8572SMark Yao 	u32 offset;
159186f8572SMark Yao 	u32 width;
1607e72214dSShixiang Zheng 	int height;
161186f8572SMark Yao 	u32 bpp;
162186f8572SMark Yao };
163186f8572SMark Yao 
164186f8572SMark Yao struct rockchip_logo_cache {
165186f8572SMark Yao 	struct list_head head;
166186f8572SMark Yao 	char name[20];
167186f8572SMark Yao 	struct logo_info logo;
168186f8572SMark Yao };
169186f8572SMark Yao 
170186f8572SMark Yao struct display_state {
171186f8572SMark Yao 	struct list_head head;
1724b8c2ef1SMark Yao 
173186f8572SMark Yao 	const void *blob;
174e2bce6e4SKever Yang 	ofnode node;
1754b8c2ef1SMark Yao 
176186f8572SMark Yao 	struct crtc_state crtc_state;
177186f8572SMark Yao 	struct connector_state conn_state;
178186f8572SMark Yao 	struct panel_state panel_state;
1794b8c2ef1SMark Yao 
18054fc9addSSandy Huang 	char ulogo_name[30];
18154fc9addSSandy Huang 	char klogo_name[30];
1824b8c2ef1SMark Yao 
1834b8c2ef1SMark Yao 	struct logo_info logo;
1844b8c2ef1SMark Yao 	int logo_mode;
1854b8c2ef1SMark Yao 	int charge_logo_mode;
1864b8c2ef1SMark Yao 	void *mem_base;
1874b8c2ef1SMark Yao 	int mem_size;
1884b8c2ef1SMark Yao 
189186f8572SMark Yao 	int enable;
190186f8572SMark Yao 	int is_init;
191186f8572SMark Yao 	int is_enable;
192186f8572SMark Yao };
193186f8572SMark Yao 
1941a8d717cSWyon Bi static inline struct rockchip_panel *state_get_panel(struct display_state *s)
1951a8d717cSWyon Bi {
1961a8d717cSWyon Bi 	struct panel_state *panel_state = &s->panel_state;
1971a8d717cSWyon Bi 
1981a8d717cSWyon Bi 	return panel_state->panel;
1991a8d717cSWyon Bi }
2001a8d717cSWyon Bi 
201186f8572SMark Yao int drm_mode_vrefresh(const struct drm_display_mode *mode);
20267b9012cSSandy Huang int display_send_mcu_cmd(struct display_state *state, u32 type, u32 val);
2038e2bab3fSAlgea Cao bool drm_mode_is_420(const struct drm_display_info *display,
2048e2bab3fSAlgea Cao 		     struct drm_display_mode *mode);
20550a9508eSSandy Huang struct base2_disp_info *rockchip_get_disp_info(int type, int id);
206186f8572SMark Yao 
207cf53642aSSandy Huang void drm_mode_max_resolution_filter(struct hdmi_edid_data *edid_data,
208cf53642aSSandy Huang 				    struct vop_rect *max_output);
209*6414e3bcSSandy Huang unsigned long get_cubic_lut_buffer(int crtc_id);
210cf53642aSSandy Huang 
211186f8572SMark Yao #endif
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