1 /* 2 * SPDX-License-Identifier: GPL-2.0+ 3 * (C) Copyright 2008-2016 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #include <config.h> 7 #include <common.h> 8 #include <errno.h> 9 #include <malloc.h> 10 #include <misc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <asm/unaligned.h> 14 #include <dm/device.h> 15 #include <dm/read.h> 16 #include <asm/io.h> 17 #include <linux/list.h> 18 #include <div64.h> 19 #include <linux/media-bus-format.h> 20 21 #include "rockchip_display.h" 22 #include "rockchip_crtc.h" 23 #include "rockchip_connector.h" 24 #include "rockchip_phy.h" 25 26 #define INNO_HDMI_PHY_TIMEOUT_LOOP_COUNT 1000 27 /*#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))*/ 28 29 /* REG: 0x00 */ 30 #define PRE_PLL_REFCLK_SEL_MASK BIT(0) 31 #define PRE_PLL_REFCLK_SEL_PCLK BIT(0) 32 #define PRE_PLL_REFCLK_SEL_OSCCLK 0 33 /* REG: 0x01 */ 34 #define BYPASS_RXSENSE_EN_MASK BIT(2) 35 #define BYPASS_RXSENSE_EN BIT(2) 36 #define BYPASS_PWRON_EN_MASK BIT(1) 37 #define BYPASS_PWRON_EN BIT(1) 38 #define BYPASS_PLLPD_EN_MASK BIT(0) 39 #define BYPASS_PLLPD_EN BIT(0) 40 /* REG: 0x02 */ 41 #define BYPASS_PDATA_EN_MASK BIT(4) 42 #define BYPASS_PDATA_EN BIT(4) 43 #define PDATAEN_MASK BIT(0) 44 #define PDATAEN_DISABLE BIT(0) 45 #define PDATAEN_ENABLE 0 46 /* REG: 0x03 */ 47 #define BYPASS_AUTO_TERM_RES_CAL BIT(7) 48 #define AUDO_TERM_RES_CAL_SPEED_14_8(x) UPDATE(x, 6, 0) 49 /* REG: 0x04 */ 50 #define AUDO_TERM_RES_CAL_SPEED_7_0(x) UPDATE(x, 7, 0) 51 /* REG: 0xaa */ 52 #define POST_PLL_CTRL_MASK BIT(0) 53 #define POST_PLL_CTRL_MANUAL BIT(0) 54 /* REG: 0xe0 */ 55 #define POST_PLL_POWER_MASK BIT(5) 56 #define POST_PLL_POWER_DOWN BIT(5) 57 #define POST_PLL_POWER_UP 0 58 #define PRE_PLL_POWER_MASK BIT(4) 59 #define PRE_PLL_POWER_DOWN BIT(4) 60 #define PRE_PLL_POWER_UP 0 61 #define RXSENSE_CLK_CH_MASK BIT(3) 62 #define RXSENSE_CLK_CH_ENABLE BIT(3) 63 #define RXSENSE_DATA_CH2_MASK BIT(2) 64 #define RXSENSE_DATA_CH2_ENABLE BIT(2) 65 #define RXSENSE_DATA_CH1_MASK BIT(1) 66 #define RXSENSE_DATA_CH1_ENABLE BIT(1) 67 #define RXSENSE_DATA_CH0_MASK BIT(0) 68 #define RXSENSE_DATA_CH0_ENABLE BIT(0) 69 /* REG: 0xe1 */ 70 #define BANDGAP_MASK BIT(4) 71 #define BANDGAP_ENABLE BIT(4) 72 #define BANDGAP_DISABLE 0 73 #define TMDS_DRIVER_MASK GENMASK(3, 0) 74 #define TMDS_DRIVER_ENABLE UPDATE(0xf, 3, 0) 75 #define TMDS_DRIVER_DISABLE 0 76 /* REG: 0xe2 */ 77 #define PRE_PLL_FB_DIV_8_MASK BIT(7) 78 #define PRE_PLL_FB_DIV_8_SHIFT 7 79 #define PRE_PLL_FB_DIV_8(x) UPDATE(x, 7, 7) 80 #define PCLK_VCO_DIV_5_MASK BIT(5) 81 #define PCLK_VCO_DIV_5_SHIFT 5 82 #define PCLK_VCO_DIV_5(x) UPDATE(x, 5, 5) 83 #define PRE_PLL_PRE_DIV_MASK GENMASK(4, 0) 84 #define PRE_PLL_PRE_DIV(x) UPDATE(x, 4, 0) 85 /* REG: 0xe3 */ 86 #define PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0) 87 /* REG: 0xe4 */ 88 #define PRE_PLL_PCLK_DIV_B_MASK GENMASK(6, 5) 89 #define PRE_PLL_PCLK_DIV_B_SHIFT 5 90 #define PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5) 91 #define PRE_PLL_PCLK_DIV_A_MASK GENMASK(4, 0) 92 #define PRE_PLL_PCLK_DIV_A_SHIFT 0 93 #define PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0) 94 /* REG: 0xe5 */ 95 #define PRE_PLL_PCLK_DIV_C_MASK GENMASK(6, 5) 96 #define PRE_PLL_PCLK_DIV_C_SHIFT 5 97 #define PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5) 98 #define PRE_PLL_PCLK_DIV_D_MASK GENMASK(4, 0) 99 #define PRE_PLL_PCLK_DIV_D_SHIFT 0 100 #define PRE_PLL_PCLK_DIV_D(x) UPDATE(x, 4, 0) 101 /* REG: 0xe6 */ 102 #define PRE_PLL_TMDSCLK_DIV_C_MASK GENMASK(5, 4) 103 #define PRE_PLL_TMDSCLK_DIV_C(x) UPDATE(x, 5, 4) 104 #define PRE_PLL_TMDSCLK_DIV_A_MASK GENMASK(3, 2) 105 #define PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 3, 2) 106 #define PRE_PLL_TMDSCLK_DIV_B_MASK GENMASK(1, 0) 107 #define PRE_PLL_TMDSCLK_DIV_B(x) UPDATE(x, 1, 0) 108 /* REG: 0xe8 */ 109 #define PRE_PLL_LOCK_STATUS BIT(0) 110 /* REG: 0xe9 */ 111 #define POST_PLL_POST_DIV_EN_MASK GENMASK(7, 6) 112 #define POST_PLL_POST_DIV_ENABLE UPDATE(3, 7, 6) 113 #define POST_PLL_POST_DIV_DISABLE 0 114 #define POST_PLL_PRE_DIV_MASK GENMASK(4, 0) 115 #define POST_PLL_PRE_DIV(x) UPDATE(x, 4, 0) 116 /* REG: 0xea */ 117 #define POST_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0) 118 /* REG: 0xeb */ 119 #define POST_PLL_FB_DIV_8_MASK BIT(7) 120 #define POST_PLL_FB_DIV_8(x) UPDATE(x, 7, 7) 121 #define POST_PLL_POST_DIV_MASK GENMASK(5, 4) 122 #define POST_PLL_POST_DIV(x) UPDATE(x, 5, 4) 123 #define POST_PLL_LOCK_STATUS BIT(0) 124 /* REG: 0xee */ 125 #define TMDS_CH_TA_MASK GENMASK(7, 4) 126 #define TMDS_CH_TA_ENABLE UPDATE(0xf, 7, 4) 127 #define TMDS_CH_TA_DISABLE 0 128 /* REG: 0xef */ 129 #define TMDS_CLK_CH_TA(x) UPDATE(x, 7, 6) 130 #define TMDS_DATA_CH2_TA(x) UPDATE(x, 5, 4) 131 #define TMDS_DATA_CH1_TA(x) UPDATE(x, 3, 2) 132 #define TMDS_DATA_CH0_TA(x) UPDATE(x, 1, 0) 133 /* REG: 0xf0 */ 134 #define TMDS_DATA_CH2_PRE_EMPHASIS_MASK GENMASK(5, 4) 135 #define TMDS_DATA_CH2_PRE_EMPHASIS(x) UPDATE(x, 5, 4) 136 #define TMDS_DATA_CH1_PRE_EMPHASIS_MASK GENMASK(3, 2) 137 #define TMDS_DATA_CH1_PRE_EMPHASIS(x) UPDATE(x, 3, 2) 138 #define TMDS_DATA_CH0_PRE_EMPHASIS_MASK GENMASK(1, 0) 139 #define TMDS_DATA_CH0_PRE_EMPHASIS(x) UPDATE(x, 1, 0) 140 /* REG: 0xf1 */ 141 #define TMDS_CLK_CH_OUTPUT_SWING(x) UPDATE(x, 7, 4) 142 #define TMDS_DATA_CH2_OUTPUT_SWING(x) UPDATE(x, 3, 0) 143 /* REG: 0xf2 */ 144 #define TMDS_DATA_CH1_OUTPUT_SWING(x) UPDATE(x, 7, 4) 145 #define TMDS_DATA_CH0_OUTPUT_SWING(x) UPDATE(x, 3, 0) 146 147 enum inno_hdmi_phy_type { 148 INNO_HDMI_PHY_RK3228, 149 INNO_HDMI_PHY_RK3328 150 }; 151 152 struct inno_hdmi_phy_drv_data; 153 154 struct phy_config { 155 unsigned long tmdsclock; 156 u8 regs[14]; 157 }; 158 159 struct inno_hdmi_phy { 160 struct udevice *dev; 161 ofnode node; 162 void *regs; 163 164 /* platform data */ 165 const struct inno_hdmi_phy_drv_data *plat_data; 166 unsigned long pixclock; 167 u32 bus_width; 168 struct phy_config *phy_cfg; 169 }; 170 171 struct pre_pll_config { 172 unsigned long pixclock; 173 unsigned long tmdsclock; 174 u8 prediv; 175 u16 fbdiv; 176 u8 tmds_div_a; 177 u8 tmds_div_b; 178 u8 tmds_div_c; 179 u8 pclk_div_a; 180 u8 pclk_div_b; 181 u8 pclk_div_c; 182 u8 pclk_div_d; 183 u8 vco_div_5_en; 184 u32 fracdiv; 185 }; 186 187 struct post_pll_config { 188 unsigned long tmdsclock; 189 u8 prediv; 190 u16 fbdiv; 191 u8 postdiv; 192 u8 version; 193 }; 194 195 struct inno_hdmi_phy_ops { 196 void (*init)(struct inno_hdmi_phy *inno); 197 int (*power_on)(struct inno_hdmi_phy *inno, 198 const struct post_pll_config *cfg, 199 const struct phy_config *phy_cfg); 200 void (*power_off)(struct inno_hdmi_phy *inno); 201 int (*pre_pll_update)(struct inno_hdmi_phy *inno, 202 const struct pre_pll_config *cfg); 203 unsigned long (*recalc_rate)(struct inno_hdmi_phy *inno, 204 unsigned long parent_rate); 205 }; 206 207 struct inno_hdmi_phy_drv_data { 208 enum inno_hdmi_phy_type dev_type; 209 const struct inno_hdmi_phy_ops *ops; 210 const struct phy_config *phy_cfg_table; 211 }; 212 213 struct rockchip_inno_data { 214 char compatible[30]; 215 const void *data; 216 }; 217 218 static const struct pre_pll_config pre_pll_cfg_table[] = { 219 { 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0}, 220 { 27000000, 33750000, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0}, 221 { 40000000, 40000000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0}, 222 { 59341000, 59341000, 1, 98, 3, 1, 2, 1, 3, 3, 4, 0, 0xE6AE6B}, 223 { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0}, 224 { 59341000, 74176250, 1, 98, 0, 3, 3, 1, 3, 3, 4, 0, 0xE6AE6B}, 225 { 59400000, 74250000, 1, 99, 1, 2, 2, 1, 3, 3, 4, 0, 0}, 226 { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B}, 227 { 74250000, 74250000, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0}, 228 { 74176000, 92720000, 4, 494, 1, 2, 2, 1, 3, 3, 4, 0, 0x816817}, 229 { 74250000, 92812500, 4, 495, 1, 2, 2, 1, 3, 3, 4, 0, 0}, 230 {148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B}, 231 {148500000, 148500000, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0}, 232 {148352000, 185440000, 4, 494, 0, 2, 2, 1, 3, 2, 2, 0, 0x816817}, 233 {148500000, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0}, 234 {296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B}, 235 {297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0}, 236 {296703000, 370878750, 4, 494, 1, 2, 0, 1, 3, 1, 1, 0, 0x816817}, 237 {297000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 0, 0}, 238 {593407000, 296703500, 1, 98, 0, 1, 1, 1, 0, 2, 1, 0, 0xE6AE6B}, 239 {594000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 1, 0, 0}, 240 {593407000, 370879375, 4, 494, 1, 2, 0, 1, 3, 1, 1, 1, 0x816817}, 241 {594000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 1, 0}, 242 {593407000, 593407000, 1, 98, 0, 2, 0, 1, 0, 1, 1, 0, 0xE6AE6B}, 243 {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0}, 244 { ~0UL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 245 }; 246 247 static const struct post_pll_config post_pll_cfg_table[] = { 248 {33750000, 1, 40, 8, 1}, 249 {33750000, 1, 80, 8, 2}, 250 {33750000, 1, 10, 2, 4}, 251 {74250000, 1, 40, 8, 1}, 252 {74250000, 18, 80, 8, 2}, 253 {148500000, 2, 40, 4, 3}, 254 {297000000, 4, 40, 2, 3}, 255 {594000000, 8, 40, 1, 3}, 256 { ~0UL, 0, 0, 0, 0} 257 }; 258 259 static const struct phy_config rk3228_phy_cfg[] = { 260 { 165000000, { 261 0xaa, 0x00, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 262 0x00, 0x00, 0x00, 0x00, 0x00, 263 }, 264 }, { 265 340000000, { 266 0xaa, 0x15, 0x6a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 267 0x00, 0x00, 0x00, 0x00, 0x00, 268 }, 269 }, { 270 594000000, { 271 0xaa, 0x15, 0x7a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 272 0x00, 0x00, 0x00, 0x00, 0x00, 273 }, 274 }, { 275 ~0UL, { 276 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 277 0x00, 0x00, 0x00, 0x00, 0x00, 278 }, 279 } 280 }; 281 282 static const struct phy_config rk3328_phy_cfg[] = { 283 { 165000000, { 284 0x07, 0x08, 0x08, 0x08, 0x00, 0x00, 0x08, 0x08, 0x08, 285 0x00, 0xac, 0xcc, 0xcc, 0xcc, 286 }, 287 }, { 288 340000000, { 289 0x0b, 0x0d, 0x0d, 0x0d, 0x07, 0x15, 0x08, 0x08, 0x08, 290 0x3f, 0xac, 0xcc, 0xcd, 0xdd, 291 }, 292 }, { 293 594000000, { 294 0x10, 0x1a, 0x1a, 0x1a, 0x07, 0x15, 0x08, 0x08, 0x08, 295 0x00, 0xac, 0xcc, 0xcc, 0xcc, 296 }, 297 }, { 298 ~0UL, { 299 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 300 0x00, 0x00, 0x00, 0x00, 0x00, 301 }, 302 } 303 }; 304 305 static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val) 306 { 307 writel(val, inno->regs + (reg * 4)); 308 } 309 310 static inline u8 inno_read(struct inno_hdmi_phy *inno, u32 reg) 311 { 312 u32 val; 313 314 val = readl(inno->regs + (reg * 4)); 315 316 return val; 317 } 318 319 static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg, 320 u8 mask, u8 val) 321 { 322 u32 tmp, orig; 323 324 orig = inno_read(inno, reg); 325 tmp = orig & ~mask; 326 tmp |= val & mask; 327 inno_write(inno, reg, tmp); 328 } 329 330 static u32 inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno, 331 unsigned long rate) 332 { 333 u32 tmdsclk; 334 335 switch (inno->bus_width) { 336 case 4: 337 tmdsclk = (u32)rate / 2; 338 break; 339 case 5: 340 tmdsclk = (u32)rate * 5 / 8; 341 break; 342 case 6: 343 tmdsclk = (u32)rate * 3 / 4; 344 break; 345 case 10: 346 tmdsclk = (u32)rate * 5 / 4; 347 break; 348 case 12: 349 tmdsclk = (u32)rate * 3 / 2; 350 break; 351 case 16: 352 tmdsclk = (u32)rate * 2; 353 break; 354 default: 355 tmdsclk = rate; 356 } 357 358 return tmdsclk; 359 } 360 361 static u8 rk_get_cpu_version(void) 362 { 363 u8 val = 0; 364 #ifdef CONFIG_ROCKCHIP_EFUSE 365 struct udevice *dev; 366 u32 regs[2] = {0}; 367 u8 fuses[1]; 368 ofnode node; 369 int ret; 370 371 ret = uclass_get_device_by_driver(UCLASS_MISC, 372 DM_GET_DRIVER(rockchip_efuse), &dev); 373 if (ret) { 374 printf("%s: no misc-device found\n", __func__); 375 return -EINVAL; 376 } 377 378 node = dev_read_subnode(dev, "cpu-version"); 379 if (!ofnode_valid(node)) 380 return -EINVAL; 381 382 ret = ofnode_read_u32_array(node, "reg", regs, 2); 383 if (ret) { 384 printf("Cannot get efuse reg\n"); 385 return -EINVAL; 386 } 387 388 ret = misc_read(dev, regs[0], &fuses, regs[1]); 389 if (ret) { 390 printf("%s: misc_read failed\n", __func__); 391 return 0; 392 } 393 394 val = fuses[0]; 395 val = (val >> 3) & 0x1; 396 #endif 397 return val; 398 } 399 400 static int inno_hdmi_phy_power_on(struct rockchip_phy *phy) 401 { 402 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); 403 const struct post_pll_config *cfg = post_pll_cfg_table; 404 const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table; 405 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, inno->pixclock); 406 u32 chipversion = 1; 407 408 printf("start Inno HDMI PHY Power On\n"); 409 410 if (inno->phy_cfg) 411 phy_cfg = inno->phy_cfg; 412 413 if (!tmdsclock) { 414 printf("TMDS clock is zero!\n"); 415 return -EINVAL; 416 } 417 418 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3328 && 419 rk_get_cpu_version()) 420 chipversion = 2; 421 else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228 && 422 tmdsclock <= 33750000) 423 chipversion = 4; 424 425 printf("tmdsclock = %d; chipversion = %d\n", tmdsclock, chipversion); 426 427 for (; cfg->tmdsclock != ~0UL; cfg++) 428 if (tmdsclock <= cfg->tmdsclock && 429 cfg->version & chipversion) 430 break; 431 432 for (; phy_cfg->tmdsclock != ~0UL; phy_cfg++) 433 if (tmdsclock <= phy_cfg->tmdsclock) 434 break; 435 436 if (cfg->tmdsclock == ~0UL || phy_cfg->tmdsclock == ~0UL) 437 return -EINVAL; 438 439 printf("Inno HDMI PHY Power On\n"); 440 if (inno->plat_data->ops->power_on) 441 return inno->plat_data->ops->power_on(inno, cfg, phy_cfg); 442 else 443 return -EINVAL; 444 } 445 446 static int inno_hdmi_phy_power_off(struct rockchip_phy *phy) 447 { 448 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); 449 450 if (inno->plat_data->ops->power_off) 451 inno->plat_data->ops->power_off(inno); 452 printf("Inno HDMI PHY Power Off\n"); 453 454 return 0; 455 } 456 457 static int inno_hdmi_phy_clk_is_prepared(struct inno_hdmi_phy *inno) 458 { 459 u8 status; 460 461 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) 462 status = inno_read(inno, 0xe0) & PRE_PLL_POWER_MASK; 463 else 464 status = inno_read(inno, 0xa0) & 1; 465 466 return status ? 0 : 1; 467 } 468 469 static int inno_hdmi_phy_clk_prepare(struct inno_hdmi_phy *inno) 470 { 471 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) 472 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, 473 PRE_PLL_POWER_UP); 474 else 475 inno_update_bits(inno, 0xa0, 1, 0); 476 477 return 0; 478 } 479 480 static int inno_hdmi_phy_clk_set_rate(struct inno_hdmi_phy *inno, 481 unsigned long rate) 482 { 483 const struct pre_pll_config *cfg = pre_pll_cfg_table; 484 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate); 485 486 for (; cfg->pixclock != ~0UL; cfg++) 487 if (cfg->pixclock == rate && cfg->tmdsclock == tmdsclock) 488 break; 489 490 if (cfg->pixclock == ~0UL) { 491 printf("unsupported rate %lu\n", rate); 492 return -EINVAL; 493 } 494 495 if (inno->plat_data->ops->pre_pll_update) 496 inno->plat_data->ops->pre_pll_update(inno, cfg); 497 498 inno->pixclock = rate; 499 500 return 0; 501 } 502 503 static void inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno) 504 { 505 u32 m, v; 506 507 /* 508 * Use phy internal register control 509 * rxsense/poweron/pllpd/pdataen signal. 510 */ 511 m = BYPASS_RXSENSE_EN_MASK | BYPASS_PWRON_EN_MASK | 512 BYPASS_PLLPD_EN_MASK; 513 v = BYPASS_RXSENSE_EN | BYPASS_PWRON_EN | BYPASS_PLLPD_EN; 514 inno_update_bits(inno, 0x01, m, v); 515 inno_update_bits(inno, 0x02, BYPASS_PDATA_EN_MASK, BYPASS_PDATA_EN); 516 517 /* manual power down post-PLL */ 518 inno_update_bits(inno, 0xaa, POST_PLL_CTRL_MASK, POST_PLL_CTRL_MANUAL); 519 } 520 521 static int 522 inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy *inno, 523 const struct post_pll_config *cfg, 524 const struct phy_config *phy_cfg) 525 { 526 int pll_tries; 527 u32 m, v; 528 529 /* pdata_en disable */ 530 inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_DISABLE); 531 532 /* Power down Post-PLL */ 533 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN); 534 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN); 535 536 /* Post-PLL update */ 537 m = POST_PLL_PRE_DIV_MASK; 538 v = POST_PLL_PRE_DIV(cfg->prediv); 539 inno_update_bits(inno, 0xe9, m, v); 540 541 m = POST_PLL_FB_DIV_8_MASK; 542 v = POST_PLL_FB_DIV_8(cfg->fbdiv >> 8); 543 inno_update_bits(inno, 0xeb, m, v); 544 inno_write(inno, 0xea, POST_PLL_FB_DIV_7_0(cfg->fbdiv)); 545 546 if (cfg->postdiv == 1) { 547 /* Disable Post-PLL post divider */ 548 m = POST_PLL_POST_DIV_EN_MASK; 549 v = POST_PLL_POST_DIV_DISABLE; 550 inno_update_bits(inno, 0xe9, m, v); 551 } else { 552 /* Enable Post-PLL post divider */ 553 m = POST_PLL_POST_DIV_EN_MASK; 554 v = POST_PLL_POST_DIV_ENABLE; 555 inno_update_bits(inno, 0xe9, m, v); 556 557 m = POST_PLL_POST_DIV_MASK; 558 v = POST_PLL_POST_DIV(cfg->postdiv / 2 - 1); 559 inno_update_bits(inno, 0xeb, m, v); 560 } 561 562 for (v = 0; v < 4; v++) 563 inno_write(inno, 0xef + v, phy_cfg->regs[v]); 564 565 /* Power up Post-PLL */ 566 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_UP); 567 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP); 568 569 /* BandGap enable */ 570 inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_ENABLE); 571 572 /* TMDS driver enable */ 573 inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_ENABLE); 574 575 /* Wait for post PLL lock */ 576 pll_tries = 0; 577 while (!(inno_read(inno, 0xeb) & POST_PLL_LOCK_STATUS)) { 578 if (pll_tries == INNO_HDMI_PHY_TIMEOUT_LOOP_COUNT) { 579 printf("Post-PLL unlock\n"); 580 return -ETIMEDOUT; 581 } 582 583 pll_tries++; 584 udelay(100); 585 } 586 587 if (cfg->tmdsclock > 340000000) 588 mdelay(100); 589 590 /* pdata_en enable */ 591 inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_ENABLE); 592 return 0; 593 } 594 595 static void inno_hdmi_phy_rk3228_power_off(struct inno_hdmi_phy *inno) 596 { 597 /* TMDS driver Disable */ 598 inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_DISABLE); 599 600 /* BandGap Disable */ 601 inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_DISABLE); 602 603 /* Post-PLL power down */ 604 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN); 605 } 606 607 static int 608 inno_hdmi_phy_rk3228_pre_pll_update(struct inno_hdmi_phy *inno, 609 const struct pre_pll_config *cfg) 610 { 611 int pll_tries; 612 u32 m, v; 613 614 /* Power down PRE-PLL */ 615 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN); 616 617 m = PRE_PLL_FB_DIV_8_MASK | PCLK_VCO_DIV_5_MASK | PRE_PLL_PRE_DIV_MASK; 618 v = PRE_PLL_FB_DIV_8(cfg->fbdiv >> 8) | 619 PCLK_VCO_DIV_5(cfg->vco_div_5_en) | PRE_PLL_PRE_DIV(cfg->prediv); 620 inno_update_bits(inno, 0xe2, m, v); 621 622 inno_write(inno, 0xe3, PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); 623 624 m = PRE_PLL_PCLK_DIV_B_MASK | PRE_PLL_PCLK_DIV_A_MASK; 625 v = PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b) | 626 PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a); 627 inno_update_bits(inno, 0xe4, m, v); 628 629 m = PRE_PLL_PCLK_DIV_C_MASK | PRE_PLL_PCLK_DIV_D_MASK; 630 v = PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) | 631 PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d); 632 inno_update_bits(inno, 0xe5, m, v); 633 634 m = PRE_PLL_TMDSCLK_DIV_C_MASK | PRE_PLL_TMDSCLK_DIV_A_MASK | 635 PRE_PLL_TMDSCLK_DIV_B_MASK; 636 v = PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) | 637 PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) | 638 PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b); 639 inno_update_bits(inno, 0xe6, m, v); 640 641 /* Power up PRE-PLL */ 642 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP); 643 644 /* Wait for Pre-PLL lock */ 645 pll_tries = 0; 646 while (!(inno_read(inno, 0xe8) & PRE_PLL_LOCK_STATUS)) { 647 if (pll_tries == INNO_HDMI_PHY_TIMEOUT_LOOP_COUNT) { 648 printf("Pre-PLL unlock\n"); 649 return -ETIMEDOUT; 650 } 651 652 pll_tries++; 653 udelay(100); 654 } 655 656 return 0; 657 } 658 659 static void inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno) 660 { 661 /* 662 * Use phy internal register control 663 * rxsense/poweron/pllpd/pdataen signal. 664 */ 665 inno_write(inno, 0x01, 0x07); 666 inno_write(inno, 0x02, 0x91); 667 } 668 669 static int 670 inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, 671 const struct post_pll_config *cfg, 672 const struct phy_config *phy_cfg) 673 { 674 u32 val; 675 676 /* set pdata_en to 0 */ 677 inno_update_bits(inno, 0x02, 1, 0); 678 /* Power off post PLL */ 679 inno_update_bits(inno, 0xaa, 1, 1); 680 681 val = cfg->fbdiv & 0xff; 682 inno_write(inno, 0xac, val); 683 if (cfg->postdiv == 1) { 684 inno_write(inno, 0xaa, 2); 685 val = (cfg->fbdiv >> 8) | cfg->prediv; 686 inno_write(inno, 0xab, val); 687 } else { 688 val = (cfg->postdiv / 2) - 1; 689 inno_write(inno, 0xad, val); 690 val = (cfg->fbdiv >> 8) | cfg->prediv; 691 inno_write(inno, 0xab, val); 692 inno_write(inno, 0xaa, 0x0e); 693 } 694 695 for (val = 0; val < 14; val++) 696 inno_write(inno, 0xb5 + val, phy_cfg->regs[val]); 697 698 /* bit[7:6] of reg c8/c9/ca/c8 is ESD detect threshold: 699 * 00 - 340mV 700 * 01 - 280mV 701 * 10 - 260mV 702 * 11 - 240mV 703 * default is 240mV, now we set it to 340mV 704 */ 705 inno_write(inno, 0xc8, 0); 706 inno_write(inno, 0xc9, 0); 707 inno_write(inno, 0xca, 0); 708 inno_write(inno, 0xcb, 0); 709 710 if (phy_cfg->tmdsclock > 340000000) { 711 /* Set termination resistor to 100ohm */ 712 val = 75000000 / 100000; 713 inno_write(inno, 0xc5, ((val >> 8) & 0xff) | 0x80); 714 inno_write(inno, 0xc6, val & 0xff); 715 inno_write(inno, 0xc7, 3 << 1); 716 inno_write(inno, 0xc5, ((val >> 8) & 0xff)); 717 } else if (phy_cfg->tmdsclock > 165000000) { 718 inno_write(inno, 0xc5, 0x81); 719 /* clk termination resistor is 50ohm 720 * data termination resistor is 150ohm 721 */ 722 inno_write(inno, 0xc8, 0x30); 723 inno_write(inno, 0xc9, 0x10); 724 inno_write(inno, 0xca, 0x10); 725 inno_write(inno, 0xcb, 0x10); 726 } else { 727 inno_write(inno, 0xc5, 0x81); 728 } 729 730 /* set TMDS sync detection counter length */ 731 val = 47520000000UL / phy_cfg->tmdsclock; 732 inno_write(inno, 0xd8, (val >> 8) & 0xff); 733 inno_write(inno, 0xd9, val & 0xff); 734 735 /* Power up post PLL */ 736 inno_update_bits(inno, 0xaa, 1, 0); 737 /* Power up tmds driver */ 738 inno_update_bits(inno, 0xb0, 4, 4); 739 inno_write(inno, 0xb2, 0x0f); 740 741 /* Wait for post PLL lock */ 742 for (val = 0; val < 5; val++) { 743 if (inno_read(inno, 0xaf) & 1) 744 break; 745 udelay(1000); 746 } 747 if (!(inno_read(inno, 0xaf) & 1)) { 748 printf("HDMI PHY Post PLL unlock\n"); 749 return -ETIMEDOUT; 750 } 751 if (phy_cfg->tmdsclock > 340000000) 752 mdelay(100); 753 /* set pdata_en to 1 */ 754 inno_update_bits(inno, 0x02, 1, 1); 755 756 return 0; 757 } 758 759 static void inno_hdmi_phy_rk3328_power_off(struct inno_hdmi_phy *inno) 760 { 761 /* Power off driver */ 762 inno_write(inno, 0xb2, 0); 763 /* Power off band gap */ 764 inno_update_bits(inno, 0xb0, 4, 0); 765 /* Power off post pll */ 766 inno_update_bits(inno, 0xaa, 1, 1); 767 } 768 769 static int 770 inno_hdmi_phy_rk3328_pre_pll_update(struct inno_hdmi_phy *inno, 771 const struct pre_pll_config *cfg) 772 { 773 u32 val; 774 775 /* Power off PLL */ 776 inno_update_bits(inno, 0xa0, 1, 1); 777 /* Configure pre-pll */ 778 inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1); 779 inno_write(inno, 0xa1, cfg->prediv); 780 if (cfg->fracdiv) 781 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xc0; 782 else 783 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xf0; 784 inno_write(inno, 0xa2, val); 785 inno_write(inno, 0xa3, cfg->fbdiv & 0xff); 786 val = (cfg->pclk_div_a & 0x1f) | 787 ((cfg->pclk_div_b & 3) << 5); 788 inno_write(inno, 0xa5, val); 789 val = (cfg->pclk_div_d & 0x1f) | 790 ((cfg->pclk_div_c & 3) << 5); 791 inno_write(inno, 0xa6, val); 792 val = ((cfg->tmds_div_a & 3) << 4) | 793 ((cfg->tmds_div_b & 3) << 2) | 794 (cfg->tmds_div_c & 3); 795 inno_write(inno, 0xa4, val); 796 797 if (cfg->fracdiv) { 798 val = cfg->fracdiv & 0xff; 799 inno_write(inno, 0xd3, val); 800 val = (cfg->fracdiv >> 8) & 0xff; 801 inno_write(inno, 0xd2, val); 802 val = (cfg->fracdiv >> 16) & 0xff; 803 inno_write(inno, 0xd1, val); 804 } else { 805 inno_write(inno, 0xd3, 0); 806 inno_write(inno, 0xd2, 0); 807 inno_write(inno, 0xd1, 0); 808 } 809 810 /* Power up PLL */ 811 inno_update_bits(inno, 0xa0, 1, 0); 812 813 /* Wait for PLL lock */ 814 for (val = 0; val < 5; val++) { 815 if (inno_read(inno, 0xa9) & 1) 816 break; 817 udelay(1000); 818 } 819 if (val == 5) { 820 printf("Pre-PLL unlock\n"); 821 return -ETIMEDOUT; 822 } 823 824 return 0; 825 } 826 827 static unsigned long 828 inno_hdmi_3328_phy_pll_recalc_rate(struct inno_hdmi_phy *inno, 829 unsigned long parent_rate) 830 { 831 unsigned long rate, vco, frac; 832 u8 nd, no_a, no_b, no_d; 833 __maybe_unused u8 no_c; 834 u16 nf; 835 836 nd = inno_read(inno, 0xa1) & 0x3f; 837 nf = ((inno_read(inno, 0xa2) & 0x0f) << 8) | inno_read(inno, 0xa3); 838 vco = parent_rate * nf; 839 if ((inno_read(inno, 0xa2) & 0x30) == 0) { 840 frac = inno_read(inno, 0xd3) | 841 (inno_read(inno, 0xd2) << 8) | 842 (inno_read(inno, 0xd1) << 16); 843 vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24)); 844 } 845 if (inno_read(inno, 0xa0) & 2) { 846 rate = vco / (nd * 5); 847 } else { 848 no_a = inno_read(inno, 0xa5) & 0x1f; 849 no_b = ((inno_read(inno, 0xa5) >> 5) & 7) + 2; 850 no_c = (1 << ((inno_read(inno, 0xa6) >> 5) & 7)); 851 no_d = inno_read(inno, 0xa6) & 0x1f; 852 if (no_a == 1) 853 rate = vco / (nd * no_b * no_d * 2); 854 else 855 rate = vco / (nd * no_a * no_d * 2); 856 } 857 inno->pixclock = rate; 858 859 return rate; 860 } 861 862 #define PHY_TAB_LEN 60 863 864 static 865 int inno_hdmi_update_phy_table(struct inno_hdmi_phy *inno, u32 *config, 866 struct phy_config *phy_cfg, 867 int phy_table_size) 868 { 869 int i, j; 870 871 for (i = 0; i < phy_table_size; i++) { 872 phy_cfg[i].tmdsclock = 873 (unsigned long)config[i * 15]; 874 875 debug("%ld ", phy_cfg[i].tmdsclock); 876 for (j = 0; j < 14; j++) { 877 phy_cfg[i].regs[j] = (u8)config[i * 15 + 1 + j]; 878 debug("0x%02x ", phy_cfg[i].regs[j]); 879 } 880 debug("\n"); 881 } 882 883 /* 884 * The last set of phy cfg is used to indicate whether 885 * there is no more phy cfg data. 886 */ 887 phy_cfg[i].tmdsclock = ~0UL; 888 for (j = 0; j < 14; j++) 889 phy_cfg[i].regs[j] = 0; 890 891 return 0; 892 } 893 894 static const struct inno_hdmi_phy_ops rk3228_hdmi_phy_ops = { 895 .init = inno_hdmi_phy_rk3228_init, 896 .power_on = inno_hdmi_phy_rk3228_power_on, 897 .power_off = inno_hdmi_phy_rk3228_power_off, 898 .pre_pll_update = inno_hdmi_phy_rk3228_pre_pll_update, 899 }; 900 901 static const struct inno_hdmi_phy_ops rk3328_hdmi_phy_ops = { 902 .init = inno_hdmi_phy_rk3328_init, 903 .power_on = inno_hdmi_phy_rk3328_power_on, 904 .power_off = inno_hdmi_phy_rk3328_power_off, 905 .pre_pll_update = inno_hdmi_phy_rk3328_pre_pll_update, 906 .recalc_rate = inno_hdmi_3328_phy_pll_recalc_rate, 907 }; 908 909 static const struct inno_hdmi_phy_drv_data rk3228_hdmi_phy_drv_data = { 910 .dev_type = INNO_HDMI_PHY_RK3228, 911 .ops = &rk3228_hdmi_phy_ops, 912 .phy_cfg_table = rk3228_phy_cfg, 913 }; 914 915 static const struct inno_hdmi_phy_drv_data rk3328_hdmi_phy_drv_data = { 916 .dev_type = INNO_HDMI_PHY_RK3328, 917 .ops = &rk3328_hdmi_phy_ops, 918 .phy_cfg_table = rk3328_phy_cfg, 919 }; 920 921 static const struct rockchip_inno_data inno_hdmi_phy_of_match[] = { 922 { .compatible = "rockchip,rk3228-hdmi-phy", 923 .data = &rk3228_hdmi_phy_drv_data 924 }, 925 { .compatible = "rockchip,rk3328-hdmi-phy", 926 .data = &rk3328_hdmi_phy_drv_data 927 }, 928 {} 929 }; 930 931 static int inno_hdmi_phy_init(struct rockchip_phy *phy) 932 { 933 struct udevice *dev = phy->dev; 934 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); 935 int i, val, phy_table_size, ret; 936 const char *name; 937 u32 *phy_config; 938 939 inno->node = dev->node; 940 941 inno->regs = dev_read_addr_ptr(dev); 942 if (!inno->regs) { 943 printf("%s: failed to get phy address\n", __func__); 944 return -ENOMEM; 945 } 946 947 name = dev_read_string(dev, "compatible"); 948 for (i = 0; i < ARRAY_SIZE(inno_hdmi_phy_of_match); i++) { 949 if (!strcmp(name, inno_hdmi_phy_of_match[i].compatible)) { 950 inno->plat_data = inno_hdmi_phy_of_match[i].data; 951 break; 952 } 953 } 954 955 dev_read_prop(dev, "rockchip,phy-table", &val); 956 957 if (val >= 0) { 958 if (val % PHY_TAB_LEN || !val) { 959 printf("Invalid phy cfg table format!\n"); 960 return -EINVAL; 961 } 962 963 phy_config = malloc(val); 964 if (!phy_config) { 965 printf("kmalloc phy table failed\n"); 966 return -ENOMEM; 967 } 968 969 phy_table_size = val / PHY_TAB_LEN; 970 /* Effective phy cfg data and the end of phy cfg table */ 971 inno->phy_cfg = malloc(val + PHY_TAB_LEN); 972 if (!inno->phy_cfg) { 973 free(phy_config); 974 return -ENOMEM; 975 } 976 977 dev_read_u32_array(dev, "rockchip,phy-table", 978 phy_config, val / sizeof(u32)); 979 ret = inno_hdmi_update_phy_table(inno, phy_config, 980 inno->phy_cfg, 981 phy_table_size); 982 if (ret) { 983 free(phy_config); 984 return ret; 985 } 986 free(phy_config); 987 } else { 988 printf("use default hdmi phy table\n"); 989 } 990 991 if (i >= ARRAY_SIZE(inno_hdmi_phy_of_match)) 992 return 0; 993 994 if (!inno->plat_data || !inno->plat_data->ops) 995 return -EINVAL; 996 997 if (inno->plat_data->ops->init) 998 inno->plat_data->ops->init(inno); 999 1000 return 0; 1001 } 1002 1003 static unsigned long inno_hdmi_phy_set_pll(struct rockchip_phy *phy, 1004 unsigned long rate) 1005 { 1006 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); 1007 1008 inno_hdmi_phy_clk_prepare(inno); 1009 inno_hdmi_phy_clk_is_prepared(inno); 1010 inno_hdmi_phy_clk_set_rate(inno, rate); 1011 return 0; 1012 } 1013 1014 static int 1015 inno_hdmi_phy_set_bus_width(struct rockchip_phy *phy, u32 bus_width) 1016 { 1017 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); 1018 1019 inno->bus_width = bus_width; 1020 1021 return 0; 1022 } 1023 1024 static long 1025 inno_hdmi_phy_clk_round_rate(struct rockchip_phy *phy, unsigned long rate) 1026 { 1027 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); 1028 int i; 1029 const struct pre_pll_config *cfg = pre_pll_cfg_table; 1030 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate); 1031 1032 for (; cfg->pixclock != ~0UL; cfg++) 1033 if (cfg->pixclock == rate) 1034 break; 1035 1036 /* 1037 * XXX: Limit pixel clock under 600MHz 1038 * rk3228 does not support non-zero fracdiv 1039 */ 1040 if ((inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228 && 1041 cfg->fracdiv) || cfg->pixclock > 600000000) 1042 return -EINVAL; 1043 1044 /* 1045 * If there is no dts phy cfg table, use default phy cfg table. 1046 * The tmds clock maximum is 594MHz. So there is no need to check 1047 * whether tmds clock is out of range. 1048 */ 1049 if (!inno->phy_cfg) 1050 return cfg->pixclock; 1051 1052 /* Check if tmds clock is out of dts phy config's range. */ 1053 for (i = 0; inno->phy_cfg[i].tmdsclock != ~0UL; i++) { 1054 if (inno->phy_cfg[i].tmdsclock >= tmdsclock) 1055 break; 1056 } 1057 1058 if (inno->phy_cfg[i].tmdsclock == ~0UL) 1059 return -EINVAL; 1060 1061 return cfg->pixclock; 1062 } 1063 1064 const struct rockchip_phy_funcs inno_hdmi_phy_funcs = { 1065 .init = inno_hdmi_phy_init, 1066 .power_on = inno_hdmi_phy_power_on, 1067 .power_off = inno_hdmi_phy_power_off, 1068 .set_pll = inno_hdmi_phy_set_pll, 1069 .set_bus_width = inno_hdmi_phy_set_bus_width, 1070 .round_rate = inno_hdmi_phy_clk_round_rate, 1071 }; 1072 1073 static struct rockchip_phy inno_hdmi_phy_driver_data = { 1074 .funcs = &inno_hdmi_phy_funcs, 1075 }; 1076 1077 static const struct udevice_id inno_hdmi_phy_ids[] = { 1078 { 1079 .compatible = "rockchip,rk3328-hdmi-phy", 1080 .data = (ulong)&inno_hdmi_phy_driver_data, 1081 }, 1082 { 1083 .compatible = "rockchip,rk3228-hdmi-phy", 1084 .data = (ulong)&inno_hdmi_phy_driver_data, 1085 }, 1086 {} 1087 }; 1088 1089 static int inno_hdmi_phy_probe(struct udevice *dev) 1090 { 1091 struct inno_hdmi_phy *inno = dev_get_priv(dev); 1092 struct rockchip_phy *phy = 1093 (struct rockchip_phy *)dev_get_driver_data(dev); 1094 1095 inno->dev = dev; 1096 phy->dev = dev; 1097 1098 return 0; 1099 } 1100 1101 U_BOOT_DRIVER(inno_hdmi_phy) = { 1102 .name = "inno_hdmi_phy", 1103 .id = UCLASS_PHY, 1104 .of_match = inno_hdmi_phy_ids, 1105 .probe = inno_hdmi_phy_probe, 1106 .priv_auto_alloc_size = sizeof(struct inno_hdmi_phy), 1107 }; 1108