1 /* 2 * SPDX-License-Identifier: GPL-2.0+ 3 * (C) Copyright 2008-2016 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #include <config.h> 7 #include <common.h> 8 #include <errno.h> 9 #include <malloc.h> 10 #include <misc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <asm/unaligned.h> 14 #include <dm/device.h> 15 #include <dm/read.h> 16 #include <asm/io.h> 17 #include <linux/list.h> 18 #include <div64.h> 19 #include <linux/media-bus-format.h> 20 21 #include "rockchip_display.h" 22 #include "rockchip_crtc.h" 23 #include "rockchip_connector.h" 24 #include "rockchip_phy.h" 25 26 #define INNO_HDMI_PHY_TIMEOUT_LOOP_COUNT 1000 27 /*#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))*/ 28 29 /* REG: 0x00 */ 30 #define PRE_PLL_REFCLK_SEL_MASK BIT(0) 31 #define PRE_PLL_REFCLK_SEL_PCLK BIT(0) 32 #define PRE_PLL_REFCLK_SEL_OSCCLK 0 33 /* REG: 0x01 */ 34 #define BYPASS_RXSENSE_EN_MASK BIT(2) 35 #define BYPASS_RXSENSE_EN BIT(2) 36 #define BYPASS_PWRON_EN_MASK BIT(1) 37 #define BYPASS_PWRON_EN BIT(1) 38 #define BYPASS_PLLPD_EN_MASK BIT(0) 39 #define BYPASS_PLLPD_EN BIT(0) 40 /* REG: 0x02 */ 41 #define BYPASS_PDATA_EN_MASK BIT(4) 42 #define BYPASS_PDATA_EN BIT(4) 43 #define PDATAEN_MASK BIT(0) 44 #define PDATAEN_DISABLE BIT(0) 45 #define PDATAEN_ENABLE 0 46 /* REG: 0x03 */ 47 #define BYPASS_AUTO_TERM_RES_CAL BIT(7) 48 #define AUDO_TERM_RES_CAL_SPEED_14_8(x) UPDATE(x, 6, 0) 49 /* REG: 0x04 */ 50 #define AUDO_TERM_RES_CAL_SPEED_7_0(x) UPDATE(x, 7, 0) 51 /* REG: 0xaa */ 52 #define POST_PLL_CTRL_MASK BIT(0) 53 #define POST_PLL_CTRL_MANUAL BIT(0) 54 /* REG: 0xe0 */ 55 #define POST_PLL_POWER_MASK BIT(5) 56 #define POST_PLL_POWER_DOWN BIT(5) 57 #define POST_PLL_POWER_UP 0 58 #define PRE_PLL_POWER_MASK BIT(4) 59 #define PRE_PLL_POWER_DOWN BIT(4) 60 #define PRE_PLL_POWER_UP 0 61 #define RXSENSE_CLK_CH_MASK BIT(3) 62 #define RXSENSE_CLK_CH_ENABLE BIT(3) 63 #define RXSENSE_DATA_CH2_MASK BIT(2) 64 #define RXSENSE_DATA_CH2_ENABLE BIT(2) 65 #define RXSENSE_DATA_CH1_MASK BIT(1) 66 #define RXSENSE_DATA_CH1_ENABLE BIT(1) 67 #define RXSENSE_DATA_CH0_MASK BIT(0) 68 #define RXSENSE_DATA_CH0_ENABLE BIT(0) 69 /* REG: 0xe1 */ 70 #define BANDGAP_MASK BIT(4) 71 #define BANDGAP_ENABLE BIT(4) 72 #define BANDGAP_DISABLE 0 73 #define TMDS_DRIVER_MASK GENMASK(3, 0) 74 #define TMDS_DRIVER_ENABLE UPDATE(0xf, 3, 0) 75 #define TMDS_DRIVER_DISABLE 0 76 /* REG: 0xe2 */ 77 #define PRE_PLL_FB_DIV_8_MASK BIT(7) 78 #define PRE_PLL_FB_DIV_8_SHIFT 7 79 #define PRE_PLL_FB_DIV_8(x) UPDATE(x, 7, 7) 80 #define PCLK_VCO_DIV_5_MASK BIT(5) 81 #define PCLK_VCO_DIV_5_SHIFT 5 82 #define PCLK_VCO_DIV_5(x) UPDATE(x, 5, 5) 83 #define PRE_PLL_PRE_DIV_MASK GENMASK(4, 0) 84 #define PRE_PLL_PRE_DIV(x) UPDATE(x, 4, 0) 85 /* REG: 0xe3 */ 86 #define PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0) 87 /* REG: 0xe4 */ 88 #define PRE_PLL_PCLK_DIV_B_MASK GENMASK(6, 5) 89 #define PRE_PLL_PCLK_DIV_B_SHIFT 5 90 #define PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5) 91 #define PRE_PLL_PCLK_DIV_A_MASK GENMASK(4, 0) 92 #define PRE_PLL_PCLK_DIV_A_SHIFT 0 93 #define PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0) 94 /* REG: 0xe5 */ 95 #define PRE_PLL_PCLK_DIV_C_MASK GENMASK(6, 5) 96 #define PRE_PLL_PCLK_DIV_C_SHIFT 5 97 #define PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5) 98 #define PRE_PLL_PCLK_DIV_D_MASK GENMASK(4, 0) 99 #define PRE_PLL_PCLK_DIV_D_SHIFT 0 100 #define PRE_PLL_PCLK_DIV_D(x) UPDATE(x, 4, 0) 101 /* REG: 0xe6 */ 102 #define PRE_PLL_TMDSCLK_DIV_C_MASK GENMASK(5, 4) 103 #define PRE_PLL_TMDSCLK_DIV_C(x) UPDATE(x, 5, 4) 104 #define PRE_PLL_TMDSCLK_DIV_A_MASK GENMASK(3, 2) 105 #define PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 3, 2) 106 #define PRE_PLL_TMDSCLK_DIV_B_MASK GENMASK(1, 0) 107 #define PRE_PLL_TMDSCLK_DIV_B(x) UPDATE(x, 1, 0) 108 /* REG: 0xe8 */ 109 #define PRE_PLL_LOCK_STATUS BIT(0) 110 /* REG: 0xe9 */ 111 #define POST_PLL_POST_DIV_EN_MASK GENMASK(7, 6) 112 #define POST_PLL_POST_DIV_ENABLE UPDATE(3, 7, 6) 113 #define POST_PLL_POST_DIV_DISABLE 0 114 #define POST_PLL_PRE_DIV_MASK GENMASK(4, 0) 115 #define POST_PLL_PRE_DIV(x) UPDATE(x, 4, 0) 116 /* REG: 0xea */ 117 #define POST_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0) 118 /* REG: 0xeb */ 119 #define POST_PLL_FB_DIV_8_MASK BIT(7) 120 #define POST_PLL_FB_DIV_8(x) UPDATE(x, 7, 7) 121 #define POST_PLL_POST_DIV_MASK GENMASK(5, 4) 122 #define POST_PLL_POST_DIV(x) UPDATE(x, 5, 4) 123 #define POST_PLL_LOCK_STATUS BIT(0) 124 /* REG: 0xee */ 125 #define TMDS_CH_TA_MASK GENMASK(7, 4) 126 #define TMDS_CH_TA_ENABLE UPDATE(0xf, 7, 4) 127 #define TMDS_CH_TA_DISABLE 0 128 /* REG: 0xef */ 129 #define TMDS_CLK_CH_TA(x) UPDATE(x, 7, 6) 130 #define TMDS_DATA_CH2_TA(x) UPDATE(x, 5, 4) 131 #define TMDS_DATA_CH1_TA(x) UPDATE(x, 3, 2) 132 #define TMDS_DATA_CH0_TA(x) UPDATE(x, 1, 0) 133 /* REG: 0xf0 */ 134 #define TMDS_DATA_CH2_PRE_EMPHASIS_MASK GENMASK(5, 4) 135 #define TMDS_DATA_CH2_PRE_EMPHASIS(x) UPDATE(x, 5, 4) 136 #define TMDS_DATA_CH1_PRE_EMPHASIS_MASK GENMASK(3, 2) 137 #define TMDS_DATA_CH1_PRE_EMPHASIS(x) UPDATE(x, 3, 2) 138 #define TMDS_DATA_CH0_PRE_EMPHASIS_MASK GENMASK(1, 0) 139 #define TMDS_DATA_CH0_PRE_EMPHASIS(x) UPDATE(x, 1, 0) 140 /* REG: 0xf1 */ 141 #define TMDS_CLK_CH_OUTPUT_SWING(x) UPDATE(x, 7, 4) 142 #define TMDS_DATA_CH2_OUTPUT_SWING(x) UPDATE(x, 3, 0) 143 /* REG: 0xf2 */ 144 #define TMDS_DATA_CH1_OUTPUT_SWING(x) UPDATE(x, 7, 4) 145 #define TMDS_DATA_CH0_OUTPUT_SWING(x) UPDATE(x, 3, 0) 146 147 enum inno_hdmi_phy_type { 148 INNO_HDMI_PHY_RK3228, 149 INNO_HDMI_PHY_RK3328 150 }; 151 152 struct inno_hdmi_phy_drv_data; 153 154 struct phy_config { 155 unsigned long tmdsclock; 156 u8 regs[14]; 157 }; 158 159 struct inno_hdmi_phy { 160 const void *blob; 161 ofnode node; 162 void *regs; 163 164 /* platform data */ 165 const struct inno_hdmi_phy_drv_data *plat_data; 166 unsigned long pixclock; 167 u32 bus_width; 168 struct phy_config *phy_cfg; 169 }; 170 171 struct pre_pll_config { 172 unsigned long pixclock; 173 unsigned long tmdsclock; 174 u8 prediv; 175 u16 fbdiv; 176 u8 tmds_div_a; 177 u8 tmds_div_b; 178 u8 tmds_div_c; 179 u8 pclk_div_a; 180 u8 pclk_div_b; 181 u8 pclk_div_c; 182 u8 pclk_div_d; 183 u8 vco_div_5_en; 184 u32 fracdiv; 185 }; 186 187 struct post_pll_config { 188 unsigned long tmdsclock; 189 u8 prediv; 190 u16 fbdiv; 191 u8 postdiv; 192 u8 version; 193 }; 194 195 struct inno_hdmi_phy_ops { 196 void (*init)(struct inno_hdmi_phy *inno); 197 int (*power_on)(struct inno_hdmi_phy *inno, 198 const struct post_pll_config *cfg, 199 const struct phy_config *phy_cfg); 200 void (*power_off)(struct inno_hdmi_phy *inno); 201 int (*pre_pll_update)(struct inno_hdmi_phy *inno, 202 const struct pre_pll_config *cfg); 203 unsigned long (*recalc_rate)(struct inno_hdmi_phy *inno, 204 unsigned long parent_rate); 205 }; 206 207 struct inno_hdmi_phy_drv_data { 208 enum inno_hdmi_phy_type dev_type; 209 const struct inno_hdmi_phy_ops *ops; 210 const struct phy_config *phy_cfg_table; 211 }; 212 213 struct rockchip_inno_data { 214 char compatible[30]; 215 const void *data; 216 }; 217 218 static const struct pre_pll_config pre_pll_cfg_table[] = { 219 { 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0}, 220 { 27000000, 33750000, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0}, 221 { 40000000, 40000000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0}, 222 { 59341000, 59341000, 1, 98, 3, 1, 2, 1, 3, 3, 4, 0, 0xE6AE6B}, 223 { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0}, 224 { 59341000, 74176250, 1, 98, 0, 3, 3, 1, 3, 3, 4, 0, 0xE6AE6B}, 225 { 59400000, 74250000, 1, 99, 1, 2, 2, 1, 3, 3, 4, 0, 0}, 226 { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B}, 227 { 74250000, 74250000, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0}, 228 { 74176000, 92720000, 4, 494, 1, 2, 2, 1, 3, 3, 4, 0, 0x816817}, 229 { 74250000, 92812500, 4, 495, 1, 2, 2, 1, 3, 3, 4, 0, 0}, 230 {148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B}, 231 {148500000, 148500000, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0}, 232 {148352000, 185440000, 4, 494, 0, 2, 2, 1, 3, 2, 2, 0, 0x816817}, 233 {148500000, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0}, 234 {296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B}, 235 {297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0}, 236 {296703000, 370878750, 4, 494, 1, 2, 0, 1, 3, 1, 1, 0, 0x816817}, 237 {297000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 0, 0}, 238 {593407000, 296703500, 1, 98, 0, 1, 1, 1, 0, 2, 1, 0, 0xE6AE6B}, 239 {594000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 1, 0, 0}, 240 {593407000, 370879375, 4, 494, 1, 2, 0, 1, 3, 1, 1, 1, 0x816817}, 241 {594000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 1, 0}, 242 {593407000, 593407000, 1, 98, 0, 2, 0, 1, 0, 1, 1, 0, 0xE6AE6B}, 243 {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0}, 244 { ~0UL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 245 }; 246 247 static const struct post_pll_config post_pll_cfg_table[] = { 248 {33750000, 1, 40, 8, 1}, 249 {33750000, 1, 80, 8, 2}, 250 {33750000, 1, 10, 2, 4}, 251 {74250000, 1, 40, 8, 1}, 252 {74250000, 18, 80, 8, 2}, 253 {148500000, 2, 40, 4, 3}, 254 {297000000, 4, 40, 2, 3}, 255 {594000000, 8, 40, 1, 3}, 256 { ~0UL, 0, 0, 0, 0} 257 }; 258 259 static const struct phy_config rk3228_phy_cfg[] = { 260 { 165000000, { 261 0xaa, 0x00, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 262 0x00, 0x00, 0x00, 0x00, 0x00, 263 }, 264 }, { 265 340000000, { 266 0xaa, 0x15, 0x6a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 267 0x00, 0x00, 0x00, 0x00, 0x00, 268 }, 269 }, { 270 594000000, { 271 0xaa, 0x15, 0x7a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 272 0x00, 0x00, 0x00, 0x00, 0x00, 273 }, 274 }, { 275 ~0UL, { 276 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 277 0x00, 0x00, 0x00, 0x00, 0x00, 278 }, 279 } 280 }; 281 282 static const struct phy_config rk3328_phy_cfg[] = { 283 { 165000000, { 284 0x07, 0x08, 0x08, 0x08, 0x00, 0x00, 0x08, 0x08, 0x08, 285 0x00, 0xac, 0xcc, 0xcc, 0xcc, 286 }, 287 }, { 288 340000000, { 289 0x0b, 0x0d, 0x0d, 0x0d, 0x07, 0x15, 0x08, 0x08, 0x08, 290 0x3f, 0xac, 0xcc, 0xcd, 0xdd, 291 }, 292 }, { 293 594000000, { 294 0x10, 0x1a, 0x1a, 0x1a, 0x07, 0x15, 0x08, 0x08, 0x08, 295 0x00, 0xac, 0xcc, 0xcc, 0xcc, 296 }, 297 }, { 298 ~0UL, { 299 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 300 0x00, 0x00, 0x00, 0x00, 0x00, 301 }, 302 } 303 }; 304 305 static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val) 306 { 307 writel(val, inno->regs + (reg * 4)); 308 } 309 310 static inline u8 inno_read(struct inno_hdmi_phy *inno, u32 reg) 311 { 312 u32 val; 313 314 val = readl(inno->regs + (reg * 4)); 315 316 return val; 317 } 318 319 static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg, 320 u8 mask, u8 val) 321 { 322 u32 tmp, orig; 323 324 orig = inno_read(inno, reg); 325 tmp = orig & ~mask; 326 tmp |= val & mask; 327 inno_write(inno, reg, tmp); 328 } 329 330 static u32 inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno, 331 unsigned long rate) 332 { 333 u32 tmdsclk; 334 335 switch (inno->bus_width) { 336 case 4: 337 tmdsclk = (u32)rate / 2; 338 break; 339 case 5: 340 tmdsclk = (u32)rate * 5 / 8; 341 break; 342 case 6: 343 tmdsclk = (u32)rate * 3 / 4; 344 break; 345 case 10: 346 tmdsclk = (u32)rate * 5 / 4; 347 break; 348 case 12: 349 tmdsclk = (u32)rate * 3 / 2; 350 break; 351 case 16: 352 tmdsclk = (u32)rate * 2; 353 break; 354 default: 355 tmdsclk = rate; 356 } 357 358 return tmdsclk; 359 } 360 361 static u8 rk_get_cpu_version(void) 362 { 363 u8 val = 0; 364 #ifdef CONFIG_ROCKCHIP_EFUSE 365 struct udevice *dev; 366 u32 regs[2] = {0}; 367 u8 fuses[1]; 368 ofnode node; 369 int ret; 370 371 ret = uclass_get_device_by_driver(UCLASS_MISC, 372 DM_GET_DRIVER(rockchip_efuse), &dev); 373 if (ret) { 374 printf("%s: no misc-device found\n", __func__); 375 return -EINVAL; 376 } 377 378 node = dev_read_subnode(dev, "cpu-version"); 379 if (!ofnode_valid(node)) 380 return -EINVAL; 381 382 ret = ofnode_read_u32_array(node, "reg", regs, 2); 383 if (ret) { 384 printf("Cannot get efuse reg\n"); 385 return -EINVAL; 386 } 387 388 ret = misc_read(dev, regs[0], &fuses, regs[1]); 389 if (ret) { 390 printf("%s: misc_read failed\n", __func__); 391 return 0; 392 } 393 394 val = fuses[0]; 395 val = (val >> 3) & 0x1; 396 #endif 397 return val; 398 } 399 400 static int inno_hdmi_phy_power_on(struct display_state *state) 401 { 402 struct connector_state *conn_state = &state->conn_state; 403 struct inno_hdmi_phy *inno = conn_state->phy_private; 404 const struct post_pll_config *cfg = post_pll_cfg_table; 405 const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table; 406 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, inno->pixclock); 407 u32 chipversion = 1; 408 409 printf("start Inno HDMI PHY Power On\n"); 410 411 if (inno->phy_cfg) 412 phy_cfg = inno->phy_cfg; 413 414 if (!tmdsclock) { 415 printf("TMDS clock is zero!\n"); 416 return -EINVAL; 417 } 418 419 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3328 && 420 rk_get_cpu_version()) 421 chipversion = 2; 422 else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228 && 423 tmdsclock <= 33750000) 424 chipversion = 4; 425 426 printf("tmdsclock = %d; chipversion = %d\n", tmdsclock, chipversion); 427 428 for (; cfg->tmdsclock != ~0UL; cfg++) 429 if (tmdsclock <= cfg->tmdsclock && 430 cfg->version & chipversion) 431 break; 432 433 for (; phy_cfg->tmdsclock != ~0UL; phy_cfg++) 434 if (tmdsclock <= phy_cfg->tmdsclock) 435 break; 436 437 if (cfg->tmdsclock == ~0UL || phy_cfg->tmdsclock == ~0UL) 438 return -EINVAL; 439 440 printf("Inno HDMI PHY Power On\n"); 441 if (inno->plat_data->ops->power_on) 442 return inno->plat_data->ops->power_on(inno, cfg, phy_cfg); 443 else 444 return -EINVAL; 445 } 446 447 static int inno_hdmi_phy_power_off(struct display_state *state) 448 { 449 struct connector_state *conn_state = &state->conn_state; 450 struct inno_hdmi_phy *inno = conn_state->phy_private; 451 452 if (inno->plat_data->ops->power_off) 453 inno->plat_data->ops->power_off(inno); 454 printf("Inno HDMI PHY Power Off\n"); 455 456 return 0; 457 } 458 459 static int inno_hdmi_phy_clk_is_prepared(struct display_state *state) 460 { 461 struct connector_state *conn_state = &state->conn_state; 462 struct inno_hdmi_phy *inno = conn_state->phy_private; 463 u8 status; 464 465 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) 466 status = inno_read(inno, 0xe0) & PRE_PLL_POWER_MASK; 467 else 468 status = inno_read(inno, 0xa0) & 1; 469 470 return status ? 0 : 1; 471 } 472 473 static int inno_hdmi_phy_clk_prepare(struct display_state *state) 474 { 475 struct connector_state *conn_state = &state->conn_state; 476 struct inno_hdmi_phy *inno = conn_state->phy_private; 477 478 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) 479 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, 480 PRE_PLL_POWER_UP); 481 else 482 inno_update_bits(inno, 0xa0, 1, 0); 483 484 return 0; 485 } 486 487 static int inno_hdmi_phy_clk_set_rate(struct display_state *state, 488 unsigned long rate) 489 { 490 struct connector_state *conn_state = &state->conn_state; 491 struct inno_hdmi_phy *inno = conn_state->phy_private; 492 const struct pre_pll_config *cfg = pre_pll_cfg_table; 493 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate); 494 495 for (; cfg->pixclock != ~0UL; cfg++) 496 if (cfg->pixclock == rate && cfg->tmdsclock == tmdsclock) 497 break; 498 499 if (cfg->pixclock == ~0UL) { 500 printf("unsupported rate %lu\n", rate); 501 return -EINVAL; 502 } 503 504 if (inno->plat_data->ops->pre_pll_update) 505 inno->plat_data->ops->pre_pll_update(inno, cfg); 506 507 inno->pixclock = rate; 508 509 return 0; 510 } 511 512 static void inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno) 513 { 514 u32 m, v; 515 516 /* 517 * Use phy internal register control 518 * rxsense/poweron/pllpd/pdataen signal. 519 */ 520 m = BYPASS_RXSENSE_EN_MASK | BYPASS_PWRON_EN_MASK | 521 BYPASS_PLLPD_EN_MASK; 522 v = BYPASS_RXSENSE_EN | BYPASS_PWRON_EN | BYPASS_PLLPD_EN; 523 inno_update_bits(inno, 0x01, m, v); 524 inno_update_bits(inno, 0x02, BYPASS_PDATA_EN_MASK, BYPASS_PDATA_EN); 525 526 /* manual power down post-PLL */ 527 inno_update_bits(inno, 0xaa, POST_PLL_CTRL_MASK, POST_PLL_CTRL_MANUAL); 528 } 529 530 static int 531 inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy *inno, 532 const struct post_pll_config *cfg, 533 const struct phy_config *phy_cfg) 534 { 535 int pll_tries; 536 u32 m, v; 537 538 /* pdata_en disable */ 539 inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_DISABLE); 540 541 /* Power down Post-PLL */ 542 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN); 543 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN); 544 545 /* Post-PLL update */ 546 m = POST_PLL_PRE_DIV_MASK; 547 v = POST_PLL_PRE_DIV(cfg->prediv); 548 inno_update_bits(inno, 0xe9, m, v); 549 550 m = POST_PLL_FB_DIV_8_MASK; 551 v = POST_PLL_FB_DIV_8(cfg->fbdiv >> 8); 552 inno_update_bits(inno, 0xeb, m, v); 553 inno_write(inno, 0xea, POST_PLL_FB_DIV_7_0(cfg->fbdiv)); 554 555 if (cfg->postdiv == 1) { 556 /* Disable Post-PLL post divider */ 557 m = POST_PLL_POST_DIV_EN_MASK; 558 v = POST_PLL_POST_DIV_DISABLE; 559 inno_update_bits(inno, 0xe9, m, v); 560 } else { 561 /* Enable Post-PLL post divider */ 562 m = POST_PLL_POST_DIV_EN_MASK; 563 v = POST_PLL_POST_DIV_ENABLE; 564 inno_update_bits(inno, 0xe9, m, v); 565 566 m = POST_PLL_POST_DIV_MASK; 567 v = POST_PLL_POST_DIV(cfg->postdiv / 2 - 1); 568 inno_update_bits(inno, 0xeb, m, v); 569 } 570 571 for (v = 0; v < 4; v++) 572 inno_write(inno, 0xef + v, phy_cfg->regs[v]); 573 574 /* Power up Post-PLL */ 575 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_UP); 576 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP); 577 578 /* BandGap enable */ 579 inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_ENABLE); 580 581 /* TMDS driver enable */ 582 inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_ENABLE); 583 584 /* Wait for post PLL lock */ 585 pll_tries = 0; 586 while (!(inno_read(inno, 0xeb) & POST_PLL_LOCK_STATUS)) { 587 if (pll_tries == INNO_HDMI_PHY_TIMEOUT_LOOP_COUNT) { 588 printf("Post-PLL unlock\n"); 589 return -ETIMEDOUT; 590 } 591 592 pll_tries++; 593 udelay(100); 594 } 595 596 if (cfg->tmdsclock > 340000000) 597 mdelay(100); 598 599 /* pdata_en enable */ 600 inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_ENABLE); 601 return 0; 602 } 603 604 static void inno_hdmi_phy_rk3228_power_off(struct inno_hdmi_phy *inno) 605 { 606 /* TMDS driver Disable */ 607 inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_DISABLE); 608 609 /* BandGap Disable */ 610 inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_DISABLE); 611 612 /* Post-PLL power down */ 613 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN); 614 } 615 616 static int 617 inno_hdmi_phy_rk3228_pre_pll_update(struct inno_hdmi_phy *inno, 618 const struct pre_pll_config *cfg) 619 { 620 int pll_tries; 621 u32 m, v; 622 623 /* Power down PRE-PLL */ 624 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN); 625 626 m = PRE_PLL_FB_DIV_8_MASK | PCLK_VCO_DIV_5_MASK | PRE_PLL_PRE_DIV_MASK; 627 v = PRE_PLL_FB_DIV_8(cfg->fbdiv >> 8) | 628 PCLK_VCO_DIV_5(cfg->vco_div_5_en) | PRE_PLL_PRE_DIV(cfg->prediv); 629 inno_update_bits(inno, 0xe2, m, v); 630 631 inno_write(inno, 0xe3, PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); 632 633 m = PRE_PLL_PCLK_DIV_B_MASK | PRE_PLL_PCLK_DIV_A_MASK; 634 v = PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b) | 635 PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a); 636 inno_update_bits(inno, 0xe4, m, v); 637 638 m = PRE_PLL_PCLK_DIV_C_MASK | PRE_PLL_PCLK_DIV_D_MASK; 639 v = PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) | 640 PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d); 641 inno_update_bits(inno, 0xe5, m, v); 642 643 m = PRE_PLL_TMDSCLK_DIV_C_MASK | PRE_PLL_TMDSCLK_DIV_A_MASK | 644 PRE_PLL_TMDSCLK_DIV_B_MASK; 645 v = PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) | 646 PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) | 647 PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b); 648 inno_update_bits(inno, 0xe6, m, v); 649 650 /* Power up PRE-PLL */ 651 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP); 652 653 /* Wait for Pre-PLL lock */ 654 pll_tries = 0; 655 while (!(inno_read(inno, 0xe8) & PRE_PLL_LOCK_STATUS)) { 656 if (pll_tries == INNO_HDMI_PHY_TIMEOUT_LOOP_COUNT) { 657 printf("Pre-PLL unlock\n"); 658 return -ETIMEDOUT; 659 } 660 661 pll_tries++; 662 udelay(100); 663 } 664 665 return 0; 666 } 667 668 static void inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno) 669 { 670 /* 671 * Use phy internal register control 672 * rxsense/poweron/pllpd/pdataen signal. 673 */ 674 inno_write(inno, 0x01, 0x07); 675 inno_write(inno, 0x02, 0x91); 676 } 677 678 static int 679 inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, 680 const struct post_pll_config *cfg, 681 const struct phy_config *phy_cfg) 682 { 683 u32 val; 684 685 /* set pdata_en to 0 */ 686 inno_update_bits(inno, 0x02, 1, 0); 687 /* Power off post PLL */ 688 inno_update_bits(inno, 0xaa, 1, 1); 689 690 val = cfg->fbdiv & 0xff; 691 inno_write(inno, 0xac, val); 692 if (cfg->postdiv == 1) { 693 inno_write(inno, 0xaa, 2); 694 val = (cfg->fbdiv >> 8) | cfg->prediv; 695 inno_write(inno, 0xab, val); 696 } else { 697 val = (cfg->postdiv / 2) - 1; 698 inno_write(inno, 0xad, val); 699 val = (cfg->fbdiv >> 8) | cfg->prediv; 700 inno_write(inno, 0xab, val); 701 inno_write(inno, 0xaa, 0x0e); 702 } 703 704 for (val = 0; val < 14; val++) 705 inno_write(inno, 0xb5 + val, phy_cfg->regs[val]); 706 707 /* bit[7:6] of reg c8/c9/ca/c8 is ESD detect threshold: 708 * 00 - 340mV 709 * 01 - 280mV 710 * 10 - 260mV 711 * 11 - 240mV 712 * default is 240mV, now we set it to 340mV 713 */ 714 inno_write(inno, 0xc8, 0); 715 inno_write(inno, 0xc9, 0); 716 inno_write(inno, 0xca, 0); 717 inno_write(inno, 0xcb, 0); 718 719 if (phy_cfg->tmdsclock > 340000000) { 720 /* Set termination resistor to 100ohm */ 721 val = 75000000 / 100000; 722 inno_write(inno, 0xc5, ((val >> 8) & 0xff) | 0x80); 723 inno_write(inno, 0xc6, val & 0xff); 724 inno_write(inno, 0xc7, 3 << 1); 725 inno_write(inno, 0xc5, ((val >> 8) & 0xff)); 726 } else if (phy_cfg->tmdsclock > 165000000) { 727 inno_write(inno, 0xc5, 0x81); 728 /* clk termination resistor is 50ohm 729 * data termination resistor is 150ohm 730 */ 731 inno_write(inno, 0xc8, 0x30); 732 inno_write(inno, 0xc9, 0x10); 733 inno_write(inno, 0xca, 0x10); 734 inno_write(inno, 0xcb, 0x10); 735 } else { 736 inno_write(inno, 0xc5, 0x81); 737 } 738 739 /* set TMDS sync detection counter length */ 740 val = 47520000000UL / phy_cfg->tmdsclock; 741 inno_write(inno, 0xd8, (val >> 8) & 0xff); 742 inno_write(inno, 0xd9, val & 0xff); 743 744 /* Power up post PLL */ 745 inno_update_bits(inno, 0xaa, 1, 0); 746 /* Power up tmds driver */ 747 inno_update_bits(inno, 0xb0, 4, 4); 748 inno_write(inno, 0xb2, 0x0f); 749 750 /* Wait for post PLL lock */ 751 for (val = 0; val < 5; val++) { 752 if (inno_read(inno, 0xaf) & 1) 753 break; 754 udelay(1000); 755 } 756 if (!(inno_read(inno, 0xaf) & 1)) { 757 printf("HDMI PHY Post PLL unlock\n"); 758 return -ETIMEDOUT; 759 } 760 if (phy_cfg->tmdsclock > 340000000) 761 mdelay(100); 762 /* set pdata_en to 1 */ 763 inno_update_bits(inno, 0x02, 1, 1); 764 765 return 0; 766 } 767 768 static void inno_hdmi_phy_rk3328_power_off(struct inno_hdmi_phy *inno) 769 { 770 /* Power off driver */ 771 inno_write(inno, 0xb2, 0); 772 /* Power off band gap */ 773 inno_update_bits(inno, 0xb0, 4, 0); 774 /* Power off post pll */ 775 inno_update_bits(inno, 0xaa, 1, 1); 776 } 777 778 static int 779 inno_hdmi_phy_rk3328_pre_pll_update(struct inno_hdmi_phy *inno, 780 const struct pre_pll_config *cfg) 781 { 782 u32 val; 783 784 /* Power off PLL */ 785 inno_update_bits(inno, 0xa0, 1, 1); 786 /* Configure pre-pll */ 787 inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1); 788 inno_write(inno, 0xa1, cfg->prediv); 789 if (cfg->fracdiv) 790 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xc0; 791 else 792 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xf0; 793 inno_write(inno, 0xa2, val); 794 inno_write(inno, 0xa3, cfg->fbdiv & 0xff); 795 val = (cfg->pclk_div_a & 0x1f) | 796 ((cfg->pclk_div_b & 3) << 5); 797 inno_write(inno, 0xa5, val); 798 val = (cfg->pclk_div_d & 0x1f) | 799 ((cfg->pclk_div_c & 3) << 5); 800 inno_write(inno, 0xa6, val); 801 val = ((cfg->tmds_div_a & 3) << 4) | 802 ((cfg->tmds_div_b & 3) << 2) | 803 (cfg->tmds_div_c & 3); 804 inno_write(inno, 0xa4, val); 805 806 if (cfg->fracdiv) { 807 val = cfg->fracdiv & 0xff; 808 inno_write(inno, 0xd3, val); 809 val = (cfg->fracdiv >> 8) & 0xff; 810 inno_write(inno, 0xd2, val); 811 val = (cfg->fracdiv >> 16) & 0xff; 812 inno_write(inno, 0xd1, val); 813 } else { 814 inno_write(inno, 0xd3, 0); 815 inno_write(inno, 0xd2, 0); 816 inno_write(inno, 0xd1, 0); 817 } 818 819 /* Power up PLL */ 820 inno_update_bits(inno, 0xa0, 1, 0); 821 822 /* Wait for PLL lock */ 823 for (val = 0; val < 5; val++) { 824 if (inno_read(inno, 0xa9) & 1) 825 break; 826 udelay(1000); 827 } 828 if (val == 5) { 829 printf("Pre-PLL unlock\n"); 830 return -ETIMEDOUT; 831 } 832 833 return 0; 834 } 835 836 static unsigned long 837 inno_hdmi_3328_phy_pll_recalc_rate(struct inno_hdmi_phy *inno, 838 unsigned long parent_rate) 839 { 840 unsigned long rate, vco, frac; 841 u8 nd, no_a, no_b, no_d; 842 __maybe_unused u8 no_c; 843 u16 nf; 844 845 nd = inno_read(inno, 0xa1) & 0x3f; 846 nf = ((inno_read(inno, 0xa2) & 0x0f) << 8) | inno_read(inno, 0xa3); 847 vco = parent_rate * nf; 848 if ((inno_read(inno, 0xa2) & 0x30) == 0) { 849 frac = inno_read(inno, 0xd3) | 850 (inno_read(inno, 0xd2) << 8) | 851 (inno_read(inno, 0xd1) << 16); 852 vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24)); 853 } 854 if (inno_read(inno, 0xa0) & 2) { 855 rate = vco / (nd * 5); 856 } else { 857 no_a = inno_read(inno, 0xa5) & 0x1f; 858 no_b = ((inno_read(inno, 0xa5) >> 5) & 7) + 2; 859 no_c = (1 << ((inno_read(inno, 0xa6) >> 5) & 7)); 860 no_d = inno_read(inno, 0xa6) & 0x1f; 861 if (no_a == 1) 862 rate = vco / (nd * no_b * no_d * 2); 863 else 864 rate = vco / (nd * no_a * no_d * 2); 865 } 866 inno->pixclock = rate; 867 868 return rate; 869 } 870 871 #define PHY_TAB_LEN 60 872 873 static 874 int inno_hdmi_update_phy_table(struct inno_hdmi_phy *inno, u32 *config, 875 struct phy_config *phy_cfg, 876 int phy_table_size) 877 { 878 int i, j; 879 880 for (i = 0; i < phy_table_size; i++) { 881 phy_cfg[i].tmdsclock = 882 (unsigned long)config[i * 15]; 883 884 debug("%ld ", phy_cfg[i].tmdsclock); 885 for (j = 0; j < 14; j++) { 886 phy_cfg[i].regs[j] = (u8)config[i * 15 + 1 + j]; 887 debug("0x%02x ", phy_cfg[i].regs[j]); 888 } 889 debug("\n"); 890 } 891 892 /* 893 * The last set of phy cfg is used to indicate whether 894 * there is no more phy cfg data. 895 */ 896 phy_cfg[i].tmdsclock = ~0UL; 897 for (j = 0; j < 14; j++) 898 phy_cfg[i].regs[j] = 0; 899 900 return 0; 901 } 902 903 static const struct inno_hdmi_phy_ops rk3228_hdmi_phy_ops = { 904 .init = inno_hdmi_phy_rk3228_init, 905 .power_on = inno_hdmi_phy_rk3228_power_on, 906 .power_off = inno_hdmi_phy_rk3228_power_off, 907 .pre_pll_update = inno_hdmi_phy_rk3228_pre_pll_update, 908 }; 909 910 static const struct inno_hdmi_phy_ops rk3328_hdmi_phy_ops = { 911 .init = inno_hdmi_phy_rk3328_init, 912 .power_on = inno_hdmi_phy_rk3328_power_on, 913 .power_off = inno_hdmi_phy_rk3328_power_off, 914 .pre_pll_update = inno_hdmi_phy_rk3328_pre_pll_update, 915 .recalc_rate = inno_hdmi_3328_phy_pll_recalc_rate, 916 }; 917 918 static const struct inno_hdmi_phy_drv_data rk3228_hdmi_phy_drv_data = { 919 .dev_type = INNO_HDMI_PHY_RK3228, 920 .ops = &rk3228_hdmi_phy_ops, 921 .phy_cfg_table = rk3228_phy_cfg, 922 }; 923 924 static const struct inno_hdmi_phy_drv_data rk3328_hdmi_phy_drv_data = { 925 .dev_type = INNO_HDMI_PHY_RK3328, 926 .ops = &rk3328_hdmi_phy_ops, 927 .phy_cfg_table = rk3328_phy_cfg, 928 }; 929 930 static const struct rockchip_inno_data inno_hdmi_phy_of_match[] = { 931 { .compatible = "rockchip,rk3228-hdmi-phy", 932 .data = &rk3228_hdmi_phy_drv_data 933 }, 934 { .compatible = "rockchip,rk3328-hdmi-phy", 935 .data = &rk3328_hdmi_phy_drv_data 936 }, 937 {} 938 }; 939 940 static int inno_hdmi_phy_init(struct display_state *state) 941 { 942 const void *blob = state->blob; 943 struct connector_state *conn_state = &state->conn_state; 944 struct udevice *dev = conn_state->phy_dev; 945 ofnode phy_node = conn_state->phy_node; 946 struct inno_hdmi_phy *inno; 947 int i, val, phy_table_size, ret; 948 const char *name; 949 u32 *phy_config; 950 951 inno = malloc(sizeof(*inno)); 952 if (!inno) 953 return -ENOMEM; 954 955 inno->blob = blob; 956 inno->node = phy_node; 957 958 inno->regs = dev_read_addr_ptr(dev); 959 if (!inno->regs) { 960 printf("%s: failed to get phy address\n", __func__); 961 return -ENOMEM; 962 } 963 conn_state->phy_private = inno; 964 965 name = dev_read_string(dev, "compatible"); 966 for (i = 0; i < ARRAY_SIZE(inno_hdmi_phy_of_match); i++) { 967 if (!strcmp(name, inno_hdmi_phy_of_match[i].compatible)) { 968 inno->plat_data = inno_hdmi_phy_of_match[i].data; 969 break; 970 } 971 } 972 973 dev_read_prop(dev, "rockchip,phy-table", &val); 974 975 if (val >= 0) { 976 if (val % PHY_TAB_LEN || !val) { 977 printf("Invalid phy cfg table format!\n"); 978 return -EINVAL; 979 } 980 981 phy_config = malloc(val); 982 if (!phy_config) { 983 printf("kmalloc phy table failed\n"); 984 return -ENOMEM; 985 } 986 987 phy_table_size = val / PHY_TAB_LEN; 988 /* Effective phy cfg data and the end of phy cfg table */ 989 inno->phy_cfg = malloc(val + PHY_TAB_LEN); 990 if (!inno->phy_cfg) { 991 free(phy_config); 992 return -ENOMEM; 993 } 994 995 dev_read_u32_array(dev, "rockchip,phy-table", 996 phy_config, val / sizeof(u32)); 997 ret = inno_hdmi_update_phy_table(inno, phy_config, 998 inno->phy_cfg, 999 phy_table_size); 1000 if (ret) { 1001 free(phy_config); 1002 return ret; 1003 } 1004 free(phy_config); 1005 } else { 1006 printf("use default hdmi phy table\n"); 1007 } 1008 1009 if (i >= ARRAY_SIZE(inno_hdmi_phy_of_match)) 1010 return 0; 1011 1012 if (!inno->plat_data || !inno->plat_data->ops) 1013 return -EINVAL; 1014 1015 if (inno->plat_data->ops->init) 1016 inno->plat_data->ops->init(inno); 1017 1018 return 0; 1019 } 1020 1021 static unsigned long inno_hdmi_phy_set_pll(struct display_state *state, 1022 unsigned long rate) 1023 { 1024 inno_hdmi_phy_clk_prepare(state); 1025 inno_hdmi_phy_clk_is_prepared(state); 1026 inno_hdmi_phy_clk_set_rate(state, rate); 1027 return 0; 1028 } 1029 1030 static void 1031 inno_hdmi_phy_set_bus_width(struct display_state *state, u32 bus_width) 1032 { 1033 struct connector_state *conn_state = &state->conn_state; 1034 struct inno_hdmi_phy *inno = conn_state->phy_private; 1035 1036 inno->bus_width = bus_width; 1037 } 1038 1039 static long 1040 inno_hdmi_phy_clk_round_rate(struct display_state *state, unsigned long rate) 1041 { 1042 int i; 1043 const struct pre_pll_config *cfg = pre_pll_cfg_table; 1044 struct connector_state *conn_state = &state->conn_state; 1045 struct inno_hdmi_phy *inno = conn_state->phy_private; 1046 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate); 1047 1048 for (; cfg->pixclock != ~0UL; cfg++) 1049 if (cfg->pixclock == rate) 1050 break; 1051 1052 /* 1053 * XXX: Limit pixel clock under 600MHz 1054 * rk3228 does not support non-zero fracdiv 1055 */ 1056 if ((inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228 && 1057 cfg->fracdiv) || cfg->pixclock > 600000000) 1058 return -EINVAL; 1059 1060 /* 1061 * If there is no dts phy cfg table, use default phy cfg table. 1062 * The tmds clock maximum is 594MHz. So there is no need to check 1063 * whether tmds clock is out of range. 1064 */ 1065 if (!inno->phy_cfg) 1066 return cfg->pixclock; 1067 1068 /* Check if tmds clock is out of dts phy config's range. */ 1069 for (i = 0; inno->phy_cfg[i].tmdsclock != ~0UL; i++) { 1070 if (inno->phy_cfg[i].tmdsclock >= tmdsclock) 1071 break; 1072 } 1073 1074 if (inno->phy_cfg[i].tmdsclock == ~0UL) 1075 return -EINVAL; 1076 1077 return cfg->pixclock; 1078 } 1079 1080 const struct rockchip_phy_funcs inno_hdmi_phy_funcs = { 1081 .init = inno_hdmi_phy_init, 1082 .power_on = inno_hdmi_phy_power_on, 1083 .power_off = inno_hdmi_phy_power_off, 1084 .set_pll = inno_hdmi_phy_set_pll, 1085 .set_bus_width = inno_hdmi_phy_set_bus_width, 1086 .round_rate = inno_hdmi_phy_clk_round_rate, 1087 }; 1088