1 /* 2 * SPDX-License-Identifier: GPL-2.0+ 3 * (C) Copyright 2008-2016 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #include <clk-uclass.h> 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <misc.h> 12 #include <fdtdec.h> 13 #include <fdt_support.h> 14 #include <asm/unaligned.h> 15 #include <asm/arch/clock.h> 16 #include <dm/device.h> 17 #include <dm/lists.h> 18 #include <dm/read.h> 19 #include <asm/io.h> 20 #include <linux/list.h> 21 #include <div64.h> 22 #include <linux/media-bus-format.h> 23 24 #include "rockchip_display.h" 25 #include "rockchip_crtc.h" 26 #include "rockchip_phy.h" 27 28 #define INNO_HDMI_PHY_TIMEOUT_LOOP_COUNT 1000 29 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) 30 31 /* REG: 0x00 */ 32 #define PRE_PLL_REFCLK_SEL_MASK BIT(0) 33 #define PRE_PLL_REFCLK_SEL_PCLK BIT(0) 34 #define PRE_PLL_REFCLK_SEL_OSCCLK 0 35 /* REG: 0x01 */ 36 #define BYPASS_RXSENSE_EN_MASK BIT(2) 37 #define BYPASS_RXSENSE_EN BIT(2) 38 #define BYPASS_PWRON_EN_MASK BIT(1) 39 #define BYPASS_PWRON_EN BIT(1) 40 #define BYPASS_PLLPD_EN_MASK BIT(0) 41 #define BYPASS_PLLPD_EN BIT(0) 42 /* REG: 0x02 */ 43 #define BYPASS_PDATA_EN_MASK BIT(4) 44 #define BYPASS_PDATA_EN BIT(4) 45 #define PDATAEN_MASK BIT(0) 46 #define PDATAEN_DISABLE BIT(0) 47 #define PDATAEN_ENABLE 0 48 /* REG: 0x03 */ 49 #define BYPASS_AUTO_TERM_RES_CAL BIT(7) 50 #define AUDO_TERM_RES_CAL_SPEED_14_8(x) UPDATE(x, 6, 0) 51 /* REG: 0x04 */ 52 #define AUDO_TERM_RES_CAL_SPEED_7_0(x) UPDATE(x, 7, 0) 53 /* REG: 0xaa */ 54 #define POST_PLL_CTRL_MASK BIT(0) 55 #define POST_PLL_CTRL_MANUAL BIT(0) 56 /* REG: 0xe0 */ 57 #define POST_PLL_POWER_MASK BIT(5) 58 #define POST_PLL_POWER_DOWN BIT(5) 59 #define POST_PLL_POWER_UP 0 60 #define PRE_PLL_POWER_MASK BIT(4) 61 #define PRE_PLL_POWER_DOWN BIT(4) 62 #define PRE_PLL_POWER_UP 0 63 #define RXSENSE_CLK_CH_MASK BIT(3) 64 #define RXSENSE_CLK_CH_ENABLE BIT(3) 65 #define RXSENSE_DATA_CH2_MASK BIT(2) 66 #define RXSENSE_DATA_CH2_ENABLE BIT(2) 67 #define RXSENSE_DATA_CH1_MASK BIT(1) 68 #define RXSENSE_DATA_CH1_ENABLE BIT(1) 69 #define RXSENSE_DATA_CH0_MASK BIT(0) 70 #define RXSENSE_DATA_CH0_ENABLE BIT(0) 71 /* REG: 0xe1 */ 72 #define BANDGAP_MASK BIT(4) 73 #define BANDGAP_ENABLE BIT(4) 74 #define BANDGAP_DISABLE 0 75 #define TMDS_DRIVER_MASK GENMASK(3, 0) 76 #define TMDS_DRIVER_ENABLE UPDATE(0xf, 3, 0) 77 #define TMDS_DRIVER_DISABLE 0 78 /* REG: 0xe2 */ 79 #define PRE_PLL_FB_DIV_8_MASK BIT(7) 80 #define PRE_PLL_FB_DIV_8_SHIFT 7 81 #define PRE_PLL_FB_DIV_8(x) UPDATE(x, 7, 7) 82 #define PCLK_VCO_DIV_5_MASK BIT(5) 83 #define PCLK_VCO_DIV_5_SHIFT 5 84 #define PCLK_VCO_DIV_5(x) UPDATE(x, 5, 5) 85 #define PRE_PLL_PRE_DIV_MASK GENMASK(4, 0) 86 #define PRE_PLL_PRE_DIV(x) UPDATE(x, 4, 0) 87 /* REG: 0xe3 */ 88 #define PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0) 89 /* REG: 0xe4 */ 90 #define PRE_PLL_PCLK_DIV_B_MASK GENMASK(6, 5) 91 #define PRE_PLL_PCLK_DIV_B_SHIFT 5 92 #define PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5) 93 #define PRE_PLL_PCLK_DIV_A_MASK GENMASK(4, 0) 94 #define PRE_PLL_PCLK_DIV_A_SHIFT 0 95 #define PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0) 96 /* REG: 0xe5 */ 97 #define PRE_PLL_PCLK_DIV_C_MASK GENMASK(6, 5) 98 #define PRE_PLL_PCLK_DIV_C_SHIFT 5 99 #define PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5) 100 #define PRE_PLL_PCLK_DIV_D_MASK GENMASK(4, 0) 101 #define PRE_PLL_PCLK_DIV_D_SHIFT 0 102 #define PRE_PLL_PCLK_DIV_D(x) UPDATE(x, 4, 0) 103 /* REG: 0xe6 */ 104 #define PRE_PLL_TMDSCLK_DIV_C_MASK GENMASK(5, 4) 105 #define PRE_PLL_TMDSCLK_DIV_C(x) UPDATE(x, 5, 4) 106 #define PRE_PLL_TMDSCLK_DIV_A_MASK GENMASK(3, 2) 107 #define PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 3, 2) 108 #define PRE_PLL_TMDSCLK_DIV_B_MASK GENMASK(1, 0) 109 #define PRE_PLL_TMDSCLK_DIV_B(x) UPDATE(x, 1, 0) 110 /* REG: 0xe8 */ 111 #define PRE_PLL_LOCK_STATUS BIT(0) 112 /* REG: 0xe9 */ 113 #define POST_PLL_POST_DIV_EN_MASK GENMASK(7, 6) 114 #define POST_PLL_POST_DIV_ENABLE UPDATE(3, 7, 6) 115 #define POST_PLL_POST_DIV_DISABLE 0 116 #define POST_PLL_PRE_DIV_MASK GENMASK(4, 0) 117 #define POST_PLL_PRE_DIV(x) UPDATE(x, 4, 0) 118 /* REG: 0xea */ 119 #define POST_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0) 120 /* REG: 0xeb */ 121 #define POST_PLL_FB_DIV_8_MASK BIT(7) 122 #define POST_PLL_FB_DIV_8(x) UPDATE(x, 7, 7) 123 #define POST_PLL_POST_DIV_MASK GENMASK(5, 4) 124 #define POST_PLL_POST_DIV(x) UPDATE(x, 5, 4) 125 #define POST_PLL_LOCK_STATUS BIT(0) 126 /* REG: 0xee */ 127 #define TMDS_CH_TA_MASK GENMASK(7, 4) 128 #define TMDS_CH_TA_ENABLE UPDATE(0xf, 7, 4) 129 #define TMDS_CH_TA_DISABLE 0 130 /* REG: 0xef */ 131 #define TMDS_CLK_CH_TA(x) UPDATE(x, 7, 6) 132 #define TMDS_DATA_CH2_TA(x) UPDATE(x, 5, 4) 133 #define TMDS_DATA_CH1_TA(x) UPDATE(x, 3, 2) 134 #define TMDS_DATA_CH0_TA(x) UPDATE(x, 1, 0) 135 /* REG: 0xf0 */ 136 #define TMDS_DATA_CH2_PRE_EMPHASIS_MASK GENMASK(5, 4) 137 #define TMDS_DATA_CH2_PRE_EMPHASIS(x) UPDATE(x, 5, 4) 138 #define TMDS_DATA_CH1_PRE_EMPHASIS_MASK GENMASK(3, 2) 139 #define TMDS_DATA_CH1_PRE_EMPHASIS(x) UPDATE(x, 3, 2) 140 #define TMDS_DATA_CH0_PRE_EMPHASIS_MASK GENMASK(1, 0) 141 #define TMDS_DATA_CH0_PRE_EMPHASIS(x) UPDATE(x, 1, 0) 142 /* REG: 0xf1 */ 143 #define TMDS_CLK_CH_OUTPUT_SWING(x) UPDATE(x, 7, 4) 144 #define TMDS_DATA_CH2_OUTPUT_SWING(x) UPDATE(x, 3, 0) 145 /* REG: 0xf2 */ 146 #define TMDS_DATA_CH1_OUTPUT_SWING(x) UPDATE(x, 7, 4) 147 #define TMDS_DATA_CH0_OUTPUT_SWING(x) UPDATE(x, 3, 0) 148 149 enum inno_hdmi_phy_type { 150 INNO_HDMI_PHY_RK3228, 151 INNO_HDMI_PHY_RK3328, 152 INNO_HDMI_PHY_RK3528 153 }; 154 155 struct inno_hdmi_phy_drv_data; 156 157 struct phy_config { 158 unsigned long tmdsclock; 159 u8 regs[14]; 160 }; 161 162 struct inno_hdmi_phy { 163 struct udevice *dev; 164 ofnode node; 165 void *regs; 166 167 /* platform data */ 168 const struct inno_hdmi_phy_drv_data *plat_data; 169 unsigned long pixclock; 170 u32 bus_width; 171 struct phy_config *phy_cfg; 172 }; 173 174 struct pre_pll_config { 175 unsigned long pixclock; 176 unsigned long tmdsclock; 177 u8 prediv; 178 u16 fbdiv; 179 u8 tmds_div_a; 180 u8 tmds_div_b; 181 u8 tmds_div_c; 182 u8 pclk_div_a; 183 u8 pclk_div_b; 184 u8 pclk_div_c; 185 u8 pclk_div_d; 186 u8 vco_div_5_en; 187 u32 fracdiv; 188 }; 189 190 struct post_pll_config { 191 unsigned long tmdsclock; 192 u8 prediv; 193 u16 fbdiv; 194 u8 postdiv; 195 u8 version; 196 }; 197 198 struct inno_hdmi_phy_ops { 199 void (*init)(struct inno_hdmi_phy *inno); 200 int (*power_on)(struct inno_hdmi_phy *inno, 201 const struct post_pll_config *cfg, 202 const struct phy_config *phy_cfg); 203 void (*power_off)(struct inno_hdmi_phy *inno); 204 int (*pre_pll_update)(struct inno_hdmi_phy *inno, 205 const struct pre_pll_config *cfg); 206 unsigned long (*recalc_rate)(struct inno_hdmi_phy *inno, 207 unsigned long parent_rate); 208 }; 209 210 struct inno_hdmi_phy_drv_data { 211 enum inno_hdmi_phy_type dev_type; 212 const struct inno_hdmi_phy_ops *ops; 213 const struct phy_config *phy_cfg_table; 214 }; 215 216 struct rockchip_inno_data { 217 char compatible[30]; 218 const void *data; 219 }; 220 221 struct clk_inno_hdmi { 222 struct udevice *dev; 223 ulong rate; 224 }; 225 226 /* global variables are used to pass reource from phy drivers to clk driver */ 227 static struct inno_hdmi_phy *g_inno; 228 229 static const struct pre_pll_config pre_pll_cfg_table[] = { 230 { 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0}, 231 { 27000000, 33750000, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0}, 232 { 40000000, 40000000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0}, 233 { 59341000, 59341000, 1, 98, 3, 1, 2, 1, 3, 3, 4, 0, 0xE6AE6B}, 234 { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0}, 235 { 59341000, 74176250, 1, 98, 0, 3, 3, 1, 3, 3, 4, 0, 0xE6AE6B}, 236 { 59400000, 74250000, 1, 99, 1, 2, 2, 1, 3, 3, 4, 0, 0}, 237 { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B}, 238 { 74250000, 74250000, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0}, 239 { 74176000, 92720000, 4, 494, 1, 2, 2, 1, 3, 3, 4, 0, 0x816817}, 240 { 74250000, 92812500, 4, 495, 1, 2, 2, 1, 3, 3, 4, 0, 0}, 241 {148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B}, 242 {148500000, 148500000, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0}, 243 {148352000, 185440000, 4, 494, 0, 2, 2, 1, 3, 2, 2, 0, 0x816817}, 244 {148500000, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0}, 245 {296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B}, 246 {297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0}, 247 {296703000, 370878750, 4, 494, 1, 2, 0, 1, 3, 1, 1, 0, 0x816817}, 248 {297000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 0, 0}, 249 {593407000, 296703500, 1, 98, 0, 1, 1, 1, 0, 2, 1, 0, 0xE6AE6B}, 250 {594000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 1, 0, 0}, 251 {593407000, 370879375, 4, 494, 1, 2, 0, 1, 3, 1, 1, 1, 0x816817}, 252 {594000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 1, 0}, 253 {593407000, 593407000, 1, 98, 0, 2, 0, 1, 0, 1, 1, 0, 0xE6AE6B}, 254 {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0}, 255 { ~0UL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 256 }; 257 258 static const struct post_pll_config post_pll_cfg_table[] = { 259 {33750000, 1, 40, 8, 1}, 260 {33750000, 1, 80, 8, 2}, 261 {33750000, 1, 10, 2, 4}, 262 {74250000, 1, 40, 8, 1}, 263 {74250000, 18, 80, 8, 2}, 264 {74250000, 1, 20, 4, 8}, 265 {148500000, 2, 40, 4, 3}, 266 {148500000, 1, 10, 2, 8}, 267 {297000000, 4, 40, 2, 3}, 268 {297000000, 2, 20, 2, 8}, 269 {594000000, 8, 40, 1, 3}, 270 {594000000, 4, 20, 1, 8}, 271 { ~0UL, 0, 0, 0, 0} 272 }; 273 274 static const struct phy_config rk3228_phy_cfg[] = { 275 { 165000000, { 276 0xaa, 0x00, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 277 0x00, 0x00, 0x00, 0x00, 0x00, 278 }, 279 }, { 280 340000000, { 281 0xaa, 0x15, 0x6a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 282 0x00, 0x00, 0x00, 0x00, 0x00, 283 }, 284 }, { 285 594000000, { 286 0xaa, 0x15, 0x7a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 287 0x00, 0x00, 0x00, 0x00, 0x00, 288 }, 289 }, { 290 ~0UL, { 291 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 292 0x00, 0x00, 0x00, 0x00, 0x00, 293 }, 294 } 295 }; 296 297 static const struct phy_config rk3328_phy_cfg[] = { 298 { 165000000, { 299 0x07, 0x08, 0x08, 0x08, 0x00, 0x00, 0x08, 0x08, 0x08, 300 0x00, 0xac, 0xcc, 0xcc, 0xcc, 301 }, 302 }, { 303 340000000, { 304 0x0b, 0x0d, 0x0d, 0x0d, 0x07, 0x15, 0x08, 0x08, 0x08, 305 0x3f, 0xac, 0xcc, 0xcd, 0xdd, 306 }, 307 }, { 308 594000000, { 309 0x10, 0x1a, 0x1a, 0x1a, 0x07, 0x15, 0x08, 0x08, 0x08, 310 0x00, 0xac, 0xcc, 0xcc, 0xcc, 311 }, 312 }, { 313 ~0UL, { 314 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 315 0x00, 0x00, 0x00, 0x00, 0x00, 316 }, 317 } 318 }; 319 320 static const struct phy_config rk3528_phy_cfg[] = { 321 /* tmdsclk bias-clk bias-data voltage-clk voltage-data pre-emphasis-data */ 322 { 165000000, { 323 0x03, 0x04, 0x0c, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 324 0x00, 0x00, 0x00, 0x00, 0x00, 325 }, 326 }, { 327 340000000, { 328 0x03, 0x04, 0x0c, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 329 0x00, 0x00, 0x00, 0x00, 0x00, 330 }, 331 }, { 332 594000000, { 333 0x02, 0x08, 0x0d, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 334 0x00, 0x00, 0x00, 0x00, 0x00, 335 }, 336 }, { 337 ~0UL, { 338 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 339 0x00, 0x00, 0x00, 0x00, 0x00, 340 }, 341 } 342 }; 343 344 static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val) 345 { 346 writel(val, inno->regs + (reg * 4)); 347 } 348 349 static inline u8 inno_read(struct inno_hdmi_phy *inno, u32 reg) 350 { 351 u32 val; 352 353 val = readl(inno->regs + (reg * 4)); 354 355 return val; 356 } 357 358 static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg, 359 u8 mask, u8 val) 360 { 361 u32 tmp, orig; 362 363 orig = inno_read(inno, reg); 364 tmp = orig & ~mask; 365 tmp |= val & mask; 366 inno_write(inno, reg, tmp); 367 } 368 369 static u32 inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno, 370 unsigned long rate) 371 { 372 u32 tmdsclk; 373 374 switch (inno->bus_width) { 375 case 4: 376 tmdsclk = (u32)rate / 2; 377 break; 378 case 5: 379 tmdsclk = (u32)rate * 5 / 8; 380 break; 381 case 6: 382 tmdsclk = (u32)rate * 3 / 4; 383 break; 384 case 10: 385 tmdsclk = (u32)rate * 5 / 4; 386 break; 387 case 12: 388 tmdsclk = (u32)rate * 3 / 2; 389 break; 390 case 16: 391 tmdsclk = (u32)rate * 2; 392 break; 393 default: 394 tmdsclk = rate; 395 } 396 397 return tmdsclk; 398 } 399 400 static u8 rk_get_cpu_version(void) 401 { 402 u8 val = 0; 403 #ifdef CONFIG_ROCKCHIP_EFUSE 404 struct udevice *dev; 405 u32 regs[2] = {0}; 406 u8 fuses[1]; 407 ofnode node; 408 int ret; 409 410 ret = uclass_get_device_by_driver(UCLASS_MISC, 411 DM_GET_DRIVER(rockchip_efuse), &dev); 412 if (ret) { 413 printf("%s: no misc-device found\n", __func__); 414 return -EINVAL; 415 } 416 417 node = dev_read_subnode(dev, "cpu-version"); 418 if (!ofnode_valid(node)) 419 return -EINVAL; 420 421 ret = ofnode_read_u32_array(node, "reg", regs, 2); 422 if (ret) { 423 printf("Cannot get efuse reg\n"); 424 return -EINVAL; 425 } 426 427 ret = misc_read(dev, regs[0], &fuses, regs[1]); 428 if (ret) { 429 printf("%s: misc_read failed\n", __func__); 430 return 0; 431 } 432 433 val = fuses[0]; 434 val = (val >> 3) & 0x1; 435 #endif 436 return val; 437 } 438 439 static int inno_hdmi_phy_power_on(struct rockchip_phy *phy) 440 { 441 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); 442 const struct post_pll_config *cfg = post_pll_cfg_table; 443 const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table; 444 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, inno->pixclock); 445 u32 chipversion = 1; 446 447 printf("start Inno HDMI PHY Power On\n"); 448 449 if (inno->phy_cfg) 450 phy_cfg = inno->phy_cfg; 451 452 if (!tmdsclock) { 453 printf("TMDS clock is zero!\n"); 454 return -EINVAL; 455 } 456 457 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3328 && 458 rk_get_cpu_version()) 459 chipversion = 2; 460 else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228 && 461 tmdsclock <= 33750000) 462 chipversion = 4; 463 else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3528) 464 chipversion = 8; 465 466 printf("tmdsclock = %d; chipversion = %d\n", tmdsclock, chipversion); 467 468 for (; cfg->tmdsclock != ~0UL; cfg++) 469 if (tmdsclock <= cfg->tmdsclock && 470 cfg->version & chipversion) 471 break; 472 473 for (; phy_cfg->tmdsclock != ~0UL; phy_cfg++) 474 if (tmdsclock <= phy_cfg->tmdsclock) 475 break; 476 477 if (cfg->tmdsclock == ~0UL || phy_cfg->tmdsclock == ~0UL) 478 return -EINVAL; 479 480 printf("Inno HDMI PHY Power On\n"); 481 if (inno->plat_data->ops->power_on) 482 return inno->plat_data->ops->power_on(inno, cfg, phy_cfg); 483 else 484 return -EINVAL; 485 } 486 487 static int inno_hdmi_phy_power_off(struct rockchip_phy *phy) 488 { 489 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); 490 491 if (inno->plat_data->ops->power_off) 492 inno->plat_data->ops->power_off(inno); 493 printf("Inno HDMI PHY Power Off\n"); 494 495 return 0; 496 } 497 498 static int inno_hdmi_phy_clk_is_prepared(struct inno_hdmi_phy *inno) 499 { 500 u8 status; 501 502 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) 503 status = inno_read(inno, 0xe0) & PRE_PLL_POWER_MASK; 504 else 505 status = inno_read(inno, 0xa0) & 1; 506 507 return status ? 0 : 1; 508 } 509 510 static int inno_hdmi_phy_clk_prepare(struct inno_hdmi_phy *inno) 511 { 512 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) 513 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, 514 PRE_PLL_POWER_UP); 515 else 516 inno_update_bits(inno, 0xa0, 1, 0); 517 518 return 0; 519 } 520 521 static int inno_hdmi_phy_clk_set_rate(struct inno_hdmi_phy *inno, 522 unsigned long rate) 523 { 524 const struct pre_pll_config *cfg = pre_pll_cfg_table; 525 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate); 526 527 for (; cfg->pixclock != ~0UL; cfg++) 528 if (cfg->pixclock == rate && cfg->tmdsclock == tmdsclock) 529 break; 530 531 if (cfg->pixclock == ~0UL) { 532 printf("unsupported rate %lu\n", rate); 533 return -EINVAL; 534 } 535 536 if (inno->plat_data->ops->pre_pll_update) 537 inno->plat_data->ops->pre_pll_update(inno, cfg); 538 539 inno->pixclock = rate; 540 541 return 0; 542 } 543 544 static void inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno) 545 { 546 u32 m, v; 547 548 /* 549 * Use phy internal register control 550 * rxsense/poweron/pllpd/pdataen signal. 551 */ 552 m = BYPASS_RXSENSE_EN_MASK | BYPASS_PWRON_EN_MASK | 553 BYPASS_PLLPD_EN_MASK; 554 v = BYPASS_RXSENSE_EN | BYPASS_PWRON_EN | BYPASS_PLLPD_EN; 555 inno_update_bits(inno, 0x01, m, v); 556 inno_update_bits(inno, 0x02, BYPASS_PDATA_EN_MASK, BYPASS_PDATA_EN); 557 558 /* manual power down post-PLL */ 559 inno_update_bits(inno, 0xaa, POST_PLL_CTRL_MASK, POST_PLL_CTRL_MANUAL); 560 } 561 562 static int 563 inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy *inno, 564 const struct post_pll_config *cfg, 565 const struct phy_config *phy_cfg) 566 { 567 int pll_tries; 568 u32 m, v; 569 570 /* pdata_en disable */ 571 inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_DISABLE); 572 573 /* Power down Post-PLL */ 574 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN); 575 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN); 576 577 /* Post-PLL update */ 578 m = POST_PLL_PRE_DIV_MASK; 579 v = POST_PLL_PRE_DIV(cfg->prediv); 580 inno_update_bits(inno, 0xe9, m, v); 581 582 m = POST_PLL_FB_DIV_8_MASK; 583 v = POST_PLL_FB_DIV_8(cfg->fbdiv >> 8); 584 inno_update_bits(inno, 0xeb, m, v); 585 inno_write(inno, 0xea, POST_PLL_FB_DIV_7_0(cfg->fbdiv)); 586 587 if (cfg->postdiv == 1) { 588 /* Disable Post-PLL post divider */ 589 m = POST_PLL_POST_DIV_EN_MASK; 590 v = POST_PLL_POST_DIV_DISABLE; 591 inno_update_bits(inno, 0xe9, m, v); 592 } else { 593 /* Enable Post-PLL post divider */ 594 m = POST_PLL_POST_DIV_EN_MASK; 595 v = POST_PLL_POST_DIV_ENABLE; 596 inno_update_bits(inno, 0xe9, m, v); 597 598 m = POST_PLL_POST_DIV_MASK; 599 v = POST_PLL_POST_DIV(cfg->postdiv / 2 - 1); 600 inno_update_bits(inno, 0xeb, m, v); 601 } 602 603 for (v = 0; v < 4; v++) 604 inno_write(inno, 0xef + v, phy_cfg->regs[v]); 605 606 /* Power up Post-PLL */ 607 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_UP); 608 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP); 609 610 /* BandGap enable */ 611 inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_ENABLE); 612 613 /* TMDS driver enable */ 614 inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_ENABLE); 615 616 /* Wait for post PLL lock */ 617 pll_tries = 0; 618 while (!(inno_read(inno, 0xeb) & POST_PLL_LOCK_STATUS)) { 619 if (pll_tries == INNO_HDMI_PHY_TIMEOUT_LOOP_COUNT) { 620 printf("Post-PLL unlock\n"); 621 return -ETIMEDOUT; 622 } 623 624 pll_tries++; 625 udelay(100); 626 } 627 628 if (cfg->tmdsclock > 340000000) 629 mdelay(100); 630 631 /* pdata_en enable */ 632 inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_ENABLE); 633 return 0; 634 } 635 636 static void inno_hdmi_phy_rk3228_power_off(struct inno_hdmi_phy *inno) 637 { 638 /* TMDS driver Disable */ 639 inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_DISABLE); 640 641 /* BandGap Disable */ 642 inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_DISABLE); 643 644 /* Post-PLL power down */ 645 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN); 646 } 647 648 static int 649 inno_hdmi_phy_rk3228_pre_pll_update(struct inno_hdmi_phy *inno, 650 const struct pre_pll_config *cfg) 651 { 652 int pll_tries; 653 u32 m, v; 654 655 /* Power down PRE-PLL */ 656 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN); 657 658 m = PRE_PLL_FB_DIV_8_MASK | PCLK_VCO_DIV_5_MASK | PRE_PLL_PRE_DIV_MASK; 659 v = PRE_PLL_FB_DIV_8(cfg->fbdiv >> 8) | 660 PCLK_VCO_DIV_5(cfg->vco_div_5_en) | PRE_PLL_PRE_DIV(cfg->prediv); 661 inno_update_bits(inno, 0xe2, m, v); 662 663 inno_write(inno, 0xe3, PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); 664 665 m = PRE_PLL_PCLK_DIV_B_MASK | PRE_PLL_PCLK_DIV_A_MASK; 666 v = PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b) | 667 PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a); 668 inno_update_bits(inno, 0xe4, m, v); 669 670 m = PRE_PLL_PCLK_DIV_C_MASK | PRE_PLL_PCLK_DIV_D_MASK; 671 v = PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) | 672 PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d); 673 inno_update_bits(inno, 0xe5, m, v); 674 675 m = PRE_PLL_TMDSCLK_DIV_C_MASK | PRE_PLL_TMDSCLK_DIV_A_MASK | 676 PRE_PLL_TMDSCLK_DIV_B_MASK; 677 v = PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) | 678 PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) | 679 PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b); 680 inno_update_bits(inno, 0xe6, m, v); 681 682 /* Power up PRE-PLL */ 683 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP); 684 685 /* Wait for Pre-PLL lock */ 686 pll_tries = 0; 687 while (!(inno_read(inno, 0xe8) & PRE_PLL_LOCK_STATUS)) { 688 if (pll_tries == INNO_HDMI_PHY_TIMEOUT_LOOP_COUNT) { 689 printf("Pre-PLL unlock\n"); 690 return -ETIMEDOUT; 691 } 692 693 pll_tries++; 694 udelay(100); 695 } 696 697 return 0; 698 } 699 700 static void inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno) 701 { 702 /* 703 * Use phy internal register control 704 * rxsense/poweron/pllpd/pdataen signal. 705 */ 706 inno_write(inno, 0x01, 0x07); 707 inno_write(inno, 0x02, 0x91); 708 } 709 710 static int 711 inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, 712 const struct post_pll_config *cfg, 713 const struct phy_config *phy_cfg) 714 { 715 u32 val; 716 717 /* set pdata_en to 0 */ 718 inno_update_bits(inno, 0x02, 1, 0); 719 /* Power off post PLL */ 720 inno_update_bits(inno, 0xaa, 1, 1); 721 722 val = cfg->fbdiv & 0xff; 723 inno_write(inno, 0xac, val); 724 if (cfg->postdiv == 1) { 725 inno_write(inno, 0xaa, 2); 726 val = (cfg->fbdiv >> 8) | cfg->prediv; 727 inno_write(inno, 0xab, val); 728 } else { 729 val = (cfg->postdiv / 2) - 1; 730 inno_write(inno, 0xad, val); 731 val = (cfg->fbdiv >> 8) | cfg->prediv; 732 inno_write(inno, 0xab, val); 733 inno_write(inno, 0xaa, 0x0e); 734 } 735 736 for (val = 0; val < 14; val++) 737 inno_write(inno, 0xb5 + val, phy_cfg->regs[val]); 738 739 /* bit[7:6] of reg c8/c9/ca/c8 is ESD detect threshold: 740 * 00 - 340mV 741 * 01 - 280mV 742 * 10 - 260mV 743 * 11 - 240mV 744 * default is 240mV, now we set it to 340mV 745 */ 746 inno_write(inno, 0xc8, 0); 747 inno_write(inno, 0xc9, 0); 748 inno_write(inno, 0xca, 0); 749 inno_write(inno, 0xcb, 0); 750 751 if (phy_cfg->tmdsclock > 340000000) { 752 /* Set termination resistor to 100ohm */ 753 val = 75000000 / 100000; 754 inno_write(inno, 0xc5, ((val >> 8) & 0xff) | 0x80); 755 inno_write(inno, 0xc6, val & 0xff); 756 inno_write(inno, 0xc7, 3 << 1); 757 inno_write(inno, 0xc5, ((val >> 8) & 0xff)); 758 } else if (phy_cfg->tmdsclock > 165000000) { 759 inno_write(inno, 0xc5, 0x81); 760 /* clk termination resistor is 50ohm 761 * data termination resistor is 150ohm 762 */ 763 inno_write(inno, 0xc8, 0x30); 764 inno_write(inno, 0xc9, 0x10); 765 inno_write(inno, 0xca, 0x10); 766 inno_write(inno, 0xcb, 0x10); 767 } else { 768 inno_write(inno, 0xc5, 0x81); 769 } 770 771 /* set TMDS sync detection counter length */ 772 val = 47520000000UL / phy_cfg->tmdsclock; 773 inno_write(inno, 0xd8, (val >> 8) & 0xff); 774 inno_write(inno, 0xd9, val & 0xff); 775 776 /* Power up post PLL */ 777 inno_update_bits(inno, 0xaa, 1, 0); 778 /* Power up tmds driver */ 779 inno_update_bits(inno, 0xb0, 4, 4); 780 inno_write(inno, 0xb2, 0x0f); 781 782 /* Wait for post PLL lock */ 783 for (val = 0; val < 5; val++) { 784 if (inno_read(inno, 0xaf) & 1) 785 break; 786 udelay(1000); 787 } 788 if (!(inno_read(inno, 0xaf) & 1)) { 789 printf("HDMI PHY Post PLL unlock\n"); 790 return -ETIMEDOUT; 791 } 792 if (phy_cfg->tmdsclock > 340000000) 793 mdelay(100); 794 /* set pdata_en to 1 */ 795 inno_update_bits(inno, 0x02, 1, 1); 796 797 return 0; 798 } 799 800 static void inno_hdmi_phy_rk3328_power_off(struct inno_hdmi_phy *inno) 801 { 802 /* Power off driver */ 803 inno_write(inno, 0xb2, 0); 804 /* Power off band gap */ 805 inno_update_bits(inno, 0xb0, 4, 0); 806 /* Power off post pll */ 807 inno_update_bits(inno, 0xaa, 1, 1); 808 } 809 810 static int 811 inno_hdmi_phy_rk3328_pre_pll_update(struct inno_hdmi_phy *inno, 812 const struct pre_pll_config *cfg) 813 { 814 u32 val; 815 816 /* Power off PLL */ 817 inno_update_bits(inno, 0xa0, 1, 1); 818 /* Configure pre-pll */ 819 inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1); 820 inno_write(inno, 0xa1, cfg->prediv); 821 if (cfg->fracdiv) 822 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xc0; 823 else 824 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xf0; 825 inno_write(inno, 0xa2, val); 826 inno_write(inno, 0xa3, cfg->fbdiv & 0xff); 827 val = (cfg->pclk_div_a & 0x1f) | 828 ((cfg->pclk_div_b & 3) << 5); 829 inno_write(inno, 0xa5, val); 830 val = (cfg->pclk_div_d & 0x1f) | 831 ((cfg->pclk_div_c & 3) << 5); 832 inno_write(inno, 0xa6, val); 833 val = ((cfg->tmds_div_a & 3) << 4) | 834 ((cfg->tmds_div_b & 3) << 2) | 835 (cfg->tmds_div_c & 3); 836 inno_write(inno, 0xa4, val); 837 838 if (cfg->fracdiv) { 839 val = cfg->fracdiv & 0xff; 840 inno_write(inno, 0xd3, val); 841 val = (cfg->fracdiv >> 8) & 0xff; 842 inno_write(inno, 0xd2, val); 843 val = (cfg->fracdiv >> 16) & 0xff; 844 inno_write(inno, 0xd1, val); 845 } else { 846 inno_write(inno, 0xd3, 0); 847 inno_write(inno, 0xd2, 0); 848 inno_write(inno, 0xd1, 0); 849 } 850 851 /* Power up PLL */ 852 inno_update_bits(inno, 0xa0, 1, 0); 853 854 /* Wait for PLL lock */ 855 for (val = 0; val < 5; val++) { 856 if (inno_read(inno, 0xa9) & 1) 857 break; 858 udelay(1000); 859 } 860 if (val == 5) { 861 printf("Pre-PLL unlock\n"); 862 return -ETIMEDOUT; 863 } 864 865 return 0; 866 } 867 868 static unsigned long 869 inno_hdmi_3328_phy_pll_recalc_rate(struct inno_hdmi_phy *inno, 870 unsigned long parent_rate) 871 { 872 unsigned long rate, vco, frac; 873 u8 nd, no_a, no_b, no_d; 874 __maybe_unused u8 no_c; 875 u16 nf; 876 877 nd = inno_read(inno, 0xa1) & 0x3f; 878 nf = ((inno_read(inno, 0xa2) & 0x0f) << 8) | inno_read(inno, 0xa3); 879 vco = parent_rate * nf; 880 if ((inno_read(inno, 0xa2) & 0x30) == 0) { 881 frac = inno_read(inno, 0xd3) | 882 (inno_read(inno, 0xd2) << 8) | 883 (inno_read(inno, 0xd1) << 16); 884 vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24)); 885 } 886 if (inno_read(inno, 0xa0) & 2) { 887 rate = vco / (nd * 5); 888 } else { 889 no_a = inno_read(inno, 0xa5) & 0x1f; 890 no_b = ((inno_read(inno, 0xa5) >> 5) & 7) + 2; 891 no_c = (1 << ((inno_read(inno, 0xa6) >> 5) & 7)); 892 no_d = inno_read(inno, 0xa6) & 0x1f; 893 if (no_a == 1) 894 rate = vco / (nd * no_b * no_d * 2); 895 else 896 rate = vco / (nd * no_a * no_d * 2); 897 } 898 inno->pixclock = rate; 899 900 return rate; 901 } 902 903 static int 904 inno_hdmi_phy_rk3528_power_on(struct inno_hdmi_phy *inno, 905 const struct post_pll_config *cfg, 906 const struct phy_config *phy_cfg) 907 { 908 u32 val; 909 u64 temp; 910 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, inno->pixclock); 911 912 /* Power off post PLL */ 913 inno_update_bits(inno, 0xaa, 1, 0); 914 915 val = cfg->prediv; 916 inno_write(inno, 0xab, val); 917 918 if (cfg->postdiv == 1) { 919 inno_write(inno, 0xad, 0x8); 920 inno_write(inno, 0xaa, 2); 921 } else { 922 val = (cfg->postdiv / 2) - 1; 923 inno_write(inno, 0xad, val); 924 inno_write(inno, 0xaa, 0x0e); 925 } 926 927 val = cfg->fbdiv & 0xff; 928 inno_write(inno, 0xac, val); 929 val = (cfg->fbdiv >> 8) & BIT(0); 930 inno_update_bits(inno, 0xad, BIT(4), val); 931 932 /* current bias clk/data 2 */ 933 val = phy_cfg->regs[0] << 4 | phy_cfg->regs[1]; 934 inno_write(inno, 0xbf, val); 935 936 /* current bias data 1/0 */ 937 val = phy_cfg->regs[1] << 4 | phy_cfg->regs[1]; 938 inno_write(inno, 0xc0, val); 939 940 /* output voltage */ 941 inno_write(inno, 0xb5, phy_cfg->regs[2]); 942 inno_write(inno, 0xb6, phy_cfg->regs[3]); 943 inno_write(inno, 0xb7, phy_cfg->regs[3]); 944 inno_write(inno, 0xb8, phy_cfg->regs[3]); 945 946 /* pre-emphasis */ 947 inno_write(inno, 0xbb, phy_cfg->regs[4]); 948 inno_write(inno, 0xbc, phy_cfg->regs[4]); 949 inno_write(inno, 0xbd, phy_cfg->regs[4]); 950 951 /* enable LDO */ 952 inno_write(inno, 0xb4, 0x7); 953 954 /* enable serializer */ 955 inno_write(inno, 0xbe, 0x70); 956 957 inno_write(inno, 0xb2, 0x0f); 958 959 for (val = 0; val < 5; val++) { 960 if (inno_read(inno, 0xaf) & 1) 961 break; 962 udelay(1000); 963 } 964 if (!(inno_read(inno, 0xaf) & 1)) { 965 dev_err(inno->dev, "HDMI PHY Post PLL unlock\n"); 966 return -ETIMEDOUT; 967 } 968 969 /* set termination resistance */ 970 if (phy_cfg->tmdsclock > 340000000) { 971 inno_write(inno, 0xc7, 0x76); 972 inno_write(inno, 0xc5, 0x83); 973 inno_write(inno, 0xc8, 0x00); 974 inno_write(inno, 0xc9, 0x2f); 975 inno_write(inno, 0xca, 0x2f); 976 inno_write(inno, 0xcb, 0x2f); 977 } else { 978 inno_write(inno, 0xc7, 0x76); 979 inno_write(inno, 0xc5, 0x83); 980 inno_write(inno, 0xc8, 0x00); 981 inno_write(inno, 0xc9, 0x0f); 982 inno_write(inno, 0xca, 0x0f); 983 inno_write(inno, 0xcb, 0x0f); 984 } 985 986 987 /* set TMDS sync detection counter length */ 988 temp = 47520000000UL / tmdsclock; 989 inno_write(inno, 0xd8, (temp >> 8) & 0xff); 990 inno_write(inno, 0xd9, temp & 0xff); 991 992 if (phy_cfg->tmdsclock > 340000000) 993 mdelay(100); 994 /* set pdata_en to 0/1 */ 995 inno_update_bits(inno, 0x02, 1, 0); 996 mdelay(1); 997 inno_update_bits(inno, 0x02, 1, 1); 998 999 /* Enable PHY IRQ */ 1000 inno_write(inno, 0x05, 0x22); 1001 inno_write(inno, 0x07, 0x22); 1002 inno_write(inno, 0xcc, 0x0f); 1003 1004 return 0; 1005 } 1006 1007 static void inno_hdmi_phy_rk3528_power_off(struct inno_hdmi_phy *inno) 1008 { 1009 /* Power off driver */ 1010 inno_write(inno, 0xb2, 0); 1011 /* Power off band gap */ 1012 inno_update_bits(inno, 0xb0, 4, 0); 1013 /* Power off post pll */ 1014 inno_update_bits(inno, 0xaa, 1, 1); 1015 1016 /* Disable PHY IRQ */ 1017 inno_write(inno, 0x05, 0); 1018 inno_write(inno, 0x07, 0); 1019 } 1020 1021 static void inno_hdmi_phy_rk3528_init(struct inno_hdmi_phy *inno) 1022 { 1023 /* 1024 * Use phy internal register control 1025 * rxsense/poweron/pllpd/pdataen signal. 1026 */ 1027 inno_write(inno, 0x02, 0x81); 1028 } 1029 1030 static int 1031 inno_hdmi_phy_rk3528_pre_pll_update(struct inno_hdmi_phy *inno, 1032 const struct pre_pll_config *cfg) 1033 { 1034 u32 val; 1035 1036 inno_update_bits(inno, 0xb0, 4, 4); 1037 inno_write(inno, 0xcc, 0x0f); 1038 1039 /* Power on PLL */ 1040 inno_update_bits(inno, 0xa0, 1, 0); 1041 /* Configure pre-pll */ 1042 inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1); 1043 inno_write(inno, 0xa1, cfg->prediv); 1044 if (cfg->fracdiv) 1045 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xc0; 1046 else 1047 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xf0; 1048 inno_write(inno, 0xa2, val); 1049 inno_write(inno, 0xa3, cfg->fbdiv & 0xff); 1050 val = (cfg->pclk_div_a & 0x1f) | 1051 ((cfg->pclk_div_b & 3) << 5); 1052 inno_write(inno, 0xa5, val); 1053 val = (cfg->pclk_div_d & 0x1f) | 1054 ((cfg->pclk_div_c & 3) << 5); 1055 inno_write(inno, 0xa6, val); 1056 val = ((cfg->tmds_div_a & 3) << 4) | 1057 ((cfg->tmds_div_b & 3) << 2) | 1058 (cfg->tmds_div_c & 3); 1059 inno_write(inno, 0xa4, val); 1060 1061 if (cfg->fracdiv) { 1062 val = cfg->fracdiv & 0xff; 1063 inno_write(inno, 0xd3, val); 1064 val = (cfg->fracdiv >> 8) & 0xff; 1065 inno_write(inno, 0xd2, val); 1066 val = (cfg->fracdiv >> 16) & 0xff; 1067 inno_write(inno, 0xd1, val); 1068 } else { 1069 inno_write(inno, 0xd3, 0); 1070 inno_write(inno, 0xd2, 0); 1071 inno_write(inno, 0xd1, 0); 1072 } 1073 1074 /* Wait for PLL lock */ 1075 for (val = 0; val < 5; val++) { 1076 if (inno_read(inno, 0xa9) & 1) 1077 break; 1078 udelay(1000); 1079 } 1080 if (val == 5) { 1081 dev_err(inno->dev, "Pre-PLL unlock\n"); 1082 return -ETIMEDOUT; 1083 } 1084 1085 return 0; 1086 } 1087 1088 static unsigned long 1089 inno_hdmi_rk3528_phy_pll_recalc_rate(struct inno_hdmi_phy *inno, 1090 unsigned long parent_rate) 1091 { 1092 unsigned long frac; 1093 u8 nd, no_a, no_b, no_d; 1094 u16 nf; 1095 u64 vco = parent_rate; 1096 1097 nd = inno_read(inno, 0xa1) & 0x3f; 1098 nf = ((inno_read(inno, 0xa2) & 0x0f) << 8) | inno_read(inno, 0xa3); 1099 vco *= nf; 1100 if ((inno_read(inno, 0xa2) & 0x30) == 0) { 1101 frac = inno_read(inno, 0xd3) | 1102 (inno_read(inno, 0xd2) << 8) | 1103 (inno_read(inno, 0xd1) << 16); 1104 vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24)); 1105 } 1106 if (inno_read(inno, 0xa0) & 2) { 1107 do_div(vco, nd * 5); 1108 } else { 1109 no_a = inno_read(inno, 0xa5) & 0x1f; 1110 no_b = ((inno_read(inno, 0xa5) >> 5) & 7) + 2; 1111 no_d = inno_read(inno, 0xa6) & 0x1f; 1112 if (no_a == 1) 1113 do_div(vco, nd * no_b * no_d * 2); 1114 else 1115 do_div(vco, nd * no_a * no_d * 2); 1116 } 1117 1118 frac = vco; 1119 inno->pixclock = DIV_ROUND_CLOSEST(frac, 1000) * 1000; 1120 1121 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock); 1122 1123 return frac; 1124 } 1125 1126 #define PHY_TAB_LEN 60 1127 1128 static 1129 int inno_hdmi_update_phy_table(struct inno_hdmi_phy *inno, u32 *config, 1130 struct phy_config *phy_cfg, 1131 int phy_table_size) 1132 { 1133 int i, j; 1134 1135 for (i = 0; i < phy_table_size; i++) { 1136 phy_cfg[i].tmdsclock = 1137 (unsigned long)config[i * 15]; 1138 1139 debug("%ld ", phy_cfg[i].tmdsclock); 1140 for (j = 0; j < 14; j++) { 1141 phy_cfg[i].regs[j] = (u8)config[i * 15 + 1 + j]; 1142 debug("0x%02x ", phy_cfg[i].regs[j]); 1143 } 1144 debug("\n"); 1145 } 1146 1147 /* 1148 * The last set of phy cfg is used to indicate whether 1149 * there is no more phy cfg data. 1150 */ 1151 phy_cfg[i].tmdsclock = ~0UL; 1152 for (j = 0; j < 14; j++) 1153 phy_cfg[i].regs[j] = 0; 1154 1155 return 0; 1156 } 1157 1158 static const struct inno_hdmi_phy_ops rk3228_hdmi_phy_ops = { 1159 .init = inno_hdmi_phy_rk3228_init, 1160 .power_on = inno_hdmi_phy_rk3228_power_on, 1161 .power_off = inno_hdmi_phy_rk3228_power_off, 1162 .pre_pll_update = inno_hdmi_phy_rk3228_pre_pll_update, 1163 }; 1164 1165 static const struct inno_hdmi_phy_ops rk3328_hdmi_phy_ops = { 1166 .init = inno_hdmi_phy_rk3328_init, 1167 .power_on = inno_hdmi_phy_rk3328_power_on, 1168 .power_off = inno_hdmi_phy_rk3328_power_off, 1169 .pre_pll_update = inno_hdmi_phy_rk3328_pre_pll_update, 1170 .recalc_rate = inno_hdmi_3328_phy_pll_recalc_rate, 1171 }; 1172 1173 static const struct inno_hdmi_phy_ops rk3528_hdmi_phy_ops = { 1174 .init = inno_hdmi_phy_rk3528_init, 1175 .power_on = inno_hdmi_phy_rk3528_power_on, 1176 .power_off = inno_hdmi_phy_rk3528_power_off, 1177 .pre_pll_update = inno_hdmi_phy_rk3528_pre_pll_update, 1178 .recalc_rate = inno_hdmi_rk3528_phy_pll_recalc_rate, 1179 }; 1180 1181 static const struct inno_hdmi_phy_drv_data rk3228_hdmi_phy_drv_data = { 1182 .dev_type = INNO_HDMI_PHY_RK3228, 1183 .ops = &rk3228_hdmi_phy_ops, 1184 .phy_cfg_table = rk3228_phy_cfg, 1185 }; 1186 1187 static const struct inno_hdmi_phy_drv_data rk3328_hdmi_phy_drv_data = { 1188 .dev_type = INNO_HDMI_PHY_RK3328, 1189 .ops = &rk3328_hdmi_phy_ops, 1190 .phy_cfg_table = rk3328_phy_cfg, 1191 }; 1192 1193 static const struct inno_hdmi_phy_drv_data rk3528_hdmi_phy_drv_data = { 1194 .dev_type = INNO_HDMI_PHY_RK3528, 1195 .ops = &rk3528_hdmi_phy_ops, 1196 .phy_cfg_table = rk3528_phy_cfg, 1197 }; 1198 1199 static const struct rockchip_inno_data inno_hdmi_phy_of_match[] = { 1200 { .compatible = "rockchip,rk3228-hdmi-phy", 1201 .data = &rk3228_hdmi_phy_drv_data 1202 }, 1203 { .compatible = "rockchip,rk3328-hdmi-phy", 1204 .data = &rk3328_hdmi_phy_drv_data 1205 }, 1206 { .compatible = "rockchip,rk3528-hdmi-phy", 1207 .data = &rk3528_hdmi_phy_drv_data 1208 }, 1209 {} 1210 }; 1211 1212 static int inno_hdmi_phy_init(struct rockchip_phy *phy) 1213 { 1214 struct udevice *dev = phy->dev; 1215 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); 1216 int i, val, phy_table_size, ret; 1217 const char *name; 1218 u32 *phy_config; 1219 1220 inno->node = dev->node; 1221 1222 inno->regs = dev_read_addr_ptr(dev); 1223 if (!inno->regs) { 1224 printf("%s: failed to get phy address\n", __func__); 1225 return -ENOMEM; 1226 } 1227 1228 name = dev_read_string(dev, "compatible"); 1229 for (i = 0; i < ARRAY_SIZE(inno_hdmi_phy_of_match); i++) { 1230 if (!strcmp(name, inno_hdmi_phy_of_match[i].compatible)) { 1231 inno->plat_data = inno_hdmi_phy_of_match[i].data; 1232 break; 1233 } 1234 } 1235 1236 dev_read_prop(dev, "rockchip,phy-table", &val); 1237 1238 if (val >= 0) { 1239 if (val % PHY_TAB_LEN || !val) { 1240 printf("Invalid phy cfg table format!\n"); 1241 return -EINVAL; 1242 } 1243 1244 phy_config = malloc(val); 1245 if (!phy_config) { 1246 printf("kmalloc phy table failed\n"); 1247 return -ENOMEM; 1248 } 1249 1250 phy_table_size = val / PHY_TAB_LEN; 1251 /* Effective phy cfg data and the end of phy cfg table */ 1252 inno->phy_cfg = malloc(val + PHY_TAB_LEN); 1253 if (!inno->phy_cfg) { 1254 free(phy_config); 1255 return -ENOMEM; 1256 } 1257 1258 dev_read_u32_array(dev, "rockchip,phy-table", 1259 phy_config, val / sizeof(u32)); 1260 ret = inno_hdmi_update_phy_table(inno, phy_config, 1261 inno->phy_cfg, 1262 phy_table_size); 1263 if (ret) { 1264 free(phy_config); 1265 return ret; 1266 } 1267 free(phy_config); 1268 } else { 1269 printf("use default hdmi phy table\n"); 1270 } 1271 1272 if (i >= ARRAY_SIZE(inno_hdmi_phy_of_match)) 1273 return 0; 1274 1275 if (!inno->plat_data || !inno->plat_data->ops) 1276 return -EINVAL; 1277 1278 if (inno->plat_data->ops->init) 1279 inno->plat_data->ops->init(inno); 1280 1281 return 0; 1282 } 1283 1284 static unsigned long inno_hdmi_phy_set_pll(struct rockchip_phy *phy, 1285 unsigned long rate) 1286 { 1287 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); 1288 1289 inno_hdmi_phy_clk_prepare(inno); 1290 inno_hdmi_phy_clk_is_prepared(inno); 1291 inno_hdmi_phy_clk_set_rate(inno, rate); 1292 return 0; 1293 } 1294 1295 static int 1296 inno_hdmi_phy_set_bus_width(struct rockchip_phy *phy, u32 bus_width) 1297 { 1298 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); 1299 1300 inno->bus_width = bus_width; 1301 1302 return 0; 1303 } 1304 1305 static long 1306 inno_hdmi_phy_clk_round_rate(struct rockchip_phy *phy, unsigned long rate) 1307 { 1308 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev); 1309 int i; 1310 const struct pre_pll_config *cfg = pre_pll_cfg_table; 1311 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate); 1312 1313 for (; cfg->pixclock != ~0UL; cfg++) 1314 if (cfg->pixclock == rate) 1315 break; 1316 1317 /* 1318 * XXX: Limit pixel clock under 600MHz 1319 * rk3228 does not support non-zero fracdiv 1320 */ 1321 if ((inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228 && 1322 cfg->fracdiv) || cfg->pixclock > 600000000) 1323 return -EINVAL; 1324 1325 /* 1326 * If there is no dts phy cfg table, use default phy cfg table. 1327 * The tmds clock maximum is 594MHz. So there is no need to check 1328 * whether tmds clock is out of range. 1329 */ 1330 if (!inno->phy_cfg) 1331 return cfg->pixclock; 1332 1333 /* Check if tmds clock is out of dts phy config's range. */ 1334 for (i = 0; inno->phy_cfg[i].tmdsclock != ~0UL; i++) { 1335 if (inno->phy_cfg[i].tmdsclock >= tmdsclock) 1336 break; 1337 } 1338 1339 if (inno->phy_cfg[i].tmdsclock == ~0UL) 1340 return -EINVAL; 1341 1342 return cfg->pixclock; 1343 } 1344 1345 const struct rockchip_phy_funcs inno_hdmi_phy_funcs = { 1346 .init = inno_hdmi_phy_init, 1347 .power_on = inno_hdmi_phy_power_on, 1348 .power_off = inno_hdmi_phy_power_off, 1349 .set_pll = inno_hdmi_phy_set_pll, 1350 .set_bus_width = inno_hdmi_phy_set_bus_width, 1351 .round_rate = inno_hdmi_phy_clk_round_rate, 1352 }; 1353 1354 static struct rockchip_phy inno_hdmi_phy_driver_data = { 1355 .funcs = &inno_hdmi_phy_funcs, 1356 }; 1357 1358 static const struct udevice_id inno_hdmi_phy_ids[] = { 1359 { 1360 .compatible = "rockchip,rk3328-hdmi-phy", 1361 .data = (ulong)&inno_hdmi_phy_driver_data, 1362 }, 1363 { 1364 .compatible = "rockchip,rk3228-hdmi-phy", 1365 .data = (ulong)&inno_hdmi_phy_driver_data, 1366 }, 1367 { 1368 .compatible = "rockchip,rk3528-hdmi-phy", 1369 .data = (ulong)&inno_hdmi_phy_driver_data, 1370 }, 1371 {} 1372 }; 1373 1374 static int inno_hdmi_phy_probe(struct udevice *dev) 1375 { 1376 struct inno_hdmi_phy *inno = dev_get_priv(dev); 1377 struct rockchip_phy *phy = 1378 (struct rockchip_phy *)dev_get_driver_data(dev); 1379 1380 inno->dev = dev; 1381 phy->dev = dev; 1382 1383 g_inno = inno; 1384 dev->driver_data = (ulong)&inno_hdmi_phy_driver_data; 1385 phy = &inno_hdmi_phy_driver_data; 1386 1387 return 0; 1388 } 1389 1390 static int rockchip_inno_phy_hdmi_bind(struct udevice *parent) 1391 { 1392 struct udevice *child; 1393 ofnode subnode; 1394 int ret; 1395 1396 subnode = ofnode_find_subnode(parent->node, "clk-port"); 1397 if (!ofnode_valid(subnode)) { 1398 printf("%s: no subnode for %s", __func__, parent->name); 1399 return -ENXIO; 1400 } 1401 1402 ret = device_bind_driver_to_node(parent, "clk_inno_hdmi", "inno_hdmi_pll_clk", subnode, &child); 1403 if (ret) { 1404 printf("%s: clk-port cannot bind its driver\n", __func__); 1405 return ret; 1406 } 1407 1408 return 0; 1409 } 1410 1411 U_BOOT_DRIVER(inno_hdmi_phy) = { 1412 .name = "inno_hdmi_phy", 1413 .id = UCLASS_PHY, 1414 .of_match = inno_hdmi_phy_ids, 1415 .probe = inno_hdmi_phy_probe, 1416 .bind = rockchip_inno_phy_hdmi_bind, 1417 .priv_auto_alloc_size = sizeof(struct inno_hdmi_phy), 1418 }; 1419 1420 1421 static ulong inno_hdmi_clk_get_rate(struct clk *clk) 1422 { 1423 struct clk_inno_hdmi *priv = dev_get_priv(clk->dev); 1424 1425 return priv->rate; 1426 } 1427 1428 static ulong inno_hdmi_clk_set_rate(struct clk *clk, ulong rate) 1429 { 1430 struct clk_inno_hdmi *priv = dev_get_priv(clk->dev); 1431 int ret; 1432 1433 inno_hdmi_phy_clk_prepare(g_inno); 1434 inno_hdmi_phy_clk_is_prepared(g_inno); 1435 ret = inno_hdmi_phy_clk_set_rate(g_inno, rate); 1436 if (ret < 0) { 1437 printf("inno hdmi set rate failed ret:%d\n", ret); 1438 return ret; 1439 } 1440 1441 priv->rate = g_inno->pixclock; 1442 1443 return priv->rate; 1444 } 1445 1446 static const struct clk_ops inno_hdmi_clk_ops = { 1447 .get_rate = inno_hdmi_clk_get_rate, 1448 .set_rate = inno_hdmi_clk_set_rate, 1449 }; 1450 1451 static int inno_hdmi_clk_probe(struct udevice *dev) 1452 { 1453 return 0; 1454 } 1455 1456 /* 1457 * In order for other display interfaces to use hdmiphy as source 1458 * for dclk, hdmiphy must register a virtual clock driver 1459 */ 1460 U_BOOT_DRIVER(clk_inno_hdmi) = { 1461 .name = "clk_inno_hdmi", 1462 .id = UCLASS_CLK, 1463 .priv_auto_alloc_size = sizeof(struct clk_inno_hdmi), 1464 .ops = &inno_hdmi_clk_ops, 1465 .probe = inno_hdmi_clk_probe, 1466 }; 1467