1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2008-2018 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 * Author: Wyon Bi <bivvy.bi@rock-chips.com> 6 */ 7 8 #include <config.h> 9 #include <common.h> 10 #include <errno.h> 11 #include <dm.h> 12 #include <div64.h> 13 #include <asm/io.h> 14 #include <linux/ioport.h> 15 #include <linux/iopoll.h> 16 #include <linux/math64.h> 17 18 #include "rockchip_phy.h" 19 20 #define USEC_PER_SEC 1000000LL 21 #define PSEC_PER_SEC 1000000000000LL 22 23 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) 24 25 /* 26 * The offset address[7:0] is distributed two parts, one from the bit7 to bit5 27 * is the first address, the other from the bit4 to bit0 is the second address. 28 * when you configure the registers, you must set both of them. The Clock Lane 29 * and Data Lane use the same registers with the same second address, but the 30 * first address is different. 31 */ 32 #define FIRST_ADDRESS(x) (((x) & 0x7) << 5) 33 #define SECOND_ADDRESS(x) (((x) & 0x1f) << 0) 34 #define PHY_REG(first, second) (FIRST_ADDRESS(first) | \ 35 SECOND_ADDRESS(second)) 36 37 /* Analog Register Part: reg00 */ 38 #define BANDGAP_POWER_MASK BIT(7) 39 #define BANDGAP_POWER_DOWN BIT(7) 40 #define BANDGAP_POWER_ON 0 41 #define LANE_EN_MASK GENMASK(6, 2) 42 #define LANE_EN_CK BIT(6) 43 #define LANE_EN_3 BIT(5) 44 #define LANE_EN_2 BIT(4) 45 #define LANE_EN_1 BIT(3) 46 #define LANE_EN_0 BIT(2) 47 #define POWER_WORK_MASK GENMASK(1, 0) 48 #define POWER_WORK_ENABLE UPDATE(1, 1, 0) 49 #define POWER_WORK_DISABLE UPDATE(2, 1, 0) 50 /* Analog Register Part: reg01 */ 51 #define REG_SYNCRST_MASK BIT(2) 52 #define REG_SYNCRST_RESET BIT(2) 53 #define REG_SYNCRST_NORMAL 0 54 #define REG_LDOPD_MASK BIT(1) 55 #define REG_LDOPD_POWER_DOWN BIT(1) 56 #define REG_LDOPD_POWER_ON 0 57 #define REG_PLLPD_MASK BIT(0) 58 #define REG_PLLPD_POWER_DOWN BIT(0) 59 #define REG_PLLPD_POWER_ON 0 60 /* Analog Register Part: reg03 */ 61 #define REG_FBDIV_HI_MASK BIT(5) 62 #define REG_FBDIV_HI(x) UPDATE(x, 5, 5) 63 #define REG_PREDIV_MASK GENMASK(4, 0) 64 #define REG_PREDIV(x) UPDATE(x, 4, 0) 65 /* Analog Register Part: reg04 */ 66 #define REG_FBDIV_LO_MASK GENMASK(7, 0) 67 #define REG_FBDIV_LO(x) UPDATE(x, 7, 0) 68 /* Analog Register Part: reg05 */ 69 #define SAMPLE_CLOCK_PHASE_MASK GENMASK(6, 4) 70 #define SAMPLE_CLOCK_PHASE(x) UPDATE(x, 6, 4) 71 #define CLOCK_LANE_SKEW_PHASE_MASK GENMASK(2, 0) 72 #define CLOCK_LANE_SKEW_PHASE(x) UPDATE(x, 2, 0) 73 /* Analog Register Part: reg06 */ 74 #define DATA_LANE_3_SKEW_PHASE_MASK GENMASK(6, 4) 75 #define DATA_LANE_3_SKEW_PHASE(x) UPDATE(x, 6, 4) 76 #define DATA_LANE_2_SKEW_PHASE_MASK GENMASK(2, 0) 77 #define DATA_LANE_2_SKEW_PHASE(x) UPDATE(x, 2, 0) 78 /* Analog Register Part: reg07 */ 79 #define DATA_LANE_1_SKEW_PHASE_MASK GENMASK(6, 4) 80 #define DATA_LANE_1_SKEW_PHASE(x) UPDATE(x, 6, 4) 81 #define DATA_LANE_0_SKEW_PHASE_MASK GENMASK(2, 0) 82 #define DATA_LANE_0_SKEW_PHASE(x) UPDATE(x, 2, 0) 83 /* Analog Register Part: reg08 */ 84 #define PRE_EMPHASIS_ENABLE_MASK BIT(7) 85 #define PRE_EMPHASIS_ENABLE BIT(7) 86 #define PRE_EMPHASIS_DISABLE 0 87 #define PLL_POST_DIV_ENABLE_MASK BIT(5) 88 #define PLL_POST_DIV_ENABLE BIT(5) 89 #define PLL_POST_DIV_DISABLE 0 90 #define DATA_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0) 91 #define DATA_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0) 92 #define SAMPLE_CLOCK_DIRECTION_MASK BIT(4) 93 #define SAMPLE_CLOCK_DIRECTION_REVERSE BIT(4) 94 #define SAMPLE_CLOCK_DIRECTION_FORWARD 0 95 #define LOWFRE_EN_MASK BIT(5) 96 #define PLL_OUTPUT_FREQUENCY_DIV_BY_1 0 97 #define PLL_OUTPUT_FREQUENCY_DIV_BY_2 1 98 /* Analog Register Part: reg0b */ 99 #define CLOCK_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0) 100 #define CLOCK_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0) 101 #define VOD_MIN_RANGE 0x1 102 #define VOD_MID_RANGE 0x3 103 #define VOD_BIG_RANGE 0x7 104 #define VOD_MAX_RANGE 0xf 105 /* Analog Register Part: reg1e */ 106 #define PLL_MODE_SEL_MASK GENMASK(6, 5) 107 #define PLL_MODE_SEL_LVDS_MODE 0 108 #define PLL_MODE_SEL_MIPI_MODE BIT(5) 109 110 /* Digital Register Part: reg00 */ 111 #define REG_DIG_RSTN_MASK BIT(0) 112 #define REG_DIG_RSTN_NORMAL BIT(0) 113 #define REG_DIG_RSTN_RESET 0 114 /* Digital Register Part: reg01 */ 115 #define INVERT_TXCLKESC_MASK BIT(1) 116 #define INVERT_TXCLKESC_ENABLE BIT(1) 117 #define INVERT_TXCLKESC_DISABLE 0 118 #define INVERT_TXBYTECLKHS_MASK BIT(0) 119 #define INVERT_TXBYTECLKHS_ENABLE BIT(0) 120 #define INVERT_TXBYTECLKHS_DISABLE 0 121 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg05 */ 122 #define T_LPX_CNT_MASK GENMASK(5, 0) 123 #define T_LPX_CNT(x) UPDATE(x, 5, 0) 124 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */ 125 #define T_HS_ZERO_CNT_HI_MASK BIT(7) 126 #define T_HS_ZERO_CNT_HI(x) UPDATE(x, 7, 7) 127 #define T_HS_PREPARE_CNT_MASK GENMASK(6, 0) 128 #define T_HS_PREPARE_CNT(x) UPDATE(x, 6, 0) 129 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */ 130 #define T_HS_ZERO_CNT_LO_MASK GENMASK(5, 0) 131 #define T_HS_ZERO_CNT_LO(x) UPDATE(x, 5, 0) 132 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */ 133 #define T_HS_TRAIL_CNT_MASK GENMASK(6, 0) 134 #define T_HS_TRAIL_CNT(x) UPDATE(x, 6, 0) 135 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */ 136 #define T_HS_EXIT_CNT_LO_MASK GENMASK(4, 0) 137 #define T_HS_EXIT_CNT_LO(x) UPDATE(x, 4, 0) 138 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */ 139 #define T_CLK_POST_CNT_LO_MASK GENMASK(3, 0) 140 #define T_CLK_POST_CNT_LO(x) UPDATE(x, 3, 0) 141 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */ 142 #define LPDT_TX_PPI_SYNC_MASK BIT(2) 143 #define LPDT_TX_PPI_SYNC_ENABLE BIT(2) 144 #define LPDT_TX_PPI_SYNC_DISABLE 0 145 #define T_WAKEUP_CNT_HI_MASK GENMASK(1, 0) 146 #define T_WAKEUP_CNT_HI(x) UPDATE(x, 1, 0) 147 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0d */ 148 #define T_WAKEUP_CNT_LO_MASK GENMASK(7, 0) 149 #define T_WAKEUP_CNT_LO(x) UPDATE(x, 7, 0) 150 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0e */ 151 #define T_CLK_PRE_CNT_MASK GENMASK(3, 0) 152 #define T_CLK_PRE_CNT(x) UPDATE(x, 3, 0) 153 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */ 154 #define T_CLK_POST_HI_MASK GENMASK(7, 6) 155 #define T_CLK_POST_HI(x) UPDATE(x, 7, 6) 156 #define T_TA_GO_CNT_MASK GENMASK(5, 0) 157 #define T_TA_GO_CNT(x) UPDATE(x, 5, 0) 158 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */ 159 #define T_HS_EXIT_CNT_HI_MASK BIT(6) 160 #define T_HS_EXIT_CNT_HI(x) UPDATE(x, 6, 6) 161 #define T_TA_SURE_CNT_MASK GENMASK(5, 0) 162 #define T_TA_SURE_CNT(x) UPDATE(x, 5, 0) 163 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */ 164 #define T_TA_WAIT_CNT_MASK GENMASK(5, 0) 165 #define T_TA_WAIT_CNT(x) UPDATE(x, 5, 0) 166 /* LVDS Register Part: reg00 */ 167 #define LVDS_DIGITAL_INTERNAL_RESET_MASK BIT(2) 168 #define LVDS_DIGITAL_INTERNAL_RESET_DISABLE BIT(2) 169 #define LVDS_DIGITAL_INTERNAL_RESET_ENABLE 0 170 /* LVDS Register Part: reg01 */ 171 #define LVDS_DIGITAL_INTERNAL_ENABLE_MASK BIT(7) 172 #define LVDS_DIGITAL_INTERNAL_ENABLE BIT(7) 173 #define LVDS_DIGITAL_INTERNAL_DISABLE 0 174 /* LVDS Register Part: reg03 */ 175 #define MODE_ENABLE_MASK GENMASK(2, 0) 176 #define TTL_MODE_ENABLE BIT(2) 177 #define LVDS_MODE_ENABLE BIT(1) 178 #define MIPI_MODE_ENABLE BIT(0) 179 /* LVDS Register Part: reg0b */ 180 #define LVDS_LANE_EN_MASK GENMASK(7, 3) 181 #define LVDS_DATA_LANE0_EN BIT(7) 182 #define LVDS_DATA_LANE1_EN BIT(6) 183 #define LVDS_DATA_LANE2_EN BIT(5) 184 #define LVDS_DATA_LANE3_EN BIT(4) 185 #define LVDS_CLK_LANE_EN BIT(3) 186 #define LVDS_PLL_POWER_MASK BIT(2) 187 #define LVDS_PLL_POWER_OFF BIT(2) 188 #define LVDS_PLL_POWER_ON 0 189 #define LVDS_BANDGAP_POWER_MASK BIT(0) 190 #define LVDS_BANDGAP_POWER_DOWN BIT(0) 191 #define LVDS_BANDGAP_POWER_ON 0 192 193 #define DSI_PHY_RSTZ 0xa0 194 #define PHY_ENABLECLK BIT(2) 195 #define DSI_PHY_STATUS 0xb0 196 #define PHY_LOCK BIT(0) 197 198 enum phy_max_rate { 199 MAX_1GHZ, 200 MAX_2_5GHZ, 201 }; 202 203 struct inno_video_mipi_dphy_timing { 204 unsigned int max_lane_mbps; 205 u8 lpx; 206 u8 hs_prepare; 207 u8 clk_lane_hs_zero; 208 u8 data_lane_hs_zero; 209 u8 hs_trail; 210 }; 211 212 struct inno_video_mipi_dphy_info { 213 const struct inno_video_mipi_dphy_timing *inno_mipi_dphy_timing_table; 214 const unsigned int num_timings; 215 enum phy_max_rate phy_max_rate; 216 }; 217 218 static const 219 struct inno_video_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1GHz[] = { 220 { 110, 0x0, 0x20, 0x16, 0x02, 0x22}, 221 { 150, 0x0, 0x06, 0x16, 0x03, 0x45}, 222 { 200, 0x0, 0x18, 0x17, 0x04, 0x0b}, 223 { 250, 0x0, 0x05, 0x17, 0x05, 0x16}, 224 { 300, 0x0, 0x51, 0x18, 0x06, 0x2c}, 225 { 400, 0x0, 0x64, 0x19, 0x07, 0x33}, 226 { 500, 0x0, 0x20, 0x1b, 0x07, 0x4e}, 227 { 600, 0x0, 0x6a, 0x1d, 0x08, 0x3a}, 228 { 700, 0x0, 0x3e, 0x1e, 0x08, 0x6a}, 229 { 800, 0x0, 0x21, 0x1f, 0x09, 0x29}, 230 {1000, 0x0, 0x09, 0x20, 0x09, 0x27}, 231 }; 232 233 static const 234 struct inno_video_mipi_dphy_timing inno_mipi_dphy_timing_table_max_2_5GHz[] = { 235 { 110, 0x02, 0x7f, 0x16, 0x02, 0x02}, 236 { 150, 0x02, 0x7f, 0x16, 0x03, 0x02}, 237 { 200, 0x02, 0x7f, 0x17, 0x04, 0x02}, 238 { 250, 0x02, 0x7f, 0x17, 0x05, 0x04}, 239 { 300, 0x02, 0x7f, 0x18, 0x06, 0x04}, 240 { 400, 0x03, 0x7e, 0x19, 0x07, 0x04}, 241 { 500, 0x03, 0x7c, 0x1b, 0x07, 0x08}, 242 { 600, 0x03, 0x70, 0x1d, 0x08, 0x10}, 243 { 700, 0x05, 0x40, 0x1e, 0x08, 0x30}, 244 { 800, 0x05, 0x02, 0x1f, 0x09, 0x30}, 245 {1000, 0x05, 0x08, 0x20, 0x09, 0x30}, 246 {1200, 0x06, 0x03, 0x32, 0x14, 0x0f}, 247 {1400, 0x09, 0x03, 0x32, 0x14, 0x0f}, 248 {1600, 0x0d, 0x42, 0x36, 0x0e, 0x0f}, 249 {1800, 0x0e, 0x47, 0x7a, 0x0e, 0x0f}, 250 {2000, 0x11, 0x64, 0x7a, 0x0e, 0x0b}, 251 {2200, 0x13, 0x64, 0x7e, 0x15, 0x0b}, 252 {2400, 0x13, 0x33, 0x7f, 0x15, 0x6a}, 253 {2500, 0x15, 0x54, 0x7f, 0x15, 0x6a}, 254 }; 255 256 const struct inno_video_mipi_dphy_info inno_video_mipi_dphy_max_1GHz = { 257 .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1GHz, 258 .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1GHz), 259 .phy_max_rate = MAX_1GHZ, 260 }; 261 262 const struct inno_video_mipi_dphy_info inno_video_mipi_dphy_max_2_5GHz = { 263 .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5GHz, 264 .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5GHz), 265 .phy_max_rate = MAX_2_5GHZ, 266 }; 267 268 struct mipi_dphy_timing { 269 unsigned int clkmiss; 270 unsigned int clkpost; 271 unsigned int clkpre; 272 unsigned int clkprepare; 273 unsigned int clksettle; 274 unsigned int clktermen; 275 unsigned int clktrail; 276 unsigned int clkzero; 277 unsigned int dtermen; 278 unsigned int eot; 279 unsigned int hsexit; 280 unsigned int hsprepare; 281 unsigned int hszero; 282 unsigned int hssettle; 283 unsigned int hsskip; 284 unsigned int hstrail; 285 unsigned int init; 286 unsigned int lpx; 287 unsigned int taget; 288 unsigned int tago; 289 unsigned int tasure; 290 unsigned int wakeup; 291 }; 292 293 struct inno_video_phy { 294 enum phy_mode mode; 295 const struct inno_video_mipi_dphy_info *mipi_dphy_info; 296 struct resource phy; 297 struct resource host; 298 int lanes; 299 struct { 300 u8 prediv; 301 u16 fbdiv; 302 unsigned long rate; 303 } pll; 304 }; 305 306 enum { 307 REGISTER_PART_ANALOG, 308 REGISTER_PART_DIGITAL, 309 REGISTER_PART_CLOCK_LANE, 310 REGISTER_PART_DATA0_LANE, 311 REGISTER_PART_DATA1_LANE, 312 REGISTER_PART_DATA2_LANE, 313 REGISTER_PART_DATA3_LANE, 314 REGISTER_PART_LVDS, 315 }; 316 317 static inline void phy_update_bits(struct inno_video_phy *inno, 318 u8 first, u8 second, u8 mask, u8 val) 319 { 320 u32 reg = PHY_REG(first, second) << 2; 321 u32 tmp, orig; 322 323 orig = readl(inno->phy.start + reg); 324 tmp = orig & ~mask; 325 tmp |= val & mask; 326 writel(tmp, inno->phy.start + reg); 327 } 328 329 static inline void host_update_bits(struct inno_video_phy *inno, 330 u32 reg, u32 mask, u32 val) 331 { 332 u32 tmp, orig; 333 334 orig = readl(inno->host.start + reg); 335 tmp = orig & ~mask; 336 tmp |= val & mask; 337 writel(tmp, inno->host.start + reg); 338 } 339 340 static void mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, 341 unsigned long period) 342 { 343 /* Global Operation Timing Parameters */ 344 timing->clkmiss = 0; 345 timing->clkpost = 70000 + 52 * period; 346 timing->clkpre = 8 * period; 347 timing->clkprepare = 65000; 348 timing->clksettle = 95000; 349 timing->clktermen = 0; 350 timing->clktrail = 80000; 351 timing->clkzero = 260000; 352 timing->dtermen = 0; 353 timing->eot = 0; 354 timing->hsexit = 120000; 355 timing->hsprepare = 65000 + 4 * period; 356 timing->hszero = 145000 + 6 * period; 357 timing->hssettle = 85000 + 6 * period; 358 timing->hsskip = 40000; 359 timing->hstrail = max(8 * period, 60000 + 4 * period); 360 timing->init = 100000000; 361 timing->lpx = 60000; 362 timing->taget = 5 * timing->lpx; 363 timing->tago = 4 * timing->lpx; 364 timing->tasure = 2 * timing->lpx; 365 timing->wakeup = 1000000000; 366 } 367 368 static const struct inno_video_mipi_dphy_timing * 369 inno_mipi_dphy_get_timing(struct inno_video_phy *inno) 370 { 371 const struct inno_video_mipi_dphy_timing *timings; 372 unsigned int num_timings; 373 unsigned int lane_mbps = inno->pll.rate / USEC_PER_SEC; 374 unsigned int i; 375 376 timings = inno->mipi_dphy_info->inno_mipi_dphy_timing_table; 377 num_timings = inno->mipi_dphy_info->num_timings; 378 379 for (i = 0; i < num_timings; i++) 380 if (lane_mbps <= timings[i].max_lane_mbps) 381 break; 382 383 if (i == num_timings) 384 --i; 385 386 return &timings[i]; 387 } 388 389 static void inno_mipi_dphy_max_2_5GHz_pll_enable(struct inno_video_phy *inno) 390 { 391 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 392 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); 393 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 394 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8)); 395 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, 396 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); 397 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08, 398 PLL_POST_DIV_ENABLE_MASK, PLL_POST_DIV_ENABLE); 399 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b, 400 CLOCK_LANE_VOD_RANGE_SET_MASK, 401 CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE)); 402 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 403 REG_LDOPD_MASK | REG_PLLPD_MASK, 404 REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON); 405 } 406 407 static void inno_mipi_dphy_max_1GHz_pll_enable(struct inno_video_phy *inno) 408 { 409 /* Configure PLL */ 410 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 411 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); 412 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 413 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8)); 414 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, 415 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); 416 /* Enable PLL and LDO */ 417 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 418 REG_LDOPD_MASK | REG_PLLPD_MASK, 419 REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON); 420 } 421 422 static void inno_mipi_dphy_reset(struct inno_video_phy *inno) 423 { 424 /* Reset analog */ 425 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 426 REG_SYNCRST_MASK, REG_SYNCRST_RESET); 427 udelay(1); 428 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 429 REG_SYNCRST_MASK, REG_SYNCRST_NORMAL); 430 /* Reset digital */ 431 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00, 432 REG_DIG_RSTN_MASK, REG_DIG_RSTN_RESET); 433 udelay(1); 434 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00, 435 REG_DIG_RSTN_MASK, REG_DIG_RSTN_NORMAL); 436 } 437 438 static void inno_mipi_dphy_timing_init(struct inno_video_phy *inno) 439 { 440 struct mipi_dphy_timing gotp; 441 u32 t_txbyteclkhs, t_txclkesc, ui; 442 u32 txbyteclkhs, txclkesc, esc_clk_div; 443 u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait; 444 u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero; 445 const struct inno_video_mipi_dphy_timing *timing; 446 unsigned int i; 447 448 txbyteclkhs = inno->pll.rate / 8; 449 t_txbyteclkhs = div_u64(PSEC_PER_SEC, txbyteclkhs); 450 esc_clk_div = DIV_ROUND_UP(txbyteclkhs, 20000000); 451 txclkesc = txbyteclkhs / esc_clk_div; 452 t_txclkesc = div_u64(PSEC_PER_SEC, txclkesc); 453 454 ui = div_u64(PSEC_PER_SEC, inno->pll.rate); 455 456 memset(&gotp, 0, sizeof(gotp)); 457 mipi_dphy_timing_get_default(&gotp, ui); 458 459 /* 460 * The value of counter for HS Ths-exit 461 * Ths-exit = Tpin_txbyteclkhs * value 462 */ 463 hs_exit = DIV_ROUND_UP(gotp.hsexit, t_txbyteclkhs); 464 /* 465 * The value of counter for HS Tclk-post 466 * Tclk-post = Tpin_txbyteclkhs * value 467 */ 468 clk_post = DIV_ROUND_UP(gotp.clkpost, t_txbyteclkhs); 469 /* 470 * The value of counter for HS Tclk-pre 471 * Tclk-pre = Tpin_txbyteclkhs * value 472 */ 473 clk_pre = DIV_ROUND_UP(gotp.clkpre, t_txbyteclkhs); 474 475 /* 476 * The value of counter for HS Tlpx Time 477 * Tlpx = Tpin_txbyteclkhs * (2 + value) 478 */ 479 lpx = DIV_ROUND_UP(gotp.lpx, t_txbyteclkhs); 480 if (lpx >= 2) 481 lpx -= 2; 482 483 /* 484 * The value of counter for HS Tta-go 485 * Tta-go for turnaround 486 * Tta-go = Ttxclkesc * value 487 */ 488 ta_go = DIV_ROUND_UP(gotp.tago, t_txclkesc); 489 /* 490 * The value of counter for HS Tta-sure 491 * Tta-sure for turnaround 492 * Tta-sure = Ttxclkesc * value 493 */ 494 ta_sure = DIV_ROUND_UP(gotp.tasure, t_txclkesc); 495 /* 496 * The value of counter for HS Tta-wait 497 * Tta-wait for turnaround 498 * Tta-wait = Ttxclkesc * value 499 */ 500 ta_wait = DIV_ROUND_UP(gotp.taget, t_txclkesc); 501 502 timing = inno_mipi_dphy_get_timing(inno); 503 504 /* 505 * The value of counter for HS Tlpx Time 506 * Tlpx = Tpin_txbyteclkhs * (2 + value) 507 */ 508 if (inno->mipi_dphy_info->phy_max_rate == MAX_1GHZ) { 509 lpx = DIV_ROUND_UP(gotp.lpx, t_txbyteclkhs); 510 if (lpx >= 2) 511 lpx -= 2; 512 } else { 513 lpx = timing->lpx; 514 } 515 516 hs_prepare = timing->hs_prepare; 517 hs_trail = timing->hs_trail; 518 clk_lane_hs_zero = timing->clk_lane_hs_zero; 519 data_lane_hs_zero = timing->data_lane_hs_zero; 520 wakeup = 0x3ff; 521 522 for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) { 523 if (i == REGISTER_PART_CLOCK_LANE) 524 hs_zero = clk_lane_hs_zero; 525 else 526 hs_zero = data_lane_hs_zero; 527 528 phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK, 529 T_LPX_CNT(lpx)); 530 phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK, 531 T_HS_PREPARE_CNT(hs_prepare)); 532 533 if (inno->mipi_dphy_info->phy_max_rate == MAX_2_5GHZ) 534 phy_update_bits(inno, i, 0x06, T_HS_ZERO_CNT_HI_MASK, 535 T_HS_ZERO_CNT_HI(hs_zero >> 6)); 536 537 phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_LO_MASK, 538 T_HS_ZERO_CNT_LO(hs_zero)); 539 phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK, 540 T_HS_TRAIL_CNT(hs_trail)); 541 542 if (inno->mipi_dphy_info->phy_max_rate == MAX_2_5GHZ) 543 phy_update_bits(inno, i, 0x11, T_HS_EXIT_CNT_HI_MASK, 544 T_HS_EXIT_CNT_HI(hs_exit >> 5)); 545 546 phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_LO_MASK, 547 T_HS_EXIT_CNT_LO(hs_exit)); 548 549 if (inno->mipi_dphy_info->phy_max_rate == MAX_2_5GHZ) 550 phy_update_bits(inno, i, 0x10, T_CLK_POST_HI_MASK, 551 T_CLK_POST_HI(clk_post >> 4)); 552 553 phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_LO_MASK, 554 T_CLK_POST_CNT_LO(clk_post)); 555 phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK, 556 T_CLK_PRE_CNT(clk_pre)); 557 phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK, 558 T_WAKEUP_CNT_HI(wakeup >> 8)); 559 phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK, 560 T_WAKEUP_CNT_LO(wakeup)); 561 phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK, 562 T_TA_GO_CNT(ta_go)); 563 phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK, 564 T_TA_SURE_CNT(ta_sure)); 565 phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK, 566 T_TA_WAIT_CNT(ta_wait)); 567 } 568 } 569 570 static void inno_mipi_dphy_lane_enable(struct inno_video_phy *inno) 571 { 572 u8 val = LANE_EN_CK; 573 574 switch (inno->lanes) { 575 case 1: 576 val |= LANE_EN_0; 577 break; 578 case 2: 579 val |= LANE_EN_1 | LANE_EN_0; 580 break; 581 case 3: 582 val |= LANE_EN_2 | LANE_EN_1 | LANE_EN_0; 583 break; 584 case 4: 585 default: 586 val |= LANE_EN_3 | LANE_EN_2 | LANE_EN_1 | LANE_EN_0; 587 break; 588 } 589 590 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, val); 591 } 592 593 static void inno_video_phy_mipi_mode_enable(struct inno_video_phy *inno) 594 { 595 /* Select MIPI mode */ 596 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, 597 MODE_ENABLE_MASK, MIPI_MODE_ENABLE); 598 599 if (inno->mipi_dphy_info->phy_max_rate == MAX_2_5GHZ) 600 inno_mipi_dphy_max_2_5GHz_pll_enable(inno); 601 else 602 inno_mipi_dphy_max_1GHz_pll_enable(inno); 603 604 inno_mipi_dphy_reset(inno); 605 inno_mipi_dphy_timing_init(inno); 606 inno_mipi_dphy_lane_enable(inno); 607 } 608 609 static void inno_video_phy_lvds_mode_enable(struct inno_video_phy *inno) 610 { 611 u8 prediv = 2; 612 u16 fbdiv = 28; 613 u32 val; 614 int ret; 615 616 /* Sample clock reverse direction */ 617 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08, 618 SAMPLE_CLOCK_DIRECTION_MASK | LOWFRE_EN_MASK, 619 SAMPLE_CLOCK_DIRECTION_REVERSE | 620 PLL_OUTPUT_FREQUENCY_DIV_BY_1); 621 /* Select LVDS mode */ 622 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, 623 MODE_ENABLE_MASK, LVDS_MODE_ENABLE); 624 /* Configure PLL */ 625 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 626 REG_PREDIV_MASK, REG_PREDIV(prediv)); 627 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 628 REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv >> 8)); 629 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, 630 REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv)); 631 phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc); 632 /* Enable PLL and Bandgap */ 633 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, 634 LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK, 635 LVDS_PLL_POWER_ON | LVDS_BANDGAP_POWER_ON); 636 637 ret = readl_poll_timeout(inno->host.start + DSI_PHY_STATUS, 638 val, val & PHY_LOCK, 10000); 639 if (ret) 640 dev_err(phy->dev, "PLL is not lock\n"); 641 642 /* Select PLL mode */ 643 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1e, 644 PLL_MODE_SEL_MASK, PLL_MODE_SEL_LVDS_MODE); 645 646 /* Reset LVDS digital logic */ 647 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, 648 LVDS_DIGITAL_INTERNAL_RESET_MASK, 649 LVDS_DIGITAL_INTERNAL_RESET_ENABLE); 650 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, 651 LVDS_DIGITAL_INTERNAL_RESET_MASK, 652 LVDS_DIGITAL_INTERNAL_RESET_DISABLE); 653 /* Enable LVDS digital logic */ 654 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, 655 LVDS_DIGITAL_INTERNAL_ENABLE_MASK, 656 LVDS_DIGITAL_INTERNAL_ENABLE); 657 /* Enable LVDS analog driver */ 658 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, 659 LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN | 660 LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN | 661 LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN); 662 } 663 664 static void inno_video_phy_ttl_mode_enable(struct inno_video_phy *inno) 665 { 666 /* Select TTL mode */ 667 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, 668 MODE_ENABLE_MASK, TTL_MODE_ENABLE); 669 /* Reset digital logic */ 670 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, 671 LVDS_DIGITAL_INTERNAL_RESET_MASK, 672 LVDS_DIGITAL_INTERNAL_RESET_ENABLE); 673 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, 674 LVDS_DIGITAL_INTERNAL_RESET_MASK, 675 LVDS_DIGITAL_INTERNAL_RESET_DISABLE); 676 /* Enable digital logic */ 677 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, 678 LVDS_DIGITAL_INTERNAL_ENABLE_MASK, 679 LVDS_DIGITAL_INTERNAL_ENABLE); 680 /* Enable analog driver */ 681 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, 682 LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN | 683 LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN | 684 LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN); 685 /* Enable for clk lane in TTL mode */ 686 host_update_bits(inno, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK); 687 } 688 689 static int inno_video_phy_power_on(struct rockchip_phy *phy) 690 { 691 struct inno_video_phy *inno = dev_get_priv(phy->dev); 692 693 /* Bandgap power on */ 694 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 695 BANDGAP_POWER_MASK, BANDGAP_POWER_ON); 696 /* Enable power work */ 697 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 698 POWER_WORK_MASK, POWER_WORK_ENABLE); 699 700 switch (inno->mode) { 701 case PHY_MODE_VIDEO_MIPI: 702 inno_video_phy_mipi_mode_enable(inno); 703 break; 704 case PHY_MODE_VIDEO_LVDS: 705 inno_video_phy_lvds_mode_enable(inno); 706 break; 707 case PHY_MODE_VIDEO_TTL: 708 inno_video_phy_ttl_mode_enable(inno); 709 break; 710 default: 711 return -EINVAL; 712 } 713 714 return 0; 715 } 716 717 static int inno_video_phy_power_off(struct rockchip_phy *phy) 718 { 719 struct inno_video_phy *inno = dev_get_priv(phy->dev); 720 721 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0); 722 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 723 REG_LDOPD_MASK | REG_PLLPD_MASK, 724 REG_LDOPD_POWER_DOWN | REG_PLLPD_POWER_DOWN); 725 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 726 POWER_WORK_MASK, POWER_WORK_DISABLE); 727 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 728 BANDGAP_POWER_MASK, BANDGAP_POWER_DOWN); 729 730 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0); 731 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, 732 LVDS_DIGITAL_INTERNAL_ENABLE_MASK, 733 LVDS_DIGITAL_INTERNAL_DISABLE); 734 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, 735 LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK, 736 LVDS_PLL_POWER_OFF | LVDS_BANDGAP_POWER_DOWN); 737 738 return 0; 739 } 740 741 static unsigned long inno_video_phy_pll_round_rate(unsigned long prate, 742 unsigned long rate, 743 u8 *prediv, u16 *fbdiv) 744 { 745 unsigned long best_freq = 0; 746 unsigned long fref, fout; 747 u8 min_prediv, max_prediv; 748 u8 _prediv, best_prediv = 1; 749 u16 _fbdiv, best_fbdiv = 1; 750 u32 min_delta = 0xffffffff; 751 752 /* 753 * The PLL output frequency can be calculated using a simple formula: 754 * PLL_Output_Frequency = (FREF / PREDIV * FBDIV) / 2 755 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2 756 */ 757 fref = prate / 2; 758 if (rate > 1000000000UL) 759 fout = 1000000000UL; 760 else 761 fout = rate; 762 763 /* 5Mhz < Fref / prediv < 40MHz */ 764 min_prediv = DIV_ROUND_UP(fref, 40000000); 765 max_prediv = fref / 5000000; 766 767 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 768 u64 tmp; 769 u32 delta; 770 771 tmp = (u64)fout * _prediv; 772 do_div(tmp, fref); 773 _fbdiv = tmp; 774 775 /* 776 * The all possible settings of feedback divider are 777 * 12, 13, 14, 16, ~ 511 778 */ 779 if (_fbdiv == 15) 780 continue; 781 782 if (_fbdiv < 12 || _fbdiv > 511) 783 continue; 784 785 tmp = (u64)_fbdiv * fref; 786 do_div(tmp, _prediv); 787 788 delta = abs(fout - tmp); 789 if (!delta) { 790 best_prediv = _prediv; 791 best_fbdiv = _fbdiv; 792 best_freq = tmp; 793 break; 794 } else if (delta < min_delta) { 795 best_prediv = _prediv; 796 best_fbdiv = _fbdiv; 797 best_freq = tmp; 798 min_delta = delta; 799 } 800 } 801 802 if (best_freq) { 803 *prediv = best_prediv; 804 *fbdiv = best_fbdiv; 805 } 806 807 return best_freq; 808 } 809 810 static unsigned long inno_video_phy_set_pll(struct rockchip_phy *phy, 811 unsigned long rate) 812 { 813 struct inno_video_phy *inno = dev_get_priv(phy->dev); 814 unsigned long fin, fout; 815 u16 fbdiv = 1; 816 u8 prediv = 1; 817 818 fin = 24000000; 819 fout = inno_video_phy_pll_round_rate(fin, rate, &prediv, &fbdiv); 820 821 dev_dbg(phy->dev, "fin=%lu, fout=%lu, prediv=%u, fbdiv=%u\n", 822 fin, fout, prediv, fbdiv); 823 824 inno->pll.prediv = prediv; 825 inno->pll.fbdiv = fbdiv; 826 inno->pll.rate = fout; 827 828 return fout; 829 } 830 831 static int inno_video_phy_set_mode(struct rockchip_phy *phy, 832 enum phy_mode mode) 833 { 834 struct inno_video_phy *inno = dev_get_priv(phy->dev); 835 836 switch (mode) { 837 case PHY_MODE_VIDEO_MIPI: 838 case PHY_MODE_VIDEO_LVDS: 839 case PHY_MODE_VIDEO_TTL: 840 inno->mode = mode; 841 break; 842 default: 843 return -EINVAL; 844 } 845 846 return 0; 847 } 848 849 static int inno_video_phy_probe(struct udevice *dev) 850 { 851 struct inno_video_phy *inno = dev_get_priv(dev); 852 struct rockchip_phy *tmp_phy; 853 struct rockchip_phy *phy; 854 int ret; 855 856 phy = calloc(1, sizeof(*phy)); 857 if (!phy) 858 return -ENOMEM; 859 860 tmp_phy = (struct rockchip_phy *)dev_get_driver_data(dev); 861 dev->driver_data = (ulong)phy; 862 memcpy(phy, tmp_phy, sizeof(*phy)); 863 864 inno->mipi_dphy_info = phy->data; 865 inno->lanes = ofnode_read_u32_default(dev->node, "inno,lanes", 4); 866 867 ret = dev_read_resource(dev, 0, &inno->phy); 868 if (ret < 0) { 869 dev_err(dev, "resource \"phy\" not found\n"); 870 return ret; 871 } 872 873 ret = dev_read_resource(dev, 1, &inno->host); 874 if (ret < 0) { 875 dev_err(dev, "resource \"host\" not found\n"); 876 return ret; 877 } 878 879 phy->dev = dev; 880 881 return 0; 882 } 883 884 static const struct rockchip_phy_funcs inno_video_phy_funcs = { 885 .power_on = inno_video_phy_power_on, 886 .power_off = inno_video_phy_power_off, 887 .set_pll = inno_video_phy_set_pll, 888 .set_mode = inno_video_phy_set_mode, 889 }; 890 891 static struct rockchip_phy px30_inno_video_phy_driver_data = { 892 .funcs = &inno_video_phy_funcs, 893 .data = &inno_video_mipi_dphy_max_1GHz, 894 }; 895 896 static struct rockchip_phy rk3568_inno_video_phy_driver_data = { 897 .funcs = &inno_video_phy_funcs, 898 .data = &inno_video_mipi_dphy_max_2_5GHz, 899 }; 900 901 static const struct udevice_id inno_video_phy_ids[] = { 902 { 903 .compatible = "rockchip,px30-video-phy", 904 .data = (ulong)&px30_inno_video_phy_driver_data, 905 }, 906 { 907 .compatible = "rockchip,rk3128-video-phy", 908 .data = (ulong)&px30_inno_video_phy_driver_data, 909 }, 910 { 911 .compatible = "rockchip,rk3368-video-phy", 912 .data = (ulong)&px30_inno_video_phy_driver_data, 913 }, 914 { 915 .compatible = "rockchip,rk3568-video-phy", 916 .data = (ulong)&rk3568_inno_video_phy_driver_data, 917 }, 918 { 919 .compatible = "rockchip,rk3568-dsi-dphy", 920 .data = (ulong)&rk3568_inno_video_phy_driver_data, 921 }, 922 {} 923 }; 924 925 U_BOOT_DRIVER(inno_video_combo_phy) = { 926 .name = "inno_video_combo_phy", 927 .id = UCLASS_PHY, 928 .of_match = inno_video_phy_ids, 929 .probe = inno_video_phy_probe, 930 .priv_auto_alloc_size = sizeof(struct inno_video_phy), 931 }; 932