1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2008-2018 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 * Author: Wyon Bi <bivvy.bi@rock-chips.com> 6 */ 7 8 #include <config.h> 9 #include <common.h> 10 #include <errno.h> 11 #include <dm.h> 12 #include <div64.h> 13 #include <asm/io.h> 14 #include <linux/ioport.h> 15 #include <linux/iopoll.h> 16 #include <linux/math64.h> 17 18 #include "rockchip_phy.h" 19 20 #define PSEC_PER_SEC 1000000000000LL 21 22 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) 23 24 /* 25 * The offset address[7:0] is distributed two parts, one from the bit7 to bit5 26 * is the first address, the other from the bit4 to bit0 is the second address. 27 * when you configure the registers, you must set both of them. The Clock Lane 28 * and Data Lane use the same registers with the same second address, but the 29 * first address is different. 30 */ 31 #define FIRST_ADDRESS(x) (((x) & 0x7) << 5) 32 #define SECOND_ADDRESS(x) (((x) & 0x1f) << 0) 33 #define PHY_REG(first, second) (FIRST_ADDRESS(first) | \ 34 SECOND_ADDRESS(second)) 35 36 /* Analog Register Part: reg00 */ 37 #define BANDGAP_POWER_MASK BIT(7) 38 #define BANDGAP_POWER_DOWN BIT(7) 39 #define BANDGAP_POWER_ON 0 40 #define LANE_EN_MASK GENMASK(6, 2) 41 #define LANE_EN_CK BIT(6) 42 #define LANE_EN_3 BIT(5) 43 #define LANE_EN_2 BIT(4) 44 #define LANE_EN_1 BIT(3) 45 #define LANE_EN_0 BIT(2) 46 #define POWER_WORK_MASK GENMASK(1, 0) 47 #define POWER_WORK_ENABLE UPDATE(1, 1, 0) 48 #define POWER_WORK_DISABLE UPDATE(2, 1, 0) 49 /* Analog Register Part: reg01 */ 50 #define REG_SYNCRST_MASK BIT(2) 51 #define REG_SYNCRST_RESET BIT(2) 52 #define REG_SYNCRST_NORMAL 0 53 #define REG_LDOPD_MASK BIT(1) 54 #define REG_LDOPD_POWER_DOWN BIT(1) 55 #define REG_LDOPD_POWER_ON 0 56 #define REG_PLLPD_MASK BIT(0) 57 #define REG_PLLPD_POWER_DOWN BIT(0) 58 #define REG_PLLPD_POWER_ON 0 59 /* Analog Register Part: reg03 */ 60 #define REG_FBDIV_HI_MASK BIT(5) 61 #define REG_FBDIV_HI(x) UPDATE(x, 5, 5) 62 #define REG_PREDIV_MASK GENMASK(4, 0) 63 #define REG_PREDIV(x) UPDATE(x, 4, 0) 64 /* Analog Register Part: reg04 */ 65 #define REG_FBDIV_LO_MASK GENMASK(7, 0) 66 #define REG_FBDIV_LO(x) UPDATE(x, 7, 0) 67 /* Analog Register Part: reg05 */ 68 #define SAMPLE_CLOCK_PHASE_MASK GENMASK(6, 4) 69 #define SAMPLE_CLOCK_PHASE(x) UPDATE(x, 6, 4) 70 #define CLOCK_LANE_SKEW_PHASE_MASK GENMASK(2, 0) 71 #define CLOCK_LANE_SKEW_PHASE(x) UPDATE(x, 2, 0) 72 /* Analog Register Part: reg06 */ 73 #define DATA_LANE_3_SKEW_PHASE_MASK GENMASK(6, 4) 74 #define DATA_LANE_3_SKEW_PHASE(x) UPDATE(x, 6, 4) 75 #define DATA_LANE_2_SKEW_PHASE_MASK GENMASK(2, 0) 76 #define DATA_LANE_2_SKEW_PHASE(x) UPDATE(x, 2, 0) 77 /* Analog Register Part: reg07 */ 78 #define DATA_LANE_1_SKEW_PHASE_MASK GENMASK(6, 4) 79 #define DATA_LANE_1_SKEW_PHASE(x) UPDATE(x, 6, 4) 80 #define DATA_LANE_0_SKEW_PHASE_MASK GENMASK(2, 0) 81 #define DATA_LANE_0_SKEW_PHASE(x) UPDATE(x, 2, 0) 82 /* Analog Register Part: reg08 */ 83 #define SAMPLE_CLOCK_DIRECTION_MASK BIT(4) 84 #define SAMPLE_CLOCK_DIRECTION_REVERSE BIT(4) 85 #define SAMPLE_CLOCK_DIRECTION_FORWARD 0 86 /* Digital Register Part: reg00 */ 87 #define REG_DIG_RSTN_MASK BIT(0) 88 #define REG_DIG_RSTN_NORMAL BIT(0) 89 #define REG_DIG_RSTN_RESET 0 90 /* Digital Register Part: reg01 */ 91 #define INVERT_TXCLKESC_MASK BIT(1) 92 #define INVERT_TXCLKESC_ENABLE BIT(1) 93 #define INVERT_TXCLKESC_DISABLE 0 94 #define INVERT_TXBYTECLKHS_MASK BIT(0) 95 #define INVERT_TXBYTECLKHS_ENABLE BIT(0) 96 #define INVERT_TXBYTECLKHS_DISABLE 0 97 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg05 */ 98 #define T_LPX_CNT_MASK GENMASK(5, 0) 99 #define T_LPX_CNT(x) UPDATE(x, 5, 0) 100 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */ 101 #define T_HS_PREPARE_CNT_MASK GENMASK(6, 0) 102 #define T_HS_PREPARE_CNT(x) UPDATE(x, 6, 0) 103 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */ 104 #define T_HS_ZERO_CNT_MASK GENMASK(5, 0) 105 #define T_HS_ZERO_CNT(x) UPDATE(x, 5, 0) 106 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */ 107 #define T_HS_TRAIL_CNT_MASK GENMASK(6, 0) 108 #define T_HS_TRAIL_CNT(x) UPDATE(x, 6, 0) 109 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */ 110 #define T_HS_EXIT_CNT_MASK GENMASK(4, 0) 111 #define T_HS_EXIT_CNT(x) UPDATE(x, 4, 0) 112 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */ 113 #define T_CLK_POST_CNT_MASK GENMASK(3, 0) 114 #define T_CLK_POST_CNT(x) UPDATE(x, 3, 0) 115 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */ 116 #define LPDT_TX_PPI_SYNC_MASK BIT(2) 117 #define LPDT_TX_PPI_SYNC_ENABLE BIT(2) 118 #define LPDT_TX_PPI_SYNC_DISABLE 0 119 #define T_WAKEUP_CNT_HI_MASK GENMASK(1, 0) 120 #define T_WAKEUP_CNT_HI(x) UPDATE(x, 1, 0) 121 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0d */ 122 #define T_WAKEUP_CNT_LO_MASK GENMASK(7, 0) 123 #define T_WAKEUP_CNT_LO(x) UPDATE(x, 7, 0) 124 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0e */ 125 #define T_CLK_PRE_CNT_MASK GENMASK(3, 0) 126 #define T_CLK_PRE_CNT(x) UPDATE(x, 3, 0) 127 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */ 128 #define T_TA_GO_CNT_MASK GENMASK(5, 0) 129 #define T_TA_GO_CNT(x) UPDATE(x, 5, 0) 130 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */ 131 #define T_TA_SURE_CNT_MASK GENMASK(5, 0) 132 #define T_TA_SURE_CNT(x) UPDATE(x, 5, 0) 133 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */ 134 #define T_TA_WAIT_CNT_MASK GENMASK(5, 0) 135 #define T_TA_WAIT_CNT(x) UPDATE(x, 5, 0) 136 /* LVDS Register Part: reg00 */ 137 #define LVDS_DIGITAL_INTERNAL_RESET_MASK BIT(2) 138 #define LVDS_DIGITAL_INTERNAL_RESET_DISABLE BIT(2) 139 #define LVDS_DIGITAL_INTERNAL_RESET_ENABLE 0 140 /* LVDS Register Part: reg01 */ 141 #define LVDS_DIGITAL_INTERNAL_ENABLE_MASK BIT(7) 142 #define LVDS_DIGITAL_INTERNAL_ENABLE BIT(7) 143 #define LVDS_DIGITAL_INTERNAL_DISABLE 0 144 /* LVDS Register Part: reg03 */ 145 #define MODE_ENABLE_MASK GENMASK(2, 0) 146 #define TTL_MODE_ENABLE BIT(2) 147 #define LVDS_MODE_ENABLE BIT(1) 148 #define MIPI_MODE_ENABLE BIT(0) 149 /* LVDS Register Part: reg0b */ 150 #define LVDS_LANE_EN_MASK GENMASK(7, 3) 151 #define LVDS_DATA_LANE0_EN BIT(7) 152 #define LVDS_DATA_LANE1_EN BIT(6) 153 #define LVDS_DATA_LANE2_EN BIT(5) 154 #define LVDS_DATA_LANE3_EN BIT(4) 155 #define LVDS_CLK_LANE_EN BIT(3) 156 #define LVDS_PLL_POWER_MASK BIT(2) 157 #define LVDS_PLL_POWER_OFF BIT(2) 158 #define LVDS_PLL_POWER_ON 0 159 #define LVDS_BANDGAP_POWER_MASK BIT(0) 160 #define LVDS_BANDGAP_POWER_DOWN BIT(0) 161 #define LVDS_BANDGAP_POWER_ON 0 162 163 #define DSI_PHY_RSTZ 0xa0 164 #define PHY_ENABLECLK BIT(2) 165 #define DSI_PHY_STATUS 0xb0 166 #define PHY_LOCK BIT(0) 167 168 struct mipi_dphy_timing { 169 unsigned int clkmiss; 170 unsigned int clkpost; 171 unsigned int clkpre; 172 unsigned int clkprepare; 173 unsigned int clksettle; 174 unsigned int clktermen; 175 unsigned int clktrail; 176 unsigned int clkzero; 177 unsigned int dtermen; 178 unsigned int eot; 179 unsigned int hsexit; 180 unsigned int hsprepare; 181 unsigned int hszero; 182 unsigned int hssettle; 183 unsigned int hsskip; 184 unsigned int hstrail; 185 unsigned int init; 186 unsigned int lpx; 187 unsigned int taget; 188 unsigned int tago; 189 unsigned int tasure; 190 unsigned int wakeup; 191 }; 192 193 struct inno_video_phy { 194 enum phy_mode mode; 195 struct resource phy; 196 struct resource host; 197 struct { 198 u8 prediv; 199 u16 fbdiv; 200 unsigned long rate; 201 } pll; 202 }; 203 204 enum { 205 REGISTER_PART_ANALOG, 206 REGISTER_PART_DIGITAL, 207 REGISTER_PART_CLOCK_LANE, 208 REGISTER_PART_DATA0_LANE, 209 REGISTER_PART_DATA1_LANE, 210 REGISTER_PART_DATA2_LANE, 211 REGISTER_PART_DATA3_LANE, 212 REGISTER_PART_LVDS, 213 }; 214 215 static inline void phy_update_bits(struct inno_video_phy *inno, 216 u8 first, u8 second, u8 mask, u8 val) 217 { 218 u32 reg = PHY_REG(first, second) << 2; 219 u32 tmp, orig; 220 221 orig = readl(inno->phy.start + reg); 222 tmp = orig & ~mask; 223 tmp |= val & mask; 224 writel(tmp, inno->phy.start + reg); 225 } 226 227 static inline void host_update_bits(struct inno_video_phy *inno, 228 u32 reg, u32 mask, u32 val) 229 { 230 u32 tmp, orig; 231 232 orig = readl(inno->host.start + reg); 233 tmp = orig & ~mask; 234 tmp |= val & mask; 235 writel(tmp, inno->host.start + reg); 236 } 237 238 static void mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, 239 unsigned long period) 240 { 241 /* Global Operation Timing Parameters */ 242 timing->clkmiss = 0; 243 timing->clkpost = 70000 + 52 * period; 244 timing->clkpre = 8 * period; 245 timing->clkprepare = 65000; 246 timing->clksettle = 95000; 247 timing->clktermen = 0; 248 timing->clktrail = 80000; 249 timing->clkzero = 260000; 250 timing->dtermen = 0; 251 timing->eot = 0; 252 timing->hsexit = 120000; 253 timing->hsprepare = 65000 + 4 * period; 254 timing->hszero = 145000 + 6 * period; 255 timing->hssettle = 85000 + 6 * period; 256 timing->hsskip = 40000; 257 timing->hstrail = max(8 * period, 60000 + 4 * period); 258 timing->init = 100000000; 259 timing->lpx = 60000; 260 timing->taget = 5 * timing->lpx; 261 timing->tago = 4 * timing->lpx; 262 timing->tasure = 2 * timing->lpx; 263 timing->wakeup = 1000000000; 264 } 265 266 static void inno_video_phy_mipi_mode_enable(struct inno_video_phy *inno) 267 { 268 struct mipi_dphy_timing gotp; 269 const struct { 270 unsigned long rate; 271 u8 hs_prepare; 272 u8 clk_lane_hs_zero; 273 u8 data_lane_hs_zero; 274 u8 hs_trail; 275 } timings[] = { 276 { 110000000, 0x20, 0x16, 0x02, 0x22}, 277 { 150000000, 0x06, 0x16, 0x03, 0x45}, 278 { 200000000, 0x18, 0x17, 0x04, 0x0b}, 279 { 250000000, 0x05, 0x17, 0x05, 0x16}, 280 { 300000000, 0x51, 0x18, 0x06, 0x2c}, 281 { 400000000, 0x64, 0x19, 0x07, 0x33}, 282 { 500000000, 0x20, 0x1b, 0x07, 0x4e}, 283 { 600000000, 0x6a, 0x1d, 0x08, 0x3a}, 284 { 700000000, 0x3e, 0x1e, 0x08, 0x6a}, 285 { 800000000, 0x21, 0x1f, 0x09, 0x29}, 286 {1000000000, 0x09, 0x20, 0x09, 0x27}, 287 }; 288 u32 t_txbyteclkhs, t_txclkesc, ui; 289 u32 txbyteclkhs, txclkesc, esc_clk_div; 290 u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait; 291 u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero; 292 unsigned int i; 293 294 /* Select MIPI mode */ 295 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, 296 MODE_ENABLE_MASK, MIPI_MODE_ENABLE); 297 /* Configure PLL */ 298 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 299 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); 300 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 301 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8)); 302 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, 303 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); 304 /* Enable PLL and LDO */ 305 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 306 REG_LDOPD_MASK | REG_PLLPD_MASK, 307 REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON); 308 /* Reset analog */ 309 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 310 REG_SYNCRST_MASK, REG_SYNCRST_RESET); 311 udelay(1); 312 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 313 REG_SYNCRST_MASK, REG_SYNCRST_NORMAL); 314 /* Reset digital */ 315 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00, 316 REG_DIG_RSTN_MASK, REG_DIG_RSTN_RESET); 317 udelay(1); 318 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00, 319 REG_DIG_RSTN_MASK, REG_DIG_RSTN_NORMAL); 320 321 txbyteclkhs = inno->pll.rate / 8; 322 t_txbyteclkhs = div_u64(PSEC_PER_SEC, txbyteclkhs); 323 324 esc_clk_div = DIV_ROUND_UP(txbyteclkhs, 20000000); 325 txclkesc = txbyteclkhs / esc_clk_div; 326 t_txclkesc = div_u64(PSEC_PER_SEC, txclkesc); 327 328 ui = div_u64(PSEC_PER_SEC, inno->pll.rate); 329 330 memset(&gotp, 0, sizeof(gotp)); 331 mipi_dphy_timing_get_default(&gotp, ui); 332 333 /* 334 * The value of counter for HS Ths-exit 335 * Ths-exit = Tpin_txbyteclkhs * value 336 */ 337 hs_exit = DIV_ROUND_UP(gotp.hsexit, t_txbyteclkhs); 338 /* 339 * The value of counter for HS Tclk-post 340 * Tclk-post = Tpin_txbyteclkhs * value 341 */ 342 clk_post = DIV_ROUND_UP(gotp.clkpost, t_txbyteclkhs); 343 /* 344 * The value of counter for HS Tclk-pre 345 * Tclk-pre = Tpin_txbyteclkhs * value 346 */ 347 clk_pre = DIV_ROUND_UP(gotp.clkpre, t_txbyteclkhs); 348 349 /* 350 * The value of counter for HS Tlpx Time 351 * Tlpx = Tpin_txbyteclkhs * (2 + value) 352 */ 353 lpx = DIV_ROUND_UP(gotp.lpx, t_txbyteclkhs); 354 if (lpx >= 2) 355 lpx -= 2; 356 357 /* 358 * The value of counter for HS Tta-go 359 * Tta-go for turnaround 360 * Tta-go = Ttxclkesc * value 361 */ 362 ta_go = DIV_ROUND_UP(gotp.tago, t_txclkesc); 363 /* 364 * The value of counter for HS Tta-sure 365 * Tta-sure for turnaround 366 * Tta-sure = Ttxclkesc * value 367 */ 368 ta_sure = DIV_ROUND_UP(gotp.tasure, t_txclkesc); 369 /* 370 * The value of counter for HS Tta-wait 371 * Tta-wait for turnaround 372 * Tta-wait = Ttxclkesc * value 373 */ 374 ta_wait = DIV_ROUND_UP(gotp.taget, t_txclkesc); 375 376 for (i = 0; i < ARRAY_SIZE(timings); i++) 377 if (inno->pll.rate <= timings[i].rate) 378 break; 379 380 if (i == ARRAY_SIZE(timings)) 381 --i; 382 383 hs_prepare = timings[i].hs_prepare; 384 hs_trail = timings[i].hs_trail; 385 clk_lane_hs_zero = timings[i].clk_lane_hs_zero; 386 data_lane_hs_zero = timings[i].data_lane_hs_zero; 387 wakeup = 0x3ff; 388 389 for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) { 390 if (i == REGISTER_PART_CLOCK_LANE) 391 hs_zero = clk_lane_hs_zero; 392 else 393 hs_zero = data_lane_hs_zero; 394 395 phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK, 396 T_LPX_CNT(lpx)); 397 phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK, 398 T_HS_PREPARE_CNT(hs_prepare)); 399 phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_MASK, 400 T_HS_ZERO_CNT(hs_zero)); 401 phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK, 402 T_HS_TRAIL_CNT(hs_trail)); 403 phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_MASK, 404 T_HS_EXIT_CNT(hs_exit)); 405 phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_MASK, 406 T_CLK_POST_CNT(clk_post)); 407 phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK, 408 T_CLK_PRE_CNT(clk_pre)); 409 phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK, 410 T_WAKEUP_CNT_HI(wakeup >> 8)); 411 phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK, 412 T_WAKEUP_CNT_LO(wakeup)); 413 phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK, 414 T_TA_GO_CNT(ta_go)); 415 phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK, 416 T_TA_SURE_CNT(ta_sure)); 417 phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK, 418 T_TA_WAIT_CNT(ta_wait)); 419 } 420 421 /* Enable all lanes on analog part */ 422 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 423 LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 | 424 LANE_EN_1 | LANE_EN_0); 425 } 426 427 static void inno_video_phy_lvds_mode_enable(struct inno_video_phy *inno) 428 { 429 u8 prediv = 2; 430 u16 fbdiv = 28; 431 u32 val; 432 int ret; 433 434 /* Sample clock reverse direction */ 435 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08, 436 SAMPLE_CLOCK_DIRECTION_MASK, 437 SAMPLE_CLOCK_DIRECTION_REVERSE); 438 /* Select LVDS mode */ 439 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, 440 MODE_ENABLE_MASK, LVDS_MODE_ENABLE); 441 /* Configure PLL */ 442 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 443 REG_PREDIV_MASK, REG_PREDIV(prediv)); 444 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 445 REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv >> 8)); 446 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, 447 REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv)); 448 phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc); 449 /* Enable PLL and Bandgap */ 450 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, 451 LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK, 452 LVDS_PLL_POWER_ON | LVDS_BANDGAP_POWER_ON); 453 454 ret = readl_poll_timeout(inno->host.start + DSI_PHY_STATUS, 455 val, val & PHY_LOCK, 10000); 456 if (ret) 457 dev_err(phy->dev, "PLL is not lock\n"); 458 459 /* Reset LVDS digital logic */ 460 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, 461 LVDS_DIGITAL_INTERNAL_RESET_MASK, 462 LVDS_DIGITAL_INTERNAL_RESET_ENABLE); 463 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, 464 LVDS_DIGITAL_INTERNAL_RESET_MASK, 465 LVDS_DIGITAL_INTERNAL_RESET_DISABLE); 466 /* Enable LVDS digital logic */ 467 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, 468 LVDS_DIGITAL_INTERNAL_ENABLE_MASK, 469 LVDS_DIGITAL_INTERNAL_ENABLE); 470 /* Enable LVDS analog driver */ 471 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, 472 LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN | 473 LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN | 474 LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN); 475 } 476 477 static void inno_video_phy_ttl_mode_enable(struct inno_video_phy *inno) 478 { 479 /* Select TTL mode */ 480 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, 481 MODE_ENABLE_MASK, TTL_MODE_ENABLE); 482 /* Reset digital logic */ 483 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, 484 LVDS_DIGITAL_INTERNAL_RESET_MASK, 485 LVDS_DIGITAL_INTERNAL_RESET_ENABLE); 486 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, 487 LVDS_DIGITAL_INTERNAL_RESET_MASK, 488 LVDS_DIGITAL_INTERNAL_RESET_DISABLE); 489 /* Enable digital logic */ 490 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, 491 LVDS_DIGITAL_INTERNAL_ENABLE_MASK, 492 LVDS_DIGITAL_INTERNAL_ENABLE); 493 /* Enable analog driver */ 494 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, 495 LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN | 496 LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN | 497 LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN); 498 /* Enable for clk lane in TTL mode */ 499 host_update_bits(inno, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK); 500 } 501 502 static int inno_video_phy_power_on(struct rockchip_phy *phy) 503 { 504 struct inno_video_phy *inno = dev_get_priv(phy->dev); 505 506 /* Bandgap power on */ 507 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 508 BANDGAP_POWER_MASK, BANDGAP_POWER_ON); 509 /* Enable power work */ 510 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 511 POWER_WORK_MASK, POWER_WORK_ENABLE); 512 513 switch (inno->mode) { 514 case PHY_MODE_VIDEO_MIPI: 515 inno_video_phy_mipi_mode_enable(inno); 516 break; 517 case PHY_MODE_VIDEO_LVDS: 518 inno_video_phy_lvds_mode_enable(inno); 519 break; 520 case PHY_MODE_VIDEO_TTL: 521 inno_video_phy_ttl_mode_enable(inno); 522 break; 523 default: 524 return -EINVAL; 525 } 526 527 return 0; 528 } 529 530 static int inno_video_phy_power_off(struct rockchip_phy *phy) 531 { 532 struct inno_video_phy *inno = dev_get_priv(phy->dev); 533 534 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0); 535 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 536 REG_LDOPD_MASK | REG_PLLPD_MASK, 537 REG_LDOPD_POWER_DOWN | REG_PLLPD_POWER_DOWN); 538 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 539 POWER_WORK_MASK, POWER_WORK_DISABLE); 540 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 541 BANDGAP_POWER_MASK, BANDGAP_POWER_DOWN); 542 543 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0); 544 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, 545 LVDS_DIGITAL_INTERNAL_ENABLE_MASK, 546 LVDS_DIGITAL_INTERNAL_DISABLE); 547 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, 548 LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK, 549 LVDS_PLL_POWER_OFF | LVDS_BANDGAP_POWER_DOWN); 550 551 return 0; 552 } 553 554 static unsigned long inno_video_phy_pll_round_rate(unsigned long prate, 555 unsigned long rate, 556 u8 *prediv, u16 *fbdiv) 557 { 558 unsigned long best_freq = 0; 559 unsigned long fref, fout; 560 u8 min_prediv, max_prediv; 561 u8 _prediv, best_prediv = 1; 562 u16 _fbdiv, best_fbdiv = 1; 563 u32 min_delta = 0xffffffff; 564 565 /* 566 * The PLL output frequency can be calculated using a simple formula: 567 * PLL_Output_Frequency = (FREF / PREDIV * FBDIV) / 2 568 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2 569 */ 570 fref = prate / 2; 571 if (rate > 1000000000UL) 572 fout = 1000000000UL; 573 else 574 fout = rate; 575 576 /* 5Mhz < Fref / prediv < 40MHz */ 577 min_prediv = DIV_ROUND_UP(fref, 40000000); 578 max_prediv = fref / 5000000; 579 580 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 581 u64 tmp; 582 u32 delta; 583 584 tmp = (u64)fout * _prediv; 585 do_div(tmp, fref); 586 _fbdiv = tmp; 587 588 /* 589 * The all possible settings of feedback divider are 590 * 12, 13, 14, 16, ~ 511 591 */ 592 if (_fbdiv == 15) 593 continue; 594 595 if (_fbdiv < 12 || _fbdiv > 511) 596 continue; 597 598 tmp = (u64)_fbdiv * fref; 599 do_div(tmp, _prediv); 600 601 delta = abs(fout - tmp); 602 if (!delta) { 603 best_prediv = _prediv; 604 best_fbdiv = _fbdiv; 605 best_freq = tmp; 606 break; 607 } else if (delta < min_delta) { 608 best_prediv = _prediv; 609 best_fbdiv = _fbdiv; 610 best_freq = tmp; 611 min_delta = delta; 612 } 613 } 614 615 if (best_freq) { 616 *prediv = best_prediv; 617 *fbdiv = best_fbdiv; 618 } 619 620 return best_freq; 621 } 622 623 static unsigned long inno_video_phy_set_pll(struct rockchip_phy *phy, 624 unsigned long rate) 625 { 626 struct inno_video_phy *inno = dev_get_priv(phy->dev); 627 unsigned long fin, fout; 628 u16 fbdiv = 1; 629 u8 prediv = 1; 630 631 fin = 24000000; 632 fout = inno_video_phy_pll_round_rate(fin, rate, &prediv, &fbdiv); 633 634 dev_dbg(phy->dev, "fin=%lu, fout=%lu, prediv=%u, fbdiv=%u\n", 635 fin, fout, prediv, fbdiv); 636 637 inno->pll.prediv = prediv; 638 inno->pll.fbdiv = fbdiv; 639 inno->pll.rate = fout; 640 641 return fout; 642 } 643 644 static int inno_video_phy_set_mode(struct rockchip_phy *phy, 645 enum phy_mode mode) 646 { 647 struct inno_video_phy *inno = dev_get_priv(phy->dev); 648 649 switch (mode) { 650 case PHY_MODE_VIDEO_MIPI: 651 case PHY_MODE_VIDEO_LVDS: 652 case PHY_MODE_VIDEO_TTL: 653 inno->mode = mode; 654 break; 655 default: 656 return -EINVAL; 657 } 658 659 return 0; 660 } 661 662 static const struct rockchip_phy_funcs inno_video_phy_funcs = { 663 .power_on = inno_video_phy_power_on, 664 .power_off = inno_video_phy_power_off, 665 .set_pll = inno_video_phy_set_pll, 666 .set_mode = inno_video_phy_set_mode, 667 }; 668 669 static int inno_video_phy_probe(struct udevice *dev) 670 { 671 struct inno_video_phy *inno = dev_get_priv(dev); 672 struct rockchip_phy *phy = 673 (struct rockchip_phy *)dev_get_driver_data(dev); 674 int ret; 675 676 ret = dev_read_resource(dev, 0, &inno->phy); 677 if (ret < 0) { 678 dev_err(dev, "resource \"phy\" not found\n"); 679 return ret; 680 } 681 682 ret = dev_read_resource(dev, 1, &inno->host); 683 if (ret < 0) { 684 dev_err(dev, "resource \"host\" not found\n"); 685 return ret; 686 } 687 688 phy->dev = dev; 689 690 return 0; 691 } 692 693 static struct rockchip_phy inno_video_phy_driver_data = { 694 .funcs = &inno_video_phy_funcs, 695 }; 696 697 static const struct udevice_id inno_video_phy_ids[] = { 698 { 699 .compatible = "rockchip,px30-video-phy", 700 .data = (ulong)&inno_video_phy_driver_data, 701 }, 702 { 703 .compatible = "rockchip,rk3128-video-phy", 704 .data = (ulong)&inno_video_phy_driver_data, 705 }, 706 { 707 .compatible = "rockchip,rk3368-video-phy", 708 .data = (ulong)&inno_video_phy_driver_data, 709 }, 710 {} 711 }; 712 713 U_BOOT_DRIVER(inno_video_combo_phy) = { 714 .name = "inno_video_combo_phy", 715 .id = UCLASS_PHY, 716 .of_match = inno_video_phy_ids, 717 .probe = inno_video_phy_probe, 718 .priv_auto_alloc_size = sizeof(struct inno_video_phy), 719 }; 720