1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2008-2018 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 * Author: Wyon Bi <bivvy.bi@rock-chips.com> 6 */ 7 8 #include <config.h> 9 #include <common.h> 10 #include <errno.h> 11 #include <dm.h> 12 #include <div64.h> 13 #include <asm/io.h> 14 #include <linux/ioport.h> 15 #include <linux/iopoll.h> 16 #include <linux/math64.h> 17 18 #include "rockchip_phy.h" 19 20 #define PSEC_PER_SEC 1000000000000LL 21 22 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) 23 24 /* 25 * The offset address[7:0] is distributed two parts, one from the bit7 to bit5 26 * is the first address, the other from the bit4 to bit0 is the second address. 27 * when you configure the registers, you must set both of them. The Clock Lane 28 * and Data Lane use the same registers with the same second address, but the 29 * first address is different. 30 */ 31 #define FIRST_ADDRESS(x) (((x) & 0x7) << 5) 32 #define SECOND_ADDRESS(x) (((x) & 0x1f) << 0) 33 #define PHY_REG(first, second) (FIRST_ADDRESS(first) | \ 34 SECOND_ADDRESS(second)) 35 36 /* Analog Register Part: reg00 */ 37 #define BANDGAP_POWER_MASK BIT(7) 38 #define BANDGAP_POWER_DOWN BIT(7) 39 #define BANDGAP_POWER_ON 0 40 #define LANE_EN_MASK GENMASK(6, 2) 41 #define LANE_EN_CK BIT(6) 42 #define LANE_EN_3 BIT(5) 43 #define LANE_EN_2 BIT(4) 44 #define LANE_EN_1 BIT(3) 45 #define LANE_EN_0 BIT(2) 46 #define POWER_WORK_MASK GENMASK(1, 0) 47 #define POWER_WORK_ENABLE UPDATE(1, 1, 0) 48 #define POWER_WORK_DISABLE UPDATE(2, 1, 0) 49 /* Analog Register Part: reg01 */ 50 #define REG_SYNCRST_MASK BIT(2) 51 #define REG_SYNCRST_RESET BIT(2) 52 #define REG_SYNCRST_NORMAL 0 53 #define REG_LDOPD_MASK BIT(1) 54 #define REG_LDOPD_POWER_DOWN BIT(1) 55 #define REG_LDOPD_POWER_ON 0 56 #define REG_PLLPD_MASK BIT(0) 57 #define REG_PLLPD_POWER_DOWN BIT(0) 58 #define REG_PLLPD_POWER_ON 0 59 /* Analog Register Part: reg03 */ 60 #define REG_FBDIV_HI_MASK BIT(5) 61 #define REG_FBDIV_HI(x) UPDATE(x, 5, 5) 62 #define REG_PREDIV_MASK GENMASK(4, 0) 63 #define REG_PREDIV(x) UPDATE(x, 4, 0) 64 /* Analog Register Part: reg04 */ 65 #define REG_FBDIV_LO_MASK GENMASK(7, 0) 66 #define REG_FBDIV_LO(x) UPDATE(x, 7, 0) 67 /* Analog Register Part: reg05 */ 68 #define SAMPLE_CLOCK_PHASE_MASK GENMASK(6, 4) 69 #define SAMPLE_CLOCK_PHASE(x) UPDATE(x, 6, 4) 70 #define CLOCK_LANE_SKEW_PHASE_MASK GENMASK(2, 0) 71 #define CLOCK_LANE_SKEW_PHASE(x) UPDATE(x, 2, 0) 72 /* Analog Register Part: reg06 */ 73 #define DATA_LANE_3_SKEW_PHASE_MASK GENMASK(6, 4) 74 #define DATA_LANE_3_SKEW_PHASE(x) UPDATE(x, 6, 4) 75 #define DATA_LANE_2_SKEW_PHASE_MASK GENMASK(2, 0) 76 #define DATA_LANE_2_SKEW_PHASE(x) UPDATE(x, 2, 0) 77 /* Analog Register Part: reg07 */ 78 #define DATA_LANE_1_SKEW_PHASE_MASK GENMASK(6, 4) 79 #define DATA_LANE_1_SKEW_PHASE(x) UPDATE(x, 6, 4) 80 #define DATA_LANE_0_SKEW_PHASE_MASK GENMASK(2, 0) 81 #define DATA_LANE_0_SKEW_PHASE(x) UPDATE(x, 2, 0) 82 /* Analog Register Part: reg08 */ 83 #define SAMPLE_CLOCK_DIRECTION_MASK BIT(4) 84 #define SAMPLE_CLOCK_DIRECTION_REVERSE BIT(4) 85 #define SAMPLE_CLOCK_DIRECTION_FORWARD 0 86 #define LOWFRE_EN_MASK BIT(5) 87 #define PLL_OUTPUT_FREQUENCY_DIV_BY_1 0 88 #define PLL_OUTPUT_FREQUENCY_DIV_BY_2 1 89 /* Analog Register Part: reg1e */ 90 #define PLL_MODE_SEL_MASK GENMASK(6, 5) 91 #define PLL_MODE_SEL_LVDS_MODE 0 92 #define PLL_MODE_SEL_MIPI_MODE BIT(5) 93 94 /* Digital Register Part: reg00 */ 95 #define REG_DIG_RSTN_MASK BIT(0) 96 #define REG_DIG_RSTN_NORMAL BIT(0) 97 #define REG_DIG_RSTN_RESET 0 98 /* Digital Register Part: reg01 */ 99 #define INVERT_TXCLKESC_MASK BIT(1) 100 #define INVERT_TXCLKESC_ENABLE BIT(1) 101 #define INVERT_TXCLKESC_DISABLE 0 102 #define INVERT_TXBYTECLKHS_MASK BIT(0) 103 #define INVERT_TXBYTECLKHS_ENABLE BIT(0) 104 #define INVERT_TXBYTECLKHS_DISABLE 0 105 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg05 */ 106 #define T_LPX_CNT_MASK GENMASK(5, 0) 107 #define T_LPX_CNT(x) UPDATE(x, 5, 0) 108 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */ 109 #define T_HS_PREPARE_CNT_MASK GENMASK(6, 0) 110 #define T_HS_PREPARE_CNT(x) UPDATE(x, 6, 0) 111 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */ 112 #define T_HS_ZERO_CNT_MASK GENMASK(5, 0) 113 #define T_HS_ZERO_CNT(x) UPDATE(x, 5, 0) 114 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */ 115 #define T_HS_TRAIL_CNT_MASK GENMASK(6, 0) 116 #define T_HS_TRAIL_CNT(x) UPDATE(x, 6, 0) 117 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */ 118 #define T_HS_EXIT_CNT_MASK GENMASK(4, 0) 119 #define T_HS_EXIT_CNT(x) UPDATE(x, 4, 0) 120 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */ 121 #define T_CLK_POST_CNT_MASK GENMASK(3, 0) 122 #define T_CLK_POST_CNT(x) UPDATE(x, 3, 0) 123 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */ 124 #define LPDT_TX_PPI_SYNC_MASK BIT(2) 125 #define LPDT_TX_PPI_SYNC_ENABLE BIT(2) 126 #define LPDT_TX_PPI_SYNC_DISABLE 0 127 #define T_WAKEUP_CNT_HI_MASK GENMASK(1, 0) 128 #define T_WAKEUP_CNT_HI(x) UPDATE(x, 1, 0) 129 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0d */ 130 #define T_WAKEUP_CNT_LO_MASK GENMASK(7, 0) 131 #define T_WAKEUP_CNT_LO(x) UPDATE(x, 7, 0) 132 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0e */ 133 #define T_CLK_PRE_CNT_MASK GENMASK(3, 0) 134 #define T_CLK_PRE_CNT(x) UPDATE(x, 3, 0) 135 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */ 136 #define T_TA_GO_CNT_MASK GENMASK(5, 0) 137 #define T_TA_GO_CNT(x) UPDATE(x, 5, 0) 138 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */ 139 #define T_TA_SURE_CNT_MASK GENMASK(5, 0) 140 #define T_TA_SURE_CNT(x) UPDATE(x, 5, 0) 141 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */ 142 #define T_TA_WAIT_CNT_MASK GENMASK(5, 0) 143 #define T_TA_WAIT_CNT(x) UPDATE(x, 5, 0) 144 /* LVDS Register Part: reg00 */ 145 #define LVDS_DIGITAL_INTERNAL_RESET_MASK BIT(2) 146 #define LVDS_DIGITAL_INTERNAL_RESET_DISABLE BIT(2) 147 #define LVDS_DIGITAL_INTERNAL_RESET_ENABLE 0 148 /* LVDS Register Part: reg01 */ 149 #define LVDS_DIGITAL_INTERNAL_ENABLE_MASK BIT(7) 150 #define LVDS_DIGITAL_INTERNAL_ENABLE BIT(7) 151 #define LVDS_DIGITAL_INTERNAL_DISABLE 0 152 /* LVDS Register Part: reg03 */ 153 #define MODE_ENABLE_MASK GENMASK(2, 0) 154 #define TTL_MODE_ENABLE BIT(2) 155 #define LVDS_MODE_ENABLE BIT(1) 156 #define MIPI_MODE_ENABLE BIT(0) 157 /* LVDS Register Part: reg0b */ 158 #define LVDS_LANE_EN_MASK GENMASK(7, 3) 159 #define LVDS_DATA_LANE0_EN BIT(7) 160 #define LVDS_DATA_LANE1_EN BIT(6) 161 #define LVDS_DATA_LANE2_EN BIT(5) 162 #define LVDS_DATA_LANE3_EN BIT(4) 163 #define LVDS_CLK_LANE_EN BIT(3) 164 #define LVDS_PLL_POWER_MASK BIT(2) 165 #define LVDS_PLL_POWER_OFF BIT(2) 166 #define LVDS_PLL_POWER_ON 0 167 #define LVDS_BANDGAP_POWER_MASK BIT(0) 168 #define LVDS_BANDGAP_POWER_DOWN BIT(0) 169 #define LVDS_BANDGAP_POWER_ON 0 170 171 #define DSI_PHY_RSTZ 0xa0 172 #define PHY_ENABLECLK BIT(2) 173 #define DSI_PHY_STATUS 0xb0 174 #define PHY_LOCK BIT(0) 175 176 struct mipi_dphy_timing { 177 unsigned int clkmiss; 178 unsigned int clkpost; 179 unsigned int clkpre; 180 unsigned int clkprepare; 181 unsigned int clksettle; 182 unsigned int clktermen; 183 unsigned int clktrail; 184 unsigned int clkzero; 185 unsigned int dtermen; 186 unsigned int eot; 187 unsigned int hsexit; 188 unsigned int hsprepare; 189 unsigned int hszero; 190 unsigned int hssettle; 191 unsigned int hsskip; 192 unsigned int hstrail; 193 unsigned int init; 194 unsigned int lpx; 195 unsigned int taget; 196 unsigned int tago; 197 unsigned int tasure; 198 unsigned int wakeup; 199 }; 200 201 struct inno_video_phy { 202 enum phy_mode mode; 203 struct resource phy; 204 struct resource host; 205 struct { 206 u8 prediv; 207 u16 fbdiv; 208 unsigned long rate; 209 } pll; 210 }; 211 212 enum { 213 REGISTER_PART_ANALOG, 214 REGISTER_PART_DIGITAL, 215 REGISTER_PART_CLOCK_LANE, 216 REGISTER_PART_DATA0_LANE, 217 REGISTER_PART_DATA1_LANE, 218 REGISTER_PART_DATA2_LANE, 219 REGISTER_PART_DATA3_LANE, 220 REGISTER_PART_LVDS, 221 }; 222 223 static inline void phy_update_bits(struct inno_video_phy *inno, 224 u8 first, u8 second, u8 mask, u8 val) 225 { 226 u32 reg = PHY_REG(first, second) << 2; 227 u32 tmp, orig; 228 229 orig = readl(inno->phy.start + reg); 230 tmp = orig & ~mask; 231 tmp |= val & mask; 232 writel(tmp, inno->phy.start + reg); 233 } 234 235 static inline void host_update_bits(struct inno_video_phy *inno, 236 u32 reg, u32 mask, u32 val) 237 { 238 u32 tmp, orig; 239 240 orig = readl(inno->host.start + reg); 241 tmp = orig & ~mask; 242 tmp |= val & mask; 243 writel(tmp, inno->host.start + reg); 244 } 245 246 static void mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, 247 unsigned long period) 248 { 249 /* Global Operation Timing Parameters */ 250 timing->clkmiss = 0; 251 timing->clkpost = 70000 + 52 * period; 252 timing->clkpre = 8 * period; 253 timing->clkprepare = 65000; 254 timing->clksettle = 95000; 255 timing->clktermen = 0; 256 timing->clktrail = 80000; 257 timing->clkzero = 260000; 258 timing->dtermen = 0; 259 timing->eot = 0; 260 timing->hsexit = 120000; 261 timing->hsprepare = 65000 + 4 * period; 262 timing->hszero = 145000 + 6 * period; 263 timing->hssettle = 85000 + 6 * period; 264 timing->hsskip = 40000; 265 timing->hstrail = max(8 * period, 60000 + 4 * period); 266 timing->init = 100000000; 267 timing->lpx = 60000; 268 timing->taget = 5 * timing->lpx; 269 timing->tago = 4 * timing->lpx; 270 timing->tasure = 2 * timing->lpx; 271 timing->wakeup = 1000000000; 272 } 273 274 static void inno_video_phy_mipi_mode_enable(struct inno_video_phy *inno) 275 { 276 struct mipi_dphy_timing gotp; 277 const struct { 278 unsigned long rate; 279 u8 hs_prepare; 280 u8 clk_lane_hs_zero; 281 u8 data_lane_hs_zero; 282 u8 hs_trail; 283 } timings[] = { 284 { 110000000, 0x20, 0x16, 0x02, 0x22}, 285 { 150000000, 0x06, 0x16, 0x03, 0x45}, 286 { 200000000, 0x18, 0x17, 0x04, 0x0b}, 287 { 250000000, 0x05, 0x17, 0x05, 0x16}, 288 { 300000000, 0x51, 0x18, 0x06, 0x2c}, 289 { 400000000, 0x64, 0x19, 0x07, 0x33}, 290 { 500000000, 0x20, 0x1b, 0x07, 0x4e}, 291 { 600000000, 0x6a, 0x1d, 0x08, 0x3a}, 292 { 700000000, 0x3e, 0x1e, 0x08, 0x6a}, 293 { 800000000, 0x21, 0x1f, 0x09, 0x29}, 294 {1000000000, 0x09, 0x20, 0x09, 0x27}, 295 }; 296 u32 t_txbyteclkhs, t_txclkesc, ui; 297 u32 txbyteclkhs, txclkesc, esc_clk_div; 298 u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait; 299 u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero; 300 unsigned int i; 301 302 /* Select MIPI mode */ 303 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, 304 MODE_ENABLE_MASK, MIPI_MODE_ENABLE); 305 /* Configure PLL */ 306 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 307 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); 308 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 309 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8)); 310 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, 311 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); 312 /* Enable PLL and LDO */ 313 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 314 REG_LDOPD_MASK | REG_PLLPD_MASK, 315 REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON); 316 /* Reset analog */ 317 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 318 REG_SYNCRST_MASK, REG_SYNCRST_RESET); 319 udelay(1); 320 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 321 REG_SYNCRST_MASK, REG_SYNCRST_NORMAL); 322 /* Reset digital */ 323 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00, 324 REG_DIG_RSTN_MASK, REG_DIG_RSTN_RESET); 325 udelay(1); 326 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00, 327 REG_DIG_RSTN_MASK, REG_DIG_RSTN_NORMAL); 328 329 txbyteclkhs = inno->pll.rate / 8; 330 t_txbyteclkhs = div_u64(PSEC_PER_SEC, txbyteclkhs); 331 332 esc_clk_div = DIV_ROUND_UP(txbyteclkhs, 20000000); 333 txclkesc = txbyteclkhs / esc_clk_div; 334 t_txclkesc = div_u64(PSEC_PER_SEC, txclkesc); 335 336 ui = div_u64(PSEC_PER_SEC, inno->pll.rate); 337 338 memset(&gotp, 0, sizeof(gotp)); 339 mipi_dphy_timing_get_default(&gotp, ui); 340 341 /* 342 * The value of counter for HS Ths-exit 343 * Ths-exit = Tpin_txbyteclkhs * value 344 */ 345 hs_exit = DIV_ROUND_UP(gotp.hsexit, t_txbyteclkhs); 346 /* 347 * The value of counter for HS Tclk-post 348 * Tclk-post = Tpin_txbyteclkhs * value 349 */ 350 clk_post = DIV_ROUND_UP(gotp.clkpost, t_txbyteclkhs); 351 /* 352 * The value of counter for HS Tclk-pre 353 * Tclk-pre = Tpin_txbyteclkhs * value 354 */ 355 clk_pre = DIV_ROUND_UP(gotp.clkpre, t_txbyteclkhs); 356 357 /* 358 * The value of counter for HS Tlpx Time 359 * Tlpx = Tpin_txbyteclkhs * (2 + value) 360 */ 361 lpx = DIV_ROUND_UP(gotp.lpx, t_txbyteclkhs); 362 if (lpx >= 2) 363 lpx -= 2; 364 365 /* 366 * The value of counter for HS Tta-go 367 * Tta-go for turnaround 368 * Tta-go = Ttxclkesc * value 369 */ 370 ta_go = DIV_ROUND_UP(gotp.tago, t_txclkesc); 371 /* 372 * The value of counter for HS Tta-sure 373 * Tta-sure for turnaround 374 * Tta-sure = Ttxclkesc * value 375 */ 376 ta_sure = DIV_ROUND_UP(gotp.tasure, t_txclkesc); 377 /* 378 * The value of counter for HS Tta-wait 379 * Tta-wait for turnaround 380 * Tta-wait = Ttxclkesc * value 381 */ 382 ta_wait = DIV_ROUND_UP(gotp.taget, t_txclkesc); 383 384 for (i = 0; i < ARRAY_SIZE(timings); i++) 385 if (inno->pll.rate <= timings[i].rate) 386 break; 387 388 if (i == ARRAY_SIZE(timings)) 389 --i; 390 391 hs_prepare = timings[i].hs_prepare; 392 hs_trail = timings[i].hs_trail; 393 clk_lane_hs_zero = timings[i].clk_lane_hs_zero; 394 data_lane_hs_zero = timings[i].data_lane_hs_zero; 395 wakeup = 0x3ff; 396 397 for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) { 398 if (i == REGISTER_PART_CLOCK_LANE) 399 hs_zero = clk_lane_hs_zero; 400 else 401 hs_zero = data_lane_hs_zero; 402 403 phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK, 404 T_LPX_CNT(lpx)); 405 phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK, 406 T_HS_PREPARE_CNT(hs_prepare)); 407 phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_MASK, 408 T_HS_ZERO_CNT(hs_zero)); 409 phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK, 410 T_HS_TRAIL_CNT(hs_trail)); 411 phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_MASK, 412 T_HS_EXIT_CNT(hs_exit)); 413 phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_MASK, 414 T_CLK_POST_CNT(clk_post)); 415 phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK, 416 T_CLK_PRE_CNT(clk_pre)); 417 phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK, 418 T_WAKEUP_CNT_HI(wakeup >> 8)); 419 phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK, 420 T_WAKEUP_CNT_LO(wakeup)); 421 phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK, 422 T_TA_GO_CNT(ta_go)); 423 phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK, 424 T_TA_SURE_CNT(ta_sure)); 425 phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK, 426 T_TA_WAIT_CNT(ta_wait)); 427 } 428 429 /* Enable all lanes on analog part */ 430 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 431 LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 | 432 LANE_EN_1 | LANE_EN_0); 433 } 434 435 static void inno_video_phy_lvds_mode_enable(struct inno_video_phy *inno) 436 { 437 u8 prediv = 2; 438 u16 fbdiv = 28; 439 u32 val; 440 int ret; 441 442 /* Sample clock reverse direction */ 443 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08, 444 SAMPLE_CLOCK_DIRECTION_MASK | LOWFRE_EN_MASK, 445 SAMPLE_CLOCK_DIRECTION_REVERSE | 446 PLL_OUTPUT_FREQUENCY_DIV_BY_1); 447 /* Select LVDS mode */ 448 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, 449 MODE_ENABLE_MASK, LVDS_MODE_ENABLE); 450 /* Configure PLL */ 451 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 452 REG_PREDIV_MASK, REG_PREDIV(prediv)); 453 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 454 REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv >> 8)); 455 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, 456 REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv)); 457 phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc); 458 /* Enable PLL and Bandgap */ 459 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, 460 LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK, 461 LVDS_PLL_POWER_ON | LVDS_BANDGAP_POWER_ON); 462 463 ret = readl_poll_timeout(inno->host.start + DSI_PHY_STATUS, 464 val, val & PHY_LOCK, 10000); 465 if (ret) 466 dev_err(phy->dev, "PLL is not lock\n"); 467 468 /* Select PLL mode */ 469 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1e, 470 PLL_MODE_SEL_MASK, PLL_MODE_SEL_LVDS_MODE); 471 472 /* Reset LVDS digital logic */ 473 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, 474 LVDS_DIGITAL_INTERNAL_RESET_MASK, 475 LVDS_DIGITAL_INTERNAL_RESET_ENABLE); 476 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, 477 LVDS_DIGITAL_INTERNAL_RESET_MASK, 478 LVDS_DIGITAL_INTERNAL_RESET_DISABLE); 479 /* Enable LVDS digital logic */ 480 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, 481 LVDS_DIGITAL_INTERNAL_ENABLE_MASK, 482 LVDS_DIGITAL_INTERNAL_ENABLE); 483 /* Enable LVDS analog driver */ 484 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, 485 LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN | 486 LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN | 487 LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN); 488 } 489 490 static void inno_video_phy_ttl_mode_enable(struct inno_video_phy *inno) 491 { 492 /* Select TTL mode */ 493 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, 494 MODE_ENABLE_MASK, TTL_MODE_ENABLE); 495 /* Reset digital logic */ 496 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, 497 LVDS_DIGITAL_INTERNAL_RESET_MASK, 498 LVDS_DIGITAL_INTERNAL_RESET_ENABLE); 499 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, 500 LVDS_DIGITAL_INTERNAL_RESET_MASK, 501 LVDS_DIGITAL_INTERNAL_RESET_DISABLE); 502 /* Enable digital logic */ 503 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, 504 LVDS_DIGITAL_INTERNAL_ENABLE_MASK, 505 LVDS_DIGITAL_INTERNAL_ENABLE); 506 /* Enable analog driver */ 507 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, 508 LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN | 509 LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN | 510 LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN); 511 /* Enable for clk lane in TTL mode */ 512 host_update_bits(inno, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK); 513 } 514 515 static int inno_video_phy_power_on(struct rockchip_phy *phy) 516 { 517 struct inno_video_phy *inno = dev_get_priv(phy->dev); 518 519 /* Bandgap power on */ 520 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 521 BANDGAP_POWER_MASK, BANDGAP_POWER_ON); 522 /* Enable power work */ 523 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 524 POWER_WORK_MASK, POWER_WORK_ENABLE); 525 526 switch (inno->mode) { 527 case PHY_MODE_VIDEO_MIPI: 528 inno_video_phy_mipi_mode_enable(inno); 529 break; 530 case PHY_MODE_VIDEO_LVDS: 531 inno_video_phy_lvds_mode_enable(inno); 532 break; 533 case PHY_MODE_VIDEO_TTL: 534 inno_video_phy_ttl_mode_enable(inno); 535 break; 536 default: 537 return -EINVAL; 538 } 539 540 return 0; 541 } 542 543 static int inno_video_phy_power_off(struct rockchip_phy *phy) 544 { 545 struct inno_video_phy *inno = dev_get_priv(phy->dev); 546 547 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0); 548 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 549 REG_LDOPD_MASK | REG_PLLPD_MASK, 550 REG_LDOPD_POWER_DOWN | REG_PLLPD_POWER_DOWN); 551 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 552 POWER_WORK_MASK, POWER_WORK_DISABLE); 553 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 554 BANDGAP_POWER_MASK, BANDGAP_POWER_DOWN); 555 556 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0); 557 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, 558 LVDS_DIGITAL_INTERNAL_ENABLE_MASK, 559 LVDS_DIGITAL_INTERNAL_DISABLE); 560 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, 561 LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK, 562 LVDS_PLL_POWER_OFF | LVDS_BANDGAP_POWER_DOWN); 563 564 return 0; 565 } 566 567 static unsigned long inno_video_phy_pll_round_rate(unsigned long prate, 568 unsigned long rate, 569 u8 *prediv, u16 *fbdiv) 570 { 571 unsigned long best_freq = 0; 572 unsigned long fref, fout; 573 u8 min_prediv, max_prediv; 574 u8 _prediv, best_prediv = 1; 575 u16 _fbdiv, best_fbdiv = 1; 576 u32 min_delta = 0xffffffff; 577 578 /* 579 * The PLL output frequency can be calculated using a simple formula: 580 * PLL_Output_Frequency = (FREF / PREDIV * FBDIV) / 2 581 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2 582 */ 583 fref = prate / 2; 584 if (rate > 1000000000UL) 585 fout = 1000000000UL; 586 else 587 fout = rate; 588 589 /* 5Mhz < Fref / prediv < 40MHz */ 590 min_prediv = DIV_ROUND_UP(fref, 40000000); 591 max_prediv = fref / 5000000; 592 593 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 594 u64 tmp; 595 u32 delta; 596 597 tmp = (u64)fout * _prediv; 598 do_div(tmp, fref); 599 _fbdiv = tmp; 600 601 /* 602 * The all possible settings of feedback divider are 603 * 12, 13, 14, 16, ~ 511 604 */ 605 if (_fbdiv == 15) 606 continue; 607 608 if (_fbdiv < 12 || _fbdiv > 511) 609 continue; 610 611 tmp = (u64)_fbdiv * fref; 612 do_div(tmp, _prediv); 613 614 delta = abs(fout - tmp); 615 if (!delta) { 616 best_prediv = _prediv; 617 best_fbdiv = _fbdiv; 618 best_freq = tmp; 619 break; 620 } else if (delta < min_delta) { 621 best_prediv = _prediv; 622 best_fbdiv = _fbdiv; 623 best_freq = tmp; 624 min_delta = delta; 625 } 626 } 627 628 if (best_freq) { 629 *prediv = best_prediv; 630 *fbdiv = best_fbdiv; 631 } 632 633 return best_freq; 634 } 635 636 static unsigned long inno_video_phy_set_pll(struct rockchip_phy *phy, 637 unsigned long rate) 638 { 639 struct inno_video_phy *inno = dev_get_priv(phy->dev); 640 unsigned long fin, fout; 641 u16 fbdiv = 1; 642 u8 prediv = 1; 643 644 fin = 24000000; 645 fout = inno_video_phy_pll_round_rate(fin, rate, &prediv, &fbdiv); 646 647 dev_dbg(phy->dev, "fin=%lu, fout=%lu, prediv=%u, fbdiv=%u\n", 648 fin, fout, prediv, fbdiv); 649 650 inno->pll.prediv = prediv; 651 inno->pll.fbdiv = fbdiv; 652 inno->pll.rate = fout; 653 654 return fout; 655 } 656 657 static int inno_video_phy_set_mode(struct rockchip_phy *phy, 658 enum phy_mode mode) 659 { 660 struct inno_video_phy *inno = dev_get_priv(phy->dev); 661 662 switch (mode) { 663 case PHY_MODE_VIDEO_MIPI: 664 case PHY_MODE_VIDEO_LVDS: 665 case PHY_MODE_VIDEO_TTL: 666 inno->mode = mode; 667 break; 668 default: 669 return -EINVAL; 670 } 671 672 return 0; 673 } 674 675 static const struct rockchip_phy_funcs inno_video_phy_funcs = { 676 .power_on = inno_video_phy_power_on, 677 .power_off = inno_video_phy_power_off, 678 .set_pll = inno_video_phy_set_pll, 679 .set_mode = inno_video_phy_set_mode, 680 }; 681 682 static int inno_video_phy_probe(struct udevice *dev) 683 { 684 struct inno_video_phy *inno = dev_get_priv(dev); 685 struct rockchip_phy *phy = 686 (struct rockchip_phy *)dev_get_driver_data(dev); 687 int ret; 688 689 ret = dev_read_resource(dev, 0, &inno->phy); 690 if (ret < 0) { 691 dev_err(dev, "resource \"phy\" not found\n"); 692 return ret; 693 } 694 695 ret = dev_read_resource(dev, 1, &inno->host); 696 if (ret < 0) { 697 dev_err(dev, "resource \"host\" not found\n"); 698 return ret; 699 } 700 701 phy->dev = dev; 702 703 return 0; 704 } 705 706 static struct rockchip_phy inno_video_phy_driver_data = { 707 .funcs = &inno_video_phy_funcs, 708 }; 709 710 static const struct udevice_id inno_video_phy_ids[] = { 711 { 712 .compatible = "rockchip,px30-video-phy", 713 .data = (ulong)&inno_video_phy_driver_data, 714 }, 715 { 716 .compatible = "rockchip,rk3128-video-phy", 717 .data = (ulong)&inno_video_phy_driver_data, 718 }, 719 { 720 .compatible = "rockchip,rk3368-video-phy", 721 .data = (ulong)&inno_video_phy_driver_data, 722 }, 723 { 724 .compatible = "rockchip,rk3568-video-phy", 725 .data = (ulong)&inno_video_phy_driver_data, 726 }, 727 {} 728 }; 729 730 U_BOOT_DRIVER(inno_video_combo_phy) = { 731 .name = "inno_video_combo_phy", 732 .id = UCLASS_PHY, 733 .of_match = inno_video_phy_ids, 734 .probe = inno_video_phy_probe, 735 .priv_auto_alloc_size = sizeof(struct inno_video_phy), 736 }; 737