1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <linux/list.h> 14 #include <div64.h> 15 #include <dm/device.h> 16 #include <dm/read.h> 17 #include <dm/uclass.h> 18 #include <dm/uclass-id.h> 19 20 #include "rockchip_phy.h" 21 22 #define NSEC_PER_USEC 1000L 23 #define USEC_PER_SEC 1000000L 24 #define NSEC_PER_SEC 1000000000L 25 26 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) 27 28 /* Innosilicon MIPI D-PHY registers */ 29 #define INNO_PHY_LANE_CTRL 0x0000 30 #define MIPI_BGPD BIT(7) 31 #define CLK_LANE_EN_MASK BIT(6) 32 #define DATA_LANE_3_EN_MASK BIT(5) 33 #define DATA_LANE_2_EN_MASK BIT(4) 34 #define DATA_LANE_1_EN_MASK BIT(3) 35 #define DATA_LANE_0_EN_MASK BIT(2) 36 #define CLK_LANE_EN BIT(6) 37 #define DATA_LANE_3_EN BIT(5) 38 #define DATA_LANE_2_EN BIT(4) 39 #define DATA_LANE_1_EN BIT(3) 40 #define DATA_LANE_0_EN BIT(2) 41 #define PWROK_BP BIT(1) 42 #define PWROK BIT(0) 43 #define INNO_PHY_POWER_CTRL 0x0004 44 #define ANALOG_RESET_MASK BIT(2) 45 #define ANALOG_RESET BIT(2) 46 #define ANALOG_NORMAL 0 47 #define LDO_POWER_MASK BIT(1) 48 #define LDO_POWER_DOWN BIT(1) 49 #define LDO_POWER_ON 0 50 #define PLL_POWER_MASK BIT(0) 51 #define PLL_POWER_DOWN BIT(0) 52 #define PLL_POWER_ON 0 53 #define INNO_PHY_PLL_CTRL_0 0x000c 54 #define FBDIV_HI_MASK BIT(5) 55 #define FBDIV_HI(x) UPDATE(x, 5, 5) 56 #define PREDIV_MASK GENMASK(4, 0) 57 #define PREDIV(x) UPDATE(x, 4, 0) 58 #define INNO_PHY_PLL_CTRL_1 0x0010 59 #define FBDIV_LO_MASK GENMASK(7, 0) 60 #define FBDIV_LO(x) UPDATE(x, 7, 0) 61 #define ANALOG_REG_08 0x0020 62 #define PRE_EMPHASIS_ENABLE_MASK BIT(7) 63 #define PRE_EMPHASIS_ENABLE BIT(7) 64 #define PRE_EMPHASIS_DISABLE 0 65 #define PLL_POST_DIV_ENABLE_MASK BIT(5) 66 #define PLL_POST_DIV_ENABLE BIT(5) 67 #define PLL_POST_DIV_DISABLE 0 68 #define DATA_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0) 69 #define DATA_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0) 70 #define ANALOG_REG_0B 0x002c 71 #define CLOCK_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0) 72 #define CLOCK_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0) 73 #define VOD_MIN_RANGE 0x1 74 #define VOD_MID_RANGE 0x3 75 #define VOD_BIG_RANGE 0x7 76 #define VOD_MAX_RANGE 0xf 77 #define INNO_PHY_DIG_CTRL 0x0080 78 #define DIGITAL_RESET_MASK BIT(0) 79 #define DIGITAL_NORMAL BIT(0) 80 #define DIGITAL_RESET 0 81 #define INNO_PHY_LVDS_CTRL 0x03ac 82 #define LVDS_BGPD BIT(0) 83 84 #define INNO_CLOCK_LANE_REG_BASE 0x0100 85 #define INNO_DATA_LANE_0_REG_BASE 0x0180 86 #define INNO_DATA_LANE_1_REG_BASE 0x0200 87 #define INNO_DATA_LANE_2_REG_BASE 0x0280 88 #define INNO_DATA_LANE_3_REG_BASE 0x0300 89 90 #define T_LPX_OFFSET 0x0014 91 #define T_HS_PREPARE_OFFSET 0x0018 92 #define T_HS_ZERO_OFFSET 0x001c 93 #define T_HS_TRAIL_OFFSET 0x0020 94 #define T_HS_EXIT_OFFSET 0x0024 95 #define T_CLK_POST_OFFSET 0x0028 96 #define T_WAKUP_H_OFFSET 0x0030 97 #define T_WAKUP_L_OFFSET 0x0034 98 #define T_CLK_PRE_OFFSET 0x0038 99 #define T_TA_GO_OFFSET 0x0040 100 #define T_TA_SURE_OFFSET 0x0044 101 #define T_TA_WAIT_OFFSET 0x0048 102 103 #define T_LPX_MASK GENMASK(5, 0) 104 #define T_LPX(x) UPDATE(x, 5, 0) 105 #define T_HS_PREPARE_MASK GENMASK(6, 0) 106 #define T_HS_PREPARE(x) UPDATE(x, 6, 0) 107 #define T_HS_ZERO_MASK GENMASK(5, 0) 108 #define T_HS_ZERO(x) UPDATE(x, 5, 0) 109 #define T_HS_TRAIL_MASK GENMASK(6, 0) 110 #define T_HS_TRAIL(x) UPDATE(x, 6, 0) 111 #define T_HS_EXIT_MASK GENMASK(4, 0) 112 #define T_HS_EXIT(x) UPDATE(x, 4, 0) 113 #define T_CLK_POST_MASK GENMASK(3, 0) 114 #define T_CLK_POST(x) UPDATE(x, 3, 0) 115 #define T_WAKUP_H_MASK GENMASK(1, 0) 116 #define T_WAKUP_H(x) UPDATE(x, 1, 0) 117 #define T_WAKUP_L_MASK GENMASK(7, 0) 118 #define T_WAKUP_L(x) UPDATE(x, 7, 0) 119 #define T_CLK_PRE_MASK GENMASK(3, 0) 120 #define T_CLK_PRE(x) UPDATE(x, 3, 0) 121 #define T_TA_GO_MASK GENMASK(5, 0) 122 #define T_TA_GO(x) UPDATE(x, 5, 0) 123 #define T_TA_SURE_MASK GENMASK(5, 0) 124 #define T_TA_SURE(x) UPDATE(x, 5, 0) 125 #define T_TA_WAIT_MASK GENMASK(5, 0) 126 #define T_TA_WAIT(x) UPDATE(x, 5, 0) 127 128 enum soc_type { 129 RV1108_MIPI_DPHY, 130 RK1808_MIPI_DPHY, 131 }; 132 133 enum lane_type { 134 CLOCK_LANE, 135 DATA_LANE_0, 136 DATA_LANE_1, 137 DATA_LANE_2, 138 DATA_LANE_3, 139 }; 140 141 struct mipi_dphy_timing { 142 unsigned int clkmiss; 143 unsigned int clkpost; 144 unsigned int clkpre; 145 unsigned int clkprepare; 146 unsigned int clksettle; 147 unsigned int clktermen; 148 unsigned int clktrail; 149 unsigned int clkzero; 150 unsigned int dtermen; 151 unsigned int eot; 152 unsigned int hsexit; 153 unsigned int hsprepare; 154 unsigned int hszero; 155 unsigned int hssettle; 156 unsigned int hsskip; 157 unsigned int hstrail; 158 unsigned int init; 159 unsigned int lpx; 160 unsigned int taget; 161 unsigned int tago; 162 unsigned int tasure; 163 unsigned int wakeup; 164 }; 165 166 struct inno_mipi_dphy_timing { 167 u8 lpx; 168 u8 hs_prepare; 169 u8 hs_zero; 170 u8 hs_trail; 171 u8 hs_exit; 172 u8 clk_post; 173 u8 wakup_h; 174 u8 wakup_l; 175 u8 clk_pre; 176 u8 ta_go; 177 u8 ta_sure; 178 u8 ta_wait; 179 }; 180 181 struct inno_mipi_dphy { 182 struct udevice *dev; 183 void __iomem *regs; 184 unsigned int lane_mbps; 185 int lanes; 186 }; 187 188 static const u32 lane_reg_offset[] = { 189 [CLOCK_LANE] = INNO_CLOCK_LANE_REG_BASE, 190 [DATA_LANE_0] = INNO_DATA_LANE_0_REG_BASE, 191 [DATA_LANE_1] = INNO_DATA_LANE_1_REG_BASE, 192 [DATA_LANE_2] = INNO_DATA_LANE_2_REG_BASE, 193 [DATA_LANE_3] = INNO_DATA_LANE_3_REG_BASE, 194 }; 195 196 #define FIXED_PARAM(_freq, _prepare, _clk_zero, _data_zero, _trail) \ 197 { \ 198 .max_freq = _freq, \ 199 .hs_prepare = _prepare, \ 200 .clk_lane = { \ 201 .hs_zero = _clk_zero, \ 202 }, \ 203 .data_lane = { \ 204 .hs_zero = _data_zero, \ 205 }, \ 206 .hs_trail = _trail, \ 207 } 208 209 struct fixed_param { 210 unsigned int max_freq; 211 u8 hs_prepare; 212 struct { 213 u8 hs_zero; 214 } clk_lane; 215 struct { 216 u8 hs_zero; 217 } data_lane; 218 u8 hs_trail; 219 }; 220 221 static const struct fixed_param fixed_param_table[] = { 222 FIXED_PARAM(110, 0x20, 0x16, 0x02, 0x22), 223 FIXED_PARAM(150, 0x06, 0x16, 0x03, 0x45), 224 FIXED_PARAM(200, 0x18, 0x17, 0x04, 0x0b), 225 FIXED_PARAM(250, 0x05, 0x17, 0x05, 0x16), 226 FIXED_PARAM(300, 0x51, 0x18, 0x06, 0x2c), 227 FIXED_PARAM(400, 0x64, 0x19, 0x07, 0x33), 228 FIXED_PARAM(500, 0x20, 0x1b, 0x07, 0x4e), 229 FIXED_PARAM(600, 0x6a, 0x1d, 0x08, 0x3a), 230 FIXED_PARAM(700, 0x3e, 0x1e, 0x08, 0x6a), 231 FIXED_PARAM(800, 0x21, 0x1f, 0x09, 0x29), 232 FIXED_PARAM(1000, 0x09, 0x20, 0x09, 0x27) 233 }; 234 235 static const struct fixed_param rk1808_fixed_param_table[] = { 236 FIXED_PARAM(110, 0x7f, 0x16, 0x02, 0x02), 237 FIXED_PARAM(150, 0x7f, 0x16, 0x03, 0x02), 238 FIXED_PARAM(200, 0x7f, 0x17, 0x04, 0x02), 239 FIXED_PARAM(250, 0x7f, 0x17, 0x05, 0x04), 240 FIXED_PARAM(300, 0x7f, 0x18, 0x06, 0x04), 241 FIXED_PARAM(400, 0x7e, 0x19, 0x07, 0x04), 242 FIXED_PARAM(500, 0x7c, 0x1b, 0x07, 0x08), 243 FIXED_PARAM(600, 0x70, 0x1d, 0x08, 0x10), 244 FIXED_PARAM(700, 0x40, 0x1e, 0x08, 0x30), 245 FIXED_PARAM(800, 0x02, 0x1f, 0x09, 0x30), 246 FIXED_PARAM(1000, 0x08, 0x20, 0x09, 0x30), 247 FIXED_PARAM(1400, 0x03, 0x32, 0x14, 0x0f), 248 FIXED_PARAM(1600, 0x42, 0x36, 0x0e, 0x0f), 249 FIXED_PARAM(1800, 0x47, 0x7a, 0x0e, 0x0f), 250 FIXED_PARAM(2000, 0x64, 0x7a, 0x0e, 0x0b), 251 }; 252 253 static inline void inno_write(struct inno_mipi_dphy *inno, u32 reg, u32 val) 254 { 255 writel(val, inno->regs + reg); 256 } 257 258 static inline u32 inno_read(struct inno_mipi_dphy *inno, u32 reg) 259 { 260 return readl(inno->regs + reg); 261 } 262 263 static inline void inno_update_bits(struct inno_mipi_dphy *inno, u32 reg, 264 u32 mask, u32 val) 265 { 266 u32 tmp, orig; 267 268 orig = inno_read(inno, reg); 269 tmp = orig & ~mask; 270 tmp |= val & mask; 271 inno_write(inno, reg, tmp); 272 } 273 274 static void mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, 275 unsigned long period) 276 { 277 /* Global Operation Timing Parameters */ 278 timing->clkmiss = 0; 279 timing->clkpost = 70 + 52 * period; 280 timing->clkpre = 8 * period; 281 timing->clkprepare = 65; 282 timing->clksettle = 95; 283 timing->clktermen = 0; 284 timing->clktrail = 80; 285 timing->clkzero = 260; 286 timing->dtermen = 0; 287 timing->eot = 0; 288 timing->hsexit = 120; 289 timing->hsprepare = 65 + 4 * period; 290 timing->hszero = 145 + 6 * period; 291 timing->hssettle = 85 + 6 * period; 292 timing->hsskip = 40; 293 timing->hstrail = max(8 * period, 60 + 4 * period); 294 timing->init = 100000; 295 timing->lpx = 60; 296 timing->taget = 5 * timing->lpx; 297 timing->tago = 4 * timing->lpx; 298 timing->tasure = 2 * timing->lpx; 299 timing->wakeup = 1000000; 300 } 301 302 static void inno_mipi_dphy_timing_update(struct inno_mipi_dphy *inno, 303 enum lane_type lane_type, 304 struct inno_mipi_dphy_timing *t) 305 { 306 u32 base = lane_reg_offset[lane_type]; 307 u32 m, v; 308 309 m = T_HS_PREPARE_MASK; 310 v = T_HS_PREPARE(t->hs_prepare); 311 inno_update_bits(inno, base + T_HS_PREPARE_OFFSET, m, v); 312 313 m = T_HS_ZERO_MASK; 314 v = T_HS_ZERO(t->hs_zero); 315 inno_update_bits(inno, base + T_HS_ZERO_OFFSET, m, v); 316 317 m = T_HS_TRAIL_MASK; 318 v = T_HS_TRAIL(t->hs_trail); 319 inno_update_bits(inno, base + T_HS_TRAIL_OFFSET, m, v); 320 321 m = T_HS_EXIT_MASK; 322 v = T_HS_EXIT(t->hs_exit); 323 inno_update_bits(inno, base + T_HS_EXIT_OFFSET, m, v); 324 325 if (lane_type == CLOCK_LANE) { 326 m = T_CLK_POST_MASK; 327 v = T_CLK_POST(t->clk_post); 328 inno_update_bits(inno, base + T_CLK_POST_OFFSET, m, v); 329 330 m = T_CLK_PRE_MASK; 331 v = T_CLK_PRE(t->clk_pre); 332 inno_update_bits(inno, base + T_CLK_PRE_OFFSET, m, v); 333 } 334 335 m = T_WAKUP_H_MASK; 336 v = T_WAKUP_H(t->wakup_h); 337 inno_update_bits(inno, base + T_WAKUP_H_OFFSET, m, v); 338 339 m = T_WAKUP_L_MASK; 340 v = T_WAKUP_L(t->wakup_l); 341 inno_update_bits(inno, base + T_WAKUP_L_OFFSET, m, v); 342 343 m = T_LPX_MASK; 344 v = T_LPX(t->lpx); 345 inno_update_bits(inno, base + T_LPX_OFFSET, m, v); 346 347 m = T_TA_GO_MASK; 348 v = T_TA_GO(t->ta_go); 349 inno_update_bits(inno, base + T_TA_GO_OFFSET, m, v); 350 351 m = T_TA_SURE_MASK; 352 v = T_TA_SURE(t->ta_sure); 353 inno_update_bits(inno, base + T_TA_SURE_OFFSET, m, v); 354 355 m = T_TA_WAIT_MASK; 356 v = T_TA_WAIT(t->ta_wait); 357 inno_update_bits(inno, base + T_TA_WAIT_OFFSET, m, v); 358 } 359 360 static void inno_mipi_dphy_get_fixed_param(struct inno_mipi_dphy_timing *t, 361 unsigned int freq, 362 enum soc_type soc_type, 363 enum lane_type lane_type) 364 { 365 const struct fixed_param *param, *param_table; 366 int i, param_num; 367 368 if (soc_type == RK1808_MIPI_DPHY) { 369 param_table = rk1808_fixed_param_table; 370 param_num = ARRAY_SIZE(rk1808_fixed_param_table); 371 } else { 372 param_table = fixed_param_table; 373 param_num = ARRAY_SIZE(fixed_param_table); 374 } 375 376 for (i = 0; i < param_num; i++) 377 if (freq <= param_table[i].max_freq) 378 break; 379 380 if (i == param_num) 381 --i; 382 383 param = ¶m_table[i]; 384 385 if (lane_type == CLOCK_LANE) 386 t->hs_zero = param->clk_lane.hs_zero; 387 else 388 t->hs_zero = param->data_lane.hs_zero; 389 390 t->hs_prepare = param->hs_prepare; 391 t->hs_trail = param->hs_trail; 392 } 393 394 static void inno_mipi_dphy_lane_timing_init(struct inno_mipi_dphy *inno, 395 enum lane_type lane_type) 396 { 397 struct rockchip_phy *phy = 398 (struct rockchip_phy *)dev_get_driver_data(inno->dev); 399 struct mipi_dphy_timing timing; 400 struct inno_mipi_dphy_timing data; 401 unsigned long txbyteclk, txclkesc, UI; 402 unsigned int esc_clk_div; 403 404 memset(&timing, 0, sizeof(timing)); 405 memset(&data, 0, sizeof(data)); 406 407 txbyteclk = inno->lane_mbps * USEC_PER_SEC / 8; 408 esc_clk_div = DIV_ROUND_UP(txbyteclk, 20000000); 409 txclkesc = txbyteclk / esc_clk_div; 410 UI = DIV_ROUND_CLOSEST(NSEC_PER_USEC, inno->lane_mbps); 411 412 debug("txbyteclk=%lu, txclkesc=%lu, esc_clk_div=%u, UI=%lu\n", 413 txbyteclk, txclkesc, esc_clk_div, UI); 414 415 mipi_dphy_timing_get_default(&timing, UI); 416 inno_mipi_dphy_get_fixed_param(&data, inno->lane_mbps, 417 phy->soc_type, lane_type); 418 419 /* 420 * Ttxbyteclk * val >= Ths-exit 421 * Ttxbyteclk * val >= Tclk-post 422 * Ttxbyteclk * val >= Tclk-pre 423 * Ttxbyteclk * (2 + val) >= Tlpx 424 */ 425 data.hs_exit = DIV_ROUND_UP(timing.hsexit * txbyteclk, NSEC_PER_SEC); 426 data.clk_post = DIV_ROUND_UP(timing.clkpost * txbyteclk, NSEC_PER_SEC); 427 data.clk_pre = DIV_ROUND_UP(timing.clkpre * txbyteclk, NSEC_PER_SEC); 428 data.wakup_h = 0x3; 429 data.wakup_l = 0xff; 430 data.lpx = DIV_ROUND_UP(txbyteclk * timing.lpx, NSEC_PER_SEC); 431 if (data.lpx > 2) 432 data.lpx -= 2; 433 434 /* 435 * Ttxclkesc * val >= Tta-go 436 * Ttxclkesc * val >= Tta-sure 437 * Ttxclkesc * val >= Tta-wait 438 */ 439 data.ta_go = DIV_ROUND_UP(timing.tago * txclkesc, NSEC_PER_SEC); 440 data.ta_sure = DIV_ROUND_UP(timing.tasure * txclkesc, NSEC_PER_SEC); 441 data.ta_wait = DIV_ROUND_UP(timing.taget * txclkesc, NSEC_PER_SEC); 442 443 inno_mipi_dphy_timing_update(inno, lane_type, &data); 444 445 #define TIMING_NS(x, freq) (((x) * (DIV_ROUND_CLOSEST(NSEC_PER_SEC, freq)))) 446 debug("hs-exit=%lu, clk-post=%lu, clk-pre=%lu, lpx=%lu\n", 447 TIMING_NS(data.hs_exit, txbyteclk), 448 TIMING_NS(data.clk_post, txbyteclk), 449 TIMING_NS(data.clk_pre, txbyteclk), 450 TIMING_NS(data.lpx + 2, txbyteclk)); 451 debug("ta-go=%lu, ta-sure=%lu, ta-wait=%lu\n", 452 TIMING_NS(data.ta_go, txclkesc), 453 TIMING_NS(data.ta_sure, txclkesc), 454 TIMING_NS(data.ta_wait, txclkesc)); 455 } 456 457 static unsigned long inno_mipi_dphy_pll_round_rate(unsigned long fin, 458 unsigned long fout, 459 u8 *prediv, u16 *fbdiv) 460 { 461 unsigned long best_freq = 0; 462 u8 min_prediv, max_prediv; 463 u8 _prediv, best_prediv = 0; 464 u16 _fbdiv, best_fbdiv = 0; 465 u32 min_delta = 0xffffffff; 466 467 fout *= 2; 468 469 min_prediv = DIV_ROUND_UP(fin, 40000000); 470 max_prediv = fin / 5000000; 471 472 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 473 u64 tmp; 474 u32 delta; 475 tmp = (u64)fout * _prediv; 476 do_div(tmp, fin); 477 _fbdiv = tmp; 478 if ((_fbdiv == 15) || (_fbdiv < 12) || (_fbdiv > 511)) 479 continue; 480 tmp = (u64)_fbdiv * fin; 481 do_div(tmp, _prediv); 482 483 delta = abs(fout - tmp); 484 if (delta < min_delta) { 485 best_prediv = _prediv; 486 best_fbdiv = _fbdiv; 487 min_delta = delta; 488 best_freq = tmp; 489 } 490 } 491 492 if (best_freq) { 493 *prediv = best_prediv; 494 *fbdiv = best_fbdiv; 495 } 496 497 return best_freq / 2; 498 } 499 500 static inline void inno_mipi_dphy_reset(struct inno_mipi_dphy *inno) 501 { 502 /* Reset analog */ 503 inno_update_bits(inno, INNO_PHY_POWER_CTRL, 504 ANALOG_RESET_MASK, ANALOG_RESET); 505 udelay(1); 506 inno_update_bits(inno, INNO_PHY_POWER_CTRL, 507 ANALOG_RESET_MASK, ANALOG_NORMAL); 508 /* Reset digital */ 509 inno_update_bits(inno, INNO_PHY_DIG_CTRL, 510 DIGITAL_RESET_MASK, DIGITAL_RESET); 511 udelay(1); 512 inno_update_bits(inno, INNO_PHY_DIG_CTRL, 513 DIGITAL_RESET_MASK, DIGITAL_NORMAL); 514 } 515 516 static void inno_mipi_dphy_timing_init(struct inno_mipi_dphy *inno) 517 { 518 switch (inno->lanes) { 519 case 4: 520 inno_mipi_dphy_lane_timing_init(inno, DATA_LANE_3); 521 /* Fall through */ 522 case 3: 523 inno_mipi_dphy_lane_timing_init(inno, DATA_LANE_2); 524 /* Fall through */ 525 case 2: 526 inno_mipi_dphy_lane_timing_init(inno, DATA_LANE_1); 527 /* Fall through */ 528 case 1: 529 default: 530 inno_mipi_dphy_lane_timing_init(inno, DATA_LANE_0); 531 inno_mipi_dphy_lane_timing_init(inno, CLOCK_LANE); 532 break; 533 } 534 } 535 536 static inline void inno_mipi_dphy_lane_enable(struct inno_mipi_dphy *inno) 537 { 538 u32 m = 0, v = 0; 539 540 switch (inno->lanes) { 541 case 4: 542 m |= DATA_LANE_3_EN_MASK; 543 v |= DATA_LANE_3_EN; 544 /* Fall through */ 545 case 3: 546 m |= DATA_LANE_2_EN_MASK; 547 v |= DATA_LANE_2_EN; 548 /* Fall through */ 549 case 2: 550 m |= DATA_LANE_1_EN_MASK; 551 v |= DATA_LANE_1_EN; 552 /* Fall through */ 553 default: 554 case 1: 555 m |= DATA_LANE_0_EN_MASK | CLK_LANE_EN_MASK; 556 v |= DATA_LANE_0_EN | CLK_LANE_EN; 557 break; 558 } 559 560 inno_update_bits(inno, INNO_PHY_LANE_CTRL, m, v); 561 } 562 563 static inline void inno_mipi_dphy_pll_ldo_disable(struct inno_mipi_dphy *inno) 564 { 565 inno_update_bits(inno, INNO_PHY_POWER_CTRL, 566 PLL_POWER_MASK | LDO_POWER_MASK, 567 PLL_POWER_DOWN | LDO_POWER_DOWN); 568 } 569 570 static inline void inno_mipi_dphy_pll_ldo_enable(struct inno_mipi_dphy *inno) 571 { 572 inno_update_bits(inno, INNO_PHY_POWER_CTRL, 573 PLL_POWER_MASK | LDO_POWER_MASK, 574 PLL_POWER_ON | LDO_POWER_ON); 575 } 576 577 static inline void inno_mipi_dphy_da_pwrok_enable(struct inno_mipi_dphy *inno) 578 { 579 inno_update_bits(inno, INNO_PHY_LANE_CTRL, PWROK_BP | PWROK, PWROK); 580 } 581 582 static inline void inno_mipi_dphy_da_pwrok_disable(struct inno_mipi_dphy *inno) 583 { 584 inno_update_bits(inno, INNO_PHY_LANE_CTRL, PWROK_BP | PWROK, PWROK_BP); 585 } 586 587 static inline void inno_mipi_dphy_bgpd_enable(struct inno_mipi_dphy *inno) 588 { 589 inno_update_bits(inno, INNO_PHY_LANE_CTRL, MIPI_BGPD, 0); 590 } 591 592 static inline void inno_mipi_dphy_bgpd_disable(struct inno_mipi_dphy *inno) 593 { 594 inno_update_bits(inno, INNO_PHY_LANE_CTRL, MIPI_BGPD, MIPI_BGPD); 595 inno_update_bits(inno, INNO_PHY_LVDS_CTRL, LVDS_BGPD, LVDS_BGPD); 596 } 597 598 static int inno_mipi_dphy_power_on(struct rockchip_phy *phy) 599 { 600 struct inno_mipi_dphy *inno = dev_get_priv(phy->dev); 601 602 inno_mipi_dphy_bgpd_enable(inno); 603 inno_mipi_dphy_da_pwrok_enable(inno); 604 inno_mipi_dphy_pll_ldo_enable(inno); 605 inno_mipi_dphy_lane_enable(inno); 606 inno_mipi_dphy_reset(inno); 607 inno_mipi_dphy_timing_init(inno); 608 udelay(1); 609 610 return 0; 611 } 612 613 static inline void inno_mipi_dphy_lane_disable(struct inno_mipi_dphy *inno) 614 { 615 inno_update_bits(inno, INNO_PHY_LANE_CTRL, 0x7c, 0x00); 616 } 617 618 static int inno_mipi_dphy_power_off(struct rockchip_phy *phy) 619 { 620 struct inno_mipi_dphy *inno = dev_get_priv(phy->dev); 621 622 inno_mipi_dphy_lane_disable(inno); 623 inno_mipi_dphy_pll_ldo_disable(inno); 624 inno_mipi_dphy_da_pwrok_disable(inno); 625 inno_mipi_dphy_bgpd_disable(inno); 626 627 return 0; 628 } 629 630 static unsigned long inno_mipi_dphy_set_pll(struct rockchip_phy *phy, 631 unsigned long rate) 632 { 633 struct inno_mipi_dphy *inno = dev_get_priv(phy->dev); 634 unsigned long fin, fout; 635 u16 fbdiv = 0; 636 u8 prediv = 0; 637 u32 m, v; 638 639 fin = 24000000; 640 fout = inno_mipi_dphy_pll_round_rate(fin, rate, &prediv, &fbdiv); 641 642 debug("%s: fin=%lu, fout=%lu, prediv=%u, fbdiv=%u\n", 643 __func__, fin, fout, prediv, fbdiv); 644 645 m = FBDIV_HI_MASK | PREDIV_MASK; 646 v = FBDIV_HI(fbdiv >> 8) | PREDIV(prediv); 647 inno_update_bits(inno, INNO_PHY_PLL_CTRL_0, m, v); 648 649 m = FBDIV_LO_MASK; 650 v = FBDIV_LO(fbdiv); 651 inno_update_bits(inno, INNO_PHY_PLL_CTRL_1, m, v); 652 653 if (phy->soc_type == RK1808_MIPI_DPHY) { 654 inno_update_bits(inno, ANALOG_REG_08, 655 PLL_POST_DIV_ENABLE_MASK, PLL_POST_DIV_ENABLE); 656 inno_update_bits(inno, ANALOG_REG_0B, 657 CLOCK_LANE_VOD_RANGE_SET_MASK, 658 CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE)); 659 } 660 661 inno->lane_mbps = fout / USEC_PER_SEC; 662 663 return fout; 664 } 665 666 static int inno_mipi_dphy_parse_dt(struct inno_mipi_dphy *inno) 667 { 668 struct udevice *dev = inno->dev; 669 670 inno->lanes = ofnode_read_u32_default(dev->node, "inno,lanes", 4); 671 672 return 0; 673 } 674 675 static int inno_mipi_dphy_init(struct rockchip_phy *phy) 676 { 677 struct inno_mipi_dphy *inno = dev_get_priv(phy->dev); 678 int ret; 679 680 ret = inno_mipi_dphy_parse_dt(inno); 681 if (ret) { 682 printf("%s: failed to parse DT\n", __func__); 683 return ret; 684 } 685 686 inno->regs = dev_read_addr_ptr(inno->dev); 687 688 return 0; 689 } 690 691 static const struct rockchip_phy_funcs inno_mipi_dphy_funcs = { 692 .init = inno_mipi_dphy_init, 693 .power_on = inno_mipi_dphy_power_on, 694 .power_off = inno_mipi_dphy_power_off, 695 .set_pll = inno_mipi_dphy_set_pll, 696 }; 697 698 static struct rockchip_phy inno_mipi_dphy_driver_data = { 699 .funcs = &inno_mipi_dphy_funcs, 700 .soc_type = RV1108_MIPI_DPHY, 701 }; 702 703 static struct rockchip_phy rk1808_inno_mipi_dphy_driver_data = { 704 .funcs = &inno_mipi_dphy_funcs, 705 .soc_type = RK1808_MIPI_DPHY, 706 }; 707 708 static const struct udevice_id inno_mipi_dphy_ids[] = { 709 { 710 .compatible = "rockchip,rv1108-mipi-dphy", 711 .data = (ulong)&inno_mipi_dphy_driver_data, 712 }, 713 { 714 .compatible = "rockchip,rk1808-mipi-dphy", 715 .data = (ulong)&rk1808_inno_mipi_dphy_driver_data, 716 }, 717 {} 718 }; 719 720 static int inno_mipi_dphy_probe(struct udevice *dev) 721 { 722 struct inno_mipi_dphy *inno = dev_get_priv(dev); 723 struct rockchip_phy *phy = 724 (struct rockchip_phy *)dev_get_driver_data(dev); 725 726 inno->dev = dev; 727 phy->dev = dev; 728 729 return 0; 730 } 731 732 U_BOOT_DRIVER(inno_mipi_dphy) = { 733 .name = "inno_mipi_dphy", 734 .id = UCLASS_PHY, 735 .of_match = inno_mipi_dphy_ids, 736 .probe = inno_mipi_dphy_probe, 737 .priv_auto_alloc_size = sizeof(struct inno_mipi_dphy), 738 }; 739