1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <drm/drm_mipi_dsi.h> 8 9 #include <config.h> 10 #include <common.h> 11 #include <errno.h> 12 #include <asm/unaligned.h> 13 #include <asm/io.h> 14 #include <asm/hardware.h> 15 #include <dm/device.h> 16 #include <dm/read.h> 17 #include <dm/of_access.h> 18 #include <syscon.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <linux/iopoll.h> 21 22 #include "rockchip_display.h" 23 #include "rockchip_crtc.h" 24 #include "rockchip_connector.h" 25 #include "rockchip_panel.h" 26 #include "rockchip_phy.h" 27 28 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) 29 30 #define DSI_VERSION 0x00 31 #define DSI_PWR_UP 0x04 32 #define RESET 0 33 #define POWERUP BIT(0) 34 35 #define DSI_CLKMGR_CFG 0x08 36 #define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) 37 #define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) 38 39 #define DSI_DPI_VCID 0x0c 40 #define DPI_VID(vid) (((vid) & 0x3) << 0) 41 42 #define DSI_DPI_COLOR_CODING 0x10 43 #define EN18_LOOSELY BIT(8) 44 #define DPI_COLOR_CODING_16BIT_1 0x0 45 #define DPI_COLOR_CODING_16BIT_2 0x1 46 #define DPI_COLOR_CODING_16BIT_3 0x2 47 #define DPI_COLOR_CODING_18BIT_1 0x3 48 #define DPI_COLOR_CODING_18BIT_2 0x4 49 #define DPI_COLOR_CODING_24BIT 0x5 50 51 #define DSI_DPI_CFG_POL 0x14 52 #define COLORM_ACTIVE_LOW BIT(4) 53 #define SHUTD_ACTIVE_LOW BIT(3) 54 #define HSYNC_ACTIVE_LOW BIT(2) 55 #define VSYNC_ACTIVE_LOW BIT(1) 56 #define DATAEN_ACTIVE_LOW BIT(0) 57 58 #define DSI_DPI_LP_CMD_TIM 0x18 59 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) 60 #define INVACT_LPCMD_TIME(p) ((p) & 0xff) 61 62 #define DSI_DBI_VCID 0x1c 63 #define DBI_VCID(x) UPDATE(x, 1, 0) 64 #define DSI_DBI_CFG 0x20 65 #define DSI_DBI_CMDSIZE 0x28 66 67 #define DSI_PCKHDL_CFG 0x2c 68 #define CRC_RX_EN BIT(4) 69 #define ECC_RX_EN BIT(3) 70 #define BTA_EN BIT(2) 71 #define EOTP_RX_EN BIT(1) 72 #define EOTP_TX_EN BIT(0) 73 #define DSI_MODE_CFG 0x34 74 #define CMD_VIDEO_MODE BIT(0) 75 #define COMMAND_MODE BIT(0) 76 #define VIDEO_MODE 0 77 #define DSI_VID_MODE_CFG 0x38 78 #define VPG_EN BIT(16) 79 #define LP_CMD_EN BIT(15) 80 #define FRAME_BTA_ACK BIT(14) 81 #define LP_HFP_EN BIT(13) 82 #define LP_HBP_EN BIT(12) 83 #define LP_VACT_EN BIT(11) 84 #define LP_VFP_EN BIT(10) 85 #define LP_VBP_EN BIT(9) 86 #define LP_VSA_EN BIT(8) 87 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0 88 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1 89 #define VID_MODE_TYPE_BURST 0x2 90 91 #define DSI_VID_PKT_SIZE 0x3c 92 #define VID_PKT_SIZE(p) (((p) & 0x3fff) << 0) 93 #define VID_PKT_MAX_SIZE 0x3fff 94 95 #define DSI_VID_NUM_CHUMKS 0x40 96 #define DSI_VID_NULL_PKT_SIZE 0x44 97 #define DSI_VID_HSA_TIME 0x48 98 #define DSI_VID_HBP_TIME 0x4c 99 #define DSI_VID_HLINE_TIME 0x50 100 #define DSI_VID_VSA_LINES 0x54 101 #define DSI_VID_VBP_LINES 0x58 102 #define DSI_VID_VFP_LINES 0x5c 103 #define DSI_VID_VACTIVE_LINES 0x60 104 #define DSI_EDPI_CMD_SIZE 0x64 105 #define DSI_CMD_MODE_CFG 0x68 106 #define MAX_RD_PKT_SIZE BIT(24) 107 #define DCS_LW_TX BIT(19) 108 #define DCS_SR_0P_TX BIT(18) 109 #define DCS_SW_1P_TX BIT(17) 110 #define DCS_SW_0P_TX BIT(16) 111 #define GEN_LW_TX BIT(14) 112 #define GEN_SR_2P_TX BIT(13) 113 #define GEN_SR_1P_TX BIT(12) 114 #define GEN_SR_0P_TX BIT(11) 115 #define GEN_SW_2P_TX BIT(10) 116 #define GEN_SW_1P_TX BIT(9) 117 #define GEN_SW_0P_TX BIT(8) 118 #define ACK_RQST_EN BIT(1) 119 #define TEAR_FX_EN BIT(0) 120 121 #define DSI_GEN_HDR 0x6c 122 #define GEN_HDATA(data) (((data) & 0xffff) << 8) 123 #define GEN_HDATA_MASK (0xffff << 8) 124 #define GEN_HTYPE(type) (((type) & 0xff) << 0) 125 #define GEN_HTYPE_MASK 0xff 126 127 #define DSI_GEN_PLD_DATA 0x70 128 129 #define DSI_CMD_PKT_STATUS 0x74 130 #define GEN_CMD_EMPTY BIT(0) 131 #define GEN_CMD_FULL BIT(1) 132 #define GEN_PLD_W_EMPTY BIT(2) 133 #define GEN_PLD_W_FULL BIT(3) 134 #define GEN_PLD_R_EMPTY BIT(4) 135 #define GEN_PLD_R_FULL BIT(5) 136 #define GEN_RD_CMD_BUSY BIT(6) 137 138 #define DSI_TO_CNT_CFG 0x78 139 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16) 140 #define LPRX_TO_CNT(p) ((p) & 0xffff) 141 142 #define DSI_BTA_TO_CNT 0x8c 143 #define DSI_LPCLK_CTRL 0x94 144 #define AUTO_CLKLANE_CTRL BIT(1) 145 #define PHY_TXREQUESTCLKHS BIT(0) 146 147 #define DSI_PHY_TMR_LPCLK_CFG 0x98 148 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16) 149 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff) 150 151 #define DSI_PHY_TMR_CFG 0x9c 152 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24) 153 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16) 154 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff) 155 156 #define DSI_PHY_RSTZ 0xa0 157 #define PHY_ENFORCEPLL BIT(3) 158 #define PHY_ENABLECLK BIT(2) 159 #define PHY_RSTZ BIT(1) 160 #define PHY_SHUTDOWNZ BIT(0) 161 162 #define DSI_PHY_IF_CFG 0xa4 163 #define N_LANES(n) ((((n) - 1) & 0x3) << 0) 164 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 165 166 #define DSI_PHY_STATUS 0xb0 167 #define PHY_STOPSTATE0LANE BIT(4) 168 #define PHY_STOPSTATECLKLANE BIT(2) 169 #define PHY_LOCK BIT(0) 170 #define PHY_STOPSTATELANE (PHY_STOPSTATE0LANE | \ 171 PHY_STOPSTATECLKLANE) 172 173 #define DSI_PHY_TST_CTRL0 0xb4 174 #define PHY_TESTCLK BIT(1) 175 #define PHY_TESTCLR BIT(0) 176 177 #define DSI_PHY_TST_CTRL1 0xb8 178 #define PHY_TESTEN BIT(16) 179 #define PHY_TESTDOUT_SHIFT 8 180 #define PHY_TESTDIN_MASK GENMASK(7, 0) 181 #define PHY_TESTDIN(x) UPDATE(x, 7, 0) 182 183 #define DSI_INT_ST0 0xbc 184 #define DSI_INT_ST1 0xc0 185 #define DSI_INT_MSK0 0xc4 186 #define DSI_INT_MSK1 0xc8 187 188 #define PHY_STATUS_TIMEOUT_US 10000 189 #define CMD_PKT_STATUS_TIMEOUT_US 20000 190 191 /* Test Code: 0x44 (HS RX Control of Lane 0) */ 192 #define HSFREQRANGE(x) UPDATE(x, 6, 1) 193 /* Test Code: 0x17 (PLL Input Divider Ratio) */ 194 #define INPUT_DIV(x) UPDATE(x, 6, 0) 195 /* Test Code: 0x18 (PLL Loop Divider Ratio) */ 196 #define FEEDBACK_DIV_LO(x) UPDATE(x, 4, 0) 197 #define FEEDBACK_DIV_HI(x) (BIT(7) | UPDATE(x, 3, 0)) 198 199 #define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 10) | ((lsb) << 5) | (msb)) 200 201 enum grf_reg_fields { 202 DPIUPDATECFG, 203 DPISHUTDN, 204 DPICOLORM, 205 VOPSEL, 206 TURNREQUEST, 207 TURNDISABLE, 208 SKEWCALHS, 209 FORCETXSTOPMODE, 210 FORCERXMODE, 211 ENABLE_N, 212 MASTERSLAVEZ, 213 ENABLECLK, 214 BASEDIR, 215 MAX_FIELDS, 216 }; 217 218 struct dw_mipi_dsi_plat_data { 219 const u32 *dsi0_grf_reg_fields; 220 const u32 *dsi1_grf_reg_fields; 221 unsigned long max_bit_rate_per_lane; 222 }; 223 224 struct mipi_dphy { 225 /* Non-SNPS PHY */ 226 struct rockchip_phy *phy; 227 228 u16 input_div; 229 u16 feedback_div; 230 }; 231 232 struct dw_mipi_dsi { 233 struct udevice *dev; 234 void *base; 235 void *grf; 236 int id; 237 struct dw_mipi_dsi *master; 238 struct dw_mipi_dsi *slave; 239 bool prepared; 240 241 unsigned int lane_mbps; /* per lane */ 242 u32 channel; 243 u32 lanes; 244 u32 format; 245 u32 mode_flags; 246 struct mipi_dphy dphy; 247 struct drm_display_mode mode; 248 bool data_swap; 249 250 const struct dw_mipi_dsi_plat_data *pdata; 251 }; 252 253 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) 254 { 255 writel(val, dsi->base + reg); 256 } 257 258 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) 259 { 260 return readl(dsi->base + reg); 261 } 262 263 static inline void dsi_update_bits(struct dw_mipi_dsi *dsi, 264 u32 reg, u32 mask, u32 val) 265 { 266 u32 orig, tmp; 267 268 orig = dsi_read(dsi, reg); 269 tmp = orig & ~mask; 270 tmp |= val & mask; 271 dsi_write(dsi, reg, tmp); 272 } 273 274 static void grf_field_write(struct dw_mipi_dsi *dsi, enum grf_reg_fields index, 275 unsigned int val) 276 { 277 const u32 field = dsi->id ? dsi->pdata->dsi1_grf_reg_fields[index] : 278 dsi->pdata->dsi0_grf_reg_fields[index]; 279 u16 reg; 280 u8 msb, lsb; 281 282 if (!field) 283 return; 284 285 reg = (field >> 10) & 0x3ffff; 286 lsb = (field >> 5) & 0x1f; 287 msb = (field >> 0) & 0x1f; 288 289 rk_clrsetreg(dsi->grf + reg, GENMASK(msb, lsb), val << lsb); 290 } 291 292 static inline void dpishutdn_assert(struct dw_mipi_dsi *dsi) 293 { 294 grf_field_write(dsi, DPISHUTDN, 1); 295 } 296 297 static inline void dpishutdn_deassert(struct dw_mipi_dsi *dsi) 298 { 299 grf_field_write(dsi, DPISHUTDN, 0); 300 } 301 302 static int genif_wait_w_pld_fifo_not_full(struct dw_mipi_dsi *dsi) 303 { 304 u32 sts; 305 int ret; 306 307 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 308 sts, !(sts & GEN_PLD_W_FULL), 309 CMD_PKT_STATUS_TIMEOUT_US); 310 if (ret < 0) { 311 printf("generic write payload fifo is full\n"); 312 return ret; 313 } 314 315 return 0; 316 } 317 318 static int genif_wait_cmd_fifo_not_full(struct dw_mipi_dsi *dsi) 319 { 320 u32 sts; 321 int ret; 322 323 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 324 sts, !(sts & GEN_CMD_FULL), 325 CMD_PKT_STATUS_TIMEOUT_US); 326 if (ret < 0) { 327 printf("generic write cmd fifo is full\n"); 328 return ret; 329 } 330 331 return 0; 332 } 333 334 static int genif_wait_write_fifo_empty(struct dw_mipi_dsi *dsi) 335 { 336 u32 sts; 337 u32 mask; 338 int ret; 339 340 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 341 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 342 sts, (sts & mask) == mask, 343 CMD_PKT_STATUS_TIMEOUT_US); 344 if (ret < 0) { 345 printf("generic write fifo is full\n"); 346 return ret; 347 } 348 349 return 0; 350 } 351 352 static inline void mipi_dphy_enableclk_assert(struct dw_mipi_dsi *dsi) 353 { 354 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK); 355 udelay(1); 356 } 357 358 static inline void mipi_dphy_enableclk_deassert(struct dw_mipi_dsi *dsi) 359 { 360 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, 0); 361 udelay(1); 362 } 363 364 static inline void mipi_dphy_shutdownz_assert(struct dw_mipi_dsi *dsi) 365 { 366 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, 0); 367 udelay(1); 368 } 369 370 static inline void mipi_dphy_shutdownz_deassert(struct dw_mipi_dsi *dsi) 371 { 372 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, PHY_SHUTDOWNZ); 373 udelay(1); 374 } 375 376 static inline void mipi_dphy_rstz_assert(struct dw_mipi_dsi *dsi) 377 { 378 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, 0); 379 udelay(1); 380 } 381 382 static inline void mipi_dphy_rstz_deassert(struct dw_mipi_dsi *dsi) 383 { 384 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, PHY_RSTZ); 385 udelay(1); 386 } 387 388 static inline void testif_testclk_assert(struct dw_mipi_dsi *dsi) 389 { 390 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK); 391 udelay(1); 392 } 393 394 static inline void testif_testclk_deassert(struct dw_mipi_dsi *dsi) 395 { 396 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK, 0); 397 udelay(1); 398 } 399 400 static inline void testif_testclr_assert(struct dw_mipi_dsi *dsi) 401 { 402 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR, PHY_TESTCLR); 403 udelay(1); 404 } 405 406 static inline void testif_testclr_deassert(struct dw_mipi_dsi *dsi) 407 { 408 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR, 0); 409 udelay(1); 410 } 411 412 static inline void testif_testen_assert(struct dw_mipi_dsi *dsi) 413 { 414 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN, PHY_TESTEN); 415 udelay(1); 416 } 417 418 static inline void testif_testen_deassert(struct dw_mipi_dsi *dsi) 419 { 420 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN, 0); 421 udelay(1); 422 } 423 424 static inline void testif_set_data(struct dw_mipi_dsi *dsi, u8 data) 425 { 426 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, 427 PHY_TESTDIN_MASK, PHY_TESTDIN(data)); 428 udelay(1); 429 } 430 431 static inline u8 testif_get_data(struct dw_mipi_dsi *dsi) 432 { 433 return dsi_read(dsi, DSI_PHY_TST_CTRL1) >> PHY_TESTDOUT_SHIFT; 434 } 435 436 static void testif_test_code_write(struct dw_mipi_dsi *dsi, u8 test_code) 437 { 438 testif_testclk_assert(dsi); 439 testif_set_data(dsi, test_code); 440 testif_testen_assert(dsi); 441 testif_testclk_deassert(dsi); 442 testif_testen_deassert(dsi); 443 } 444 445 static void testif_test_data_write(struct dw_mipi_dsi *dsi, u8 test_data) 446 { 447 testif_testclk_deassert(dsi); 448 testif_set_data(dsi, test_data); 449 testif_testclk_assert(dsi); 450 } 451 452 static void testif_write(struct dw_mipi_dsi *dsi, u8 test_code, u8 test_data) 453 { 454 testif_test_code_write(dsi, test_code); 455 testif_test_data_write(dsi, test_data); 456 457 dev_dbg(dsi->dev, 458 "test_code=0x%02x, test_data=0x%02x, monitor_data=0x%02x\n", 459 test_code, test_data, testif_get_data(dsi)); 460 } 461 462 static int mipi_dphy_power_on(struct dw_mipi_dsi *dsi) 463 { 464 u32 mask, val; 465 int ret; 466 467 mipi_dphy_shutdownz_deassert(dsi); 468 mipi_dphy_rstz_deassert(dsi); 469 mdelay(2); 470 471 if (dsi->dphy.phy) { 472 rockchip_phy_set_mode(dsi->dphy.phy, PHY_MODE_VIDEO_MIPI); 473 rockchip_phy_power_on(dsi->dphy.phy); 474 } 475 476 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 477 val, val & PHY_LOCK, PHY_STATUS_TIMEOUT_US); 478 if (ret < 0) { 479 dev_err(dsi->dev, "PHY is not locked\n"); 480 return ret; 481 } 482 483 udelay(200); 484 485 mask = PHY_STOPSTATELANE; 486 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 487 val, (val & mask) == mask, 488 PHY_STATUS_TIMEOUT_US); 489 if (ret < 0) { 490 dev_err(dsi->dev, "lane module is not in stop state\n"); 491 return ret; 492 } 493 494 udelay(10); 495 496 return 0; 497 } 498 499 static void dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) 500 { 501 /* Table 5-1 Frequency Ranges */ 502 const struct { 503 unsigned long max_lane_mbps; 504 u8 hsfreqrange; 505 } hsfreqrange_table[] = { 506 { 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01}, 507 { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12}, 508 { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23}, 509 { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15}, 510 { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07}, 511 { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09}, 512 { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a}, 513 {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b}, 514 {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c}, 515 {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c} 516 }; 517 u8 hsfreqrange, counter; 518 unsigned int index, txbyteclkhs; 519 u16 n, m; 520 521 for (index = 0; index < ARRAY_SIZE(hsfreqrange_table); index++) 522 if (dsi->lane_mbps <= hsfreqrange_table[index].max_lane_mbps) 523 break; 524 525 if (index == ARRAY_SIZE(hsfreqrange_table)) 526 --index; 527 528 hsfreqrange = hsfreqrange_table[index].hsfreqrange; 529 testif_write(dsi, 0x44, HSFREQRANGE(hsfreqrange)); 530 531 txbyteclkhs = dsi->lane_mbps >> 3; 532 counter = txbyteclkhs * 60 / 1000; 533 testif_write(dsi, 0x60, 0x80 | counter); 534 testif_write(dsi, 0x70, 0x80 | counter); 535 536 n = dsi->dphy.input_div - 1; 537 m = dsi->dphy.feedback_div - 1; 538 testif_write(dsi, 0x19, 0x30); 539 testif_write(dsi, 0x17, INPUT_DIV(n)); 540 testif_write(dsi, 0x18, FEEDBACK_DIV_LO(m)); 541 testif_write(dsi, 0x18, FEEDBACK_DIV_HI(m >> 5)); 542 } 543 544 static unsigned long dw_mipi_dsi_get_lane_rate(struct dw_mipi_dsi *dsi) 545 { 546 const struct drm_display_mode *mode = &dsi->mode; 547 unsigned long max_lane_rate = dsi->pdata->max_bit_rate_per_lane; 548 unsigned long lane_rate; 549 unsigned int value; 550 int bpp, lanes; 551 u64 tmp; 552 553 /* optional override of the desired bandwidth */ 554 value = dev_read_u32_default(dsi->dev, "rockchip,lane-rate", 0); 555 if (value > 0) 556 return value * 1000 * 1000; 557 558 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 559 if (bpp < 0) 560 bpp = 24; 561 562 lanes = dsi->slave ? dsi->lanes * 2 : dsi->lanes; 563 tmp = (u64)mode->clock * 1000 * bpp; 564 do_div(tmp, lanes); 565 566 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */ 567 tmp *= 10; 568 do_div(tmp, 9); 569 570 if (tmp > max_lane_rate) 571 lane_rate = max_lane_rate; 572 else 573 lane_rate = tmp; 574 575 return lane_rate; 576 } 577 578 static void dw_mipi_dsi_set_pll(struct dw_mipi_dsi *dsi, unsigned long rate) 579 { 580 unsigned long fin, fout; 581 unsigned long fvco_min, fvco_max, best_freq = 984000000; 582 u8 min_prediv, max_prediv; 583 u8 _prediv, best_prediv = 2; 584 u16 _fbdiv, best_fbdiv = 82; 585 u32 min_delta = ~0U; 586 587 fin = 24000000; 588 fout = rate; 589 590 /* 5Mhz < Fref / N < 40MHz, 80MHz < Fvco < 1500Mhz */ 591 min_prediv = DIV_ROUND_UP(fin, 40000000); 592 max_prediv = fin / 5000000; 593 fvco_min = 80000000; 594 fvco_max = 1500000000; 595 596 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 597 u64 tmp, _fout; 598 u32 delta; 599 600 /* Fvco = Fref * M / N */ 601 tmp = (u64)fout * _prediv; 602 do_div(tmp, fin); 603 _fbdiv = tmp; 604 605 /* 606 * Due to the use of a "by 2 pre-scaler," the range of the 607 * feedback multiplication value M is limited to even division 608 * numbers, and m must be greater than 12, less than 1000. 609 */ 610 if (_fbdiv <= 12 || _fbdiv >= 1000) 611 continue; 612 613 if (_fbdiv % 2) 614 ++_fbdiv; 615 616 _fout = (u64)_fbdiv * fin; 617 do_div(_fout, _prediv); 618 619 if (_fout < fvco_min || _fout > fvco_max) 620 continue; 621 622 delta = abs(fout - _fout); 623 if (!delta) { 624 best_prediv = _prediv; 625 best_fbdiv = _fbdiv; 626 best_freq = _fout; 627 break; 628 } else if (delta < min_delta) { 629 best_prediv = _prediv; 630 best_fbdiv = _fbdiv; 631 best_freq = _fout; 632 min_delta = delta; 633 } 634 } 635 636 dsi->lane_mbps = best_freq / 1000 / 1000; 637 dsi->dphy.input_div = best_prediv; 638 dsi->dphy.feedback_div = best_fbdiv; 639 if (dsi->slave) { 640 dsi->slave->lane_mbps = dsi->lane_mbps; 641 dsi->slave->dphy.input_div = dsi->dphy.input_div; 642 dsi->slave->dphy.feedback_div = dsi->dphy.feedback_div; 643 } 644 if (dsi->master) { 645 dsi->master->lane_mbps = dsi->lane_mbps; 646 dsi->master->dphy.input_div = dsi->dphy.input_div; 647 dsi->master->dphy.feedback_div = dsi->dphy.feedback_div; 648 } 649 } 650 651 static int dw_mipi_dsi_read_from_fifo(struct dw_mipi_dsi *dsi, 652 const struct mipi_dsi_msg *msg) 653 { 654 u8 *payload = msg->rx_buf; 655 u16 length; 656 u32 val; 657 int ret; 658 659 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 660 val, !(val & GEN_RD_CMD_BUSY), 5000); 661 if (ret) { 662 printf("entire response isn't stored in the FIFO\n"); 663 return ret; 664 } 665 666 /* Receive payload */ 667 for (length = msg->rx_len; length; length -= 4) { 668 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 669 val, !(val & GEN_PLD_R_EMPTY), 5000); 670 if (ret) { 671 printf("Read payload FIFO is empty\n"); 672 return ret; 673 } 674 675 val = dsi_read(dsi, DSI_GEN_PLD_DATA); 676 677 switch (length) { 678 case 3: 679 payload[2] = (val >> 16) & 0xff; 680 /* Fall through */ 681 case 2: 682 payload[1] = (val >> 8) & 0xff; 683 /* Fall through */ 684 case 1: 685 payload[0] = val & 0xff; 686 return 0; 687 } 688 689 payload[0] = (val >> 0) & 0xff; 690 payload[1] = (val >> 8) & 0xff; 691 payload[2] = (val >> 16) & 0xff; 692 payload[3] = (val >> 24) & 0xff; 693 payload += 4; 694 } 695 696 return 0; 697 } 698 699 static int dw_mipi_dsi_turn_on_peripheral(struct dw_mipi_dsi *dsi) 700 { 701 dpishutdn_assert(dsi); 702 udelay(20); 703 dpishutdn_deassert(dsi); 704 705 return 0; 706 } 707 708 static int dw_mipi_dsi_shutdown_peripheral(struct dw_mipi_dsi *dsi) 709 { 710 dpishutdn_deassert(dsi); 711 udelay(20); 712 dpishutdn_assert(dsi); 713 714 return 0; 715 } 716 717 static ssize_t dw_mipi_dsi_transfer(struct dw_mipi_dsi *dsi, 718 const struct mipi_dsi_msg *msg) 719 { 720 struct mipi_dsi_packet packet; 721 int ret; 722 int val; 723 724 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { 725 dsi_update_bits(dsi, DSI_VID_MODE_CFG, LP_CMD_EN, LP_CMD_EN); 726 dsi_update_bits(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS, 0); 727 } else { 728 dsi_update_bits(dsi, DSI_VID_MODE_CFG, LP_CMD_EN, 0); 729 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 730 PHY_TXREQUESTCLKHS, PHY_TXREQUESTCLKHS); 731 } 732 733 switch (msg->type) { 734 case MIPI_DSI_SHUTDOWN_PERIPHERAL: 735 return dw_mipi_dsi_shutdown_peripheral(dsi); 736 case MIPI_DSI_TURN_ON_PERIPHERAL: 737 return dw_mipi_dsi_turn_on_peripheral(dsi); 738 case MIPI_DSI_DCS_SHORT_WRITE: 739 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_0P_TX, 740 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 741 DCS_SW_0P_TX : 0); 742 break; 743 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 744 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_1P_TX, 745 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 746 DCS_SW_1P_TX : 0); 747 break; 748 case MIPI_DSI_DCS_LONG_WRITE: 749 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX, 750 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 751 DCS_LW_TX : 0); 752 break; 753 case MIPI_DSI_DCS_READ: 754 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SR_0P_TX, 755 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 756 DCS_SR_0P_TX : 0); 757 break; 758 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: 759 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, MAX_RD_PKT_SIZE, 760 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 761 MAX_RD_PKT_SIZE : 0); 762 break; 763 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 764 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_0P_TX, 765 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 766 GEN_SW_0P_TX : 0); 767 break; 768 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 769 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_1P_TX, 770 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 771 GEN_SW_1P_TX : 0); 772 break; 773 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 774 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_2P_TX, 775 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 776 GEN_SW_2P_TX : 0); 777 break; 778 case MIPI_DSI_GENERIC_LONG_WRITE: 779 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_LW_TX, 780 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 781 GEN_LW_TX : 0); 782 break; 783 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 784 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_0P_TX, 785 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 786 GEN_SR_0P_TX : 0); 787 break; 788 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 789 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_1P_TX, 790 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 791 GEN_SR_1P_TX : 0); 792 break; 793 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 794 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_2P_TX, 795 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 796 GEN_SR_2P_TX : 0); 797 break; 798 default: 799 return -EINVAL; 800 } 801 802 if (msg->flags & MIPI_DSI_MSG_REQ_ACK) 803 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, 804 ACK_RQST_EN, ACK_RQST_EN); 805 806 /* create a packet to the DSI protocol */ 807 ret = mipi_dsi_create_packet(&packet, msg); 808 if (ret) { 809 printf("failed to create packet: %d\n", ret); 810 return ret; 811 } 812 813 /* Send payload */ 814 while (DIV_ROUND_UP(packet.payload_length, 4)) { 815 /* 816 * Alternatively, you can always keep the FIFO 817 * nearly full by monitoring the FIFO state until 818 * it is not full, and then writea single word of data. 819 * This solution is more resource consuming 820 * but it simultaneously avoids FIFO starvation, 821 * making it possible to use FIFO sizes smaller than 822 * the amount of data of the longest packet to be written. 823 */ 824 ret = genif_wait_w_pld_fifo_not_full(dsi); 825 if (ret) 826 return ret; 827 828 if (packet.payload_length < 4) { 829 /* send residu payload */ 830 val = 0; 831 memcpy(&val, packet.payload, packet.payload_length); 832 dsi_write(dsi, DSI_GEN_PLD_DATA, val); 833 packet.payload_length = 0; 834 } else { 835 val = get_unaligned_le32(packet.payload); 836 dsi_write(dsi, DSI_GEN_PLD_DATA, val); 837 packet.payload += 4; 838 packet.payload_length -= 4; 839 } 840 } 841 842 ret = genif_wait_cmd_fifo_not_full(dsi); 843 if (ret) 844 return ret; 845 846 /* Send packet header */ 847 val = get_unaligned_le32(packet.header); 848 dsi_write(dsi, DSI_GEN_HDR, val); 849 850 ret = genif_wait_write_fifo_empty(dsi); 851 if (ret) 852 return ret; 853 854 if (msg->rx_len) { 855 ret = dw_mipi_dsi_read_from_fifo(dsi, msg); 856 if (ret < 0) 857 return ret; 858 } 859 860 if (dsi->slave) { 861 ret = dw_mipi_dsi_transfer(dsi->slave, msg); 862 if (ret < 0) 863 return ret; 864 } 865 866 return msg->rx_len ? msg->rx_len : msg->tx_len; 867 } 868 869 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) 870 { 871 u32 val = LP_VACT_EN | LP_VFP_EN | LP_VBP_EN | LP_VSA_EN | 872 LP_HFP_EN | LP_HBP_EN; 873 874 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) 875 val &= ~LP_HFP_EN; 876 877 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) 878 val &= ~LP_HBP_EN; 879 880 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 881 val |= VID_MODE_TYPE_BURST; 882 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 883 val |= VID_MODE_TYPE_BURST_SYNC_PULSES; 884 else 885 val |= VID_MODE_TYPE_BURST_SYNC_EVENTS; 886 887 dsi_write(dsi, DSI_VID_MODE_CFG, val); 888 889 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 890 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 891 AUTO_CLKLANE_CTRL, AUTO_CLKLANE_CTRL); 892 } 893 894 static void dw_mipi_dsi_enable(struct dw_mipi_dsi *dsi) 895 { 896 const struct drm_display_mode *mode = &dsi->mode; 897 898 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 899 PHY_TXREQUESTCLKHS, PHY_TXREQUESTCLKHS); 900 901 dsi_write(dsi, DSI_PWR_UP, RESET); 902 903 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 904 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, VIDEO_MODE); 905 } else { 906 dsi_write(dsi, DSI_DBI_VCID, DBI_VCID(dsi->channel)); 907 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX, 0); 908 dsi_write(dsi, DSI_EDPI_CMD_SIZE, mode->hdisplay); 909 dsi_update_bits(dsi, DSI_MODE_CFG, 910 CMD_VIDEO_MODE, COMMAND_MODE); 911 } 912 913 dsi_write(dsi, DSI_PWR_UP, POWERUP); 914 915 if (dsi->slave) 916 dw_mipi_dsi_enable(dsi->slave); 917 } 918 919 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) 920 { 921 dsi_write(dsi, DSI_PWR_UP, RESET); 922 dsi_write(dsi, DSI_LPCLK_CTRL, 0); 923 dsi_write(dsi, DSI_EDPI_CMD_SIZE, 0); 924 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, COMMAND_MODE); 925 dsi_write(dsi, DSI_PWR_UP, POWERUP); 926 927 if (dsi->slave) 928 dw_mipi_dsi_disable(dsi->slave); 929 } 930 931 static void dw_mipi_dsi_post_disable(struct dw_mipi_dsi *dsi) 932 { 933 if (!dsi->prepared) 934 return; 935 936 if (dsi->master) 937 dw_mipi_dsi_post_disable(dsi->master); 938 939 dsi_write(dsi, DSI_PWR_UP, RESET); 940 dsi_write(dsi, DSI_PHY_RSTZ, 0); 941 942 if (dsi->dphy.phy) 943 rockchip_phy_power_off(dsi->dphy.phy); 944 945 dsi->prepared = false; 946 947 if (dsi->slave) 948 dw_mipi_dsi_post_disable(dsi->slave); 949 } 950 951 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) 952 { 953 u32 esc_clk_div; 954 955 dsi_write(dsi, DSI_PWR_UP, RESET); 956 957 /* The maximum value of the escape clock frequency is 20MHz */ 958 esc_clk_div = DIV_ROUND_UP(dsi->lane_mbps >> 3, 20); 959 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) | 960 TX_ESC_CLK_DIVIDSION(esc_clk_div)); 961 } 962 963 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, 964 struct drm_display_mode *mode) 965 { 966 u32 val = 0, color = 0; 967 968 switch (dsi->format) { 969 case MIPI_DSI_FMT_RGB888: 970 color = DPI_COLOR_CODING_24BIT; 971 break; 972 case MIPI_DSI_FMT_RGB666: 973 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY; 974 break; 975 case MIPI_DSI_FMT_RGB666_PACKED: 976 color = DPI_COLOR_CODING_18BIT_1; 977 break; 978 case MIPI_DSI_FMT_RGB565: 979 color = DPI_COLOR_CODING_16BIT_1; 980 break; 981 } 982 983 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 984 val |= VSYNC_ACTIVE_LOW; 985 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 986 val |= HSYNC_ACTIVE_LOW; 987 988 dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel)); 989 dsi_write(dsi, DSI_DPI_COLOR_CODING, color); 990 dsi_write(dsi, DSI_DPI_CFG_POL, val); 991 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4) 992 | INVACT_LPCMD_TIME(4)); 993 } 994 995 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi) 996 { 997 u32 val = CRC_RX_EN | ECC_RX_EN | BTA_EN | EOTP_TX_EN; 998 999 if (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 1000 val &= ~EOTP_TX_EN; 1001 1002 dsi_write(dsi, DSI_PCKHDL_CFG, val); 1003 } 1004 1005 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, 1006 struct drm_display_mode *mode) 1007 { 1008 dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay)); 1009 } 1010 1011 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) 1012 { 1013 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000)); 1014 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); 1015 } 1016 1017 /* Get lane byte clock cycles. */ 1018 static int dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, 1019 u32 hcomponent) 1020 { 1021 u32 lbcc; 1022 1023 lbcc = hcomponent * dsi->lane_mbps * 1000 / 8; 1024 1025 if (!dsi->mode.clock) 1026 return 0; 1027 1028 return DIV_ROUND_CLOSEST(lbcc, dsi->mode.clock); 1029 } 1030 1031 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi) 1032 { 1033 int htotal, hsa, hbp, lbcc; 1034 struct drm_display_mode *mode = &dsi->mode; 1035 1036 htotal = mode->htotal; 1037 hsa = mode->hsync_end - mode->hsync_start; 1038 hbp = mode->htotal - mode->hsync_end; 1039 1040 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal); 1041 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); 1042 1043 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa); 1044 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); 1045 1046 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp); 1047 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); 1048 } 1049 1050 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi) 1051 { 1052 u32 vactive, vsa, vfp, vbp; 1053 struct drm_display_mode *mode = &dsi->mode; 1054 1055 vactive = mode->vdisplay; 1056 vsa = mode->vsync_end - mode->vsync_start; 1057 vfp = mode->vsync_start - mode->vdisplay; 1058 vbp = mode->vtotal - mode->vsync_end; 1059 1060 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); 1061 dsi_write(dsi, DSI_VID_VSA_LINES, vsa); 1062 dsi_write(dsi, DSI_VID_VFP_LINES, vfp); 1063 dsi_write(dsi, DSI_VID_VBP_LINES, vbp); 1064 } 1065 1066 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) 1067 { 1068 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14) 1069 | PHY_LP2HS_TIME(0x10) | MAX_RD_TIME(10000)); 1070 1071 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40) 1072 | PHY_CLKLP2HS_TIME(0x40)); 1073 } 1074 1075 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) 1076 { 1077 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) | 1078 N_LANES(dsi->lanes)); 1079 } 1080 1081 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) 1082 { 1083 dsi_read(dsi, DSI_INT_ST0); 1084 dsi_read(dsi, DSI_INT_ST1); 1085 dsi_write(dsi, DSI_INT_MSK0, 0); 1086 dsi_write(dsi, DSI_INT_MSK1, 0); 1087 } 1088 1089 static int dw_mipi_dsi_connector_pre_init(struct display_state *state) 1090 { 1091 struct connector_state *conn_state = &state->conn_state; 1092 1093 conn_state->type = DRM_MODE_CONNECTOR_DSI; 1094 1095 return 0; 1096 } 1097 1098 static int dw_mipi_dsi_connector_init(struct display_state *state) 1099 { 1100 struct connector_state *conn_state = &state->conn_state; 1101 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1102 1103 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dsi->id); 1104 dsi->dphy.phy = conn_state->phy; 1105 1106 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 1107 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 1108 conn_state->output_if |= 1109 dsi->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0; 1110 1111 #ifndef CONFIG_ROCKCHIP_RK3568 1112 if (dsi->id) { 1113 struct udevice *dev; 1114 int ret; 1115 1116 ret = uclass_get_device_by_name(UCLASS_DISPLAY, "dsi@ff960000", 1117 &dev); 1118 if (ret) 1119 return ret; 1120 1121 dsi->master = dev_get_priv(dev); 1122 if (!dsi->master) 1123 return -ENODEV; 1124 1125 conn_state->output_flags = ROCKCHIP_OUTPUT_DATA_SWAP; 1126 } 1127 #endif 1128 1129 if (dsi->lanes > 4) { 1130 struct udevice *dev; 1131 int ret; 1132 1133 ret = uclass_get_device_by_name(UCLASS_DISPLAY, 1134 #if defined(CONFIG_ROCKCHIP_RK3288) 1135 "dsi@ff964000", 1136 #elif defined(CONFIG_ROCKCHIP_RK3399) 1137 "dsi@ff968000", 1138 #else 1139 "dsi@fe070000", 1140 #endif 1141 &dev); 1142 if (ret) 1143 return ret; 1144 1145 dsi->slave = dev_get_priv(dev); 1146 if (!dsi->slave) 1147 return -ENODEV; 1148 1149 dsi->lanes /= 2; 1150 dsi->slave->lanes = dsi->lanes; 1151 dsi->slave->format = dsi->format; 1152 dsi->slave->mode_flags = dsi->mode_flags; 1153 dsi->slave->channel = dsi->channel; 1154 conn_state->output_flags = 1155 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; 1156 if (dsi->data_swap) 1157 conn_state->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP; 1158 1159 conn_state->output_if |= VOP_OUTPUT_IF_MIPI1; 1160 1161 #if defined(CONFIG_ROCKCHIP_RK3568) 1162 struct rockchip_phy *phy = NULL; 1163 struct udevice *phy_dev; 1164 1165 ret = uclass_get_device_by_phandle(UCLASS_PHY, dev, 1166 "phys", &phy_dev); 1167 if (ret) 1168 return -ENODEV; 1169 1170 phy = (struct rockchip_phy *)dev_get_driver_data(phy_dev); 1171 if (!phy) 1172 return -ENODEV; 1173 1174 dsi->slave->dphy.phy = phy; 1175 if (phy->funcs && phy->funcs->init) 1176 return phy->funcs->init(phy); 1177 #endif 1178 1179 } 1180 1181 return 0; 1182 } 1183 1184 static void dw_mipi_dsi_set_hs_clk(struct dw_mipi_dsi *dsi, unsigned long rate) 1185 { 1186 rate = rockchip_phy_set_pll(dsi->dphy.phy, rate); 1187 dsi->lane_mbps = rate / 1000 / 1000; 1188 } 1189 1190 static void dw_mipi_dsi_host_init(struct dw_mipi_dsi *dsi) 1191 { 1192 dw_mipi_dsi_init(dsi); 1193 dw_mipi_dsi_dpi_config(dsi, &dsi->mode); 1194 dw_mipi_dsi_packet_handler_config(dsi); 1195 dw_mipi_dsi_video_mode_config(dsi); 1196 dw_mipi_dsi_video_packet_config(dsi, &dsi->mode); 1197 dw_mipi_dsi_command_mode_config(dsi); 1198 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, COMMAND_MODE); 1199 dw_mipi_dsi_line_timer_config(dsi); 1200 dw_mipi_dsi_vertical_timing_config(dsi); 1201 dw_mipi_dsi_dphy_timing_config(dsi); 1202 dw_mipi_dsi_dphy_interface_config(dsi); 1203 dw_mipi_dsi_clear_err(dsi); 1204 } 1205 1206 static void dw_mipi_dsi_vop_routing(struct dw_mipi_dsi *dsi, int vop_id) 1207 { 1208 grf_field_write(dsi, VOPSEL, vop_id); 1209 1210 if (dsi->slave) 1211 grf_field_write(dsi->slave, VOPSEL, vop_id); 1212 } 1213 1214 static void mipi_dphy_init(struct dw_mipi_dsi *dsi) 1215 { 1216 u32 map[] = {0x0, 0x1, 0x3, 0x7, 0xf}; 1217 1218 mipi_dphy_enableclk_deassert(dsi); 1219 mipi_dphy_shutdownz_assert(dsi); 1220 mipi_dphy_rstz_assert(dsi); 1221 testif_testclr_assert(dsi); 1222 1223 /* Configures DPHY to work as a Master */ 1224 grf_field_write(dsi, MASTERSLAVEZ, 1); 1225 1226 /* Configures lane as TX */ 1227 grf_field_write(dsi, BASEDIR, 0); 1228 1229 /* Set all REQUEST inputs to zero */ 1230 grf_field_write(dsi, TURNREQUEST, 0); 1231 grf_field_write(dsi, TURNDISABLE, 0); 1232 grf_field_write(dsi, FORCETXSTOPMODE, 0); 1233 grf_field_write(dsi, FORCERXMODE, 0); 1234 udelay(1); 1235 1236 testif_testclr_deassert(dsi); 1237 1238 if (!dsi->dphy.phy) 1239 dw_mipi_dsi_phy_init(dsi); 1240 1241 /* Enable Data Lane Module */ 1242 grf_field_write(dsi, ENABLE_N, map[dsi->lanes]); 1243 1244 /* Enable Clock Lane Module */ 1245 grf_field_write(dsi, ENABLECLK, 1); 1246 1247 mipi_dphy_enableclk_assert(dsi); 1248 } 1249 1250 static void dw_mipi_dsi_pre_enable(struct dw_mipi_dsi *dsi) 1251 { 1252 if (dsi->prepared) 1253 return; 1254 1255 if (dsi->master) 1256 dw_mipi_dsi_pre_enable(dsi->master); 1257 1258 dw_mipi_dsi_host_init(dsi); 1259 mipi_dphy_init(dsi); 1260 mipi_dphy_power_on(dsi); 1261 dsi_write(dsi, DSI_PWR_UP, POWERUP); 1262 1263 dsi->prepared = true; 1264 1265 if (dsi->slave) 1266 dw_mipi_dsi_pre_enable(dsi->slave); 1267 } 1268 1269 static int dw_mipi_dsi_connector_prepare(struct display_state *state) 1270 { 1271 struct connector_state *conn_state = &state->conn_state; 1272 struct crtc_state *crtc_state = &state->crtc_state; 1273 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1274 unsigned long lane_rate; 1275 1276 memcpy(&dsi->mode, &conn_state->mode, sizeof(struct drm_display_mode)); 1277 if (dsi->slave) { 1278 dsi->mode.hdisplay /= 2; 1279 memcpy(&dsi->slave->mode, &dsi->mode, 1280 sizeof(struct drm_display_mode)); 1281 } 1282 1283 lane_rate = dw_mipi_dsi_get_lane_rate(dsi); 1284 if (dsi->dphy.phy) 1285 dw_mipi_dsi_set_hs_clk(dsi, lane_rate); 1286 else 1287 dw_mipi_dsi_set_pll(dsi, lane_rate); 1288 1289 if (dsi->slave && dsi->slave->dphy.phy) 1290 dw_mipi_dsi_set_hs_clk(dsi->slave, lane_rate); 1291 1292 printf("final DSI-Link bandwidth: %u Mbps x %d\n", 1293 dsi->lane_mbps, dsi->slave ? dsi->lanes * 2 : dsi->lanes); 1294 1295 dw_mipi_dsi_vop_routing(dsi, crtc_state->crtc_id); 1296 dw_mipi_dsi_pre_enable(dsi); 1297 1298 return 0; 1299 } 1300 1301 static void dw_mipi_dsi_connector_unprepare(struct display_state *state) 1302 { 1303 struct connector_state *conn_state = &state->conn_state; 1304 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1305 1306 dw_mipi_dsi_post_disable(dsi); 1307 } 1308 1309 static int dw_mipi_dsi_connector_enable(struct display_state *state) 1310 { 1311 struct connector_state *conn_state = &state->conn_state; 1312 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1313 1314 dw_mipi_dsi_enable(dsi); 1315 1316 return 0; 1317 } 1318 1319 static int dw_mipi_dsi_connector_disable(struct display_state *state) 1320 { 1321 struct connector_state *conn_state = &state->conn_state; 1322 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1323 1324 dw_mipi_dsi_disable(dsi); 1325 1326 return 0; 1327 } 1328 1329 static const struct rockchip_connector_funcs dw_mipi_dsi_connector_funcs = { 1330 .pre_init = dw_mipi_dsi_connector_pre_init, 1331 .init = dw_mipi_dsi_connector_init, 1332 .prepare = dw_mipi_dsi_connector_prepare, 1333 .unprepare = dw_mipi_dsi_connector_unprepare, 1334 .enable = dw_mipi_dsi_connector_enable, 1335 .disable = dw_mipi_dsi_connector_disable, 1336 }; 1337 1338 static int dw_mipi_dsi_probe(struct udevice *dev) 1339 { 1340 struct dw_mipi_dsi *dsi = dev_get_priv(dev); 1341 const struct rockchip_connector *connector = 1342 (const struct rockchip_connector *)dev_get_driver_data(dev); 1343 const struct dw_mipi_dsi_plat_data *pdata = connector->data; 1344 int id; 1345 1346 dsi->base = dev_read_addr_ptr(dev); 1347 dsi->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1348 if (IS_ERR(dsi->grf)) 1349 return PTR_ERR(dsi->grf); 1350 1351 id = of_alias_get_id(ofnode_to_np(dev->node), "dsi"); 1352 if (id < 0) 1353 id = 0; 1354 1355 dsi->dev = dev; 1356 dsi->pdata = pdata; 1357 dsi->id = id; 1358 dsi->data_swap = dev_read_bool(dsi->dev, "rockchip,data-swap"); 1359 1360 return 0; 1361 } 1362 1363 static const u32 px30_dsi_grf_reg_fields[MAX_FIELDS] = { 1364 [DPIUPDATECFG] = GRF_REG_FIELD(0x0434, 7, 7), 1365 [DPICOLORM] = GRF_REG_FIELD(0x0434, 3, 3), 1366 [DPISHUTDN] = GRF_REG_FIELD(0x0434, 2, 2), 1367 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0438, 7, 10), 1368 [TURNDISABLE] = GRF_REG_FIELD(0x0438, 5, 5), 1369 [VOPSEL] = GRF_REG_FIELD(0x0438, 0, 0), 1370 }; 1371 1372 static const struct dw_mipi_dsi_plat_data px30_mipi_dsi_plat_data = { 1373 .dsi0_grf_reg_fields = px30_dsi_grf_reg_fields, 1374 .max_bit_rate_per_lane = 1000000000UL, 1375 }; 1376 1377 static const struct rockchip_connector px30_mipi_dsi_driver_data = { 1378 .funcs = &dw_mipi_dsi_connector_funcs, 1379 .data = &px30_mipi_dsi_plat_data, 1380 }; 1381 1382 static const u32 rk1808_dsi_grf_reg_fields[MAX_FIELDS] = { 1383 [MASTERSLAVEZ] = GRF_REG_FIELD(0x0440, 8, 8), 1384 [DPIUPDATECFG] = GRF_REG_FIELD(0x0440, 7, 7), 1385 [DPICOLORM] = GRF_REG_FIELD(0x0440, 3, 3), 1386 [DPISHUTDN] = GRF_REG_FIELD(0x0440, 2, 2), 1387 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0444, 7, 10), 1388 [FORCERXMODE] = GRF_REG_FIELD(0x0444, 6, 6), 1389 [TURNDISABLE] = GRF_REG_FIELD(0x0444, 5, 5), 1390 }; 1391 1392 static const struct dw_mipi_dsi_plat_data rk1808_mipi_dsi_plat_data = { 1393 .dsi0_grf_reg_fields = rk1808_dsi_grf_reg_fields, 1394 .max_bit_rate_per_lane = 2000000000UL, 1395 }; 1396 1397 static const struct rockchip_connector rk1808_mipi_dsi_driver_data = { 1398 .funcs = &dw_mipi_dsi_connector_funcs, 1399 .data = &rk1808_mipi_dsi_plat_data, 1400 }; 1401 1402 static const u32 rk3128_dsi_grf_reg_fields[MAX_FIELDS] = { 1403 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0150, 10, 13), 1404 [FORCERXMODE] = GRF_REG_FIELD(0x0150, 9, 9), 1405 [TURNDISABLE] = GRF_REG_FIELD(0x0150, 8, 8), 1406 [DPICOLORM] = GRF_REG_FIELD(0x0150, 5, 5), 1407 [DPISHUTDN] = GRF_REG_FIELD(0x0150, 4, 4), 1408 }; 1409 1410 static const struct dw_mipi_dsi_plat_data rk3128_mipi_dsi_plat_data = { 1411 .dsi0_grf_reg_fields = rk3128_dsi_grf_reg_fields, 1412 .max_bit_rate_per_lane = 1000000000UL, 1413 }; 1414 1415 static const struct rockchip_connector rk3128_mipi_dsi_driver_data = { 1416 .funcs = &dw_mipi_dsi_connector_funcs, 1417 .data = &rk3128_mipi_dsi_plat_data, 1418 }; 1419 1420 static const u32 rk3288_dsi0_grf_reg_fields[MAX_FIELDS] = { 1421 [DPICOLORM] = GRF_REG_FIELD(0x025c, 8, 8), 1422 [DPISHUTDN] = GRF_REG_FIELD(0x025c, 7, 7), 1423 [VOPSEL] = GRF_REG_FIELD(0x025c, 6, 6), 1424 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0264, 8, 11), 1425 [FORCERXMODE] = GRF_REG_FIELD(0x0264, 4, 7), 1426 [TURNDISABLE] = GRF_REG_FIELD(0x0264, 0, 3), 1427 [TURNREQUEST] = GRF_REG_FIELD(0x03a4, 8, 10), 1428 [DPIUPDATECFG] = GRF_REG_FIELD(0x03a8, 0, 0), 1429 }; 1430 1431 static const u32 rk3288_dsi1_grf_reg_fields[MAX_FIELDS] = { 1432 [DPICOLORM] = GRF_REG_FIELD(0x025c, 11, 11), 1433 [DPISHUTDN] = GRF_REG_FIELD(0x025c, 10, 10), 1434 [VOPSEL] = GRF_REG_FIELD(0x025c, 9, 9), 1435 [ENABLE_N] = GRF_REG_FIELD(0x0268, 12, 15), 1436 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0268, 8, 11), 1437 [FORCERXMODE] = GRF_REG_FIELD(0x0268, 4, 7), 1438 [TURNDISABLE] = GRF_REG_FIELD(0x0268, 0, 3), 1439 [BASEDIR] = GRF_REG_FIELD(0x027c, 15, 15), 1440 [MASTERSLAVEZ] = GRF_REG_FIELD(0x027c, 14, 14), 1441 [ENABLECLK] = GRF_REG_FIELD(0x027c, 12, 12), 1442 [TURNREQUEST] = GRF_REG_FIELD(0x03a4, 4, 7), 1443 [DPIUPDATECFG] = GRF_REG_FIELD(0x03a8, 1, 1), 1444 }; 1445 1446 static const struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_plat_data = { 1447 .dsi0_grf_reg_fields = rk3288_dsi0_grf_reg_fields, 1448 .dsi1_grf_reg_fields = rk3288_dsi1_grf_reg_fields, 1449 .max_bit_rate_per_lane = 1500000000UL, 1450 }; 1451 1452 static const struct rockchip_connector rk3288_mipi_dsi_driver_data = { 1453 .funcs = &dw_mipi_dsi_connector_funcs, 1454 .data = &rk3288_mipi_dsi_plat_data, 1455 }; 1456 1457 static const u32 rk3366_dsi_grf_reg_fields[MAX_FIELDS] = { 1458 [VOPSEL] = GRF_REG_FIELD(0x0400, 2, 2), 1459 [DPIUPDATECFG] = GRF_REG_FIELD(0x0410, 9, 9), 1460 [DPICOLORM] = GRF_REG_FIELD(0x0410, 3, 3), 1461 [DPISHUTDN] = GRF_REG_FIELD(0x0410, 2, 2), 1462 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0414, 7, 10), 1463 [FORCERXMODE] = GRF_REG_FIELD(0x0414, 6, 6), 1464 [TURNDISABLE] = GRF_REG_FIELD(0x0414, 5, 5), 1465 }; 1466 1467 static const struct dw_mipi_dsi_plat_data rk3366_mipi_dsi_plat_data = { 1468 .dsi0_grf_reg_fields = rk3366_dsi_grf_reg_fields, 1469 .max_bit_rate_per_lane = 1000000000UL, 1470 }; 1471 1472 static const struct rockchip_connector rk3366_mipi_dsi_driver_data = { 1473 .funcs = &dw_mipi_dsi_connector_funcs, 1474 .data = &rk3366_mipi_dsi_plat_data, 1475 }; 1476 1477 static const u32 rk3368_dsi_grf_reg_fields[MAX_FIELDS] = { 1478 [DPIUPDATECFG] = GRF_REG_FIELD(0x0418, 7, 7), 1479 [DPICOLORM] = GRF_REG_FIELD(0x0418, 3, 3), 1480 [DPISHUTDN] = GRF_REG_FIELD(0x0418, 2, 2), 1481 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x041c, 7, 10), 1482 [FORCERXMODE] = GRF_REG_FIELD(0x041c, 6, 6), 1483 [TURNDISABLE] = GRF_REG_FIELD(0x041c, 5, 5), 1484 }; 1485 1486 static const struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_plat_data = { 1487 .dsi0_grf_reg_fields = rk3368_dsi_grf_reg_fields, 1488 .max_bit_rate_per_lane = 1000000000UL, 1489 }; 1490 1491 static const struct rockchip_connector rk3368_mipi_dsi_driver_data = { 1492 .funcs = &dw_mipi_dsi_connector_funcs, 1493 .data = &rk3368_mipi_dsi_plat_data, 1494 }; 1495 1496 static const u32 rk3399_dsi0_grf_reg_fields[MAX_FIELDS] = { 1497 [DPIUPDATECFG] = GRF_REG_FIELD(0x6224, 15, 15), 1498 [DPISHUTDN] = GRF_REG_FIELD(0x6224, 14, 14), 1499 [DPICOLORM] = GRF_REG_FIELD(0x6224, 13, 13), 1500 [VOPSEL] = GRF_REG_FIELD(0x6250, 0, 0), 1501 [TURNREQUEST] = GRF_REG_FIELD(0x6258, 12, 15), 1502 [TURNDISABLE] = GRF_REG_FIELD(0x6258, 8, 11), 1503 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x6258, 4, 7), 1504 [FORCERXMODE] = GRF_REG_FIELD(0x6258, 0, 3), 1505 }; 1506 1507 static const u32 rk3399_dsi1_grf_reg_fields[MAX_FIELDS] = { 1508 [VOPSEL] = GRF_REG_FIELD(0x6250, 4, 4), 1509 [DPIUPDATECFG] = GRF_REG_FIELD(0x6250, 3, 3), 1510 [DPISHUTDN] = GRF_REG_FIELD(0x6250, 2, 2), 1511 [DPICOLORM] = GRF_REG_FIELD(0x6250, 1, 1), 1512 [TURNDISABLE] = GRF_REG_FIELD(0x625c, 12, 15), 1513 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x625c, 8, 11), 1514 [FORCERXMODE] = GRF_REG_FIELD(0x625c, 4, 7), 1515 [ENABLE_N] = GRF_REG_FIELD(0x625c, 0, 3), 1516 [MASTERSLAVEZ] = GRF_REG_FIELD(0x6260, 7, 7), 1517 [ENABLECLK] = GRF_REG_FIELD(0x6260, 6, 6), 1518 [BASEDIR] = GRF_REG_FIELD(0x6260, 5, 5), 1519 [TURNREQUEST] = GRF_REG_FIELD(0x6260, 0, 3), 1520 }; 1521 1522 static const struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_plat_data = { 1523 .dsi0_grf_reg_fields = rk3399_dsi0_grf_reg_fields, 1524 .dsi1_grf_reg_fields = rk3399_dsi1_grf_reg_fields, 1525 .max_bit_rate_per_lane = 1500000000UL, 1526 }; 1527 1528 static const struct rockchip_connector rk3399_mipi_dsi_driver_data = { 1529 .funcs = &dw_mipi_dsi_connector_funcs, 1530 .data = &rk3399_mipi_dsi_plat_data, 1531 }; 1532 1533 static const u32 rk3568_dsi0_grf_reg_fields[MAX_FIELDS] = { 1534 [DPIUPDATECFG] = GRF_REG_FIELD(0x0360, 2, 2), 1535 [DPICOLORM] = GRF_REG_FIELD(0x0360, 1, 1), 1536 [DPISHUTDN] = GRF_REG_FIELD(0x0360, 0, 0), 1537 [SKEWCALHS] = GRF_REG_FIELD(0x0368, 11, 15), 1538 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0368, 4, 7), 1539 [TURNDISABLE] = GRF_REG_FIELD(0x0368, 2, 2), 1540 [FORCERXMODE] = GRF_REG_FIELD(0x0368, 0, 0), 1541 }; 1542 1543 static const u32 rk3568_dsi1_grf_reg_fields[MAX_FIELDS] = { 1544 [DPIUPDATECFG] = GRF_REG_FIELD(0x0360, 10, 10), 1545 [DPICOLORM] = GRF_REG_FIELD(0x0360, 9, 9), 1546 [DPISHUTDN] = GRF_REG_FIELD(0x0360, 8, 8), 1547 [SKEWCALHS] = GRF_REG_FIELD(0x036c, 11, 15), 1548 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x036c, 4, 7), 1549 [TURNDISABLE] = GRF_REG_FIELD(0x036c, 2, 2), 1550 [FORCERXMODE] = GRF_REG_FIELD(0x036c, 0, 0), 1551 }; 1552 1553 static const struct dw_mipi_dsi_plat_data rk3568_mipi_dsi_plat_data = { 1554 .dsi0_grf_reg_fields = rk3568_dsi0_grf_reg_fields, 1555 .dsi1_grf_reg_fields = rk3568_dsi1_grf_reg_fields, 1556 .max_bit_rate_per_lane = 1200000000UL, 1557 }; 1558 static const struct rockchip_connector rk3568_mipi_dsi_driver_data = { 1559 .funcs = &dw_mipi_dsi_connector_funcs, 1560 .data = &rk3568_mipi_dsi_plat_data, 1561 }; 1562 1563 static const u32 rv1108_dsi_grf_reg_fields[MAX_FIELDS] = { 1564 [DPICOLORM] = GRF_REG_FIELD(0x0410, 7, 7), 1565 [DPISHUTDN] = GRF_REG_FIELD(0x0410, 6, 6), 1566 [DPIUPDATECFG] = GRF_REG_FIELD(0x0410, 8, 8), 1567 [FORCERXMODE] = GRF_REG_FIELD(0x0414, 5, 5), 1568 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0414, 6, 9), 1569 [TURNDISABLE] = GRF_REG_FIELD(0x0414, 4, 4), 1570 }; 1571 1572 static const struct dw_mipi_dsi_plat_data rv1108_mipi_dsi_plat_data = { 1573 .dsi0_grf_reg_fields = rv1108_dsi_grf_reg_fields, 1574 .max_bit_rate_per_lane = 1000000000UL, 1575 }; 1576 1577 static const struct rockchip_connector rv1108_mipi_dsi_driver_data = { 1578 .funcs = &dw_mipi_dsi_connector_funcs, 1579 .data = &rv1108_mipi_dsi_plat_data, 1580 }; 1581 1582 static const u32 rv1126_dsi_grf_reg_fields[MAX_FIELDS] = { 1583 [DPIUPDATECFG] = GRF_REG_FIELD(0x0008, 5, 5), 1584 [DPISHUTDN] = GRF_REG_FIELD(0x0008, 4, 4), 1585 [DPICOLORM] = GRF_REG_FIELD(0x0008, 3, 3), 1586 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x10220, 4, 7), 1587 [TURNDISABLE] = GRF_REG_FIELD(0x10220, 2, 2), 1588 [FORCERXMODE] = GRF_REG_FIELD(0x10220, 0, 0), 1589 }; 1590 1591 static const struct dw_mipi_dsi_plat_data rv1126_mipi_dsi_plat_data = { 1592 .dsi0_grf_reg_fields = rv1126_dsi_grf_reg_fields, 1593 .max_bit_rate_per_lane = 1000000000UL, 1594 }; 1595 1596 static const struct rockchip_connector rv1126_mipi_dsi_driver_data = { 1597 .funcs = &dw_mipi_dsi_connector_funcs, 1598 .data = &rv1126_mipi_dsi_plat_data, 1599 }; 1600 1601 static const struct udevice_id dw_mipi_dsi_ids[] = { 1602 { 1603 .compatible = "rockchip,px30-mipi-dsi", 1604 .data = (ulong)&px30_mipi_dsi_driver_data, 1605 }, 1606 { 1607 .compatible = "rockchip,rk1808-mipi-dsi", 1608 .data = (ulong)&rk1808_mipi_dsi_driver_data, 1609 }, 1610 { 1611 .compatible = "rockchip,rk3128-mipi-dsi", 1612 .data = (ulong)&rk3128_mipi_dsi_driver_data, 1613 }, 1614 { 1615 .compatible = "rockchip,rk3288-mipi-dsi", 1616 .data = (ulong)&rk3288_mipi_dsi_driver_data, 1617 }, 1618 { 1619 .compatible = "rockchip,rk3366-mipi-dsi", 1620 .data = (ulong)&rk3366_mipi_dsi_driver_data, 1621 }, 1622 { 1623 .compatible = "rockchip,rk3368-mipi-dsi", 1624 .data = (ulong)&rk3368_mipi_dsi_driver_data, 1625 }, 1626 { 1627 .compatible = "rockchip,rk3399-mipi-dsi", 1628 .data = (ulong)&rk3399_mipi_dsi_driver_data, 1629 }, 1630 { 1631 .compatible = "rockchip,rk3568-mipi-dsi", 1632 .data = (ulong)&rk3568_mipi_dsi_driver_data, 1633 }, 1634 { 1635 .compatible = "rockchip,rv1108-mipi-dsi", 1636 .data = (ulong)&rv1108_mipi_dsi_driver_data, 1637 }, 1638 { 1639 .compatible = "rockchip,rv1126-mipi-dsi", 1640 .data = (ulong)&rv1126_mipi_dsi_driver_data, 1641 }, 1642 {} 1643 }; 1644 1645 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host, 1646 const struct mipi_dsi_msg *msg) 1647 { 1648 struct dw_mipi_dsi *dsi = dev_get_priv(host->dev); 1649 1650 return dw_mipi_dsi_transfer(dsi, msg); 1651 } 1652 1653 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 1654 struct mipi_dsi_device *device) 1655 { 1656 struct dw_mipi_dsi *dsi = dev_get_priv(host->dev); 1657 1658 if (device->lanes < 1 || device->lanes > 8) 1659 return -EINVAL; 1660 1661 dsi->lanes = device->lanes; 1662 dsi->channel = device->channel; 1663 dsi->format = device->format; 1664 dsi->mode_flags = device->mode_flags; 1665 1666 return 0; 1667 } 1668 1669 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = { 1670 .attach = dw_mipi_dsi_host_attach, 1671 .transfer = dw_mipi_dsi_host_transfer, 1672 }; 1673 1674 static int dw_mipi_dsi_bind(struct udevice *dev) 1675 { 1676 struct mipi_dsi_host *host = dev_get_platdata(dev); 1677 1678 host->dev = dev; 1679 host->ops = &dw_mipi_dsi_host_ops; 1680 1681 return dm_scan_fdt_dev(dev); 1682 } 1683 1684 static int dw_mipi_dsi_child_post_bind(struct udevice *dev) 1685 { 1686 struct mipi_dsi_host *host = dev_get_platdata(dev->parent); 1687 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1688 char name[20]; 1689 1690 sprintf(name, "%s.%d", host->dev->name, device->channel); 1691 device_set_name(dev, name); 1692 1693 device->dev = dev; 1694 device->host = host; 1695 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4); 1696 device->format = dev_read_u32_default(dev, "dsi,format", 1697 MIPI_DSI_FMT_RGB888); 1698 device->mode_flags = dev_read_u32_default(dev, "dsi,flags", 1699 MIPI_DSI_MODE_VIDEO | 1700 MIPI_DSI_MODE_VIDEO_BURST | 1701 MIPI_DSI_MODE_VIDEO_HBP | 1702 MIPI_DSI_MODE_LPM | 1703 MIPI_DSI_MODE_EOT_PACKET); 1704 device->channel = dev_read_u32_default(dev, "reg", 0); 1705 1706 return 0; 1707 } 1708 1709 static int dw_mipi_dsi_child_pre_probe(struct udevice *dev) 1710 { 1711 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1712 int ret; 1713 1714 ret = mipi_dsi_attach(device); 1715 if (ret) { 1716 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret); 1717 return ret; 1718 } 1719 1720 return 0; 1721 } 1722 1723 U_BOOT_DRIVER(dw_mipi_dsi) = { 1724 .name = "dw_mipi_dsi", 1725 .id = UCLASS_DISPLAY, 1726 .of_match = dw_mipi_dsi_ids, 1727 .probe = dw_mipi_dsi_probe, 1728 .bind = dw_mipi_dsi_bind, 1729 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi), 1730 .per_child_platdata_auto_alloc_size = sizeof(struct mipi_dsi_device), 1731 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_host), 1732 .child_post_bind = dw_mipi_dsi_child_post_bind, 1733 .child_pre_probe = dw_mipi_dsi_child_pre_probe, 1734 }; 1735