1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <drm/drm_mipi_dsi.h> 8 9 #include <config.h> 10 #include <common.h> 11 #include <errno.h> 12 #include <asm/unaligned.h> 13 #include <asm/io.h> 14 #include <asm/hardware.h> 15 #include <dm/device.h> 16 #include <dm/read.h> 17 #include <dm/of_access.h> 18 #include <syscon.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <linux/iopoll.h> 21 22 #include "rockchip_display.h" 23 #include "rockchip_crtc.h" 24 #include "rockchip_connector.h" 25 #include "rockchip_panel.h" 26 #include "rockchip_phy.h" 27 28 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) 29 30 #define DSI_VERSION 0x00 31 #define DSI_PWR_UP 0x04 32 #define RESET 0 33 #define POWERUP BIT(0) 34 35 #define DSI_CLKMGR_CFG 0x08 36 #define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) 37 #define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) 38 39 #define DSI_DPI_VCID 0x0c 40 #define DPI_VID(vid) (((vid) & 0x3) << 0) 41 42 #define DSI_DPI_COLOR_CODING 0x10 43 #define EN18_LOOSELY BIT(8) 44 #define DPI_COLOR_CODING_16BIT_1 0x0 45 #define DPI_COLOR_CODING_16BIT_2 0x1 46 #define DPI_COLOR_CODING_16BIT_3 0x2 47 #define DPI_COLOR_CODING_18BIT_1 0x3 48 #define DPI_COLOR_CODING_18BIT_2 0x4 49 #define DPI_COLOR_CODING_24BIT 0x5 50 51 #define DSI_DPI_CFG_POL 0x14 52 #define COLORM_ACTIVE_LOW BIT(4) 53 #define SHUTD_ACTIVE_LOW BIT(3) 54 #define HSYNC_ACTIVE_LOW BIT(2) 55 #define VSYNC_ACTIVE_LOW BIT(1) 56 #define DATAEN_ACTIVE_LOW BIT(0) 57 58 #define DSI_DPI_LP_CMD_TIM 0x18 59 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) 60 #define INVACT_LPCMD_TIME(p) ((p) & 0xff) 61 62 #define DSI_DBI_VCID 0x1c 63 #define DBI_VCID(x) UPDATE(x, 1, 0) 64 #define DSI_DBI_CFG 0x20 65 #define DSI_DBI_CMDSIZE 0x28 66 67 #define DSI_PCKHDL_CFG 0x2c 68 #define CRC_RX_EN BIT(4) 69 #define ECC_RX_EN BIT(3) 70 #define BTA_EN BIT(2) 71 #define EOTP_RX_EN BIT(1) 72 #define EOTP_TX_EN BIT(0) 73 #define DSI_MODE_CFG 0x34 74 #define CMD_VIDEO_MODE BIT(0) 75 #define COMMAND_MODE BIT(0) 76 #define VIDEO_MODE 0 77 #define DSI_VID_MODE_CFG 0x38 78 #define VPG_EN BIT(16) 79 #define LP_CMD_EN BIT(15) 80 #define FRAME_BTA_ACK BIT(14) 81 #define LP_HFP_EN BIT(13) 82 #define LP_HBP_EN BIT(12) 83 #define LP_VACT_EN BIT(11) 84 #define LP_VFP_EN BIT(10) 85 #define LP_VBP_EN BIT(9) 86 #define LP_VSA_EN BIT(8) 87 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0 88 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1 89 #define VID_MODE_TYPE_BURST 0x2 90 91 #define DSI_VID_PKT_SIZE 0x3c 92 #define VID_PKT_SIZE(p) (((p) & 0x3fff) << 0) 93 #define VID_PKT_MAX_SIZE 0x3fff 94 95 #define DSI_VID_NUM_CHUMKS 0x40 96 #define DSI_VID_NULL_PKT_SIZE 0x44 97 #define DSI_VID_HSA_TIME 0x48 98 #define DSI_VID_HBP_TIME 0x4c 99 #define DSI_VID_HLINE_TIME 0x50 100 #define DSI_VID_VSA_LINES 0x54 101 #define DSI_VID_VBP_LINES 0x58 102 #define DSI_VID_VFP_LINES 0x5c 103 #define DSI_VID_VACTIVE_LINES 0x60 104 #define DSI_EDPI_CMD_SIZE 0x64 105 #define DSI_CMD_MODE_CFG 0x68 106 #define MAX_RD_PKT_SIZE BIT(24) 107 #define DCS_LW_TX BIT(19) 108 #define DCS_SR_0P_TX BIT(18) 109 #define DCS_SW_1P_TX BIT(17) 110 #define DCS_SW_0P_TX BIT(16) 111 #define GEN_LW_TX BIT(14) 112 #define GEN_SR_2P_TX BIT(13) 113 #define GEN_SR_1P_TX BIT(12) 114 #define GEN_SR_0P_TX BIT(11) 115 #define GEN_SW_2P_TX BIT(10) 116 #define GEN_SW_1P_TX BIT(9) 117 #define GEN_SW_0P_TX BIT(8) 118 #define ACK_RQST_EN BIT(1) 119 #define TEAR_FX_EN BIT(0) 120 121 #define DSI_GEN_HDR 0x6c 122 #define GEN_HDATA(data) (((data) & 0xffff) << 8) 123 #define GEN_HDATA_MASK (0xffff << 8) 124 #define GEN_HTYPE(type) (((type) & 0xff) << 0) 125 #define GEN_HTYPE_MASK 0xff 126 127 #define DSI_GEN_PLD_DATA 0x70 128 129 #define DSI_CMD_PKT_STATUS 0x74 130 #define GEN_CMD_EMPTY BIT(0) 131 #define GEN_CMD_FULL BIT(1) 132 #define GEN_PLD_W_EMPTY BIT(2) 133 #define GEN_PLD_W_FULL BIT(3) 134 #define GEN_PLD_R_EMPTY BIT(4) 135 #define GEN_PLD_R_FULL BIT(5) 136 #define GEN_RD_CMD_BUSY BIT(6) 137 138 #define DSI_TO_CNT_CFG 0x78 139 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16) 140 #define LPRX_TO_CNT(p) ((p) & 0xffff) 141 142 #define DSI_BTA_TO_CNT 0x8c 143 #define DSI_LPCLK_CTRL 0x94 144 #define AUTO_CLKLANE_CTRL BIT(1) 145 #define PHY_TXREQUESTCLKHS BIT(0) 146 147 #define DSI_PHY_TMR_LPCLK_CFG 0x98 148 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16) 149 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff) 150 151 #define DSI_PHY_TMR_CFG 0x9c 152 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24) 153 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16) 154 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff) 155 156 #define DSI_PHY_RSTZ 0xa0 157 #define PHY_ENFORCEPLL BIT(3) 158 #define PHY_ENABLECLK BIT(2) 159 #define PHY_RSTZ BIT(1) 160 #define PHY_SHUTDOWNZ BIT(0) 161 162 #define DSI_PHY_IF_CFG 0xa4 163 #define N_LANES(n) ((((n) - 1) & 0x3) << 0) 164 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 165 166 #define DSI_PHY_STATUS 0xb0 167 #define PHY_STOPSTATE0LANE BIT(4) 168 #define PHY_STOPSTATECLKLANE BIT(2) 169 #define PHY_LOCK BIT(0) 170 #define PHY_STOPSTATELANE (PHY_STOPSTATE0LANE | \ 171 PHY_STOPSTATECLKLANE) 172 173 #define DSI_PHY_TST_CTRL0 0xb4 174 #define PHY_TESTCLK BIT(1) 175 #define PHY_TESTCLR BIT(0) 176 177 #define DSI_PHY_TST_CTRL1 0xb8 178 #define PHY_TESTEN BIT(16) 179 #define PHY_TESTDOUT_SHIFT 8 180 #define PHY_TESTDIN_MASK GENMASK(7, 0) 181 #define PHY_TESTDIN(x) UPDATE(x, 7, 0) 182 183 #define DSI_INT_ST0 0xbc 184 #define DSI_INT_ST1 0xc0 185 #define DSI_INT_MSK0 0xc4 186 #define DSI_INT_MSK1 0xc8 187 188 #define PHY_STATUS_TIMEOUT_US 10000 189 #define CMD_PKT_STATUS_TIMEOUT_US 20000 190 191 /* Test Code: 0x44 (HS RX Control of Lane 0) */ 192 #define HSFREQRANGE(x) UPDATE(x, 6, 1) 193 /* Test Code: 0x17 (PLL Input Divider Ratio) */ 194 #define INPUT_DIV(x) UPDATE(x, 6, 0) 195 /* Test Code: 0x18 (PLL Loop Divider Ratio) */ 196 #define FEEDBACK_DIV_LO(x) UPDATE(x, 4, 0) 197 #define FEEDBACK_DIV_HI(x) (BIT(7) | UPDATE(x, 3, 0)) 198 199 #define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 10) | ((lsb) << 5) | (msb)) 200 201 enum grf_reg_fields { 202 DPIUPDATECFG, 203 DPISHUTDN, 204 DPICOLORM, 205 VOPSEL, 206 TURNREQUEST, 207 TURNDISABLE, 208 SKEWCALHS, 209 FORCETXSTOPMODE, 210 FORCERXMODE, 211 ENABLE_N, 212 MASTERSLAVEZ, 213 ENABLECLK, 214 BASEDIR, 215 MAX_FIELDS, 216 }; 217 218 struct dw_mipi_dsi_plat_data { 219 const u32 *dsi0_grf_reg_fields; 220 const u32 *dsi1_grf_reg_fields; 221 unsigned long max_bit_rate_per_lane; 222 }; 223 224 struct mipi_dphy { 225 /* Non-SNPS PHY */ 226 struct rockchip_phy *phy; 227 228 u16 input_div; 229 u16 feedback_div; 230 }; 231 232 struct dw_mipi_dsi { 233 struct udevice *dev; 234 void *base; 235 void *grf; 236 int id; 237 struct dw_mipi_dsi *master; 238 struct dw_mipi_dsi *slave; 239 bool prepared; 240 241 unsigned int lane_mbps; /* per lane */ 242 u32 channel; 243 u32 lanes; 244 u32 format; 245 u32 mode_flags; 246 struct mipi_dphy dphy; 247 struct drm_display_mode mode; 248 249 const struct dw_mipi_dsi_plat_data *pdata; 250 }; 251 252 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) 253 { 254 writel(val, dsi->base + reg); 255 } 256 257 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) 258 { 259 return readl(dsi->base + reg); 260 } 261 262 static inline void dsi_update_bits(struct dw_mipi_dsi *dsi, 263 u32 reg, u32 mask, u32 val) 264 { 265 u32 orig, tmp; 266 267 orig = dsi_read(dsi, reg); 268 tmp = orig & ~mask; 269 tmp |= val & mask; 270 dsi_write(dsi, reg, tmp); 271 } 272 273 static void grf_field_write(struct dw_mipi_dsi *dsi, enum grf_reg_fields index, 274 unsigned int val) 275 { 276 const u32 field = dsi->id ? dsi->pdata->dsi1_grf_reg_fields[index] : 277 dsi->pdata->dsi0_grf_reg_fields[index]; 278 u16 reg; 279 u8 msb, lsb; 280 281 if (!field) 282 return; 283 284 reg = (field >> 10) & 0x3ffff; 285 lsb = (field >> 5) & 0x1f; 286 msb = (field >> 0) & 0x1f; 287 288 rk_clrsetreg(dsi->grf + reg, GENMASK(msb, lsb), val << lsb); 289 } 290 291 static inline void dpishutdn_assert(struct dw_mipi_dsi *dsi) 292 { 293 grf_field_write(dsi, DPISHUTDN, 1); 294 } 295 296 static inline void dpishutdn_deassert(struct dw_mipi_dsi *dsi) 297 { 298 grf_field_write(dsi, DPISHUTDN, 0); 299 } 300 301 static int genif_wait_w_pld_fifo_not_full(struct dw_mipi_dsi *dsi) 302 { 303 u32 sts; 304 int ret; 305 306 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 307 sts, !(sts & GEN_PLD_W_FULL), 308 CMD_PKT_STATUS_TIMEOUT_US); 309 if (ret < 0) { 310 printf("generic write payload fifo is full\n"); 311 return ret; 312 } 313 314 return 0; 315 } 316 317 static int genif_wait_cmd_fifo_not_full(struct dw_mipi_dsi *dsi) 318 { 319 u32 sts; 320 int ret; 321 322 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 323 sts, !(sts & GEN_CMD_FULL), 324 CMD_PKT_STATUS_TIMEOUT_US); 325 if (ret < 0) { 326 printf("generic write cmd fifo is full\n"); 327 return ret; 328 } 329 330 return 0; 331 } 332 333 static int genif_wait_write_fifo_empty(struct dw_mipi_dsi *dsi) 334 { 335 u32 sts; 336 u32 mask; 337 int ret; 338 339 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 340 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 341 sts, (sts & mask) == mask, 342 CMD_PKT_STATUS_TIMEOUT_US); 343 if (ret < 0) { 344 printf("generic write fifo is full\n"); 345 return ret; 346 } 347 348 return 0; 349 } 350 351 static inline void mipi_dphy_enableclk_assert(struct dw_mipi_dsi *dsi) 352 { 353 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK); 354 udelay(1); 355 } 356 357 static inline void mipi_dphy_enableclk_deassert(struct dw_mipi_dsi *dsi) 358 { 359 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, 0); 360 udelay(1); 361 } 362 363 static inline void mipi_dphy_shutdownz_assert(struct dw_mipi_dsi *dsi) 364 { 365 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, 0); 366 udelay(1); 367 } 368 369 static inline void mipi_dphy_shutdownz_deassert(struct dw_mipi_dsi *dsi) 370 { 371 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, PHY_SHUTDOWNZ); 372 udelay(1); 373 } 374 375 static inline void mipi_dphy_rstz_assert(struct dw_mipi_dsi *dsi) 376 { 377 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, 0); 378 udelay(1); 379 } 380 381 static inline void mipi_dphy_rstz_deassert(struct dw_mipi_dsi *dsi) 382 { 383 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, PHY_RSTZ); 384 udelay(1); 385 } 386 387 static inline void testif_testclk_assert(struct dw_mipi_dsi *dsi) 388 { 389 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK); 390 udelay(1); 391 } 392 393 static inline void testif_testclk_deassert(struct dw_mipi_dsi *dsi) 394 { 395 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK, 0); 396 udelay(1); 397 } 398 399 static inline void testif_testclr_assert(struct dw_mipi_dsi *dsi) 400 { 401 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR, PHY_TESTCLR); 402 udelay(1); 403 } 404 405 static inline void testif_testclr_deassert(struct dw_mipi_dsi *dsi) 406 { 407 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR, 0); 408 udelay(1); 409 } 410 411 static inline void testif_testen_assert(struct dw_mipi_dsi *dsi) 412 { 413 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN, PHY_TESTEN); 414 udelay(1); 415 } 416 417 static inline void testif_testen_deassert(struct dw_mipi_dsi *dsi) 418 { 419 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN, 0); 420 udelay(1); 421 } 422 423 static inline void testif_set_data(struct dw_mipi_dsi *dsi, u8 data) 424 { 425 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, 426 PHY_TESTDIN_MASK, PHY_TESTDIN(data)); 427 udelay(1); 428 } 429 430 static inline u8 testif_get_data(struct dw_mipi_dsi *dsi) 431 { 432 return dsi_read(dsi, DSI_PHY_TST_CTRL1) >> PHY_TESTDOUT_SHIFT; 433 } 434 435 static void testif_test_code_write(struct dw_mipi_dsi *dsi, u8 test_code) 436 { 437 testif_testclk_assert(dsi); 438 testif_set_data(dsi, test_code); 439 testif_testen_assert(dsi); 440 testif_testclk_deassert(dsi); 441 testif_testen_deassert(dsi); 442 } 443 444 static void testif_test_data_write(struct dw_mipi_dsi *dsi, u8 test_data) 445 { 446 testif_testclk_deassert(dsi); 447 testif_set_data(dsi, test_data); 448 testif_testclk_assert(dsi); 449 } 450 451 static void testif_write(struct dw_mipi_dsi *dsi, u8 test_code, u8 test_data) 452 { 453 testif_test_code_write(dsi, test_code); 454 testif_test_data_write(dsi, test_data); 455 456 dev_dbg(dsi->dev, 457 "test_code=0x%02x, test_data=0x%02x, monitor_data=0x%02x\n", 458 test_code, test_data, testif_get_data(dsi)); 459 } 460 461 static int mipi_dphy_power_on(struct dw_mipi_dsi *dsi) 462 { 463 u32 mask, val; 464 int ret; 465 466 mipi_dphy_shutdownz_deassert(dsi); 467 mipi_dphy_rstz_deassert(dsi); 468 mdelay(2); 469 470 if (dsi->dphy.phy) { 471 rockchip_phy_set_mode(dsi->dphy.phy, PHY_MODE_VIDEO_MIPI); 472 rockchip_phy_power_on(dsi->dphy.phy); 473 } 474 475 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 476 val, val & PHY_LOCK, PHY_STATUS_TIMEOUT_US); 477 if (ret < 0) { 478 dev_err(dsi->dev, "PHY is not locked\n"); 479 return ret; 480 } 481 482 udelay(200); 483 484 mask = PHY_STOPSTATELANE; 485 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 486 val, (val & mask) == mask, 487 PHY_STATUS_TIMEOUT_US); 488 if (ret < 0) { 489 dev_err(dsi->dev, "lane module is not in stop state\n"); 490 return ret; 491 } 492 493 udelay(10); 494 495 return 0; 496 } 497 498 static void dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) 499 { 500 /* Table 5-1 Frequency Ranges */ 501 const struct { 502 unsigned long max_lane_mbps; 503 u8 hsfreqrange; 504 } hsfreqrange_table[] = { 505 { 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01}, 506 { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12}, 507 { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23}, 508 { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15}, 509 { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07}, 510 { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09}, 511 { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a}, 512 {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b}, 513 {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c}, 514 {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c} 515 }; 516 u8 hsfreqrange, counter; 517 unsigned int index, txbyteclkhs; 518 u16 n, m; 519 520 for (index = 0; index < ARRAY_SIZE(hsfreqrange_table); index++) 521 if (dsi->lane_mbps <= hsfreqrange_table[index].max_lane_mbps) 522 break; 523 524 if (index == ARRAY_SIZE(hsfreqrange_table)) 525 --index; 526 527 hsfreqrange = hsfreqrange_table[index].hsfreqrange; 528 testif_write(dsi, 0x44, HSFREQRANGE(hsfreqrange)); 529 530 txbyteclkhs = dsi->lane_mbps >> 3; 531 counter = txbyteclkhs * 60 / 1000; 532 testif_write(dsi, 0x60, 0x80 | counter); 533 testif_write(dsi, 0x70, 0x80 | counter); 534 535 n = dsi->dphy.input_div - 1; 536 m = dsi->dphy.feedback_div - 1; 537 testif_write(dsi, 0x19, 0x30); 538 testif_write(dsi, 0x17, INPUT_DIV(n)); 539 testif_write(dsi, 0x18, FEEDBACK_DIV_LO(m)); 540 testif_write(dsi, 0x18, FEEDBACK_DIV_HI(m >> 5)); 541 } 542 543 static unsigned long dw_mipi_dsi_get_lane_rate(struct dw_mipi_dsi *dsi) 544 { 545 const struct drm_display_mode *mode = &dsi->mode; 546 unsigned long max_lane_rate = dsi->pdata->max_bit_rate_per_lane; 547 unsigned long lane_rate; 548 unsigned int value; 549 int bpp, lanes; 550 u64 tmp; 551 552 /* optional override of the desired bandwidth */ 553 value = dev_read_u32_default(dsi->dev, "rockchip,lane-rate", 0); 554 if (value > 0) 555 return value * 1000 * 1000; 556 557 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 558 if (bpp < 0) 559 bpp = 24; 560 561 lanes = dsi->slave ? dsi->lanes * 2 : dsi->lanes; 562 tmp = (u64)mode->clock * 1000 * bpp; 563 do_div(tmp, lanes); 564 565 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */ 566 tmp *= 10; 567 do_div(tmp, 9); 568 569 if (tmp > max_lane_rate) 570 lane_rate = max_lane_rate; 571 else 572 lane_rate = tmp; 573 574 return lane_rate; 575 } 576 577 static void dw_mipi_dsi_set_pll(struct dw_mipi_dsi *dsi, unsigned long rate) 578 { 579 unsigned long fin, fout; 580 unsigned long fvco_min, fvco_max, best_freq = 984000000; 581 u8 min_prediv, max_prediv; 582 u8 _prediv, best_prediv = 2; 583 u16 _fbdiv, best_fbdiv = 82; 584 u32 min_delta = ~0U; 585 586 fin = 24000000; 587 fout = rate; 588 589 /* 5Mhz < Fref / N < 40MHz, 80MHz < Fvco < 1500Mhz */ 590 min_prediv = DIV_ROUND_UP(fin, 40000000); 591 max_prediv = fin / 5000000; 592 fvco_min = 80000000; 593 fvco_max = 1500000000; 594 595 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 596 u64 tmp, _fout; 597 u32 delta; 598 599 /* Fvco = Fref * M / N */ 600 tmp = (u64)fout * _prediv; 601 do_div(tmp, fin); 602 _fbdiv = tmp; 603 604 /* 605 * Due to the use of a "by 2 pre-scaler," the range of the 606 * feedback multiplication value M is limited to even division 607 * numbers, and m must be greater than 12, less than 1000. 608 */ 609 if (_fbdiv <= 12 || _fbdiv >= 1000) 610 continue; 611 612 if (_fbdiv % 2) 613 ++_fbdiv; 614 615 _fout = (u64)_fbdiv * fin; 616 do_div(_fout, _prediv); 617 618 if (_fout < fvco_min || _fout > fvco_max) 619 continue; 620 621 delta = abs(fout - _fout); 622 if (!delta) { 623 best_prediv = _prediv; 624 best_fbdiv = _fbdiv; 625 best_freq = _fout; 626 break; 627 } else if (delta < min_delta) { 628 best_prediv = _prediv; 629 best_fbdiv = _fbdiv; 630 best_freq = _fout; 631 min_delta = delta; 632 } 633 } 634 635 dsi->lane_mbps = best_freq / 1000 / 1000; 636 dsi->dphy.input_div = best_prediv; 637 dsi->dphy.feedback_div = best_fbdiv; 638 if (dsi->slave) { 639 dsi->slave->lane_mbps = dsi->lane_mbps; 640 dsi->slave->dphy.input_div = dsi->dphy.input_div; 641 dsi->slave->dphy.feedback_div = dsi->dphy.feedback_div; 642 } 643 if (dsi->master) { 644 dsi->master->lane_mbps = dsi->lane_mbps; 645 dsi->master->dphy.input_div = dsi->dphy.input_div; 646 dsi->master->dphy.feedback_div = dsi->dphy.feedback_div; 647 } 648 } 649 650 static int dw_mipi_dsi_read_from_fifo(struct dw_mipi_dsi *dsi, 651 const struct mipi_dsi_msg *msg) 652 { 653 u8 *payload = msg->rx_buf; 654 u16 length; 655 u32 val; 656 int ret; 657 658 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 659 val, !(val & GEN_RD_CMD_BUSY), 5000); 660 if (ret) { 661 printf("entire response isn't stored in the FIFO\n"); 662 return ret; 663 } 664 665 /* Receive payload */ 666 for (length = msg->rx_len; length; length -= 4) { 667 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 668 val, !(val & GEN_PLD_R_EMPTY), 5000); 669 if (ret) { 670 printf("Read payload FIFO is empty\n"); 671 return ret; 672 } 673 674 val = dsi_read(dsi, DSI_GEN_PLD_DATA); 675 676 switch (length) { 677 case 3: 678 payload[2] = (val >> 16) & 0xff; 679 /* Fall through */ 680 case 2: 681 payload[1] = (val >> 8) & 0xff; 682 /* Fall through */ 683 case 1: 684 payload[0] = val & 0xff; 685 return 0; 686 } 687 688 payload[0] = (val >> 0) & 0xff; 689 payload[1] = (val >> 8) & 0xff; 690 payload[2] = (val >> 16) & 0xff; 691 payload[3] = (val >> 24) & 0xff; 692 payload += 4; 693 } 694 695 return 0; 696 } 697 698 static int dw_mipi_dsi_turn_on_peripheral(struct dw_mipi_dsi *dsi) 699 { 700 dpishutdn_assert(dsi); 701 udelay(20); 702 dpishutdn_deassert(dsi); 703 704 return 0; 705 } 706 707 static int dw_mipi_dsi_shutdown_peripheral(struct dw_mipi_dsi *dsi) 708 { 709 dpishutdn_deassert(dsi); 710 udelay(20); 711 dpishutdn_assert(dsi); 712 713 return 0; 714 } 715 716 static ssize_t dw_mipi_dsi_transfer(struct dw_mipi_dsi *dsi, 717 const struct mipi_dsi_msg *msg) 718 { 719 struct mipi_dsi_packet packet; 720 int ret; 721 int val; 722 723 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { 724 dsi_update_bits(dsi, DSI_VID_MODE_CFG, LP_CMD_EN, LP_CMD_EN); 725 dsi_update_bits(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS, 0); 726 } else { 727 dsi_update_bits(dsi, DSI_VID_MODE_CFG, LP_CMD_EN, 0); 728 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 729 PHY_TXREQUESTCLKHS, PHY_TXREQUESTCLKHS); 730 } 731 732 switch (msg->type) { 733 case MIPI_DSI_SHUTDOWN_PERIPHERAL: 734 return dw_mipi_dsi_shutdown_peripheral(dsi); 735 case MIPI_DSI_TURN_ON_PERIPHERAL: 736 return dw_mipi_dsi_turn_on_peripheral(dsi); 737 case MIPI_DSI_DCS_SHORT_WRITE: 738 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_0P_TX, 739 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 740 DCS_SW_0P_TX : 0); 741 break; 742 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 743 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_1P_TX, 744 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 745 DCS_SW_1P_TX : 0); 746 break; 747 case MIPI_DSI_DCS_LONG_WRITE: 748 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX, 749 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 750 DCS_LW_TX : 0); 751 break; 752 case MIPI_DSI_DCS_READ: 753 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SR_0P_TX, 754 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 755 DCS_SR_0P_TX : 0); 756 break; 757 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: 758 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, MAX_RD_PKT_SIZE, 759 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 760 MAX_RD_PKT_SIZE : 0); 761 break; 762 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 763 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_0P_TX, 764 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 765 GEN_SW_0P_TX : 0); 766 break; 767 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 768 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_1P_TX, 769 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 770 GEN_SW_1P_TX : 0); 771 break; 772 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 773 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_2P_TX, 774 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 775 GEN_SW_2P_TX : 0); 776 break; 777 case MIPI_DSI_GENERIC_LONG_WRITE: 778 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_LW_TX, 779 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 780 GEN_LW_TX : 0); 781 break; 782 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 783 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_0P_TX, 784 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 785 GEN_SR_0P_TX : 0); 786 break; 787 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 788 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_1P_TX, 789 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 790 GEN_SR_1P_TX : 0); 791 break; 792 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 793 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_2P_TX, 794 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 795 GEN_SR_2P_TX : 0); 796 break; 797 default: 798 return -EINVAL; 799 } 800 801 if (msg->flags & MIPI_DSI_MSG_REQ_ACK) 802 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, 803 ACK_RQST_EN, ACK_RQST_EN); 804 805 /* create a packet to the DSI protocol */ 806 ret = mipi_dsi_create_packet(&packet, msg); 807 if (ret) { 808 printf("failed to create packet: %d\n", ret); 809 return ret; 810 } 811 812 /* Send payload */ 813 while (DIV_ROUND_UP(packet.payload_length, 4)) { 814 /* 815 * Alternatively, you can always keep the FIFO 816 * nearly full by monitoring the FIFO state until 817 * it is not full, and then writea single word of data. 818 * This solution is more resource consuming 819 * but it simultaneously avoids FIFO starvation, 820 * making it possible to use FIFO sizes smaller than 821 * the amount of data of the longest packet to be written. 822 */ 823 ret = genif_wait_w_pld_fifo_not_full(dsi); 824 if (ret) 825 return ret; 826 827 if (packet.payload_length < 4) { 828 /* send residu payload */ 829 val = 0; 830 memcpy(&val, packet.payload, packet.payload_length); 831 dsi_write(dsi, DSI_GEN_PLD_DATA, val); 832 packet.payload_length = 0; 833 } else { 834 val = get_unaligned_le32(packet.payload); 835 dsi_write(dsi, DSI_GEN_PLD_DATA, val); 836 packet.payload += 4; 837 packet.payload_length -= 4; 838 } 839 } 840 841 ret = genif_wait_cmd_fifo_not_full(dsi); 842 if (ret) 843 return ret; 844 845 /* Send packet header */ 846 val = get_unaligned_le32(packet.header); 847 dsi_write(dsi, DSI_GEN_HDR, val); 848 849 ret = genif_wait_write_fifo_empty(dsi); 850 if (ret) 851 return ret; 852 853 if (msg->rx_len) { 854 ret = dw_mipi_dsi_read_from_fifo(dsi, msg); 855 if (ret < 0) 856 return ret; 857 } 858 859 if (dsi->slave) { 860 ret = dw_mipi_dsi_transfer(dsi->slave, msg); 861 if (ret < 0) 862 return ret; 863 } 864 865 return msg->rx_len ? msg->rx_len : msg->tx_len; 866 } 867 868 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) 869 { 870 u32 val = LP_VACT_EN | LP_VFP_EN | LP_VBP_EN | LP_VSA_EN | 871 LP_HFP_EN | LP_HBP_EN; 872 873 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) 874 val &= ~LP_HFP_EN; 875 876 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) 877 val &= ~LP_HBP_EN; 878 879 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 880 val |= VID_MODE_TYPE_BURST; 881 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 882 val |= VID_MODE_TYPE_BURST_SYNC_PULSES; 883 else 884 val |= VID_MODE_TYPE_BURST_SYNC_EVENTS; 885 886 dsi_write(dsi, DSI_VID_MODE_CFG, val); 887 888 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 889 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 890 AUTO_CLKLANE_CTRL, AUTO_CLKLANE_CTRL); 891 } 892 893 static void dw_mipi_dsi_enable(struct dw_mipi_dsi *dsi) 894 { 895 const struct drm_display_mode *mode = &dsi->mode; 896 897 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 898 PHY_TXREQUESTCLKHS, PHY_TXREQUESTCLKHS); 899 900 dsi_write(dsi, DSI_PWR_UP, RESET); 901 902 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 903 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, VIDEO_MODE); 904 } else { 905 dsi_write(dsi, DSI_DBI_VCID, DBI_VCID(dsi->channel)); 906 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX, 0); 907 dsi_write(dsi, DSI_EDPI_CMD_SIZE, mode->hdisplay); 908 dsi_update_bits(dsi, DSI_MODE_CFG, 909 CMD_VIDEO_MODE, COMMAND_MODE); 910 } 911 912 dsi_write(dsi, DSI_PWR_UP, POWERUP); 913 914 if (dsi->slave) 915 dw_mipi_dsi_enable(dsi->slave); 916 } 917 918 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) 919 { 920 dsi_write(dsi, DSI_PWR_UP, RESET); 921 dsi_write(dsi, DSI_LPCLK_CTRL, 0); 922 dsi_write(dsi, DSI_EDPI_CMD_SIZE, 0); 923 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, COMMAND_MODE); 924 dsi_write(dsi, DSI_PWR_UP, POWERUP); 925 926 if (dsi->slave) 927 dw_mipi_dsi_disable(dsi->slave); 928 } 929 930 static void dw_mipi_dsi_post_disable(struct dw_mipi_dsi *dsi) 931 { 932 if (!dsi->prepared) 933 return; 934 935 if (dsi->master) 936 dw_mipi_dsi_post_disable(dsi->master); 937 938 dsi_write(dsi, DSI_PWR_UP, RESET); 939 dsi_write(dsi, DSI_PHY_RSTZ, 0); 940 941 dsi->prepared = false; 942 943 if (dsi->slave) 944 dw_mipi_dsi_post_disable(dsi->slave); 945 } 946 947 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) 948 { 949 u32 esc_clk_div; 950 951 dsi_write(dsi, DSI_PWR_UP, RESET); 952 953 /* The maximum value of the escape clock frequency is 20MHz */ 954 esc_clk_div = DIV_ROUND_UP(dsi->lane_mbps >> 3, 20); 955 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) | 956 TX_ESC_CLK_DIVIDSION(esc_clk_div)); 957 } 958 959 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, 960 struct drm_display_mode *mode) 961 { 962 u32 val = 0, color = 0; 963 964 switch (dsi->format) { 965 case MIPI_DSI_FMT_RGB888: 966 color = DPI_COLOR_CODING_24BIT; 967 break; 968 case MIPI_DSI_FMT_RGB666: 969 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY; 970 break; 971 case MIPI_DSI_FMT_RGB666_PACKED: 972 color = DPI_COLOR_CODING_18BIT_1; 973 break; 974 case MIPI_DSI_FMT_RGB565: 975 color = DPI_COLOR_CODING_16BIT_1; 976 break; 977 } 978 979 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 980 val |= VSYNC_ACTIVE_LOW; 981 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 982 val |= HSYNC_ACTIVE_LOW; 983 984 dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel)); 985 dsi_write(dsi, DSI_DPI_COLOR_CODING, color); 986 dsi_write(dsi, DSI_DPI_CFG_POL, val); 987 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4) 988 | INVACT_LPCMD_TIME(4)); 989 } 990 991 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi) 992 { 993 u32 val = CRC_RX_EN | ECC_RX_EN | BTA_EN | EOTP_TX_EN; 994 995 if (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 996 val &= ~EOTP_TX_EN; 997 998 dsi_write(dsi, DSI_PCKHDL_CFG, val); 999 } 1000 1001 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, 1002 struct drm_display_mode *mode) 1003 { 1004 dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay)); 1005 } 1006 1007 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) 1008 { 1009 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000)); 1010 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); 1011 } 1012 1013 /* Get lane byte clock cycles. */ 1014 static int dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, 1015 u32 hcomponent) 1016 { 1017 u32 lbcc; 1018 1019 lbcc = hcomponent * dsi->lane_mbps * 1000 / 8; 1020 1021 if (!dsi->mode.clock) 1022 return 0; 1023 1024 return DIV_ROUND_CLOSEST(lbcc, dsi->mode.clock); 1025 } 1026 1027 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi) 1028 { 1029 int htotal, hsa, hbp, lbcc; 1030 struct drm_display_mode *mode = &dsi->mode; 1031 1032 htotal = mode->htotal; 1033 hsa = mode->hsync_end - mode->hsync_start; 1034 hbp = mode->htotal - mode->hsync_end; 1035 1036 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal); 1037 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); 1038 1039 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa); 1040 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); 1041 1042 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp); 1043 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); 1044 } 1045 1046 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi) 1047 { 1048 u32 vactive, vsa, vfp, vbp; 1049 struct drm_display_mode *mode = &dsi->mode; 1050 1051 vactive = mode->vdisplay; 1052 vsa = mode->vsync_end - mode->vsync_start; 1053 vfp = mode->vsync_start - mode->vdisplay; 1054 vbp = mode->vtotal - mode->vsync_end; 1055 1056 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); 1057 dsi_write(dsi, DSI_VID_VSA_LINES, vsa); 1058 dsi_write(dsi, DSI_VID_VFP_LINES, vfp); 1059 dsi_write(dsi, DSI_VID_VBP_LINES, vbp); 1060 } 1061 1062 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) 1063 { 1064 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14) 1065 | PHY_LP2HS_TIME(0x10) | MAX_RD_TIME(10000)); 1066 1067 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40) 1068 | PHY_CLKLP2HS_TIME(0x40)); 1069 } 1070 1071 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) 1072 { 1073 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) | 1074 N_LANES(dsi->lanes)); 1075 } 1076 1077 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) 1078 { 1079 dsi_read(dsi, DSI_INT_ST0); 1080 dsi_read(dsi, DSI_INT_ST1); 1081 dsi_write(dsi, DSI_INT_MSK0, 0); 1082 dsi_write(dsi, DSI_INT_MSK1, 0); 1083 } 1084 1085 static int dw_mipi_dsi_connector_init(struct display_state *state) 1086 { 1087 struct connector_state *conn_state = &state->conn_state; 1088 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1089 1090 dsi->dphy.phy = conn_state->phy; 1091 1092 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 1093 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 1094 conn_state->type = DRM_MODE_CONNECTOR_DSI; 1095 conn_state->output_if |= 1096 dsi->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0; 1097 1098 #ifndef CONFIG_ROCKCHIP_RK3568 1099 if (dsi->id) { 1100 struct udevice *dev; 1101 int ret; 1102 1103 ret = uclass_get_device_by_name(UCLASS_DISPLAY, "dsi@ff960000", 1104 &dev); 1105 if (ret) 1106 return ret; 1107 1108 dsi->master = dev_get_priv(dev); 1109 if (!dsi->master) 1110 return -ENODEV; 1111 1112 conn_state->output_flags = ROCKCHIP_OUTPUT_DATA_SWAP; 1113 } 1114 #endif 1115 1116 if (dsi->lanes > 4) { 1117 struct udevice *dev; 1118 int ret; 1119 1120 ret = uclass_get_device_by_name(UCLASS_DISPLAY, 1121 #if defined(CONFIG_ROCKCHIP_RK3288) 1122 "dsi@ff964000", 1123 #elif defined(CONFIG_ROCKCHIP_RK3399) 1124 "dsi@ff968000", 1125 #else 1126 "dsi@fe070000", 1127 #endif 1128 &dev); 1129 if (ret) 1130 return ret; 1131 1132 dsi->slave = dev_get_priv(dev); 1133 if (!dsi->slave) 1134 return -ENODEV; 1135 1136 dsi->lanes /= 2; 1137 dsi->slave->lanes = dsi->lanes; 1138 dsi->slave->format = dsi->format; 1139 dsi->slave->mode_flags = dsi->mode_flags; 1140 dsi->slave->channel = dsi->channel; 1141 conn_state->output_flags = 1142 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; 1143 conn_state->output_if |= VOP_OUTPUT_IF_MIPI1; 1144 1145 #if defined(CONFIG_ROCKCHIP_RK3568) 1146 struct rockchip_phy *phy = NULL; 1147 struct udevice *phy_dev; 1148 1149 ret = uclass_get_device_by_phandle(UCLASS_PHY, dev, 1150 "phys", &phy_dev); 1151 if (ret) 1152 return -ENODEV; 1153 1154 phy = (struct rockchip_phy *)dev_get_driver_data(phy_dev); 1155 if (!phy) 1156 return -ENODEV; 1157 1158 dsi->slave->dphy.phy = phy; 1159 if (phy->funcs && phy->funcs->init) 1160 return phy->funcs->init(phy); 1161 #endif 1162 1163 } 1164 1165 return 0; 1166 } 1167 1168 static void dw_mipi_dsi_set_hs_clk(struct dw_mipi_dsi *dsi, unsigned long rate) 1169 { 1170 rate = rockchip_phy_set_pll(dsi->dphy.phy, rate); 1171 dsi->lane_mbps = rate / 1000 / 1000; 1172 } 1173 1174 static void dw_mipi_dsi_host_init(struct dw_mipi_dsi *dsi) 1175 { 1176 dw_mipi_dsi_init(dsi); 1177 dw_mipi_dsi_dpi_config(dsi, &dsi->mode); 1178 dw_mipi_dsi_packet_handler_config(dsi); 1179 dw_mipi_dsi_video_mode_config(dsi); 1180 dw_mipi_dsi_video_packet_config(dsi, &dsi->mode); 1181 dw_mipi_dsi_command_mode_config(dsi); 1182 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, COMMAND_MODE); 1183 dw_mipi_dsi_line_timer_config(dsi); 1184 dw_mipi_dsi_vertical_timing_config(dsi); 1185 dw_mipi_dsi_dphy_timing_config(dsi); 1186 dw_mipi_dsi_dphy_interface_config(dsi); 1187 dw_mipi_dsi_clear_err(dsi); 1188 } 1189 1190 static void dw_mipi_dsi_vop_routing(struct dw_mipi_dsi *dsi, int vop_id) 1191 { 1192 grf_field_write(dsi, VOPSEL, vop_id); 1193 1194 if (dsi->slave) 1195 grf_field_write(dsi->slave, VOPSEL, vop_id); 1196 } 1197 1198 static void mipi_dphy_init(struct dw_mipi_dsi *dsi) 1199 { 1200 u32 map[] = {0x0, 0x1, 0x3, 0x7, 0xf}; 1201 1202 mipi_dphy_enableclk_deassert(dsi); 1203 mipi_dphy_shutdownz_assert(dsi); 1204 mipi_dphy_rstz_assert(dsi); 1205 testif_testclr_assert(dsi); 1206 1207 /* Configures DPHY to work as a Master */ 1208 grf_field_write(dsi, MASTERSLAVEZ, 1); 1209 1210 /* Configures lane as TX */ 1211 grf_field_write(dsi, BASEDIR, 0); 1212 1213 /* Set all REQUEST inputs to zero */ 1214 grf_field_write(dsi, TURNREQUEST, 0); 1215 grf_field_write(dsi, TURNDISABLE, 0); 1216 grf_field_write(dsi, FORCETXSTOPMODE, 0); 1217 grf_field_write(dsi, FORCERXMODE, 0); 1218 udelay(1); 1219 1220 testif_testclr_deassert(dsi); 1221 1222 if (!dsi->dphy.phy) 1223 dw_mipi_dsi_phy_init(dsi); 1224 1225 /* Enable Data Lane Module */ 1226 grf_field_write(dsi, ENABLE_N, map[dsi->lanes]); 1227 1228 /* Enable Clock Lane Module */ 1229 grf_field_write(dsi, ENABLECLK, 1); 1230 1231 mipi_dphy_enableclk_assert(dsi); 1232 } 1233 1234 static void dw_mipi_dsi_pre_enable(struct dw_mipi_dsi *dsi) 1235 { 1236 if (dsi->prepared) 1237 return; 1238 1239 if (dsi->master) 1240 dw_mipi_dsi_pre_enable(dsi->master); 1241 1242 dw_mipi_dsi_host_init(dsi); 1243 mipi_dphy_init(dsi); 1244 mipi_dphy_power_on(dsi); 1245 dsi_write(dsi, DSI_PWR_UP, POWERUP); 1246 1247 dsi->prepared = true; 1248 1249 if (dsi->slave) 1250 dw_mipi_dsi_pre_enable(dsi->slave); 1251 } 1252 1253 static int dw_mipi_dsi_connector_prepare(struct display_state *state) 1254 { 1255 struct connector_state *conn_state = &state->conn_state; 1256 struct crtc_state *crtc_state = &state->crtc_state; 1257 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1258 unsigned long lane_rate; 1259 1260 memcpy(&dsi->mode, &conn_state->mode, sizeof(struct drm_display_mode)); 1261 if (dsi->slave) { 1262 dsi->mode.hdisplay /= 2; 1263 memcpy(&dsi->slave->mode, &dsi->mode, 1264 sizeof(struct drm_display_mode)); 1265 } 1266 1267 lane_rate = dw_mipi_dsi_get_lane_rate(dsi); 1268 if (dsi->dphy.phy) 1269 dw_mipi_dsi_set_hs_clk(dsi, lane_rate); 1270 else 1271 dw_mipi_dsi_set_pll(dsi, lane_rate); 1272 1273 if (dsi->slave && dsi->slave->dphy.phy) 1274 dw_mipi_dsi_set_hs_clk(dsi->slave, lane_rate); 1275 1276 printf("final DSI-Link bandwidth: %u Mbps x %d\n", 1277 dsi->lane_mbps, dsi->slave ? dsi->lanes * 2 : dsi->lanes); 1278 1279 dw_mipi_dsi_vop_routing(dsi, crtc_state->crtc_id); 1280 dw_mipi_dsi_pre_enable(dsi); 1281 1282 return 0; 1283 } 1284 1285 static void dw_mipi_dsi_connector_unprepare(struct display_state *state) 1286 { 1287 struct connector_state *conn_state = &state->conn_state; 1288 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1289 1290 dw_mipi_dsi_post_disable(dsi); 1291 } 1292 1293 static int dw_mipi_dsi_connector_enable(struct display_state *state) 1294 { 1295 struct connector_state *conn_state = &state->conn_state; 1296 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1297 1298 dw_mipi_dsi_enable(dsi); 1299 1300 return 0; 1301 } 1302 1303 static int dw_mipi_dsi_connector_disable(struct display_state *state) 1304 { 1305 struct connector_state *conn_state = &state->conn_state; 1306 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1307 1308 dw_mipi_dsi_disable(dsi); 1309 1310 return 0; 1311 } 1312 1313 static const struct rockchip_connector_funcs dw_mipi_dsi_connector_funcs = { 1314 .init = dw_mipi_dsi_connector_init, 1315 .prepare = dw_mipi_dsi_connector_prepare, 1316 .unprepare = dw_mipi_dsi_connector_unprepare, 1317 .enable = dw_mipi_dsi_connector_enable, 1318 .disable = dw_mipi_dsi_connector_disable, 1319 }; 1320 1321 static int dw_mipi_dsi_probe(struct udevice *dev) 1322 { 1323 struct dw_mipi_dsi *dsi = dev_get_priv(dev); 1324 const struct rockchip_connector *connector = 1325 (const struct rockchip_connector *)dev_get_driver_data(dev); 1326 const struct dw_mipi_dsi_plat_data *pdata = connector->data; 1327 int id; 1328 1329 dsi->base = dev_read_addr_ptr(dev); 1330 dsi->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1331 if (IS_ERR(dsi->grf)) 1332 return PTR_ERR(dsi->grf); 1333 1334 id = of_alias_get_id(ofnode_to_np(dev->node), "dsi"); 1335 if (id < 0) 1336 id = 0; 1337 1338 dsi->dev = dev; 1339 dsi->pdata = pdata; 1340 dsi->id = id; 1341 1342 return 0; 1343 } 1344 1345 static const u32 px30_dsi_grf_reg_fields[MAX_FIELDS] = { 1346 [DPIUPDATECFG] = GRF_REG_FIELD(0x0434, 7, 7), 1347 [DPICOLORM] = GRF_REG_FIELD(0x0434, 3, 3), 1348 [DPISHUTDN] = GRF_REG_FIELD(0x0434, 2, 2), 1349 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0438, 7, 10), 1350 [TURNDISABLE] = GRF_REG_FIELD(0x0438, 5, 5), 1351 [VOPSEL] = GRF_REG_FIELD(0x0438, 0, 0), 1352 }; 1353 1354 static const struct dw_mipi_dsi_plat_data px30_mipi_dsi_plat_data = { 1355 .dsi0_grf_reg_fields = px30_dsi_grf_reg_fields, 1356 .max_bit_rate_per_lane = 1000000000UL, 1357 }; 1358 1359 static const struct rockchip_connector px30_mipi_dsi_driver_data = { 1360 .funcs = &dw_mipi_dsi_connector_funcs, 1361 .data = &px30_mipi_dsi_plat_data, 1362 }; 1363 1364 static const u32 rk1808_dsi_grf_reg_fields[MAX_FIELDS] = { 1365 [MASTERSLAVEZ] = GRF_REG_FIELD(0x0440, 8, 8), 1366 [DPIUPDATECFG] = GRF_REG_FIELD(0x0440, 7, 7), 1367 [DPICOLORM] = GRF_REG_FIELD(0x0440, 3, 3), 1368 [DPISHUTDN] = GRF_REG_FIELD(0x0440, 2, 2), 1369 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0444, 7, 10), 1370 [FORCERXMODE] = GRF_REG_FIELD(0x0444, 6, 6), 1371 [TURNDISABLE] = GRF_REG_FIELD(0x0444, 5, 5), 1372 }; 1373 1374 static const struct dw_mipi_dsi_plat_data rk1808_mipi_dsi_plat_data = { 1375 .dsi0_grf_reg_fields = rk1808_dsi_grf_reg_fields, 1376 .max_bit_rate_per_lane = 2000000000UL, 1377 }; 1378 1379 static const struct rockchip_connector rk1808_mipi_dsi_driver_data = { 1380 .funcs = &dw_mipi_dsi_connector_funcs, 1381 .data = &rk1808_mipi_dsi_plat_data, 1382 }; 1383 1384 static const u32 rk3128_dsi_grf_reg_fields[MAX_FIELDS] = { 1385 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0150, 10, 13), 1386 [FORCERXMODE] = GRF_REG_FIELD(0x0150, 9, 9), 1387 [TURNDISABLE] = GRF_REG_FIELD(0x0150, 8, 8), 1388 [DPICOLORM] = GRF_REG_FIELD(0x0150, 5, 5), 1389 [DPISHUTDN] = GRF_REG_FIELD(0x0150, 4, 4), 1390 }; 1391 1392 static const struct dw_mipi_dsi_plat_data rk3128_mipi_dsi_plat_data = { 1393 .dsi0_grf_reg_fields = rk3128_dsi_grf_reg_fields, 1394 .max_bit_rate_per_lane = 1000000000UL, 1395 }; 1396 1397 static const struct rockchip_connector rk3128_mipi_dsi_driver_data = { 1398 .funcs = &dw_mipi_dsi_connector_funcs, 1399 .data = &rk3128_mipi_dsi_plat_data, 1400 }; 1401 1402 static const u32 rk3288_dsi0_grf_reg_fields[MAX_FIELDS] = { 1403 [DPICOLORM] = GRF_REG_FIELD(0x025c, 8, 8), 1404 [DPISHUTDN] = GRF_REG_FIELD(0x025c, 7, 7), 1405 [VOPSEL] = GRF_REG_FIELD(0x025c, 6, 6), 1406 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0264, 8, 11), 1407 [FORCERXMODE] = GRF_REG_FIELD(0x0264, 4, 7), 1408 [TURNDISABLE] = GRF_REG_FIELD(0x0264, 0, 3), 1409 [TURNREQUEST] = GRF_REG_FIELD(0x03a4, 8, 10), 1410 [DPIUPDATECFG] = GRF_REG_FIELD(0x03a8, 0, 0), 1411 }; 1412 1413 static const u32 rk3288_dsi1_grf_reg_fields[MAX_FIELDS] = { 1414 [DPICOLORM] = GRF_REG_FIELD(0x025c, 11, 11), 1415 [DPISHUTDN] = GRF_REG_FIELD(0x025c, 10, 10), 1416 [VOPSEL] = GRF_REG_FIELD(0x025c, 9, 9), 1417 [ENABLE_N] = GRF_REG_FIELD(0x0268, 12, 15), 1418 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0268, 8, 11), 1419 [FORCERXMODE] = GRF_REG_FIELD(0x0268, 4, 7), 1420 [TURNDISABLE] = GRF_REG_FIELD(0x0268, 0, 3), 1421 [BASEDIR] = GRF_REG_FIELD(0x027c, 15, 15), 1422 [MASTERSLAVEZ] = GRF_REG_FIELD(0x027c, 14, 14), 1423 [ENABLECLK] = GRF_REG_FIELD(0x027c, 12, 12), 1424 [TURNREQUEST] = GRF_REG_FIELD(0x03a4, 4, 7), 1425 [DPIUPDATECFG] = GRF_REG_FIELD(0x03a8, 1, 1), 1426 }; 1427 1428 static const struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_plat_data = { 1429 .dsi0_grf_reg_fields = rk3288_dsi0_grf_reg_fields, 1430 .dsi1_grf_reg_fields = rk3288_dsi1_grf_reg_fields, 1431 .max_bit_rate_per_lane = 1500000000UL, 1432 }; 1433 1434 static const struct rockchip_connector rk3288_mipi_dsi_driver_data = { 1435 .funcs = &dw_mipi_dsi_connector_funcs, 1436 .data = &rk3288_mipi_dsi_plat_data, 1437 }; 1438 1439 static const u32 rk3366_dsi_grf_reg_fields[MAX_FIELDS] = { 1440 [VOPSEL] = GRF_REG_FIELD(0x0400, 2, 2), 1441 [DPIUPDATECFG] = GRF_REG_FIELD(0x0410, 9, 9), 1442 [DPICOLORM] = GRF_REG_FIELD(0x0410, 3, 3), 1443 [DPISHUTDN] = GRF_REG_FIELD(0x0410, 2, 2), 1444 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0414, 7, 10), 1445 [FORCERXMODE] = GRF_REG_FIELD(0x0414, 6, 6), 1446 [TURNDISABLE] = GRF_REG_FIELD(0x0414, 5, 5), 1447 }; 1448 1449 static const struct dw_mipi_dsi_plat_data rk3366_mipi_dsi_plat_data = { 1450 .dsi0_grf_reg_fields = rk3366_dsi_grf_reg_fields, 1451 .max_bit_rate_per_lane = 1000000000UL, 1452 }; 1453 1454 static const struct rockchip_connector rk3366_mipi_dsi_driver_data = { 1455 .funcs = &dw_mipi_dsi_connector_funcs, 1456 .data = &rk3366_mipi_dsi_plat_data, 1457 }; 1458 1459 static const u32 rk3368_dsi_grf_reg_fields[MAX_FIELDS] = { 1460 [DPIUPDATECFG] = GRF_REG_FIELD(0x0418, 7, 7), 1461 [DPICOLORM] = GRF_REG_FIELD(0x0418, 3, 3), 1462 [DPISHUTDN] = GRF_REG_FIELD(0x0418, 2, 2), 1463 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x041c, 7, 10), 1464 [FORCERXMODE] = GRF_REG_FIELD(0x041c, 6, 6), 1465 [TURNDISABLE] = GRF_REG_FIELD(0x041c, 5, 5), 1466 }; 1467 1468 static const struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_plat_data = { 1469 .dsi0_grf_reg_fields = rk3368_dsi_grf_reg_fields, 1470 .max_bit_rate_per_lane = 1000000000UL, 1471 }; 1472 1473 static const struct rockchip_connector rk3368_mipi_dsi_driver_data = { 1474 .funcs = &dw_mipi_dsi_connector_funcs, 1475 .data = &rk3368_mipi_dsi_plat_data, 1476 }; 1477 1478 static const u32 rk3399_dsi0_grf_reg_fields[MAX_FIELDS] = { 1479 [DPIUPDATECFG] = GRF_REG_FIELD(0x6224, 15, 15), 1480 [DPISHUTDN] = GRF_REG_FIELD(0x6224, 14, 14), 1481 [DPICOLORM] = GRF_REG_FIELD(0x6224, 13, 13), 1482 [VOPSEL] = GRF_REG_FIELD(0x6250, 0, 0), 1483 [TURNREQUEST] = GRF_REG_FIELD(0x6258, 12, 15), 1484 [TURNDISABLE] = GRF_REG_FIELD(0x6258, 8, 11), 1485 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x6258, 4, 7), 1486 [FORCERXMODE] = GRF_REG_FIELD(0x6258, 0, 3), 1487 }; 1488 1489 static const u32 rk3399_dsi1_grf_reg_fields[MAX_FIELDS] = { 1490 [VOPSEL] = GRF_REG_FIELD(0x6250, 4, 4), 1491 [DPIUPDATECFG] = GRF_REG_FIELD(0x6250, 3, 3), 1492 [DPISHUTDN] = GRF_REG_FIELD(0x6250, 2, 2), 1493 [DPICOLORM] = GRF_REG_FIELD(0x6250, 1, 1), 1494 [TURNDISABLE] = GRF_REG_FIELD(0x625c, 12, 15), 1495 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x625c, 8, 11), 1496 [FORCERXMODE] = GRF_REG_FIELD(0x625c, 4, 7), 1497 [ENABLE_N] = GRF_REG_FIELD(0x625c, 0, 3), 1498 [MASTERSLAVEZ] = GRF_REG_FIELD(0x6260, 7, 7), 1499 [ENABLECLK] = GRF_REG_FIELD(0x6260, 6, 6), 1500 [BASEDIR] = GRF_REG_FIELD(0x6260, 5, 5), 1501 [TURNREQUEST] = GRF_REG_FIELD(0x6260, 0, 3), 1502 }; 1503 1504 static const struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_plat_data = { 1505 .dsi0_grf_reg_fields = rk3399_dsi0_grf_reg_fields, 1506 .dsi1_grf_reg_fields = rk3399_dsi1_grf_reg_fields, 1507 .max_bit_rate_per_lane = 1500000000UL, 1508 }; 1509 1510 static const struct rockchip_connector rk3399_mipi_dsi_driver_data = { 1511 .funcs = &dw_mipi_dsi_connector_funcs, 1512 .data = &rk3399_mipi_dsi_plat_data, 1513 }; 1514 1515 static const u32 rk3568_dsi0_grf_reg_fields[MAX_FIELDS] = { 1516 [DPIUPDATECFG] = GRF_REG_FIELD(0x0360, 2, 2), 1517 [DPICOLORM] = GRF_REG_FIELD(0x0360, 1, 1), 1518 [DPISHUTDN] = GRF_REG_FIELD(0x0360, 0, 0), 1519 [SKEWCALHS] = GRF_REG_FIELD(0x0368, 11, 15), 1520 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0368, 4, 7), 1521 [TURNDISABLE] = GRF_REG_FIELD(0x0368, 2, 2), 1522 [FORCERXMODE] = GRF_REG_FIELD(0x0368, 0, 0), 1523 }; 1524 1525 static const u32 rk3568_dsi1_grf_reg_fields[MAX_FIELDS] = { 1526 [DPIUPDATECFG] = GRF_REG_FIELD(0x0360, 10, 10), 1527 [DPICOLORM] = GRF_REG_FIELD(0x0360, 9, 9), 1528 [DPISHUTDN] = GRF_REG_FIELD(0x0360, 8, 8), 1529 [SKEWCALHS] = GRF_REG_FIELD(0x036c, 11, 15), 1530 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x036c, 4, 7), 1531 [TURNDISABLE] = GRF_REG_FIELD(0x036c, 2, 2), 1532 [FORCERXMODE] = GRF_REG_FIELD(0x036c, 0, 0), 1533 }; 1534 1535 static const struct dw_mipi_dsi_plat_data rk3568_mipi_dsi_plat_data = { 1536 .dsi0_grf_reg_fields = rk3568_dsi0_grf_reg_fields, 1537 .dsi1_grf_reg_fields = rk3568_dsi1_grf_reg_fields, 1538 .max_bit_rate_per_lane = 1000000000UL, 1539 }; 1540 static const struct rockchip_connector rk3568_mipi_dsi_driver_data = { 1541 .funcs = &dw_mipi_dsi_connector_funcs, 1542 .data = &rk3568_mipi_dsi_plat_data, 1543 }; 1544 1545 static const u32 rv1108_dsi_grf_reg_fields[MAX_FIELDS] = { 1546 [DPICOLORM] = GRF_REG_FIELD(0x0410, 7, 7), 1547 [DPISHUTDN] = GRF_REG_FIELD(0x0410, 6, 6), 1548 [DPIUPDATECFG] = GRF_REG_FIELD(0x0410, 8, 8), 1549 [FORCERXMODE] = GRF_REG_FIELD(0x0414, 5, 5), 1550 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0414, 6, 9), 1551 [TURNDISABLE] = GRF_REG_FIELD(0x0414, 4, 4), 1552 }; 1553 1554 static const struct dw_mipi_dsi_plat_data rv1108_mipi_dsi_plat_data = { 1555 .dsi0_grf_reg_fields = rv1108_dsi_grf_reg_fields, 1556 .max_bit_rate_per_lane = 1000000000UL, 1557 }; 1558 1559 static const struct rockchip_connector rv1108_mipi_dsi_driver_data = { 1560 .funcs = &dw_mipi_dsi_connector_funcs, 1561 .data = &rv1108_mipi_dsi_plat_data, 1562 }; 1563 1564 static const u32 rv1126_dsi_grf_reg_fields[MAX_FIELDS] = { 1565 [DPIUPDATECFG] = GRF_REG_FIELD(0x0008, 5, 5), 1566 [DPISHUTDN] = GRF_REG_FIELD(0x0008, 4, 4), 1567 [DPICOLORM] = GRF_REG_FIELD(0x0008, 3, 3), 1568 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x10220, 4, 7), 1569 [TURNDISABLE] = GRF_REG_FIELD(0x10220, 2, 2), 1570 [FORCERXMODE] = GRF_REG_FIELD(0x10220, 0, 0), 1571 }; 1572 1573 static const struct dw_mipi_dsi_plat_data rv1126_mipi_dsi_plat_data = { 1574 .dsi0_grf_reg_fields = rv1126_dsi_grf_reg_fields, 1575 .max_bit_rate_per_lane = 1000000000UL, 1576 }; 1577 1578 static const struct rockchip_connector rv1126_mipi_dsi_driver_data = { 1579 .funcs = &dw_mipi_dsi_connector_funcs, 1580 .data = &rv1126_mipi_dsi_plat_data, 1581 }; 1582 1583 static const struct udevice_id dw_mipi_dsi_ids[] = { 1584 { 1585 .compatible = "rockchip,px30-mipi-dsi", 1586 .data = (ulong)&px30_mipi_dsi_driver_data, 1587 }, 1588 { 1589 .compatible = "rockchip,rk1808-mipi-dsi", 1590 .data = (ulong)&rk1808_mipi_dsi_driver_data, 1591 }, 1592 { 1593 .compatible = "rockchip,rk3128-mipi-dsi", 1594 .data = (ulong)&rk3128_mipi_dsi_driver_data, 1595 }, 1596 { 1597 .compatible = "rockchip,rk3288-mipi-dsi", 1598 .data = (ulong)&rk3288_mipi_dsi_driver_data, 1599 }, 1600 { 1601 .compatible = "rockchip,rk3366-mipi-dsi", 1602 .data = (ulong)&rk3366_mipi_dsi_driver_data, 1603 }, 1604 { 1605 .compatible = "rockchip,rk3368-mipi-dsi", 1606 .data = (ulong)&rk3368_mipi_dsi_driver_data, 1607 }, 1608 { 1609 .compatible = "rockchip,rk3399-mipi-dsi", 1610 .data = (ulong)&rk3399_mipi_dsi_driver_data, 1611 }, 1612 { 1613 .compatible = "rockchip,rk3568-mipi-dsi", 1614 .data = (ulong)&rk3568_mipi_dsi_driver_data, 1615 }, 1616 { 1617 .compatible = "rockchip,rv1108-mipi-dsi", 1618 .data = (ulong)&rv1108_mipi_dsi_driver_data, 1619 }, 1620 { 1621 .compatible = "rockchip,rv1126-mipi-dsi", 1622 .data = (ulong)&rv1126_mipi_dsi_driver_data, 1623 }, 1624 {} 1625 }; 1626 1627 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host, 1628 const struct mipi_dsi_msg *msg) 1629 { 1630 struct dw_mipi_dsi *dsi = dev_get_priv(host->dev); 1631 1632 return dw_mipi_dsi_transfer(dsi, msg); 1633 } 1634 1635 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 1636 struct mipi_dsi_device *device) 1637 { 1638 struct dw_mipi_dsi *dsi = dev_get_priv(host->dev); 1639 1640 if (device->lanes < 1 || device->lanes > 8) 1641 return -EINVAL; 1642 1643 dsi->lanes = device->lanes; 1644 dsi->channel = device->channel; 1645 dsi->format = device->format; 1646 dsi->mode_flags = device->mode_flags; 1647 1648 return 0; 1649 } 1650 1651 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = { 1652 .attach = dw_mipi_dsi_host_attach, 1653 .transfer = dw_mipi_dsi_host_transfer, 1654 }; 1655 1656 static int dw_mipi_dsi_bind(struct udevice *dev) 1657 { 1658 struct mipi_dsi_host *host = dev_get_platdata(dev); 1659 1660 host->dev = dev; 1661 host->ops = &dw_mipi_dsi_host_ops; 1662 1663 return dm_scan_fdt_dev(dev); 1664 } 1665 1666 static int dw_mipi_dsi_child_post_bind(struct udevice *dev) 1667 { 1668 struct mipi_dsi_host *host = dev_get_platdata(dev->parent); 1669 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1670 char name[20]; 1671 1672 sprintf(name, "%s.%d", host->dev->name, device->channel); 1673 device_set_name(dev, name); 1674 1675 device->dev = dev; 1676 device->host = host; 1677 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4); 1678 device->format = dev_read_u32_default(dev, "dsi,format", 1679 MIPI_DSI_FMT_RGB888); 1680 device->mode_flags = dev_read_u32_default(dev, "dsi,flags", 1681 MIPI_DSI_MODE_VIDEO | 1682 MIPI_DSI_MODE_VIDEO_BURST | 1683 MIPI_DSI_MODE_VIDEO_HBP | 1684 MIPI_DSI_MODE_LPM | 1685 MIPI_DSI_MODE_EOT_PACKET); 1686 device->channel = dev_read_u32_default(dev, "reg", 0); 1687 1688 return 0; 1689 } 1690 1691 static int dw_mipi_dsi_child_pre_probe(struct udevice *dev) 1692 { 1693 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1694 int ret; 1695 1696 ret = mipi_dsi_attach(device); 1697 if (ret) { 1698 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret); 1699 return ret; 1700 } 1701 1702 return 0; 1703 } 1704 1705 U_BOOT_DRIVER(dw_mipi_dsi) = { 1706 .name = "dw_mipi_dsi", 1707 .id = UCLASS_DISPLAY, 1708 .of_match = dw_mipi_dsi_ids, 1709 .probe = dw_mipi_dsi_probe, 1710 .bind = dw_mipi_dsi_bind, 1711 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi), 1712 .per_child_platdata_auto_alloc_size = sizeof(struct mipi_dsi_device), 1713 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_host), 1714 .child_post_bind = dw_mipi_dsi_child_post_bind, 1715 .child_pre_probe = dw_mipi_dsi_child_pre_probe, 1716 }; 1717