1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <drm/drm_mipi_dsi.h> 8 9 #include <config.h> 10 #include <common.h> 11 #include <errno.h> 12 #include <asm/unaligned.h> 13 #include <asm/io.h> 14 #include <asm/hardware.h> 15 #include <dm/device.h> 16 #include <dm/read.h> 17 #include <dm/of_access.h> 18 #include <syscon.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <linux/iopoll.h> 21 22 #include "rockchip_display.h" 23 #include "rockchip_crtc.h" 24 #include "rockchip_connector.h" 25 #include "rockchip_panel.h" 26 #include "rockchip_phy.h" 27 28 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) 29 30 #define DSI_VERSION 0x00 31 #define DSI_PWR_UP 0x04 32 #define RESET 0 33 #define POWERUP BIT(0) 34 35 #define DSI_CLKMGR_CFG 0x08 36 #define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) 37 #define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) 38 39 #define DSI_DPI_VCID 0x0c 40 #define DPI_VID(vid) (((vid) & 0x3) << 0) 41 42 #define DSI_DPI_COLOR_CODING 0x10 43 #define EN18_LOOSELY BIT(8) 44 #define DPI_COLOR_CODING_16BIT_1 0x0 45 #define DPI_COLOR_CODING_16BIT_2 0x1 46 #define DPI_COLOR_CODING_16BIT_3 0x2 47 #define DPI_COLOR_CODING_18BIT_1 0x3 48 #define DPI_COLOR_CODING_18BIT_2 0x4 49 #define DPI_COLOR_CODING_24BIT 0x5 50 51 #define DSI_DPI_CFG_POL 0x14 52 #define COLORM_ACTIVE_LOW BIT(4) 53 #define SHUTD_ACTIVE_LOW BIT(3) 54 #define HSYNC_ACTIVE_LOW BIT(2) 55 #define VSYNC_ACTIVE_LOW BIT(1) 56 #define DATAEN_ACTIVE_LOW BIT(0) 57 58 #define DSI_DPI_LP_CMD_TIM 0x18 59 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) 60 #define INVACT_LPCMD_TIME(p) ((p) & 0xff) 61 62 #define DSI_DBI_VCID 0x1c 63 #define DBI_VCID(x) UPDATE(x, 1, 0) 64 #define DSI_DBI_CFG 0x20 65 #define DSI_DBI_CMDSIZE 0x28 66 67 #define DSI_PCKHDL_CFG 0x2c 68 #define CRC_RX_EN BIT(4) 69 #define ECC_RX_EN BIT(3) 70 #define BTA_EN BIT(2) 71 #define EOTP_RX_EN BIT(1) 72 #define EOTP_TX_EN BIT(0) 73 #define DSI_MODE_CFG 0x34 74 #define CMD_VIDEO_MODE BIT(0) 75 #define COMMAND_MODE BIT(0) 76 #define VIDEO_MODE 0 77 #define DSI_VID_MODE_CFG 0x38 78 #define VPG_EN BIT(16) 79 #define LP_CMD_EN BIT(15) 80 #define FRAME_BTA_ACK BIT(14) 81 #define LP_HFP_EN BIT(13) 82 #define LP_HBP_EN BIT(12) 83 #define LP_VACT_EN BIT(11) 84 #define LP_VFP_EN BIT(10) 85 #define LP_VBP_EN BIT(9) 86 #define LP_VSA_EN BIT(8) 87 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0 88 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1 89 #define VID_MODE_TYPE_BURST 0x2 90 91 #define DSI_VID_PKT_SIZE 0x3c 92 #define VID_PKT_SIZE(p) (((p) & 0x3fff) << 0) 93 #define VID_PKT_MAX_SIZE 0x3fff 94 95 #define DSI_VID_NUM_CHUMKS 0x40 96 #define DSI_VID_NULL_PKT_SIZE 0x44 97 #define DSI_VID_HSA_TIME 0x48 98 #define DSI_VID_HBP_TIME 0x4c 99 #define DSI_VID_HLINE_TIME 0x50 100 #define DSI_VID_VSA_LINES 0x54 101 #define DSI_VID_VBP_LINES 0x58 102 #define DSI_VID_VFP_LINES 0x5c 103 #define DSI_VID_VACTIVE_LINES 0x60 104 #define DSI_EDPI_CMD_SIZE 0x64 105 #define DSI_CMD_MODE_CFG 0x68 106 #define MAX_RD_PKT_SIZE BIT(24) 107 #define DCS_LW_TX BIT(19) 108 #define DCS_SR_0P_TX BIT(18) 109 #define DCS_SW_1P_TX BIT(17) 110 #define DCS_SW_0P_TX BIT(16) 111 #define GEN_LW_TX BIT(14) 112 #define GEN_SR_2P_TX BIT(13) 113 #define GEN_SR_1P_TX BIT(12) 114 #define GEN_SR_0P_TX BIT(11) 115 #define GEN_SW_2P_TX BIT(10) 116 #define GEN_SW_1P_TX BIT(9) 117 #define GEN_SW_0P_TX BIT(8) 118 #define ACK_RQST_EN BIT(1) 119 #define TEAR_FX_EN BIT(0) 120 121 #define DSI_GEN_HDR 0x6c 122 #define GEN_HDATA(data) (((data) & 0xffff) << 8) 123 #define GEN_HDATA_MASK (0xffff << 8) 124 #define GEN_HTYPE(type) (((type) & 0xff) << 0) 125 #define GEN_HTYPE_MASK 0xff 126 127 #define DSI_GEN_PLD_DATA 0x70 128 129 #define DSI_CMD_PKT_STATUS 0x74 130 #define GEN_CMD_EMPTY BIT(0) 131 #define GEN_CMD_FULL BIT(1) 132 #define GEN_PLD_W_EMPTY BIT(2) 133 #define GEN_PLD_W_FULL BIT(3) 134 #define GEN_PLD_R_EMPTY BIT(4) 135 #define GEN_PLD_R_FULL BIT(5) 136 #define GEN_RD_CMD_BUSY BIT(6) 137 138 #define DSI_TO_CNT_CFG 0x78 139 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16) 140 #define LPRX_TO_CNT(p) ((p) & 0xffff) 141 142 #define DSI_BTA_TO_CNT 0x8c 143 #define DSI_LPCLK_CTRL 0x94 144 #define AUTO_CLKLANE_CTRL BIT(1) 145 #define PHY_TXREQUESTCLKHS BIT(0) 146 147 #define DSI_PHY_TMR_LPCLK_CFG 0x98 148 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16) 149 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff) 150 151 #define DSI_PHY_TMR_CFG 0x9c 152 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24) 153 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16) 154 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff) 155 156 #define DSI_PHY_RSTZ 0xa0 157 #define PHY_ENFORCEPLL BIT(3) 158 #define PHY_ENABLECLK BIT(2) 159 #define PHY_RSTZ BIT(1) 160 #define PHY_SHUTDOWNZ BIT(0) 161 162 #define DSI_PHY_IF_CFG 0xa4 163 #define N_LANES(n) ((((n) - 1) & 0x3) << 0) 164 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 165 166 #define DSI_PHY_STATUS 0xb0 167 #define PHY_STOPSTATE0LANE BIT(4) 168 #define PHY_STOPSTATECLKLANE BIT(2) 169 #define PHY_LOCK BIT(0) 170 #define PHY_STOPSTATELANE (PHY_STOPSTATE0LANE | \ 171 PHY_STOPSTATECLKLANE) 172 173 #define DSI_PHY_TST_CTRL0 0xb4 174 #define PHY_TESTCLK BIT(1) 175 #define PHY_TESTCLR BIT(0) 176 177 #define DSI_PHY_TST_CTRL1 0xb8 178 #define PHY_TESTEN BIT(16) 179 #define PHY_TESTDOUT_SHIFT 8 180 #define PHY_TESTDIN_MASK GENMASK(7, 0) 181 #define PHY_TESTDIN(x) UPDATE(x, 7, 0) 182 183 #define DSI_INT_ST0 0xbc 184 #define DSI_INT_ST1 0xc0 185 #define DSI_INT_MSK0 0xc4 186 #define DSI_INT_MSK1 0xc8 187 188 #define PHY_STATUS_TIMEOUT_US 10000 189 #define CMD_PKT_STATUS_TIMEOUT_US 20000 190 191 /* Test Code: 0x44 (HS RX Control of Lane 0) */ 192 #define HSFREQRANGE(x) UPDATE(x, 6, 1) 193 /* Test Code: 0x17 (PLL Input Divider Ratio) */ 194 #define INPUT_DIV(x) UPDATE(x, 6, 0) 195 /* Test Code: 0x18 (PLL Loop Divider Ratio) */ 196 #define FEEDBACK_DIV_LO(x) UPDATE(x, 4, 0) 197 #define FEEDBACK_DIV_HI(x) (BIT(7) | UPDATE(x, 3, 0)) 198 199 #define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 10) | ((lsb) << 5) | (msb)) 200 201 enum grf_reg_fields { 202 DPIUPDATECFG, 203 DPISHUTDN, 204 DPICOLORM, 205 VOPSEL, 206 TURNREQUEST, 207 TURNDISABLE, 208 SKEWCALHS, 209 FORCETXSTOPMODE, 210 FORCERXMODE, 211 ENABLE_N, 212 MASTERSLAVEZ, 213 ENABLECLK, 214 BASEDIR, 215 MAX_FIELDS, 216 }; 217 218 struct dw_mipi_dsi_plat_data { 219 const u32 *dsi0_grf_reg_fields; 220 const u32 *dsi1_grf_reg_fields; 221 unsigned long max_bit_rate_per_lane; 222 }; 223 224 struct mipi_dphy { 225 /* Non-SNPS PHY */ 226 struct rockchip_phy *phy; 227 228 u16 input_div; 229 u16 feedback_div; 230 }; 231 232 struct dw_mipi_dsi { 233 struct rockchip_connector connector; 234 struct udevice *dev; 235 void *base; 236 void *grf; 237 int id; 238 struct dw_mipi_dsi *master; 239 struct dw_mipi_dsi *slave; 240 bool prepared; 241 242 unsigned int lane_mbps; /* per lane */ 243 u32 channel; 244 u32 lanes; 245 u32 format; 246 u32 mode_flags; 247 struct mipi_dphy dphy; 248 struct drm_display_mode mode; 249 bool data_swap; 250 bool dual_channel; 251 252 const struct dw_mipi_dsi_plat_data *pdata; 253 }; 254 255 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) 256 { 257 writel(val, dsi->base + reg); 258 } 259 260 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) 261 { 262 return readl(dsi->base + reg); 263 } 264 265 static inline void dsi_update_bits(struct dw_mipi_dsi *dsi, 266 u32 reg, u32 mask, u32 val) 267 { 268 u32 orig, tmp; 269 270 orig = dsi_read(dsi, reg); 271 tmp = orig & ~mask; 272 tmp |= val & mask; 273 dsi_write(dsi, reg, tmp); 274 } 275 276 static void grf_field_write(struct dw_mipi_dsi *dsi, enum grf_reg_fields index, 277 unsigned int val) 278 { 279 const u32 field = dsi->id ? dsi->pdata->dsi1_grf_reg_fields[index] : 280 dsi->pdata->dsi0_grf_reg_fields[index]; 281 u16 reg; 282 u8 msb, lsb; 283 284 if (!field) 285 return; 286 287 reg = (field >> 10) & 0x3ffff; 288 lsb = (field >> 5) & 0x1f; 289 msb = (field >> 0) & 0x1f; 290 291 rk_clrsetreg(dsi->grf + reg, GENMASK(msb, lsb), val << lsb); 292 } 293 294 static inline void dpishutdn_assert(struct dw_mipi_dsi *dsi) 295 { 296 grf_field_write(dsi, DPISHUTDN, 1); 297 } 298 299 static inline void dpishutdn_deassert(struct dw_mipi_dsi *dsi) 300 { 301 grf_field_write(dsi, DPISHUTDN, 0); 302 } 303 304 static int genif_wait_w_pld_fifo_not_full(struct dw_mipi_dsi *dsi) 305 { 306 u32 sts; 307 int ret; 308 309 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 310 sts, !(sts & GEN_PLD_W_FULL), 311 CMD_PKT_STATUS_TIMEOUT_US); 312 if (ret < 0) { 313 printf("generic write payload fifo is full\n"); 314 return ret; 315 } 316 317 return 0; 318 } 319 320 static int genif_wait_cmd_fifo_not_full(struct dw_mipi_dsi *dsi) 321 { 322 u32 sts; 323 int ret; 324 325 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 326 sts, !(sts & GEN_CMD_FULL), 327 CMD_PKT_STATUS_TIMEOUT_US); 328 if (ret < 0) { 329 printf("generic write cmd fifo is full\n"); 330 return ret; 331 } 332 333 return 0; 334 } 335 336 static int genif_wait_write_fifo_empty(struct dw_mipi_dsi *dsi) 337 { 338 u32 sts; 339 u32 mask; 340 int ret; 341 342 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 343 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 344 sts, (sts & mask) == mask, 345 CMD_PKT_STATUS_TIMEOUT_US); 346 if (ret < 0) { 347 printf("generic write fifo is full\n"); 348 return ret; 349 } 350 351 return 0; 352 } 353 354 static inline void mipi_dphy_enableclk_assert(struct dw_mipi_dsi *dsi) 355 { 356 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK); 357 udelay(1); 358 } 359 360 static inline void mipi_dphy_enableclk_deassert(struct dw_mipi_dsi *dsi) 361 { 362 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, 0); 363 udelay(1); 364 } 365 366 static inline void mipi_dphy_shutdownz_assert(struct dw_mipi_dsi *dsi) 367 { 368 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, 0); 369 udelay(1); 370 } 371 372 static inline void mipi_dphy_shutdownz_deassert(struct dw_mipi_dsi *dsi) 373 { 374 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, PHY_SHUTDOWNZ); 375 udelay(1); 376 } 377 378 static inline void mipi_dphy_rstz_assert(struct dw_mipi_dsi *dsi) 379 { 380 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, 0); 381 udelay(1); 382 } 383 384 static inline void mipi_dphy_rstz_deassert(struct dw_mipi_dsi *dsi) 385 { 386 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, PHY_RSTZ); 387 udelay(1); 388 } 389 390 static inline void testif_testclk_assert(struct dw_mipi_dsi *dsi) 391 { 392 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK); 393 udelay(1); 394 } 395 396 static inline void testif_testclk_deassert(struct dw_mipi_dsi *dsi) 397 { 398 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK, 0); 399 udelay(1); 400 } 401 402 static inline void testif_testclr_assert(struct dw_mipi_dsi *dsi) 403 { 404 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR, PHY_TESTCLR); 405 udelay(1); 406 } 407 408 static inline void testif_testclr_deassert(struct dw_mipi_dsi *dsi) 409 { 410 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR, 0); 411 udelay(1); 412 } 413 414 static inline void testif_testen_assert(struct dw_mipi_dsi *dsi) 415 { 416 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN, PHY_TESTEN); 417 udelay(1); 418 } 419 420 static inline void testif_testen_deassert(struct dw_mipi_dsi *dsi) 421 { 422 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN, 0); 423 udelay(1); 424 } 425 426 static inline void testif_set_data(struct dw_mipi_dsi *dsi, u8 data) 427 { 428 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, 429 PHY_TESTDIN_MASK, PHY_TESTDIN(data)); 430 udelay(1); 431 } 432 433 static inline u8 testif_get_data(struct dw_mipi_dsi *dsi) 434 { 435 return dsi_read(dsi, DSI_PHY_TST_CTRL1) >> PHY_TESTDOUT_SHIFT; 436 } 437 438 static void testif_test_code_write(struct dw_mipi_dsi *dsi, u8 test_code) 439 { 440 testif_testclk_assert(dsi); 441 testif_set_data(dsi, test_code); 442 testif_testen_assert(dsi); 443 testif_testclk_deassert(dsi); 444 testif_testen_deassert(dsi); 445 } 446 447 static void testif_test_data_write(struct dw_mipi_dsi *dsi, u8 test_data) 448 { 449 testif_testclk_deassert(dsi); 450 testif_set_data(dsi, test_data); 451 testif_testclk_assert(dsi); 452 } 453 454 static void testif_write(struct dw_mipi_dsi *dsi, u8 test_code, u8 test_data) 455 { 456 testif_test_code_write(dsi, test_code); 457 testif_test_data_write(dsi, test_data); 458 459 dev_dbg(dsi->dev, 460 "test_code=0x%02x, test_data=0x%02x, monitor_data=0x%02x\n", 461 test_code, test_data, testif_get_data(dsi)); 462 } 463 464 static int mipi_dphy_power_on(struct dw_mipi_dsi *dsi) 465 { 466 u32 mask, val; 467 int ret; 468 469 mipi_dphy_shutdownz_deassert(dsi); 470 mipi_dphy_rstz_deassert(dsi); 471 mdelay(2); 472 473 if (dsi->dphy.phy) { 474 rockchip_phy_set_mode(dsi->dphy.phy, PHY_MODE_MIPI_DPHY); 475 rockchip_phy_power_on(dsi->dphy.phy); 476 } 477 478 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 479 val, val & PHY_LOCK, PHY_STATUS_TIMEOUT_US); 480 if (ret < 0) { 481 dev_err(dsi->dev, "PHY is not locked\n"); 482 return ret; 483 } 484 485 udelay(200); 486 487 mask = PHY_STOPSTATELANE; 488 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 489 val, (val & mask) == mask, 490 PHY_STATUS_TIMEOUT_US); 491 if (ret < 0) { 492 dev_err(dsi->dev, "lane module is not in stop state\n"); 493 return ret; 494 } 495 496 udelay(10); 497 498 return 0; 499 } 500 501 static void dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) 502 { 503 /* Table 5-1 Frequency Ranges */ 504 const struct { 505 unsigned long max_lane_mbps; 506 u8 hsfreqrange; 507 } hsfreqrange_table[] = { 508 { 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01}, 509 { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12}, 510 { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23}, 511 { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15}, 512 { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07}, 513 { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09}, 514 { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a}, 515 {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b}, 516 {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c}, 517 {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c} 518 }; 519 u8 hsfreqrange, counter; 520 unsigned int index, txbyteclkhs; 521 u16 n, m; 522 523 for (index = 0; index < ARRAY_SIZE(hsfreqrange_table); index++) 524 if (dsi->lane_mbps <= hsfreqrange_table[index].max_lane_mbps) 525 break; 526 527 if (index == ARRAY_SIZE(hsfreqrange_table)) 528 --index; 529 530 hsfreqrange = hsfreqrange_table[index].hsfreqrange; 531 testif_write(dsi, 0x44, HSFREQRANGE(hsfreqrange)); 532 533 txbyteclkhs = dsi->lane_mbps >> 3; 534 counter = txbyteclkhs * 60 / 1000; 535 testif_write(dsi, 0x60, 0x80 | counter); 536 testif_write(dsi, 0x70, 0x80 | counter); 537 538 n = dsi->dphy.input_div - 1; 539 m = dsi->dphy.feedback_div - 1; 540 testif_write(dsi, 0x19, 0x30); 541 testif_write(dsi, 0x17, INPUT_DIV(n)); 542 testif_write(dsi, 0x18, FEEDBACK_DIV_LO(m)); 543 testif_write(dsi, 0x18, FEEDBACK_DIV_HI(m >> 5)); 544 } 545 546 static unsigned long dw_mipi_dsi_get_lane_rate(struct dw_mipi_dsi *dsi) 547 { 548 const struct drm_display_mode *mode = &dsi->mode; 549 unsigned long max_lane_rate = dsi->pdata->max_bit_rate_per_lane; 550 unsigned long lane_rate; 551 unsigned int value; 552 int bpp, lanes; 553 u64 tmp; 554 555 /* optional override of the desired bandwidth */ 556 value = dev_read_u32_default(dsi->dev, "rockchip,lane-rate", 0); 557 if (value > 0) 558 return value * 1000 * 1000; 559 560 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 561 if (bpp < 0) 562 bpp = 24; 563 564 lanes = dsi->slave ? dsi->lanes * 2 : dsi->lanes; 565 tmp = (u64)mode->clock * 1000 * bpp; 566 do_div(tmp, lanes); 567 568 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */ 569 tmp *= 10; 570 do_div(tmp, 9); 571 572 if (tmp > max_lane_rate) 573 lane_rate = max_lane_rate; 574 else 575 lane_rate = tmp; 576 577 return lane_rate; 578 } 579 580 static void dw_mipi_dsi_set_pll(struct dw_mipi_dsi *dsi, unsigned long rate) 581 { 582 unsigned long fin, fout; 583 unsigned long fvco_min, fvco_max, best_freq = 984000000; 584 u8 min_prediv, max_prediv; 585 u8 _prediv, best_prediv = 2; 586 u16 _fbdiv, best_fbdiv = 82; 587 u32 min_delta = ~0U; 588 589 fin = 24000000; 590 fout = rate; 591 592 /* 5Mhz < Fref / N < 40MHz, 80MHz < Fvco < 1500Mhz */ 593 min_prediv = DIV_ROUND_UP(fin, 40000000); 594 max_prediv = fin / 5000000; 595 fvco_min = 80000000; 596 fvco_max = 1500000000; 597 598 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 599 u64 tmp, _fout; 600 u32 delta; 601 602 /* Fvco = Fref * M / N */ 603 tmp = (u64)fout * _prediv; 604 do_div(tmp, fin); 605 _fbdiv = tmp; 606 607 /* 608 * Due to the use of a "by 2 pre-scaler," the range of the 609 * feedback multiplication value M is limited to even division 610 * numbers, and m must be greater than 12, less than 1000. 611 */ 612 if (_fbdiv <= 12 || _fbdiv >= 1000) 613 continue; 614 615 if (_fbdiv % 2) 616 ++_fbdiv; 617 618 _fout = (u64)_fbdiv * fin; 619 do_div(_fout, _prediv); 620 621 if (_fout < fvco_min || _fout > fvco_max) 622 continue; 623 624 delta = abs(fout - _fout); 625 if (!delta) { 626 best_prediv = _prediv; 627 best_fbdiv = _fbdiv; 628 best_freq = _fout; 629 break; 630 } else if (delta < min_delta) { 631 best_prediv = _prediv; 632 best_fbdiv = _fbdiv; 633 best_freq = _fout; 634 min_delta = delta; 635 } 636 } 637 638 dsi->lane_mbps = best_freq / 1000 / 1000; 639 dsi->dphy.input_div = best_prediv; 640 dsi->dphy.feedback_div = best_fbdiv; 641 if (dsi->slave) { 642 dsi->slave->lane_mbps = dsi->lane_mbps; 643 dsi->slave->dphy.input_div = dsi->dphy.input_div; 644 dsi->slave->dphy.feedback_div = dsi->dphy.feedback_div; 645 } 646 if (dsi->master) { 647 dsi->master->lane_mbps = dsi->lane_mbps; 648 dsi->master->dphy.input_div = dsi->dphy.input_div; 649 dsi->master->dphy.feedback_div = dsi->dphy.feedback_div; 650 } 651 } 652 653 static int dw_mipi_dsi_read_from_fifo(struct dw_mipi_dsi *dsi, 654 const struct mipi_dsi_msg *msg) 655 { 656 u8 *payload = msg->rx_buf; 657 u16 length; 658 u32 val; 659 int ret; 660 661 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 662 val, !(val & GEN_RD_CMD_BUSY), 5000); 663 if (ret) { 664 printf("entire response isn't stored in the FIFO\n"); 665 return ret; 666 } 667 668 /* Receive payload */ 669 for (length = msg->rx_len; length; length -= 4) { 670 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 671 val, !(val & GEN_PLD_R_EMPTY), 5000); 672 if (ret) { 673 printf("Read payload FIFO is empty\n"); 674 return ret; 675 } 676 677 val = dsi_read(dsi, DSI_GEN_PLD_DATA); 678 679 switch (length) { 680 case 3: 681 payload[2] = (val >> 16) & 0xff; 682 /* Fall through */ 683 case 2: 684 payload[1] = (val >> 8) & 0xff; 685 /* Fall through */ 686 case 1: 687 payload[0] = val & 0xff; 688 return 0; 689 } 690 691 payload[0] = (val >> 0) & 0xff; 692 payload[1] = (val >> 8) & 0xff; 693 payload[2] = (val >> 16) & 0xff; 694 payload[3] = (val >> 24) & 0xff; 695 payload += 4; 696 } 697 698 return 0; 699 } 700 701 static int dw_mipi_dsi_turn_on_peripheral(struct dw_mipi_dsi *dsi) 702 { 703 dpishutdn_assert(dsi); 704 udelay(20); 705 dpishutdn_deassert(dsi); 706 707 return 0; 708 } 709 710 static int dw_mipi_dsi_shutdown_peripheral(struct dw_mipi_dsi *dsi) 711 { 712 dpishutdn_deassert(dsi); 713 udelay(20); 714 dpishutdn_assert(dsi); 715 716 return 0; 717 } 718 719 static ssize_t dw_mipi_dsi_transfer(struct dw_mipi_dsi *dsi, 720 const struct mipi_dsi_msg *msg) 721 { 722 struct mipi_dsi_packet packet; 723 int ret; 724 int val; 725 726 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { 727 dsi_update_bits(dsi, DSI_VID_MODE_CFG, LP_CMD_EN, LP_CMD_EN); 728 dsi_update_bits(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS, 0); 729 } else { 730 dsi_update_bits(dsi, DSI_VID_MODE_CFG, LP_CMD_EN, 0); 731 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 732 PHY_TXREQUESTCLKHS, PHY_TXREQUESTCLKHS); 733 } 734 735 switch (msg->type) { 736 case MIPI_DSI_SHUTDOWN_PERIPHERAL: 737 return dw_mipi_dsi_shutdown_peripheral(dsi); 738 case MIPI_DSI_TURN_ON_PERIPHERAL: 739 return dw_mipi_dsi_turn_on_peripheral(dsi); 740 case MIPI_DSI_DCS_SHORT_WRITE: 741 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_0P_TX, 742 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 743 DCS_SW_0P_TX : 0); 744 break; 745 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 746 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_1P_TX, 747 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 748 DCS_SW_1P_TX : 0); 749 break; 750 case MIPI_DSI_DCS_LONG_WRITE: 751 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX, 752 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 753 DCS_LW_TX : 0); 754 break; 755 case MIPI_DSI_DCS_READ: 756 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SR_0P_TX, 757 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 758 DCS_SR_0P_TX : 0); 759 break; 760 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: 761 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, MAX_RD_PKT_SIZE, 762 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 763 MAX_RD_PKT_SIZE : 0); 764 break; 765 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 766 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_0P_TX, 767 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 768 GEN_SW_0P_TX : 0); 769 break; 770 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 771 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_1P_TX, 772 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 773 GEN_SW_1P_TX : 0); 774 break; 775 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 776 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_2P_TX, 777 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 778 GEN_SW_2P_TX : 0); 779 break; 780 case MIPI_DSI_GENERIC_LONG_WRITE: 781 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_LW_TX, 782 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 783 GEN_LW_TX : 0); 784 break; 785 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 786 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_0P_TX, 787 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 788 GEN_SR_0P_TX : 0); 789 break; 790 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 791 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_1P_TX, 792 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 793 GEN_SR_1P_TX : 0); 794 break; 795 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 796 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_2P_TX, 797 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 798 GEN_SR_2P_TX : 0); 799 break; 800 default: 801 return -EINVAL; 802 } 803 804 if (msg->flags & MIPI_DSI_MSG_REQ_ACK) 805 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, 806 ACK_RQST_EN, ACK_RQST_EN); 807 808 /* create a packet to the DSI protocol */ 809 ret = mipi_dsi_create_packet(&packet, msg); 810 if (ret) { 811 printf("failed to create packet: %d\n", ret); 812 return ret; 813 } 814 815 /* Send payload */ 816 while (DIV_ROUND_UP(packet.payload_length, 4)) { 817 /* 818 * Alternatively, you can always keep the FIFO 819 * nearly full by monitoring the FIFO state until 820 * it is not full, and then writea single word of data. 821 * This solution is more resource consuming 822 * but it simultaneously avoids FIFO starvation, 823 * making it possible to use FIFO sizes smaller than 824 * the amount of data of the longest packet to be written. 825 */ 826 ret = genif_wait_w_pld_fifo_not_full(dsi); 827 if (ret) 828 return ret; 829 830 if (packet.payload_length < 4) { 831 /* send residu payload */ 832 val = 0; 833 memcpy(&val, packet.payload, packet.payload_length); 834 dsi_write(dsi, DSI_GEN_PLD_DATA, val); 835 packet.payload_length = 0; 836 } else { 837 val = get_unaligned_le32(packet.payload); 838 dsi_write(dsi, DSI_GEN_PLD_DATA, val); 839 packet.payload += 4; 840 packet.payload_length -= 4; 841 } 842 } 843 844 ret = genif_wait_cmd_fifo_not_full(dsi); 845 if (ret) 846 return ret; 847 848 /* Send packet header */ 849 val = get_unaligned_le32(packet.header); 850 dsi_write(dsi, DSI_GEN_HDR, val); 851 852 ret = genif_wait_write_fifo_empty(dsi); 853 if (ret) 854 return ret; 855 856 if (msg->rx_len) { 857 ret = dw_mipi_dsi_read_from_fifo(dsi, msg); 858 if (ret < 0) 859 return ret; 860 } 861 862 if (dsi->slave) { 863 ret = dw_mipi_dsi_transfer(dsi->slave, msg); 864 if (ret < 0) 865 return ret; 866 } 867 868 return msg->rx_len ? msg->rx_len : msg->tx_len; 869 } 870 871 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) 872 { 873 u32 val = LP_VACT_EN | LP_VFP_EN | LP_VBP_EN | LP_VSA_EN | 874 LP_HFP_EN | LP_HBP_EN; 875 876 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) 877 val &= ~LP_HFP_EN; 878 879 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) 880 val &= ~LP_HBP_EN; 881 882 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 883 val |= VID_MODE_TYPE_BURST; 884 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 885 val |= VID_MODE_TYPE_BURST_SYNC_PULSES; 886 else 887 val |= VID_MODE_TYPE_BURST_SYNC_EVENTS; 888 889 dsi_write(dsi, DSI_VID_MODE_CFG, val); 890 891 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 892 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 893 AUTO_CLKLANE_CTRL, AUTO_CLKLANE_CTRL); 894 } 895 896 static void dw_mipi_dsi_enable(struct dw_mipi_dsi *dsi) 897 { 898 const struct drm_display_mode *mode = &dsi->mode; 899 900 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 901 PHY_TXREQUESTCLKHS, PHY_TXREQUESTCLKHS); 902 903 dsi_write(dsi, DSI_PWR_UP, RESET); 904 905 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 906 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, VIDEO_MODE); 907 } else { 908 dsi_write(dsi, DSI_DBI_VCID, DBI_VCID(dsi->channel)); 909 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX, 0); 910 dsi_write(dsi, DSI_EDPI_CMD_SIZE, mode->hdisplay); 911 dsi_update_bits(dsi, DSI_MODE_CFG, 912 CMD_VIDEO_MODE, COMMAND_MODE); 913 } 914 915 dsi_write(dsi, DSI_PWR_UP, POWERUP); 916 917 if (dsi->slave) 918 dw_mipi_dsi_enable(dsi->slave); 919 } 920 921 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) 922 { 923 dsi_write(dsi, DSI_PWR_UP, RESET); 924 dsi_write(dsi, DSI_LPCLK_CTRL, 0); 925 dsi_write(dsi, DSI_EDPI_CMD_SIZE, 0); 926 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, COMMAND_MODE); 927 dsi_write(dsi, DSI_PWR_UP, POWERUP); 928 929 if (dsi->slave) 930 dw_mipi_dsi_disable(dsi->slave); 931 } 932 933 static void dw_mipi_dsi_post_disable(struct dw_mipi_dsi *dsi) 934 { 935 if (!dsi->prepared) 936 return; 937 938 if (dsi->master) 939 dw_mipi_dsi_post_disable(dsi->master); 940 941 dsi_write(dsi, DSI_PWR_UP, RESET); 942 dsi_write(dsi, DSI_PHY_RSTZ, 0); 943 944 if (dsi->dphy.phy) 945 rockchip_phy_power_off(dsi->dphy.phy); 946 947 dsi->prepared = false; 948 949 if (dsi->slave) 950 dw_mipi_dsi_post_disable(dsi->slave); 951 } 952 953 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) 954 { 955 u32 esc_clk_div; 956 957 dsi_write(dsi, DSI_PWR_UP, RESET); 958 959 /* The maximum value of the escape clock frequency is 20MHz */ 960 esc_clk_div = DIV_ROUND_UP(dsi->lane_mbps >> 3, 20); 961 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) | 962 TX_ESC_CLK_DIVIDSION(esc_clk_div)); 963 } 964 965 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, 966 struct drm_display_mode *mode) 967 { 968 u32 val = 0, color = 0; 969 970 switch (dsi->format) { 971 case MIPI_DSI_FMT_RGB888: 972 color = DPI_COLOR_CODING_24BIT; 973 break; 974 case MIPI_DSI_FMT_RGB666: 975 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY; 976 break; 977 case MIPI_DSI_FMT_RGB666_PACKED: 978 color = DPI_COLOR_CODING_18BIT_1; 979 break; 980 case MIPI_DSI_FMT_RGB565: 981 color = DPI_COLOR_CODING_16BIT_1; 982 break; 983 } 984 985 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 986 val |= VSYNC_ACTIVE_LOW; 987 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 988 val |= HSYNC_ACTIVE_LOW; 989 990 dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel)); 991 dsi_write(dsi, DSI_DPI_COLOR_CODING, color); 992 dsi_write(dsi, DSI_DPI_CFG_POL, val); 993 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4) 994 | INVACT_LPCMD_TIME(4)); 995 } 996 997 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi) 998 { 999 u32 val = CRC_RX_EN | ECC_RX_EN | BTA_EN | EOTP_TX_EN; 1000 1001 if (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 1002 val &= ~EOTP_TX_EN; 1003 1004 dsi_write(dsi, DSI_PCKHDL_CFG, val); 1005 } 1006 1007 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, 1008 struct drm_display_mode *mode) 1009 { 1010 dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay)); 1011 } 1012 1013 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) 1014 { 1015 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000)); 1016 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); 1017 } 1018 1019 /* Get lane byte clock cycles. */ 1020 static int dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, 1021 u32 hcomponent) 1022 { 1023 u32 lbcc; 1024 1025 lbcc = hcomponent * dsi->lane_mbps * 1000 / 8; 1026 1027 if (!dsi->mode.clock) 1028 return 0; 1029 1030 return DIV_ROUND_CLOSEST(lbcc, dsi->mode.clock); 1031 } 1032 1033 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi) 1034 { 1035 int htotal, hsa, hbp, lbcc; 1036 struct drm_display_mode *mode = &dsi->mode; 1037 1038 htotal = mode->htotal; 1039 hsa = mode->hsync_end - mode->hsync_start; 1040 hbp = mode->htotal - mode->hsync_end; 1041 1042 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal); 1043 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); 1044 1045 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa); 1046 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); 1047 1048 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp); 1049 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); 1050 } 1051 1052 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi) 1053 { 1054 u32 vactive, vsa, vfp, vbp; 1055 struct drm_display_mode *mode = &dsi->mode; 1056 1057 vactive = mode->vdisplay; 1058 vsa = mode->vsync_end - mode->vsync_start; 1059 vfp = mode->vsync_start - mode->vdisplay; 1060 vbp = mode->vtotal - mode->vsync_end; 1061 1062 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); 1063 dsi_write(dsi, DSI_VID_VSA_LINES, vsa); 1064 dsi_write(dsi, DSI_VID_VFP_LINES, vfp); 1065 dsi_write(dsi, DSI_VID_VBP_LINES, vbp); 1066 } 1067 1068 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) 1069 { 1070 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14) 1071 | PHY_LP2HS_TIME(0x10) | MAX_RD_TIME(10000)); 1072 1073 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40) 1074 | PHY_CLKLP2HS_TIME(0x40)); 1075 } 1076 1077 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) 1078 { 1079 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) | 1080 N_LANES(dsi->lanes)); 1081 } 1082 1083 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) 1084 { 1085 dsi_read(dsi, DSI_INT_ST0); 1086 dsi_read(dsi, DSI_INT_ST1); 1087 dsi_write(dsi, DSI_INT_MSK0, 0); 1088 dsi_write(dsi, DSI_INT_MSK1, 0); 1089 } 1090 1091 static int dw_mipi_dsi_connector_init(struct rockchip_connector *conn, struct display_state *state) 1092 { 1093 struct connector_state *conn_state = &state->conn_state; 1094 struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev); 1095 1096 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dsi->id); 1097 dsi->dphy.phy = conn->phy; 1098 1099 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 1100 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709; 1101 conn_state->color_range = DRM_COLOR_YCBCR_FULL_RANGE; 1102 conn_state->output_if |= 1103 dsi->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0; 1104 1105 #ifndef CONFIG_ROCKCHIP_RK3568 1106 if (dsi->id) { 1107 struct udevice *dev; 1108 int ret; 1109 1110 ret = uclass_get_device_by_name(UCLASS_DISPLAY, "dsi@ff960000", 1111 &dev); 1112 if (ret) 1113 return ret; 1114 1115 dsi->master = dev_get_priv(dev); 1116 if (!dsi->master) 1117 return -ENODEV; 1118 1119 conn_state->output_flags = ROCKCHIP_OUTPUT_DATA_SWAP; 1120 } 1121 #endif 1122 1123 if (dsi->dual_channel) { 1124 struct udevice *dev; 1125 int ret; 1126 1127 ret = uclass_get_device_by_name(UCLASS_DISPLAY, 1128 #if defined(CONFIG_ROCKCHIP_RK3288) 1129 "dsi@ff964000", 1130 #elif defined(CONFIG_ROCKCHIP_RK3399) 1131 "dsi@ff968000", 1132 #else 1133 "dsi@fe070000", 1134 #endif 1135 &dev); 1136 if (ret) 1137 return ret; 1138 1139 dsi->slave = dev_get_priv(dev); 1140 if (!dsi->slave) 1141 return -ENODEV; 1142 1143 dsi->lanes /= 2; 1144 dsi->slave->lanes = dsi->lanes; 1145 dsi->slave->format = dsi->format; 1146 dsi->slave->mode_flags = dsi->mode_flags; 1147 dsi->slave->channel = dsi->channel; 1148 conn_state->output_flags = 1149 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; 1150 if (dsi->data_swap) 1151 conn_state->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP; 1152 1153 conn_state->output_if |= VOP_OUTPUT_IF_MIPI1; 1154 1155 #if defined(CONFIG_ROCKCHIP_RK3568) 1156 struct rockchip_phy *phy = NULL; 1157 struct udevice *phy_dev; 1158 1159 ret = uclass_get_device_by_phandle(UCLASS_PHY, dev, 1160 "phys", &phy_dev); 1161 if (ret) 1162 return -ENODEV; 1163 1164 phy = (struct rockchip_phy *)dev_get_driver_data(phy_dev); 1165 if (!phy) 1166 return -ENODEV; 1167 1168 dsi->slave->dphy.phy = phy; 1169 if (phy->funcs && phy->funcs->init) 1170 return phy->funcs->init(phy); 1171 #endif 1172 1173 } 1174 1175 return 0; 1176 } 1177 1178 static void dw_mipi_dsi_set_hs_clk(struct dw_mipi_dsi *dsi, unsigned long rate) 1179 { 1180 rate = rockchip_phy_set_pll(dsi->dphy.phy, rate); 1181 dsi->lane_mbps = rate / 1000 / 1000; 1182 } 1183 1184 static void dw_mipi_dsi_host_init(struct dw_mipi_dsi *dsi) 1185 { 1186 dw_mipi_dsi_init(dsi); 1187 dw_mipi_dsi_dpi_config(dsi, &dsi->mode); 1188 dw_mipi_dsi_packet_handler_config(dsi); 1189 dw_mipi_dsi_video_mode_config(dsi); 1190 dw_mipi_dsi_video_packet_config(dsi, &dsi->mode); 1191 dw_mipi_dsi_command_mode_config(dsi); 1192 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, COMMAND_MODE); 1193 dw_mipi_dsi_line_timer_config(dsi); 1194 dw_mipi_dsi_vertical_timing_config(dsi); 1195 dw_mipi_dsi_dphy_timing_config(dsi); 1196 dw_mipi_dsi_dphy_interface_config(dsi); 1197 dw_mipi_dsi_clear_err(dsi); 1198 } 1199 1200 static void dw_mipi_dsi_vop_routing(struct dw_mipi_dsi *dsi, int vop_id) 1201 { 1202 grf_field_write(dsi, VOPSEL, vop_id); 1203 1204 if (dsi->slave) 1205 grf_field_write(dsi->slave, VOPSEL, vop_id); 1206 } 1207 1208 static void mipi_dphy_init(struct dw_mipi_dsi *dsi) 1209 { 1210 u32 map[] = {0x0, 0x1, 0x3, 0x7, 0xf}; 1211 1212 mipi_dphy_enableclk_deassert(dsi); 1213 mipi_dphy_shutdownz_assert(dsi); 1214 mipi_dphy_rstz_assert(dsi); 1215 testif_testclr_assert(dsi); 1216 1217 /* Configures DPHY to work as a Master */ 1218 grf_field_write(dsi, MASTERSLAVEZ, 1); 1219 1220 /* Configures lane as TX */ 1221 grf_field_write(dsi, BASEDIR, 0); 1222 1223 /* Set all REQUEST inputs to zero */ 1224 grf_field_write(dsi, TURNREQUEST, 0); 1225 grf_field_write(dsi, TURNDISABLE, 0); 1226 grf_field_write(dsi, FORCETXSTOPMODE, 0); 1227 grf_field_write(dsi, FORCERXMODE, 0); 1228 udelay(1); 1229 1230 testif_testclr_deassert(dsi); 1231 1232 if (!dsi->dphy.phy) 1233 dw_mipi_dsi_phy_init(dsi); 1234 1235 /* Enable Data Lane Module */ 1236 grf_field_write(dsi, ENABLE_N, map[dsi->lanes]); 1237 1238 /* Enable Clock Lane Module */ 1239 grf_field_write(dsi, ENABLECLK, 1); 1240 1241 mipi_dphy_enableclk_assert(dsi); 1242 } 1243 1244 static void dw_mipi_dsi_pre_enable(struct dw_mipi_dsi *dsi) 1245 { 1246 if (dsi->prepared) 1247 return; 1248 1249 if (dsi->master) 1250 dw_mipi_dsi_pre_enable(dsi->master); 1251 1252 dw_mipi_dsi_host_init(dsi); 1253 mipi_dphy_init(dsi); 1254 mipi_dphy_power_on(dsi); 1255 dsi_write(dsi, DSI_PWR_UP, POWERUP); 1256 1257 dsi->prepared = true; 1258 1259 if (dsi->slave) 1260 dw_mipi_dsi_pre_enable(dsi->slave); 1261 } 1262 1263 static int dw_mipi_dsi_connector_prepare(struct rockchip_connector *conn, 1264 struct display_state *state) 1265 { 1266 struct connector_state *conn_state = &state->conn_state; 1267 struct crtc_state *crtc_state = &state->crtc_state; 1268 struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev); 1269 unsigned long lane_rate; 1270 1271 memcpy(&dsi->mode, &conn_state->mode, sizeof(struct drm_display_mode)); 1272 if (dsi->slave) { 1273 dsi->mode.hdisplay /= 2; 1274 memcpy(&dsi->slave->mode, &dsi->mode, 1275 sizeof(struct drm_display_mode)); 1276 } 1277 1278 lane_rate = dw_mipi_dsi_get_lane_rate(dsi); 1279 if (dsi->dphy.phy) 1280 dw_mipi_dsi_set_hs_clk(dsi, lane_rate); 1281 else 1282 dw_mipi_dsi_set_pll(dsi, lane_rate); 1283 1284 if (dsi->slave && dsi->slave->dphy.phy) 1285 dw_mipi_dsi_set_hs_clk(dsi->slave, lane_rate); 1286 1287 printf("final DSI-Link bandwidth: %u Mbps x %d\n", 1288 dsi->lane_mbps, dsi->slave ? dsi->lanes * 2 : dsi->lanes); 1289 1290 dw_mipi_dsi_vop_routing(dsi, crtc_state->crtc_id); 1291 dw_mipi_dsi_pre_enable(dsi); 1292 1293 return 0; 1294 } 1295 1296 static void dw_mipi_dsi_connector_unprepare(struct rockchip_connector *conn, 1297 struct display_state *state) 1298 { 1299 struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev); 1300 1301 dw_mipi_dsi_post_disable(dsi); 1302 } 1303 1304 static int dw_mipi_dsi_connector_enable(struct rockchip_connector *conn, 1305 struct display_state *state) 1306 { 1307 struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev); 1308 1309 dw_mipi_dsi_enable(dsi); 1310 1311 return 0; 1312 } 1313 1314 static int dw_mipi_dsi_connector_disable(struct rockchip_connector *conn, 1315 struct display_state *state) 1316 { 1317 struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev); 1318 1319 dw_mipi_dsi_disable(dsi); 1320 1321 return 0; 1322 } 1323 1324 static const struct rockchip_connector_funcs dw_mipi_dsi_connector_funcs = { 1325 .init = dw_mipi_dsi_connector_init, 1326 .prepare = dw_mipi_dsi_connector_prepare, 1327 .unprepare = dw_mipi_dsi_connector_unprepare, 1328 .enable = dw_mipi_dsi_connector_enable, 1329 .disable = dw_mipi_dsi_connector_disable, 1330 }; 1331 1332 static int dw_mipi_dsi_probe(struct udevice *dev) 1333 { 1334 struct dw_mipi_dsi *dsi = dev_get_priv(dev); 1335 const struct dw_mipi_dsi_plat_data *pdata = 1336 (const struct dw_mipi_dsi_plat_data *)dev_get_driver_data(dev); 1337 int id; 1338 1339 dsi->base = dev_read_addr_ptr(dev); 1340 dsi->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1341 if (IS_ERR(dsi->grf)) 1342 return PTR_ERR(dsi->grf); 1343 1344 id = of_alias_get_id(ofnode_to_np(dev->node), "dsi"); 1345 if (id < 0) 1346 id = 0; 1347 1348 dsi->dev = dev; 1349 dsi->pdata = pdata; 1350 dsi->id = id; 1351 dsi->dual_channel = dev_read_bool(dsi->dev, "rockchip,dual-channel"); 1352 dsi->data_swap = dev_read_bool(dsi->dev, "rockchip,data-swap"); 1353 1354 rockchip_connector_bind(&dsi->connector, dev, dsi->id, &dw_mipi_dsi_connector_funcs, NULL, 1355 DRM_MODE_CONNECTOR_DSI); 1356 1357 return 0; 1358 } 1359 1360 static const u32 px30_dsi_grf_reg_fields[MAX_FIELDS] = { 1361 [DPIUPDATECFG] = GRF_REG_FIELD(0x0434, 7, 7), 1362 [DPICOLORM] = GRF_REG_FIELD(0x0434, 3, 3), 1363 [DPISHUTDN] = GRF_REG_FIELD(0x0434, 2, 2), 1364 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0438, 7, 10), 1365 [TURNDISABLE] = GRF_REG_FIELD(0x0438, 5, 5), 1366 [VOPSEL] = GRF_REG_FIELD(0x0438, 0, 0), 1367 }; 1368 1369 static const struct dw_mipi_dsi_plat_data px30_mipi_dsi_plat_data = { 1370 .dsi0_grf_reg_fields = px30_dsi_grf_reg_fields, 1371 .max_bit_rate_per_lane = 1000000000UL, 1372 }; 1373 1374 static const u32 rk1808_dsi_grf_reg_fields[MAX_FIELDS] = { 1375 [MASTERSLAVEZ] = GRF_REG_FIELD(0x0440, 8, 8), 1376 [DPIUPDATECFG] = GRF_REG_FIELD(0x0440, 7, 7), 1377 [DPICOLORM] = GRF_REG_FIELD(0x0440, 3, 3), 1378 [DPISHUTDN] = GRF_REG_FIELD(0x0440, 2, 2), 1379 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0444, 7, 10), 1380 [FORCERXMODE] = GRF_REG_FIELD(0x0444, 6, 6), 1381 [TURNDISABLE] = GRF_REG_FIELD(0x0444, 5, 5), 1382 }; 1383 1384 static const struct dw_mipi_dsi_plat_data rk1808_mipi_dsi_plat_data = { 1385 .dsi0_grf_reg_fields = rk1808_dsi_grf_reg_fields, 1386 .max_bit_rate_per_lane = 2000000000UL, 1387 }; 1388 1389 static const u32 rk3128_dsi_grf_reg_fields[MAX_FIELDS] = { 1390 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0150, 10, 13), 1391 [FORCERXMODE] = GRF_REG_FIELD(0x0150, 9, 9), 1392 [TURNDISABLE] = GRF_REG_FIELD(0x0150, 8, 8), 1393 [DPICOLORM] = GRF_REG_FIELD(0x0150, 5, 5), 1394 [DPISHUTDN] = GRF_REG_FIELD(0x0150, 4, 4), 1395 }; 1396 1397 static const struct dw_mipi_dsi_plat_data rk3128_mipi_dsi_plat_data = { 1398 .dsi0_grf_reg_fields = rk3128_dsi_grf_reg_fields, 1399 .max_bit_rate_per_lane = 1000000000UL, 1400 }; 1401 1402 static const u32 rk3288_dsi0_grf_reg_fields[MAX_FIELDS] = { 1403 [DPICOLORM] = GRF_REG_FIELD(0x025c, 8, 8), 1404 [DPISHUTDN] = GRF_REG_FIELD(0x025c, 7, 7), 1405 [VOPSEL] = GRF_REG_FIELD(0x025c, 6, 6), 1406 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0264, 8, 11), 1407 [FORCERXMODE] = GRF_REG_FIELD(0x0264, 4, 7), 1408 [TURNDISABLE] = GRF_REG_FIELD(0x0264, 0, 3), 1409 [TURNREQUEST] = GRF_REG_FIELD(0x03a4, 8, 10), 1410 [DPIUPDATECFG] = GRF_REG_FIELD(0x03a8, 0, 0), 1411 }; 1412 1413 static const u32 rk3288_dsi1_grf_reg_fields[MAX_FIELDS] = { 1414 [DPICOLORM] = GRF_REG_FIELD(0x025c, 11, 11), 1415 [DPISHUTDN] = GRF_REG_FIELD(0x025c, 10, 10), 1416 [VOPSEL] = GRF_REG_FIELD(0x025c, 9, 9), 1417 [ENABLE_N] = GRF_REG_FIELD(0x0268, 12, 15), 1418 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0268, 8, 11), 1419 [FORCERXMODE] = GRF_REG_FIELD(0x0268, 4, 7), 1420 [TURNDISABLE] = GRF_REG_FIELD(0x0268, 0, 3), 1421 [BASEDIR] = GRF_REG_FIELD(0x027c, 15, 15), 1422 [MASTERSLAVEZ] = GRF_REG_FIELD(0x027c, 14, 14), 1423 [ENABLECLK] = GRF_REG_FIELD(0x027c, 12, 12), 1424 [TURNREQUEST] = GRF_REG_FIELD(0x03a4, 4, 7), 1425 [DPIUPDATECFG] = GRF_REG_FIELD(0x03a8, 1, 1), 1426 }; 1427 1428 static const struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_plat_data = { 1429 .dsi0_grf_reg_fields = rk3288_dsi0_grf_reg_fields, 1430 .dsi1_grf_reg_fields = rk3288_dsi1_grf_reg_fields, 1431 .max_bit_rate_per_lane = 1500000000UL, 1432 }; 1433 1434 static const u32 rk3366_dsi_grf_reg_fields[MAX_FIELDS] = { 1435 [VOPSEL] = GRF_REG_FIELD(0x0400, 2, 2), 1436 [DPIUPDATECFG] = GRF_REG_FIELD(0x0410, 9, 9), 1437 [DPICOLORM] = GRF_REG_FIELD(0x0410, 3, 3), 1438 [DPISHUTDN] = GRF_REG_FIELD(0x0410, 2, 2), 1439 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0414, 7, 10), 1440 [FORCERXMODE] = GRF_REG_FIELD(0x0414, 6, 6), 1441 [TURNDISABLE] = GRF_REG_FIELD(0x0414, 5, 5), 1442 }; 1443 1444 static const struct dw_mipi_dsi_plat_data rk3366_mipi_dsi_plat_data = { 1445 .dsi0_grf_reg_fields = rk3366_dsi_grf_reg_fields, 1446 .max_bit_rate_per_lane = 1000000000UL, 1447 }; 1448 1449 static const u32 rk3368_dsi_grf_reg_fields[MAX_FIELDS] = { 1450 [DPIUPDATECFG] = GRF_REG_FIELD(0x0418, 7, 7), 1451 [DPICOLORM] = GRF_REG_FIELD(0x0418, 3, 3), 1452 [DPISHUTDN] = GRF_REG_FIELD(0x0418, 2, 2), 1453 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x041c, 7, 10), 1454 [FORCERXMODE] = GRF_REG_FIELD(0x041c, 6, 6), 1455 [TURNDISABLE] = GRF_REG_FIELD(0x041c, 5, 5), 1456 }; 1457 1458 static const struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_plat_data = { 1459 .dsi0_grf_reg_fields = rk3368_dsi_grf_reg_fields, 1460 .max_bit_rate_per_lane = 1000000000UL, 1461 }; 1462 1463 static const u32 rk3399_dsi0_grf_reg_fields[MAX_FIELDS] = { 1464 [DPIUPDATECFG] = GRF_REG_FIELD(0x6224, 15, 15), 1465 [DPISHUTDN] = GRF_REG_FIELD(0x6224, 14, 14), 1466 [DPICOLORM] = GRF_REG_FIELD(0x6224, 13, 13), 1467 [VOPSEL] = GRF_REG_FIELD(0x6250, 0, 0), 1468 [TURNREQUEST] = GRF_REG_FIELD(0x6258, 12, 15), 1469 [TURNDISABLE] = GRF_REG_FIELD(0x6258, 8, 11), 1470 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x6258, 4, 7), 1471 [FORCERXMODE] = GRF_REG_FIELD(0x6258, 0, 3), 1472 }; 1473 1474 static const u32 rk3399_dsi1_grf_reg_fields[MAX_FIELDS] = { 1475 [VOPSEL] = GRF_REG_FIELD(0x6250, 4, 4), 1476 [DPIUPDATECFG] = GRF_REG_FIELD(0x6250, 3, 3), 1477 [DPISHUTDN] = GRF_REG_FIELD(0x6250, 2, 2), 1478 [DPICOLORM] = GRF_REG_FIELD(0x6250, 1, 1), 1479 [TURNDISABLE] = GRF_REG_FIELD(0x625c, 12, 15), 1480 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x625c, 8, 11), 1481 [FORCERXMODE] = GRF_REG_FIELD(0x625c, 4, 7), 1482 [ENABLE_N] = GRF_REG_FIELD(0x625c, 0, 3), 1483 [MASTERSLAVEZ] = GRF_REG_FIELD(0x6260, 7, 7), 1484 [ENABLECLK] = GRF_REG_FIELD(0x6260, 6, 6), 1485 [BASEDIR] = GRF_REG_FIELD(0x6260, 5, 5), 1486 [TURNREQUEST] = GRF_REG_FIELD(0x6260, 0, 3), 1487 }; 1488 1489 static const struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_plat_data = { 1490 .dsi0_grf_reg_fields = rk3399_dsi0_grf_reg_fields, 1491 .dsi1_grf_reg_fields = rk3399_dsi1_grf_reg_fields, 1492 .max_bit_rate_per_lane = 1500000000UL, 1493 }; 1494 1495 static const u32 rk3562_dsi_grf_reg_fields[MAX_FIELDS] = { 1496 [DPIUPDATECFG] = GRF_REG_FIELD(0x05d0, 2, 2), 1497 [DPICOLORM] = GRF_REG_FIELD(0x05d0, 1, 1), 1498 [DPISHUTDN] = GRF_REG_FIELD(0x05d0, 0, 0), 1499 [SKEWCALHS] = GRF_REG_FIELD(0x05d4, 11, 15), 1500 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x05d4, 4, 7), 1501 [TURNDISABLE] = GRF_REG_FIELD(0x05d4, 2, 2), 1502 [FORCERXMODE] = GRF_REG_FIELD(0x05d4, 0, 0), 1503 }; 1504 1505 static const struct dw_mipi_dsi_plat_data rk3562_mipi_dsi_plat_data = { 1506 .dsi0_grf_reg_fields = rk3562_dsi_grf_reg_fields, 1507 .max_bit_rate_per_lane = 1200000000UL, 1508 }; 1509 1510 static const u32 rk3568_dsi0_grf_reg_fields[MAX_FIELDS] = { 1511 [DPIUPDATECFG] = GRF_REG_FIELD(0x0360, 2, 2), 1512 [DPICOLORM] = GRF_REG_FIELD(0x0360, 1, 1), 1513 [DPISHUTDN] = GRF_REG_FIELD(0x0360, 0, 0), 1514 [SKEWCALHS] = GRF_REG_FIELD(0x0368, 11, 15), 1515 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0368, 4, 7), 1516 [TURNDISABLE] = GRF_REG_FIELD(0x0368, 2, 2), 1517 [FORCERXMODE] = GRF_REG_FIELD(0x0368, 0, 0), 1518 }; 1519 1520 static const u32 rk3568_dsi1_grf_reg_fields[MAX_FIELDS] = { 1521 [DPIUPDATECFG] = GRF_REG_FIELD(0x0360, 10, 10), 1522 [DPICOLORM] = GRF_REG_FIELD(0x0360, 9, 9), 1523 [DPISHUTDN] = GRF_REG_FIELD(0x0360, 8, 8), 1524 [SKEWCALHS] = GRF_REG_FIELD(0x036c, 11, 15), 1525 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x036c, 4, 7), 1526 [TURNDISABLE] = GRF_REG_FIELD(0x036c, 2, 2), 1527 [FORCERXMODE] = GRF_REG_FIELD(0x036c, 0, 0), 1528 }; 1529 1530 static const struct dw_mipi_dsi_plat_data rk3568_mipi_dsi_plat_data = { 1531 .dsi0_grf_reg_fields = rk3568_dsi0_grf_reg_fields, 1532 .dsi1_grf_reg_fields = rk3568_dsi1_grf_reg_fields, 1533 .max_bit_rate_per_lane = 1200000000UL, 1534 }; 1535 1536 static const u32 rv1108_dsi_grf_reg_fields[MAX_FIELDS] = { 1537 [DPICOLORM] = GRF_REG_FIELD(0x0410, 7, 7), 1538 [DPISHUTDN] = GRF_REG_FIELD(0x0410, 6, 6), 1539 [DPIUPDATECFG] = GRF_REG_FIELD(0x0410, 8, 8), 1540 [FORCERXMODE] = GRF_REG_FIELD(0x0414, 5, 5), 1541 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0414, 6, 9), 1542 [TURNDISABLE] = GRF_REG_FIELD(0x0414, 4, 4), 1543 }; 1544 1545 static const struct dw_mipi_dsi_plat_data rv1108_mipi_dsi_plat_data = { 1546 .dsi0_grf_reg_fields = rv1108_dsi_grf_reg_fields, 1547 .max_bit_rate_per_lane = 1000000000UL, 1548 }; 1549 1550 static const u32 rv1126_dsi_grf_reg_fields[MAX_FIELDS] = { 1551 [DPIUPDATECFG] = GRF_REG_FIELD(0x0008, 5, 5), 1552 [DPISHUTDN] = GRF_REG_FIELD(0x0008, 4, 4), 1553 [DPICOLORM] = GRF_REG_FIELD(0x0008, 3, 3), 1554 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x10220, 4, 7), 1555 [TURNDISABLE] = GRF_REG_FIELD(0x10220, 2, 2), 1556 [FORCERXMODE] = GRF_REG_FIELD(0x10220, 0, 0), 1557 }; 1558 1559 static const struct dw_mipi_dsi_plat_data rv1126_mipi_dsi_plat_data = { 1560 .dsi0_grf_reg_fields = rv1126_dsi_grf_reg_fields, 1561 .max_bit_rate_per_lane = 1000000000UL, 1562 }; 1563 1564 static const struct udevice_id dw_mipi_dsi_ids[] = { 1565 { 1566 .compatible = "rockchip,px30-mipi-dsi", 1567 .data = (ulong)&px30_mipi_dsi_plat_data, 1568 }, 1569 { 1570 .compatible = "rockchip,rk1808-mipi-dsi", 1571 .data = (ulong)&rk1808_mipi_dsi_plat_data, 1572 }, 1573 { 1574 .compatible = "rockchip,rk3128-mipi-dsi", 1575 .data = (ulong)&rk3128_mipi_dsi_plat_data, 1576 }, 1577 { 1578 .compatible = "rockchip,rk3288-mipi-dsi", 1579 .data = (ulong)&rk3288_mipi_dsi_plat_data, 1580 }, 1581 { 1582 .compatible = "rockchip,rk3366-mipi-dsi", 1583 .data = (ulong)&rk3366_mipi_dsi_plat_data, 1584 }, 1585 { 1586 .compatible = "rockchip,rk3368-mipi-dsi", 1587 .data = (ulong)&rk3368_mipi_dsi_plat_data, 1588 }, 1589 { 1590 .compatible = "rockchip,rk3399-mipi-dsi", 1591 .data = (ulong)&rk3399_mipi_dsi_plat_data, 1592 }, 1593 { 1594 .compatible = "rockchip,rk3562-mipi-dsi", 1595 .data = (ulong)&rk3562_mipi_dsi_plat_data, 1596 }, 1597 { 1598 .compatible = "rockchip,rk3568-mipi-dsi", 1599 .data = (ulong)&rk3568_mipi_dsi_plat_data, 1600 }, 1601 { 1602 .compatible = "rockchip,rv1108-mipi-dsi", 1603 .data = (ulong)&rv1108_mipi_dsi_plat_data, 1604 }, 1605 { 1606 .compatible = "rockchip,rv1126-mipi-dsi", 1607 .data = (ulong)&rv1126_mipi_dsi_plat_data, 1608 }, 1609 {} 1610 }; 1611 1612 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host, 1613 const struct mipi_dsi_msg *msg) 1614 { 1615 struct dw_mipi_dsi *dsi = dev_get_priv(host->dev); 1616 1617 return dw_mipi_dsi_transfer(dsi, msg); 1618 } 1619 1620 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 1621 struct mipi_dsi_device *device) 1622 { 1623 struct dw_mipi_dsi *dsi = dev_get_priv(host->dev); 1624 1625 if (device->lanes < 1 || device->lanes > 8) 1626 return -EINVAL; 1627 1628 dsi->lanes = device->lanes; 1629 dsi->channel = device->channel; 1630 dsi->format = device->format; 1631 dsi->mode_flags = device->mode_flags; 1632 1633 return 0; 1634 } 1635 1636 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = { 1637 .attach = dw_mipi_dsi_host_attach, 1638 .transfer = dw_mipi_dsi_host_transfer, 1639 }; 1640 1641 static int dw_mipi_dsi_bind(struct udevice *dev) 1642 { 1643 struct mipi_dsi_host *host = dev_get_platdata(dev); 1644 1645 host->dev = dev; 1646 host->ops = &dw_mipi_dsi_host_ops; 1647 1648 return dm_scan_fdt_dev(dev); 1649 } 1650 1651 static int dw_mipi_dsi_child_post_bind(struct udevice *dev) 1652 { 1653 struct mipi_dsi_host *host = dev_get_platdata(dev->parent); 1654 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1655 char name[20]; 1656 1657 sprintf(name, "%s.%d", host->dev->name, device->channel); 1658 device_set_name(dev, name); 1659 1660 device->dev = dev; 1661 device->host = host; 1662 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4); 1663 device->format = dev_read_u32_default(dev, "dsi,format", 1664 MIPI_DSI_FMT_RGB888); 1665 device->mode_flags = dev_read_u32_default(dev, "dsi,flags", 1666 MIPI_DSI_MODE_VIDEO | 1667 MIPI_DSI_MODE_VIDEO_BURST | 1668 MIPI_DSI_MODE_VIDEO_HBP | 1669 MIPI_DSI_MODE_LPM | 1670 MIPI_DSI_MODE_EOT_PACKET); 1671 device->channel = dev_read_u32_default(dev, "reg", 0); 1672 1673 return 0; 1674 } 1675 1676 static int dw_mipi_dsi_child_pre_probe(struct udevice *dev) 1677 { 1678 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1679 int ret; 1680 1681 ret = mipi_dsi_attach(device); 1682 if (ret) { 1683 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret); 1684 return ret; 1685 } 1686 1687 return 0; 1688 } 1689 1690 U_BOOT_DRIVER(dw_mipi_dsi) = { 1691 .name = "dw_mipi_dsi", 1692 .id = UCLASS_DISPLAY, 1693 .of_match = dw_mipi_dsi_ids, 1694 .probe = dw_mipi_dsi_probe, 1695 .bind = dw_mipi_dsi_bind, 1696 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi), 1697 .per_child_platdata_auto_alloc_size = sizeof(struct mipi_dsi_device), 1698 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_host), 1699 .child_post_bind = dw_mipi_dsi_child_post_bind, 1700 .child_pre_probe = dw_mipi_dsi_child_pre_probe, 1701 }; 1702