1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <asm/unaligned.h> 11 #include <asm/io.h> 12 #include <asm/hardware.h> 13 #include <dm/device.h> 14 #include <dm/read.h> 15 #include <dm/of_access.h> 16 #include <syscon.h> 17 #include <asm/arch-rockchip/clock.h> 18 19 #include "rockchip_display.h" 20 #include "rockchip_crtc.h" 21 #include "rockchip_connector.h" 22 #include "rockchip_panel.h" 23 #include "rockchip_phy.h" 24 #include "rockchip_mipi_dsi.h" 25 26 #define DSI_VERSION 0x00 27 #define DSI_PWR_UP 0x04 28 #define RESET 0 29 #define POWERUP BIT(0) 30 31 #define DSI_CLKMGR_CFG 0x08 32 #define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) 33 #define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) 34 35 #define DSI_DPI_VCID 0x0c 36 #define DPI_VID(vid) (((vid) & 0x3) << 0) 37 38 #define DSI_DPI_COLOR_CODING 0x10 39 #define EN18_LOOSELY BIT(8) 40 #define DPI_COLOR_CODING_16BIT_1 0x0 41 #define DPI_COLOR_CODING_16BIT_2 0x1 42 #define DPI_COLOR_CODING_16BIT_3 0x2 43 #define DPI_COLOR_CODING_18BIT_1 0x3 44 #define DPI_COLOR_CODING_18BIT_2 0x4 45 #define DPI_COLOR_CODING_24BIT 0x5 46 47 #define DSI_DPI_CFG_POL 0x14 48 #define COLORM_ACTIVE_LOW BIT(4) 49 #define SHUTD_ACTIVE_LOW BIT(3) 50 #define HSYNC_ACTIVE_LOW BIT(2) 51 #define VSYNC_ACTIVE_LOW BIT(1) 52 #define DATAEN_ACTIVE_LOW BIT(0) 53 54 #define DSI_DPI_LP_CMD_TIM 0x18 55 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) 56 #define INVACT_LPCMD_TIME(p) ((p) & 0xff) 57 58 #define DSI_DBI_VCID 0x1c 59 #define DBI_VCID(x) UPDATE(x, 1, 0) 60 #define DSI_DBI_CFG 0x20 61 #define DSI_DBI_CMDSIZE 0x28 62 63 #define DSI_PCKHDL_CFG 0x2c 64 #define CRC_RX_EN BIT(4) 65 #define ECC_RX_EN BIT(3) 66 #define BTA_EN BIT(2) 67 #define EOTP_RX_EN BIT(1) 68 #define EOTP_TX_EN BIT(0) 69 #define DSI_MODE_CFG 0x34 70 #define CMD_VIDEO_MODE BIT(0) 71 #define COMMAND_MODE BIT(0) 72 #define VIDEO_MODE 0 73 #define DSI_VID_MODE_CFG 0x38 74 #define VPG_EN BIT(16) 75 #define LP_CMD_EN BIT(15) 76 #define FRAME_BTA_ACK BIT(14) 77 #define LP_HFP_EN BIT(13) 78 #define LP_HBP_EN BIT(12) 79 #define LP_VACT_EN BIT(11) 80 #define LP_VFP_EN BIT(10) 81 #define LP_VBP_EN BIT(9) 82 #define LP_VSA_EN BIT(8) 83 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0 84 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1 85 #define VID_MODE_TYPE_BURST 0x2 86 87 #define DSI_VID_PKT_SIZE 0x3c 88 #define VID_PKT_SIZE(p) (((p) & 0x3fff) << 0) 89 #define VID_PKT_MAX_SIZE 0x3fff 90 91 #define DSI_VID_NUM_CHUMKS 0x40 92 #define DSI_VID_NULL_PKT_SIZE 0x44 93 #define DSI_VID_HSA_TIME 0x48 94 #define DSI_VID_HBP_TIME 0x4c 95 #define DSI_VID_HLINE_TIME 0x50 96 #define DSI_VID_VSA_LINES 0x54 97 #define DSI_VID_VBP_LINES 0x58 98 #define DSI_VID_VFP_LINES 0x5c 99 #define DSI_VID_VACTIVE_LINES 0x60 100 #define DSI_EDPI_CMD_SIZE 0x64 101 #define DSI_CMD_MODE_CFG 0x68 102 #define MAX_RD_PKT_SIZE BIT(24) 103 #define DCS_LW_TX BIT(19) 104 #define DCS_SR_0P_TX BIT(18) 105 #define DCS_SW_1P_TX BIT(17) 106 #define DCS_SW_0P_TX BIT(16) 107 #define GEN_LW_TX BIT(14) 108 #define GEN_SR_2P_TX BIT(13) 109 #define GEN_SR_1P_TX BIT(12) 110 #define GEN_SR_0P_TX BIT(11) 111 #define GEN_SW_2P_TX BIT(10) 112 #define GEN_SW_1P_TX BIT(9) 113 #define GEN_SW_0P_TX BIT(8) 114 #define ACK_RQST_EN BIT(1) 115 #define TEAR_FX_EN BIT(0) 116 117 #define DSI_GEN_HDR 0x6c 118 #define GEN_HDATA(data) (((data) & 0xffff) << 8) 119 #define GEN_HDATA_MASK (0xffff << 8) 120 #define GEN_HTYPE(type) (((type) & 0xff) << 0) 121 #define GEN_HTYPE_MASK 0xff 122 123 #define DSI_GEN_PLD_DATA 0x70 124 125 #define DSI_CMD_PKT_STATUS 0x74 126 #define GEN_CMD_EMPTY BIT(0) 127 #define GEN_CMD_FULL BIT(1) 128 #define GEN_PLD_W_EMPTY BIT(2) 129 #define GEN_PLD_W_FULL BIT(3) 130 #define GEN_PLD_R_EMPTY BIT(4) 131 #define GEN_PLD_R_FULL BIT(5) 132 #define GEN_RD_CMD_BUSY BIT(6) 133 134 #define DSI_TO_CNT_CFG 0x78 135 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16) 136 #define LPRX_TO_CNT(p) ((p) & 0xffff) 137 138 #define DSI_BTA_TO_CNT 0x8c 139 #define DSI_LPCLK_CTRL 0x94 140 #define AUTO_CLKLANE_CTRL BIT(1) 141 #define PHY_TXREQUESTCLKHS BIT(0) 142 143 #define DSI_PHY_TMR_LPCLK_CFG 0x98 144 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16) 145 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff) 146 147 #define DSI_PHY_TMR_CFG 0x9c 148 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24) 149 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16) 150 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff) 151 152 #define DSI_PHY_RSTZ 0xa0 153 #define PHY_ENFORCEPLL BIT(3) 154 #define PHY_ENABLECLK BIT(2) 155 #define PHY_RSTZ BIT(1) 156 #define PHY_SHUTDOWNZ BIT(0) 157 158 #define DSI_PHY_IF_CFG 0xa4 159 #define N_LANES(n) ((((n) - 1) & 0x3) << 0) 160 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 161 162 #define DSI_PHY_STATUS 0xb0 163 #define PHY_STOPSTATE0LANE BIT(4) 164 #define PHY_STOPSTATECLKLANE BIT(2) 165 #define PHY_LOCK BIT(0) 166 #define PHY_STOPSTATELANE (PHY_STOPSTATE0LANE | \ 167 PHY_STOPSTATECLKLANE) 168 169 #define DSI_PHY_TST_CTRL0 0xb4 170 #define PHY_TESTCLK BIT(1) 171 #define PHY_TESTCLR BIT(0) 172 173 #define DSI_PHY_TST_CTRL1 0xb8 174 #define PHY_TESTEN BIT(16) 175 #define PHY_TESTDOUT_SHIFT 8 176 #define PHY_TESTDIN_MASK GENMASK(7, 0) 177 #define PHY_TESTDIN(x) UPDATE(x, 7, 0) 178 179 #define DSI_INT_ST0 0xbc 180 #define DSI_INT_ST1 0xc0 181 #define DSI_INT_MSK0 0xc4 182 #define DSI_INT_MSK1 0xc8 183 184 #define PHY_STATUS_TIMEOUT_US 10000 185 #define CMD_PKT_STATUS_TIMEOUT_US 20000 186 187 /* Test Code: 0x44 (HS RX Control of Lane 0) */ 188 #define HSFREQRANGE(x) UPDATE(x, 6, 1) 189 /* Test Code: 0x17 (PLL Input Divider Ratio) */ 190 #define INPUT_DIV(x) UPDATE(x, 6, 0) 191 /* Test Code: 0x18 (PLL Loop Divider Ratio) */ 192 #define FEEDBACK_DIV_LO(x) UPDATE(x, 4, 0) 193 #define FEEDBACK_DIV_HI(x) (BIT(7) | UPDATE(x, 3, 0)) 194 195 #define GRF_REG_FIELD(reg, lsb, msb) ((reg << 16) | (lsb << 8) | (msb)) 196 197 enum grf_reg_fields { 198 DPIUPDATECFG, 199 DPISHUTDN, 200 DPICOLORM, 201 VOPSEL, 202 TURNREQUEST, 203 TURNDISABLE, 204 FORCETXSTOPMODE, 205 FORCERXMODE, 206 ENABLE_N, 207 MASTERSLAVEZ, 208 ENABLECLK, 209 BASEDIR, 210 MAX_FIELDS, 211 }; 212 213 struct dw_mipi_dsi_plat_data { 214 const u32 *dsi0_grf_reg_fields; 215 const u32 *dsi1_grf_reg_fields; 216 unsigned long max_bit_rate_per_lane; 217 }; 218 219 struct mipi_dphy { 220 /* Non-SNPS PHY */ 221 struct rockchip_phy *phy; 222 223 u16 input_div; 224 u16 feedback_div; 225 }; 226 227 struct dw_mipi_dsi { 228 struct udevice *dev; 229 void *base; 230 void *grf; 231 int id; 232 233 /* for dual-channel */ 234 struct dw_mipi_dsi *master; 235 struct dw_mipi_dsi *slave; 236 237 unsigned int lane_mbps; /* per lane */ 238 u32 channel; 239 u32 lanes; 240 u32 format; 241 u32 mode_flags; 242 struct mipi_dphy dphy; 243 struct drm_display_mode *mode; 244 245 const struct dw_mipi_dsi_plat_data *pdata; 246 }; 247 248 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) 249 { 250 writel(val, dsi->base + reg); 251 } 252 253 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) 254 { 255 return readl(dsi->base + reg); 256 } 257 258 static inline void dsi_update_bits(struct dw_mipi_dsi *dsi, 259 u32 reg, u32 mask, u32 val) 260 { 261 u32 orig, tmp; 262 263 orig = dsi_read(dsi, reg); 264 tmp = orig & ~mask; 265 tmp |= val & mask; 266 dsi_write(dsi, reg, tmp); 267 } 268 269 static void grf_field_write(struct dw_mipi_dsi *dsi, enum grf_reg_fields index, 270 unsigned int val) 271 { 272 const u32 field = dsi->id ? dsi->pdata->dsi1_grf_reg_fields[index] : 273 dsi->pdata->dsi0_grf_reg_fields[index]; 274 u16 reg; 275 u8 msb, lsb; 276 277 if (!field) 278 return; 279 280 reg = (field >> 16) & 0xffff; 281 lsb = (field >> 8) & 0xff; 282 msb = (field >> 0) & 0xff; 283 284 rk_clrsetreg(dsi->grf + reg, GENMASK(msb, lsb), val << lsb); 285 } 286 287 static inline void dpishutdn_assert(struct dw_mipi_dsi *dsi) 288 { 289 grf_field_write(dsi, DPISHUTDN, 1); 290 } 291 292 static inline void dpishutdn_deassert(struct dw_mipi_dsi *dsi) 293 { 294 grf_field_write(dsi, DPISHUTDN, 0); 295 } 296 297 static int genif_wait_w_pld_fifo_not_full(struct dw_mipi_dsi *dsi) 298 { 299 u32 sts; 300 int ret; 301 302 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 303 sts, !(sts & GEN_PLD_W_FULL), 10, 304 CMD_PKT_STATUS_TIMEOUT_US); 305 if (ret < 0) { 306 printf("generic write payload fifo is full\n"); 307 return ret; 308 } 309 310 return 0; 311 } 312 313 static int genif_wait_cmd_fifo_not_full(struct dw_mipi_dsi *dsi) 314 { 315 u32 sts; 316 int ret; 317 318 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 319 sts, !(sts & GEN_CMD_FULL), 10, 320 CMD_PKT_STATUS_TIMEOUT_US); 321 if (ret < 0) { 322 printf("generic write cmd fifo is full\n"); 323 return ret; 324 } 325 326 return 0; 327 } 328 329 static int genif_wait_write_fifo_empty(struct dw_mipi_dsi *dsi) 330 { 331 u32 sts; 332 u32 mask; 333 int ret; 334 335 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 336 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 337 sts, (sts & mask) == mask, 10, 338 CMD_PKT_STATUS_TIMEOUT_US); 339 if (ret < 0) { 340 printf("generic write fifo is full\n"); 341 return ret; 342 } 343 344 return 0; 345 } 346 347 static inline void mipi_dphy_enableclk_assert(struct dw_mipi_dsi *dsi) 348 { 349 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK); 350 udelay(1); 351 } 352 353 static inline void mipi_dphy_enableclk_deassert(struct dw_mipi_dsi *dsi) 354 { 355 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, 0); 356 udelay(1); 357 } 358 359 static inline void mipi_dphy_shutdownz_assert(struct dw_mipi_dsi *dsi) 360 { 361 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, 0); 362 udelay(1); 363 } 364 365 static inline void mipi_dphy_shutdownz_deassert(struct dw_mipi_dsi *dsi) 366 { 367 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, PHY_SHUTDOWNZ); 368 udelay(1); 369 } 370 371 static inline void mipi_dphy_rstz_assert(struct dw_mipi_dsi *dsi) 372 { 373 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, 0); 374 udelay(1); 375 } 376 377 static inline void mipi_dphy_rstz_deassert(struct dw_mipi_dsi *dsi) 378 { 379 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, PHY_RSTZ); 380 udelay(1); 381 } 382 383 static inline void testif_testclk_assert(struct dw_mipi_dsi *dsi) 384 { 385 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK); 386 udelay(1); 387 } 388 389 static inline void testif_testclk_deassert(struct dw_mipi_dsi *dsi) 390 { 391 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK, 0); 392 udelay(1); 393 } 394 395 static inline void testif_testclr_assert(struct dw_mipi_dsi *dsi) 396 { 397 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR, PHY_TESTCLR); 398 udelay(1); 399 } 400 401 static inline void testif_testclr_deassert(struct dw_mipi_dsi *dsi) 402 { 403 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR, 0); 404 udelay(1); 405 } 406 407 static inline void testif_testen_assert(struct dw_mipi_dsi *dsi) 408 { 409 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN, PHY_TESTEN); 410 udelay(1); 411 } 412 413 static inline void testif_testen_deassert(struct dw_mipi_dsi *dsi) 414 { 415 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN, 0); 416 udelay(1); 417 } 418 419 static inline void testif_set_data(struct dw_mipi_dsi *dsi, u8 data) 420 { 421 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, 422 PHY_TESTDIN_MASK, PHY_TESTDIN(data)); 423 udelay(1); 424 } 425 426 static inline u8 testif_get_data(struct dw_mipi_dsi *dsi) 427 { 428 return dsi_read(dsi, DSI_PHY_TST_CTRL1) >> PHY_TESTDOUT_SHIFT; 429 } 430 431 static void testif_test_code_write(struct dw_mipi_dsi *dsi, u8 test_code) 432 { 433 testif_testclk_assert(dsi); 434 testif_set_data(dsi, test_code); 435 testif_testen_assert(dsi); 436 testif_testclk_deassert(dsi); 437 testif_testen_deassert(dsi); 438 } 439 440 static void testif_test_data_write(struct dw_mipi_dsi *dsi, u8 test_data) 441 { 442 testif_testclk_deassert(dsi); 443 testif_set_data(dsi, test_data); 444 testif_testclk_assert(dsi); 445 } 446 447 static void testif_write(struct dw_mipi_dsi *dsi, u8 test_code, u8 test_data) 448 { 449 testif_test_code_write(dsi, test_code); 450 testif_test_data_write(dsi, test_data); 451 452 dev_dbg(dsi->dev, 453 "test_code=0x%02x, test_data=0x%02x, monitor_data=0x%02x\n", 454 test_code, test_data, testif_get_data(dsi)); 455 } 456 457 static int mipi_dphy_power_on(struct dw_mipi_dsi *dsi) 458 { 459 u32 mask, val; 460 int ret; 461 462 mipi_dphy_shutdownz_deassert(dsi); 463 mipi_dphy_rstz_deassert(dsi); 464 mdelay(2); 465 466 if (dsi->dphy.phy) { 467 rockchip_phy_set_mode(dsi->dphy.phy, PHY_MODE_VIDEO_MIPI); 468 rockchip_phy_power_on(dsi->dphy.phy); 469 } 470 471 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 472 val, val & PHY_LOCK, 473 1000, PHY_STATUS_TIMEOUT_US); 474 if (ret < 0) { 475 dev_err(dsi->dev, "PHY is not locked\n"); 476 return ret; 477 } 478 479 udelay(200); 480 481 mask = PHY_STOPSTATELANE; 482 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 483 val, (val & mask) == mask, 484 1000, PHY_STATUS_TIMEOUT_US); 485 if (ret < 0) { 486 dev_err(dsi->dev, "lane module is not in stop state\n"); 487 return ret; 488 } 489 490 udelay(10); 491 492 return 0; 493 } 494 495 static void dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) 496 { 497 /* Table 5-1 Frequency Ranges */ 498 const struct { 499 unsigned long max_lane_mbps; 500 u8 hsfreqrange; 501 } hsfreqrange_table[] = { 502 { 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01}, 503 { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12}, 504 { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23}, 505 { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15}, 506 { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07}, 507 { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09}, 508 { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a}, 509 {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b}, 510 {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c}, 511 {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c} 512 }; 513 u8 hsfreqrange, counter; 514 unsigned int index, txbyteclkhs; 515 u16 n, m; 516 517 for (index = 0; index < ARRAY_SIZE(hsfreqrange_table); index++) 518 if (dsi->lane_mbps <= hsfreqrange_table[index].max_lane_mbps) 519 break; 520 521 if (index == ARRAY_SIZE(hsfreqrange_table)) 522 --index; 523 524 hsfreqrange = hsfreqrange_table[index].hsfreqrange; 525 testif_write(dsi, 0x44, HSFREQRANGE(hsfreqrange)); 526 527 txbyteclkhs = dsi->lane_mbps >> 3; 528 counter = txbyteclkhs * 60 / NSEC_PER_USEC; 529 testif_write(dsi, 0x60, 0x80 | counter); 530 testif_write(dsi, 0x70, 0x80 | counter); 531 532 n = dsi->dphy.input_div - 1; 533 m = dsi->dphy.feedback_div - 1; 534 testif_write(dsi, 0x19, 0x30); 535 testif_write(dsi, 0x17, INPUT_DIV(n)); 536 testif_write(dsi, 0x18, FEEDBACK_DIV_LO(m)); 537 testif_write(dsi, 0x18, FEEDBACK_DIV_HI(m >> 5)); 538 } 539 540 static unsigned long dw_mipi_dsi_get_lane_rate(struct dw_mipi_dsi *dsi) 541 { 542 const struct drm_display_mode *mode = dsi->mode; 543 unsigned long max_lane_rate = dsi->pdata->max_bit_rate_per_lane; 544 unsigned long lane_rate; 545 unsigned int value; 546 int bpp, lanes; 547 u64 tmp; 548 549 /* optional override of the desired bandwidth */ 550 value = dev_read_u32_default(dsi->dev, "rockchip,lane-rate", 0); 551 if (value > 0) 552 return value * USEC_PER_SEC; 553 554 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 555 if (bpp < 0) 556 bpp = 24; 557 558 lanes = dsi->slave ? dsi->lanes * 2 : dsi->lanes; 559 tmp = (u64)mode->clock * 1000 * bpp; 560 do_div(tmp, lanes); 561 562 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */ 563 tmp *= 10; 564 do_div(tmp, 9); 565 566 if (tmp > max_lane_rate) 567 lane_rate = max_lane_rate; 568 else 569 lane_rate = tmp; 570 571 return lane_rate; 572 } 573 574 static void dw_mipi_dsi_set_pll(struct dw_mipi_dsi *dsi, unsigned long rate) 575 { 576 unsigned long fin, fout; 577 unsigned long fvco_min, fvco_max, best_freq = 984000000; 578 u8 min_prediv, max_prediv; 579 u8 _prediv, best_prediv = 2; 580 u16 _fbdiv, best_fbdiv = 82; 581 u32 min_delta = ~0U; 582 583 fin = 24000000; 584 fout = rate; 585 586 /* 5Mhz < Fref / N < 40MHz, 80MHz < Fvco < 1500Mhz */ 587 min_prediv = DIV_ROUND_UP(fin, 40000000); 588 max_prediv = fin / 5000000; 589 fvco_min = 80000000; 590 fvco_max = 1500000000; 591 592 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 593 u64 tmp, _fout; 594 u32 delta; 595 596 /* Fvco = Fref * M / N */ 597 tmp = (u64)fout * _prediv; 598 do_div(tmp, fin); 599 _fbdiv = tmp; 600 601 /* 602 * Due to the use of a "by 2 pre-scaler," the range of the 603 * feedback multiplication value M is limited to even division 604 * numbers, and m must be greater than 12, less than 1000. 605 */ 606 if (_fbdiv <= 12 || _fbdiv >= 1000) 607 continue; 608 609 if (_fbdiv % 2) 610 ++_fbdiv; 611 612 _fout = (u64)_fbdiv * fin; 613 do_div(_fout, _prediv); 614 615 if (_fout < fvco_min || _fout > fvco_max) 616 continue; 617 618 delta = abs(fout - _fout); 619 if (!delta) { 620 best_prediv = _prediv; 621 best_fbdiv = _fbdiv; 622 best_freq = _fout; 623 break; 624 } else if (delta < min_delta) { 625 best_prediv = _prediv; 626 best_fbdiv = _fbdiv; 627 best_freq = _fout; 628 min_delta = delta; 629 } 630 } 631 632 dsi->lane_mbps = best_freq / USEC_PER_SEC; 633 dsi->dphy.input_div = best_prediv; 634 dsi->dphy.feedback_div = best_fbdiv; 635 if (dsi->slave) { 636 dsi->slave->lane_mbps = dsi->lane_mbps; 637 dsi->slave->dphy.input_div = dsi->dphy.input_div; 638 dsi->slave->dphy.feedback_div = dsi->dphy.feedback_div; 639 } 640 } 641 642 static int dw_mipi_dsi_read_from_fifo(struct dw_mipi_dsi *dsi, 643 const struct mipi_dsi_msg *msg) 644 { 645 u8 *payload = msg->rx_buf; 646 u16 length; 647 u32 val; 648 int ret; 649 650 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 651 val, !(val & GEN_RD_CMD_BUSY), 50, 5000); 652 if (ret) { 653 printf("entire response isn't stored in the FIFO\n"); 654 return ret; 655 } 656 657 /* Receive payload */ 658 for (length = msg->rx_len; length; length -= 4) { 659 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 660 val, !(val & GEN_PLD_R_EMPTY), 661 50, 5000); 662 if (ret) { 663 printf("Read payload FIFO is empty\n"); 664 return ret; 665 } 666 667 val = dsi_read(dsi, DSI_GEN_PLD_DATA); 668 669 switch (length) { 670 case 3: 671 payload[2] = (val >> 16) & 0xff; 672 /* Fall through */ 673 case 2: 674 payload[1] = (val >> 8) & 0xff; 675 /* Fall through */ 676 case 1: 677 payload[0] = val & 0xff; 678 return 0; 679 } 680 681 payload[0] = (val >> 0) & 0xff; 682 payload[1] = (val >> 8) & 0xff; 683 payload[2] = (val >> 16) & 0xff; 684 payload[3] = (val >> 24) & 0xff; 685 payload += 4; 686 } 687 688 return 0; 689 } 690 691 static int dw_mipi_dsi_turn_on_peripheral(struct dw_mipi_dsi *dsi) 692 { 693 dpishutdn_assert(dsi); 694 udelay(20); 695 dpishutdn_deassert(dsi); 696 697 return 0; 698 } 699 700 static int dw_mipi_dsi_shutdown_peripheral(struct dw_mipi_dsi *dsi) 701 { 702 dpishutdn_deassert(dsi); 703 udelay(20); 704 dpishutdn_assert(dsi); 705 706 return 0; 707 } 708 709 static ssize_t dw_mipi_dsi_transfer(struct dw_mipi_dsi *dsi, 710 const struct mipi_dsi_msg *msg) 711 { 712 struct mipi_dsi_packet packet; 713 int ret; 714 int val; 715 716 if (dsi->mode_flags & MIPI_DSI_MODE_LPM) { 717 dsi_update_bits(dsi, DSI_VID_MODE_CFG, LP_CMD_EN, LP_CMD_EN); 718 dsi_update_bits(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS, 0); 719 } else { 720 dsi_update_bits(dsi, DSI_VID_MODE_CFG, LP_CMD_EN, 0); 721 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 722 PHY_TXREQUESTCLKHS, PHY_TXREQUESTCLKHS); 723 } 724 725 switch (msg->type) { 726 case MIPI_DSI_SHUTDOWN_PERIPHERAL: 727 return dw_mipi_dsi_shutdown_peripheral(dsi); 728 case MIPI_DSI_TURN_ON_PERIPHERAL: 729 return dw_mipi_dsi_turn_on_peripheral(dsi); 730 case MIPI_DSI_DCS_SHORT_WRITE: 731 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_0P_TX, 732 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 733 DCS_SW_0P_TX : 0); 734 break; 735 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 736 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_1P_TX, 737 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 738 DCS_SW_1P_TX : 0); 739 break; 740 case MIPI_DSI_DCS_LONG_WRITE: 741 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX, 742 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 743 DCS_LW_TX : 0); 744 break; 745 case MIPI_DSI_DCS_READ: 746 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SR_0P_TX, 747 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 748 DCS_SR_0P_TX : 0); 749 break; 750 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: 751 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, MAX_RD_PKT_SIZE, 752 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 753 MAX_RD_PKT_SIZE : 0); 754 break; 755 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 756 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_0P_TX, 757 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 758 GEN_SW_0P_TX : 0); 759 break; 760 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 761 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_1P_TX, 762 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 763 GEN_SW_1P_TX : 0); 764 break; 765 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 766 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_2P_TX, 767 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 768 GEN_SW_2P_TX : 0); 769 break; 770 case MIPI_DSI_GENERIC_LONG_WRITE: 771 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_LW_TX, 772 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 773 GEN_LW_TX : 0); 774 break; 775 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 776 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_0P_TX, 777 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 778 GEN_SR_0P_TX : 0); 779 break; 780 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 781 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_1P_TX, 782 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 783 GEN_SR_1P_TX : 0); 784 break; 785 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 786 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_2P_TX, 787 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 788 GEN_SR_2P_TX : 0); 789 break; 790 default: 791 return -EINVAL; 792 } 793 794 if (msg->flags & MIPI_DSI_MSG_REQ_ACK) 795 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, 796 ACK_RQST_EN, ACK_RQST_EN); 797 798 /* create a packet to the DSI protocol */ 799 ret = mipi_dsi_create_packet(&packet, msg); 800 if (ret) { 801 printf("failed to create packet: %d\n", ret); 802 return ret; 803 } 804 805 /* Send payload */ 806 while (DIV_ROUND_UP(packet.payload_length, 4)) { 807 /* 808 * Alternatively, you can always keep the FIFO 809 * nearly full by monitoring the FIFO state until 810 * it is not full, and then writea single word of data. 811 * This solution is more resource consuming 812 * but it simultaneously avoids FIFO starvation, 813 * making it possible to use FIFO sizes smaller than 814 * the amount of data of the longest packet to be written. 815 */ 816 ret = genif_wait_w_pld_fifo_not_full(dsi); 817 if (ret) 818 return ret; 819 820 if (packet.payload_length < 4) { 821 /* send residu payload */ 822 val = 0; 823 memcpy(&val, packet.payload, packet.payload_length); 824 dsi_write(dsi, DSI_GEN_PLD_DATA, val); 825 packet.payload_length = 0; 826 } else { 827 val = get_unaligned_le32(packet.payload); 828 dsi_write(dsi, DSI_GEN_PLD_DATA, val); 829 packet.payload += 4; 830 packet.payload_length -= 4; 831 } 832 } 833 834 ret = genif_wait_cmd_fifo_not_full(dsi); 835 if (ret) 836 return ret; 837 838 /* Send packet header */ 839 val = get_unaligned_le32(packet.header); 840 dsi_write(dsi, DSI_GEN_HDR, val); 841 842 ret = genif_wait_write_fifo_empty(dsi); 843 if (ret) 844 return ret; 845 846 if (msg->rx_len) { 847 ret = dw_mipi_dsi_read_from_fifo(dsi, msg); 848 if (ret < 0) 849 return ret; 850 } 851 852 if (dsi->slave) { 853 ret = dw_mipi_dsi_transfer(dsi->slave, msg); 854 if (ret < 0) 855 return ret; 856 } 857 858 return msg->rx_len ? msg->rx_len : msg->tx_len; 859 } 860 861 static ssize_t dw_mipi_dsi_connector_transfer(struct display_state *state, 862 const struct mipi_dsi_msg *msg) 863 { 864 struct connector_state *conn_state = &state->conn_state; 865 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 866 867 return dw_mipi_dsi_transfer(dsi, msg); 868 } 869 870 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) 871 { 872 u32 val = LP_VACT_EN | LP_VFP_EN | LP_VBP_EN | LP_VSA_EN | 873 LP_HFP_EN | LP_HBP_EN; 874 875 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) 876 val &= ~LP_HFP_EN; 877 878 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) 879 val &= ~LP_HBP_EN; 880 881 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 882 val |= VID_MODE_TYPE_BURST; 883 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 884 val |= VID_MODE_TYPE_BURST_SYNC_PULSES; 885 else 886 val |= VID_MODE_TYPE_BURST_SYNC_EVENTS; 887 888 dsi_write(dsi, DSI_VID_MODE_CFG, val); 889 890 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 891 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 892 AUTO_CLKLANE_CTRL, AUTO_CLKLANE_CTRL); 893 } 894 895 static void dw_mipi_dsi_enable(struct dw_mipi_dsi *dsi) 896 { 897 const struct drm_display_mode *mode = dsi->mode; 898 899 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 900 PHY_TXREQUESTCLKHS, PHY_TXREQUESTCLKHS); 901 902 dsi_write(dsi, DSI_PWR_UP, RESET); 903 904 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 905 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, VIDEO_MODE); 906 } else { 907 dsi_write(dsi, DSI_DBI_VCID, DBI_VCID(dsi->channel)); 908 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX, 0); 909 dsi_write(dsi, DSI_EDPI_CMD_SIZE, mode->hdisplay); 910 dsi_update_bits(dsi, DSI_MODE_CFG, 911 CMD_VIDEO_MODE, COMMAND_MODE); 912 } 913 914 dsi_write(dsi, DSI_PWR_UP, POWERUP); 915 916 if (dsi->slave) 917 dw_mipi_dsi_enable(dsi->slave); 918 } 919 920 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) 921 { 922 dsi_write(dsi, DSI_PWR_UP, RESET); 923 dsi_write(dsi, DSI_LPCLK_CTRL, 0); 924 dsi_write(dsi, DSI_EDPI_CMD_SIZE, 0); 925 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, COMMAND_MODE); 926 dsi_write(dsi, DSI_PWR_UP, POWERUP); 927 928 if (dsi->slave) 929 dw_mipi_dsi_disable(dsi->slave); 930 } 931 932 static void dw_mipi_dsi_post_disable(struct dw_mipi_dsi *dsi) 933 { 934 dsi_write(dsi, DSI_PWR_UP, RESET); 935 dsi_write(dsi, DSI_PHY_RSTZ, 0); 936 937 if (dsi->slave) 938 dw_mipi_dsi_post_disable(dsi->slave); 939 } 940 941 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) 942 { 943 u32 esc_clk_div; 944 945 dsi_write(dsi, DSI_PWR_UP, RESET); 946 947 /* The maximum value of the escape clock frequency is 20MHz */ 948 esc_clk_div = DIV_ROUND_UP(dsi->lane_mbps >> 3, 20); 949 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) | 950 TX_ESC_CLK_DIVIDSION(esc_clk_div)); 951 } 952 953 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, 954 struct drm_display_mode *mode) 955 { 956 u32 val = 0, color = 0; 957 958 switch (dsi->format) { 959 case MIPI_DSI_FMT_RGB888: 960 color = DPI_COLOR_CODING_24BIT; 961 break; 962 case MIPI_DSI_FMT_RGB666: 963 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY; 964 break; 965 case MIPI_DSI_FMT_RGB666_PACKED: 966 color = DPI_COLOR_CODING_18BIT_1; 967 break; 968 case MIPI_DSI_FMT_RGB565: 969 color = DPI_COLOR_CODING_16BIT_1; 970 break; 971 } 972 973 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 974 val |= VSYNC_ACTIVE_LOW; 975 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 976 val |= HSYNC_ACTIVE_LOW; 977 978 dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel)); 979 dsi_write(dsi, DSI_DPI_COLOR_CODING, color); 980 dsi_write(dsi, DSI_DPI_CFG_POL, val); 981 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4) 982 | INVACT_LPCMD_TIME(4)); 983 } 984 985 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi) 986 { 987 u32 val = CRC_RX_EN | ECC_RX_EN | BTA_EN | EOTP_TX_EN; 988 989 if (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 990 val &= ~EOTP_TX_EN; 991 992 dsi_write(dsi, DSI_PCKHDL_CFG, val); 993 } 994 995 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, 996 struct drm_display_mode *mode) 997 { 998 int pkt_size; 999 1000 if (dsi->slave || dsi->master) 1001 pkt_size = VID_PKT_SIZE(mode->hdisplay / 2); 1002 else 1003 pkt_size = VID_PKT_SIZE(mode->hdisplay); 1004 1005 dsi_write(dsi, DSI_VID_PKT_SIZE, pkt_size); 1006 } 1007 1008 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) 1009 { 1010 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000)); 1011 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); 1012 } 1013 1014 /* Get lane byte clock cycles. */ 1015 static int dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, 1016 u32 hcomponent) 1017 { 1018 u32 lbcc; 1019 1020 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8; 1021 1022 if (dsi->mode->clock == 0) { 1023 printf("dsi mode clock is 0!\n"); 1024 return 0; 1025 } 1026 1027 return DIV_ROUND_CLOSEST(lbcc, dsi->mode->clock); 1028 } 1029 1030 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi) 1031 { 1032 int htotal, hsa, hbp, lbcc; 1033 struct drm_display_mode *mode = dsi->mode; 1034 1035 htotal = mode->htotal; 1036 hsa = mode->hsync_end - mode->hsync_start; 1037 hbp = mode->htotal - mode->hsync_end; 1038 1039 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal); 1040 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); 1041 1042 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa); 1043 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); 1044 1045 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp); 1046 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); 1047 } 1048 1049 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi) 1050 { 1051 u32 vactive, vsa, vfp, vbp; 1052 struct drm_display_mode *mode = dsi->mode; 1053 1054 vactive = mode->vdisplay; 1055 vsa = mode->vsync_end - mode->vsync_start; 1056 vfp = mode->vsync_start - mode->vdisplay; 1057 vbp = mode->vtotal - mode->vsync_end; 1058 1059 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); 1060 dsi_write(dsi, DSI_VID_VSA_LINES, vsa); 1061 dsi_write(dsi, DSI_VID_VFP_LINES, vfp); 1062 dsi_write(dsi, DSI_VID_VBP_LINES, vbp); 1063 } 1064 1065 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) 1066 { 1067 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14) 1068 | PHY_LP2HS_TIME(0x10) | MAX_RD_TIME(10000)); 1069 1070 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40) 1071 | PHY_CLKLP2HS_TIME(0x40)); 1072 } 1073 1074 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) 1075 { 1076 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) | 1077 N_LANES(dsi->lanes)); 1078 } 1079 1080 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) 1081 { 1082 dsi_read(dsi, DSI_INT_ST0); 1083 dsi_read(dsi, DSI_INT_ST1); 1084 dsi_write(dsi, DSI_INT_MSK0, 0); 1085 dsi_write(dsi, DSI_INT_MSK1, 0); 1086 } 1087 1088 static int dw_mipi_dsi_connector_init(struct display_state *state) 1089 { 1090 struct connector_state *conn_state = &state->conn_state; 1091 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1092 struct rockchip_panel *panel = state_get_panel(state); 1093 1094 dsi->dphy.phy = conn_state->phy; 1095 1096 dsi->lanes = dev_read_u32_default(panel->dev, "dsi,lanes", 4); 1097 dsi->format = dev_read_u32_default(panel->dev, "dsi,format", 1098 MIPI_DSI_FMT_RGB888); 1099 dsi->mode_flags = dev_read_u32_default(panel->dev, "dsi,flags", 1100 MIPI_DSI_MODE_VIDEO | 1101 MIPI_DSI_MODE_VIDEO_BURST | 1102 MIPI_DSI_MODE_LPM | 1103 MIPI_DSI_MODE_EOT_PACKET); 1104 dsi->channel = dev_read_u32_default(panel->dev, "reg", 0); 1105 1106 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 1107 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 1108 conn_state->type = DRM_MODE_CONNECTOR_DSI; 1109 1110 if (dsi->slave) { 1111 dsi->lanes /= 2; 1112 dsi->slave->lanes = dsi->lanes; 1113 dsi->slave->format = dsi->format; 1114 dsi->slave->mode_flags = dsi->mode_flags; 1115 dsi->slave->channel = dsi->channel; 1116 conn_state->output_type = ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL; 1117 } 1118 1119 return 0; 1120 } 1121 1122 static void dw_mipi_dsi_set_hs_clk(struct dw_mipi_dsi *dsi, unsigned long rate) 1123 { 1124 rate = rockchip_phy_set_pll(dsi->dphy.phy, rate); 1125 dsi->lane_mbps = rate / USEC_PER_SEC; 1126 } 1127 1128 static void dw_mipi_dsi_host_init(struct dw_mipi_dsi *dsi) 1129 { 1130 dw_mipi_dsi_init(dsi); 1131 dw_mipi_dsi_dpi_config(dsi, dsi->mode); 1132 dw_mipi_dsi_packet_handler_config(dsi); 1133 dw_mipi_dsi_video_mode_config(dsi); 1134 dw_mipi_dsi_video_packet_config(dsi, dsi->mode); 1135 dw_mipi_dsi_command_mode_config(dsi); 1136 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, COMMAND_MODE); 1137 dw_mipi_dsi_line_timer_config(dsi); 1138 dw_mipi_dsi_vertical_timing_config(dsi); 1139 dw_mipi_dsi_dphy_timing_config(dsi); 1140 dw_mipi_dsi_dphy_interface_config(dsi); 1141 dw_mipi_dsi_clear_err(dsi); 1142 } 1143 1144 static void dw_mipi_dsi_vop_routing(struct dw_mipi_dsi *dsi, int vop_id) 1145 { 1146 grf_field_write(dsi, VOPSEL, vop_id); 1147 1148 if (dsi->slave) 1149 grf_field_write(dsi->slave, VOPSEL, vop_id); 1150 } 1151 1152 static void mipi_dphy_init(struct dw_mipi_dsi *dsi) 1153 { 1154 u32 map[] = {0x1, 0x3, 0x7, 0xf}; 1155 1156 mipi_dphy_enableclk_deassert(dsi); 1157 mipi_dphy_shutdownz_assert(dsi); 1158 mipi_dphy_rstz_assert(dsi); 1159 testif_testclr_assert(dsi); 1160 1161 /* Configures DPHY to work as a Master */ 1162 grf_field_write(dsi, MASTERSLAVEZ, 1); 1163 1164 /* Configures lane as TX */ 1165 grf_field_write(dsi, BASEDIR, 0); 1166 1167 /* Set all REQUEST inputs to zero */ 1168 grf_field_write(dsi, TURNREQUEST, 0); 1169 grf_field_write(dsi, TURNDISABLE, 0); 1170 grf_field_write(dsi, FORCETXSTOPMODE, 0); 1171 grf_field_write(dsi, FORCERXMODE, 0); 1172 udelay(1); 1173 1174 testif_testclr_deassert(dsi); 1175 1176 if (!dsi->dphy.phy) 1177 dw_mipi_dsi_phy_init(dsi); 1178 1179 /* Enable Data Lane Module */ 1180 grf_field_write(dsi, ENABLE_N, map[dsi->lanes - 1]); 1181 1182 /* Enable Clock Lane Module */ 1183 grf_field_write(dsi, ENABLECLK, 1); 1184 1185 mipi_dphy_enableclk_assert(dsi); 1186 } 1187 1188 static void dw_mipi_dsi_pre_enable(struct dw_mipi_dsi *dsi) 1189 { 1190 dw_mipi_dsi_host_init(dsi); 1191 mipi_dphy_init(dsi); 1192 mipi_dphy_power_on(dsi); 1193 dsi_write(dsi, DSI_PWR_UP, POWERUP); 1194 1195 if (dsi->slave) 1196 dw_mipi_dsi_pre_enable(dsi->slave); 1197 } 1198 1199 static int dw_mipi_dsi_connector_prepare(struct display_state *state) 1200 { 1201 struct connector_state *conn_state = &state->conn_state; 1202 struct crtc_state *crtc_state = &state->crtc_state; 1203 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1204 unsigned long lane_rate; 1205 1206 dsi->mode = &conn_state->mode; 1207 if (dsi->slave) 1208 dsi->slave->mode = dsi->mode; 1209 1210 lane_rate = dw_mipi_dsi_get_lane_rate(dsi); 1211 if (dsi->dphy.phy) 1212 dw_mipi_dsi_set_hs_clk(dsi, lane_rate); 1213 else 1214 dw_mipi_dsi_set_pll(dsi, lane_rate); 1215 1216 printf("final DSI-Link bandwidth: %u Mbps x %d\n", 1217 dsi->lane_mbps, dsi->slave ? dsi->lanes * 2 : dsi->lanes); 1218 1219 dw_mipi_dsi_vop_routing(dsi, crtc_state->crtc_id); 1220 dw_mipi_dsi_pre_enable(dsi); 1221 1222 return 0; 1223 } 1224 1225 static void dw_mipi_dsi_connector_unprepare(struct display_state *state) 1226 { 1227 struct connector_state *conn_state = &state->conn_state; 1228 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1229 1230 dw_mipi_dsi_post_disable(dsi); 1231 } 1232 1233 static int dw_mipi_dsi_connector_enable(struct display_state *state) 1234 { 1235 struct connector_state *conn_state = &state->conn_state; 1236 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1237 1238 dw_mipi_dsi_enable(dsi); 1239 1240 return 0; 1241 } 1242 1243 static int dw_mipi_dsi_connector_disable(struct display_state *state) 1244 { 1245 struct connector_state *conn_state = &state->conn_state; 1246 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1247 1248 dw_mipi_dsi_disable(dsi); 1249 1250 return 0; 1251 } 1252 1253 static const struct rockchip_connector_funcs dw_mipi_dsi_connector_funcs = { 1254 .init = dw_mipi_dsi_connector_init, 1255 .prepare = dw_mipi_dsi_connector_prepare, 1256 .unprepare = dw_mipi_dsi_connector_unprepare, 1257 .enable = dw_mipi_dsi_connector_enable, 1258 .disable = dw_mipi_dsi_connector_disable, 1259 .transfer = dw_mipi_dsi_connector_transfer, 1260 }; 1261 1262 static int dw_mipi_dsi_dual_channel_probe(struct dw_mipi_dsi *master) 1263 { 1264 struct udevice *dev; 1265 struct dw_mipi_dsi *slave; 1266 int ret; 1267 1268 ret = uclass_get_device_by_phandle(UCLASS_DISPLAY, master->dev, 1269 "rockchip,dual-channel", &dev); 1270 if (ret == -ENOENT) { 1271 return 0; 1272 } else if (ret) { 1273 dev_err(dev, "failed to find slave device: %d\n", ret); 1274 return ret; 1275 } 1276 1277 slave = dev_get_priv(dev); 1278 if (!slave) { 1279 dev_err(dev, "failed to get slave channel\n"); 1280 return -ENODEV; 1281 } 1282 1283 master->slave = slave; 1284 slave->master = master; 1285 1286 return 0; 1287 } 1288 1289 static int dw_mipi_dsi_probe(struct udevice *dev) 1290 { 1291 struct dw_mipi_dsi *dsi = dev_get_priv(dev); 1292 const struct rockchip_connector *connector = 1293 (const struct rockchip_connector *)dev_get_driver_data(dev); 1294 const struct dw_mipi_dsi_plat_data *pdata = connector->data; 1295 int id, ret; 1296 1297 dsi->base = dev_read_addr_ptr(dev); 1298 dsi->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1299 if (IS_ERR(dsi->grf)) 1300 return PTR_ERR(dsi->grf); 1301 1302 id = of_alias_get_id(ofnode_to_np(dev->node), "dsi"); 1303 if (id < 0) 1304 id = 0; 1305 1306 dsi->dev = dev; 1307 dsi->pdata = pdata; 1308 dsi->id = id; 1309 1310 ret = dw_mipi_dsi_dual_channel_probe(dsi); 1311 if (ret) 1312 return ret; 1313 1314 return 0; 1315 } 1316 1317 static const u32 px30_dsi_grf_reg_fields[MAX_FIELDS] = { 1318 [DPIUPDATECFG] = GRF_REG_FIELD(0x0434, 7, 7), 1319 [DPICOLORM] = GRF_REG_FIELD(0x0434, 3, 3), 1320 [DPISHUTDN] = GRF_REG_FIELD(0x0434, 2, 2), 1321 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0438, 7, 10), 1322 [TURNDISABLE] = GRF_REG_FIELD(0x0438, 5, 5), 1323 [VOPSEL] = GRF_REG_FIELD(0x0438, 0, 0), 1324 }; 1325 1326 static const struct dw_mipi_dsi_plat_data px30_mipi_dsi_plat_data = { 1327 .dsi0_grf_reg_fields = px30_dsi_grf_reg_fields, 1328 .max_bit_rate_per_lane = 1000000000UL, 1329 }; 1330 1331 static const struct rockchip_connector px30_mipi_dsi_driver_data = { 1332 .funcs = &dw_mipi_dsi_connector_funcs, 1333 .data = &px30_mipi_dsi_plat_data, 1334 }; 1335 1336 static const u32 rk3128_dsi_grf_reg_fields[MAX_FIELDS] = { 1337 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0150, 10, 13), 1338 [FORCERXMODE] = GRF_REG_FIELD(0x0150, 9, 9), 1339 [TURNDISABLE] = GRF_REG_FIELD(0x0150, 8, 8), 1340 [DPICOLORM] = GRF_REG_FIELD(0x0150, 5, 5), 1341 [DPISHUTDN] = GRF_REG_FIELD(0x0150, 4, 4), 1342 }; 1343 1344 static const struct dw_mipi_dsi_plat_data rk3128_mipi_dsi_plat_data = { 1345 .dsi0_grf_reg_fields = rk3128_dsi_grf_reg_fields, 1346 .max_bit_rate_per_lane = 1000000000UL, 1347 }; 1348 1349 static const struct rockchip_connector rk3128_mipi_dsi_driver_data = { 1350 .funcs = &dw_mipi_dsi_connector_funcs, 1351 .data = &rk3128_mipi_dsi_plat_data, 1352 }; 1353 1354 static const u32 rk3288_dsi0_grf_reg_fields[MAX_FIELDS] = { 1355 [DPICOLORM] = GRF_REG_FIELD(0x025c, 8, 8), 1356 [DPISHUTDN] = GRF_REG_FIELD(0x025c, 7, 7), 1357 [VOPSEL] = GRF_REG_FIELD(0x025c, 6, 6), 1358 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0264, 8, 11), 1359 [FORCERXMODE] = GRF_REG_FIELD(0x0264, 4, 7), 1360 [TURNDISABLE] = GRF_REG_FIELD(0x0264, 0, 3), 1361 [TURNREQUEST] = GRF_REG_FIELD(0x03a4, 8, 10), 1362 [DPIUPDATECFG] = GRF_REG_FIELD(0x03a8, 0, 0), 1363 }; 1364 1365 static const u32 rk3288_dsi1_grf_reg_fields[MAX_FIELDS] = { 1366 [DPICOLORM] = GRF_REG_FIELD(0x025c, 11, 11), 1367 [DPISHUTDN] = GRF_REG_FIELD(0x025c, 10, 10), 1368 [VOPSEL] = GRF_REG_FIELD(0x025c, 9, 9), 1369 [ENABLE_N] = GRF_REG_FIELD(0x0268, 12, 15), 1370 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0268, 8, 11), 1371 [FORCERXMODE] = GRF_REG_FIELD(0x0268, 4, 7), 1372 [TURNDISABLE] = GRF_REG_FIELD(0x0268, 0, 3), 1373 [BASEDIR] = GRF_REG_FIELD(0x027c, 15, 15), 1374 [MASTERSLAVEZ] = GRF_REG_FIELD(0x027c, 14, 14), 1375 [ENABLECLK] = GRF_REG_FIELD(0x027c, 12, 12), 1376 [TURNREQUEST] = GRF_REG_FIELD(0x03a4, 4, 7), 1377 [DPIUPDATECFG] = GRF_REG_FIELD(0x03a8, 1, 1), 1378 }; 1379 1380 static const struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_plat_data = { 1381 .dsi0_grf_reg_fields = rk3288_dsi0_grf_reg_fields, 1382 .dsi1_grf_reg_fields = rk3288_dsi1_grf_reg_fields, 1383 .max_bit_rate_per_lane = 1500000000UL, 1384 }; 1385 1386 static const struct rockchip_connector rk3288_mipi_dsi_driver_data = { 1387 .funcs = &dw_mipi_dsi_connector_funcs, 1388 .data = &rk3288_mipi_dsi_plat_data, 1389 }; 1390 1391 static const u32 rk3366_dsi_grf_reg_fields[MAX_FIELDS] = { 1392 [VOPSEL] = GRF_REG_FIELD(0x0400, 2, 2), 1393 [DPIUPDATECFG] = GRF_REG_FIELD(0x0410, 9, 9), 1394 [DPICOLORM] = GRF_REG_FIELD(0x0410, 3, 3), 1395 [DPISHUTDN] = GRF_REG_FIELD(0x0410, 2, 2), 1396 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0414, 7, 10), 1397 [FORCERXMODE] = GRF_REG_FIELD(0x0414, 6, 6), 1398 [TURNDISABLE] = GRF_REG_FIELD(0x0414, 5, 5), 1399 }; 1400 1401 static const struct dw_mipi_dsi_plat_data rk3366_mipi_dsi_plat_data = { 1402 .dsi0_grf_reg_fields = rk3366_dsi_grf_reg_fields, 1403 .max_bit_rate_per_lane = 1000000000UL, 1404 }; 1405 1406 static const struct rockchip_connector rk3366_mipi_dsi_driver_data = { 1407 .funcs = &dw_mipi_dsi_connector_funcs, 1408 .data = &rk3366_mipi_dsi_plat_data, 1409 }; 1410 1411 static const u32 rk3368_dsi_grf_reg_fields[MAX_FIELDS] = { 1412 [DPIUPDATECFG] = GRF_REG_FIELD(0x0418, 7, 7), 1413 [DPICOLORM] = GRF_REG_FIELD(0x0418, 3, 3), 1414 [DPISHUTDN] = GRF_REG_FIELD(0x0418, 2, 2), 1415 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x041c, 7, 10), 1416 [FORCERXMODE] = GRF_REG_FIELD(0x041c, 6, 6), 1417 [TURNDISABLE] = GRF_REG_FIELD(0x041c, 5, 5), 1418 }; 1419 1420 static const struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_plat_data = { 1421 .dsi0_grf_reg_fields = rk3368_dsi_grf_reg_fields, 1422 .max_bit_rate_per_lane = 1000000000UL, 1423 }; 1424 1425 static const struct rockchip_connector rk3368_mipi_dsi_driver_data = { 1426 .funcs = &dw_mipi_dsi_connector_funcs, 1427 .data = &rk3368_mipi_dsi_plat_data, 1428 }; 1429 1430 static const u32 rk3399_dsi0_grf_reg_fields[MAX_FIELDS] = { 1431 [DPIUPDATECFG] = GRF_REG_FIELD(0x6224, 15, 15), 1432 [DPISHUTDN] = GRF_REG_FIELD(0x6224, 14, 14), 1433 [DPICOLORM] = GRF_REG_FIELD(0x6224, 13, 13), 1434 [VOPSEL] = GRF_REG_FIELD(0x6250, 0, 0), 1435 [TURNREQUEST] = GRF_REG_FIELD(0x6258, 12, 15), 1436 [TURNDISABLE] = GRF_REG_FIELD(0x6258, 8, 11), 1437 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x6258, 4, 7), 1438 [FORCERXMODE] = GRF_REG_FIELD(0x6258, 0, 3), 1439 }; 1440 1441 static const u32 rk3399_dsi1_grf_reg_fields[MAX_FIELDS] = { 1442 [VOPSEL] = GRF_REG_FIELD(0x6250, 4, 4), 1443 [DPIUPDATECFG] = GRF_REG_FIELD(0x6250, 3, 3), 1444 [DPISHUTDN] = GRF_REG_FIELD(0x6250, 2, 2), 1445 [DPICOLORM] = GRF_REG_FIELD(0x6250, 1, 1), 1446 [TURNDISABLE] = GRF_REG_FIELD(0x625c, 12, 15), 1447 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x625c, 8, 11), 1448 [FORCERXMODE] = GRF_REG_FIELD(0x625c, 4, 7), 1449 [ENABLE_N] = GRF_REG_FIELD(0x625c, 0, 3), 1450 [MASTERSLAVEZ] = GRF_REG_FIELD(0x6260, 7, 7), 1451 [ENABLECLK] = GRF_REG_FIELD(0x6260, 6, 6), 1452 [BASEDIR] = GRF_REG_FIELD(0x6260, 5, 5), 1453 [TURNREQUEST] = GRF_REG_FIELD(0x6260, 0, 3), 1454 }; 1455 1456 static const struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_plat_data = { 1457 .dsi0_grf_reg_fields = rk3399_dsi0_grf_reg_fields, 1458 .dsi1_grf_reg_fields = rk3399_dsi1_grf_reg_fields, 1459 .max_bit_rate_per_lane = 1500000000UL, 1460 }; 1461 1462 static const struct rockchip_connector rk3399_mipi_dsi_driver_data = { 1463 .funcs = &dw_mipi_dsi_connector_funcs, 1464 .data = &rk3399_mipi_dsi_plat_data, 1465 }; 1466 1467 static const u32 rv1108_dsi_grf_reg_fields[MAX_FIELDS] = { 1468 [DPICOLORM] = GRF_REG_FIELD(0x0410, 7, 7), 1469 [DPISHUTDN] = GRF_REG_FIELD(0x0410, 6, 6), 1470 [DPIUPDATECFG] = GRF_REG_FIELD(0x0410, 8, 8), 1471 [FORCERXMODE] = GRF_REG_FIELD(0x0414, 5, 5), 1472 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0414, 6, 9), 1473 [TURNDISABLE] = GRF_REG_FIELD(0x0414, 4, 4), 1474 }; 1475 1476 static const struct dw_mipi_dsi_plat_data rv1108_mipi_dsi_plat_data = { 1477 .dsi0_grf_reg_fields = rv1108_dsi_grf_reg_fields, 1478 .max_bit_rate_per_lane = 1000000000UL, 1479 }; 1480 1481 static const struct rockchip_connector rv1108_mipi_dsi_driver_data = { 1482 .funcs = &dw_mipi_dsi_connector_funcs, 1483 .data = &rv1108_mipi_dsi_plat_data, 1484 }; 1485 1486 static const struct udevice_id dw_mipi_dsi_ids[] = { 1487 { 1488 .compatible = "rockchip,px30-mipi-dsi", 1489 .data = (ulong)&px30_mipi_dsi_driver_data, 1490 }, 1491 { 1492 .compatible = "rockchip,rk3128-mipi-dsi", 1493 .data = (ulong)&rk3128_mipi_dsi_driver_data, 1494 }, 1495 { 1496 .compatible = "rockchip,rk3288-mipi-dsi", 1497 .data = (ulong)&rk3288_mipi_dsi_driver_data, 1498 }, 1499 { 1500 .compatible = "rockchip,rk3366-mipi-dsi", 1501 .data = (ulong)&rk3366_mipi_dsi_driver_data, 1502 }, 1503 { 1504 .compatible = "rockchip,rk3368-mipi-dsi", 1505 .data = (ulong)&rk3368_mipi_dsi_driver_data, 1506 }, 1507 { 1508 .compatible = "rockchip,rk3399-mipi-dsi", 1509 .data = (ulong)&rk3399_mipi_dsi_driver_data, 1510 }, 1511 { 1512 .compatible = "rockchip,rv1108-mipi-dsi", 1513 .data = (ulong)&rv1108_mipi_dsi_driver_data, 1514 }, 1515 {} 1516 }; 1517 1518 U_BOOT_DRIVER(dw_mipi_dsi) = { 1519 .name = "dw_mipi_dsi", 1520 .id = UCLASS_DISPLAY, 1521 .of_match = dw_mipi_dsi_ids, 1522 .probe = dw_mipi_dsi_probe, 1523 .bind = dm_scan_fdt_dev, 1524 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi), 1525 }; 1526