1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <drm/drm_mipi_dsi.h> 8 9 #include <config.h> 10 #include <common.h> 11 #include <errno.h> 12 #include <asm/unaligned.h> 13 #include <asm/io.h> 14 #include <asm/hardware.h> 15 #include <dm/device.h> 16 #include <dm/read.h> 17 #include <dm/of_access.h> 18 #include <syscon.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <linux/iopoll.h> 21 22 #include "rockchip_display.h" 23 #include "rockchip_crtc.h" 24 #include "rockchip_connector.h" 25 #include "rockchip_panel.h" 26 #include "rockchip_phy.h" 27 28 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) 29 30 #define DSI_VERSION 0x00 31 #define DSI_PWR_UP 0x04 32 #define RESET 0 33 #define POWERUP BIT(0) 34 35 #define DSI_CLKMGR_CFG 0x08 36 #define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) 37 #define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) 38 39 #define DSI_DPI_VCID 0x0c 40 #define DPI_VID(vid) (((vid) & 0x3) << 0) 41 42 #define DSI_DPI_COLOR_CODING 0x10 43 #define EN18_LOOSELY BIT(8) 44 #define DPI_COLOR_CODING_16BIT_1 0x0 45 #define DPI_COLOR_CODING_16BIT_2 0x1 46 #define DPI_COLOR_CODING_16BIT_3 0x2 47 #define DPI_COLOR_CODING_18BIT_1 0x3 48 #define DPI_COLOR_CODING_18BIT_2 0x4 49 #define DPI_COLOR_CODING_24BIT 0x5 50 51 #define DSI_DPI_CFG_POL 0x14 52 #define COLORM_ACTIVE_LOW BIT(4) 53 #define SHUTD_ACTIVE_LOW BIT(3) 54 #define HSYNC_ACTIVE_LOW BIT(2) 55 #define VSYNC_ACTIVE_LOW BIT(1) 56 #define DATAEN_ACTIVE_LOW BIT(0) 57 58 #define DSI_DPI_LP_CMD_TIM 0x18 59 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) 60 #define INVACT_LPCMD_TIME(p) ((p) & 0xff) 61 62 #define DSI_DBI_VCID 0x1c 63 #define DBI_VCID(x) UPDATE(x, 1, 0) 64 #define DSI_DBI_CFG 0x20 65 #define DSI_DBI_CMDSIZE 0x28 66 67 #define DSI_PCKHDL_CFG 0x2c 68 #define CRC_RX_EN BIT(4) 69 #define ECC_RX_EN BIT(3) 70 #define BTA_EN BIT(2) 71 #define EOTP_RX_EN BIT(1) 72 #define EOTP_TX_EN BIT(0) 73 #define DSI_MODE_CFG 0x34 74 #define CMD_VIDEO_MODE BIT(0) 75 #define COMMAND_MODE BIT(0) 76 #define VIDEO_MODE 0 77 #define DSI_VID_MODE_CFG 0x38 78 #define VPG_EN BIT(16) 79 #define LP_CMD_EN BIT(15) 80 #define FRAME_BTA_ACK BIT(14) 81 #define LP_HFP_EN BIT(13) 82 #define LP_HBP_EN BIT(12) 83 #define LP_VACT_EN BIT(11) 84 #define LP_VFP_EN BIT(10) 85 #define LP_VBP_EN BIT(9) 86 #define LP_VSA_EN BIT(8) 87 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0 88 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1 89 #define VID_MODE_TYPE_BURST 0x2 90 91 #define DSI_VID_PKT_SIZE 0x3c 92 #define VID_PKT_SIZE(p) (((p) & 0x3fff) << 0) 93 #define VID_PKT_MAX_SIZE 0x3fff 94 95 #define DSI_VID_NUM_CHUMKS 0x40 96 #define DSI_VID_NULL_PKT_SIZE 0x44 97 #define DSI_VID_HSA_TIME 0x48 98 #define DSI_VID_HBP_TIME 0x4c 99 #define DSI_VID_HLINE_TIME 0x50 100 #define DSI_VID_VSA_LINES 0x54 101 #define DSI_VID_VBP_LINES 0x58 102 #define DSI_VID_VFP_LINES 0x5c 103 #define DSI_VID_VACTIVE_LINES 0x60 104 #define DSI_EDPI_CMD_SIZE 0x64 105 #define DSI_CMD_MODE_CFG 0x68 106 #define MAX_RD_PKT_SIZE BIT(24) 107 #define DCS_LW_TX BIT(19) 108 #define DCS_SR_0P_TX BIT(18) 109 #define DCS_SW_1P_TX BIT(17) 110 #define DCS_SW_0P_TX BIT(16) 111 #define GEN_LW_TX BIT(14) 112 #define GEN_SR_2P_TX BIT(13) 113 #define GEN_SR_1P_TX BIT(12) 114 #define GEN_SR_0P_TX BIT(11) 115 #define GEN_SW_2P_TX BIT(10) 116 #define GEN_SW_1P_TX BIT(9) 117 #define GEN_SW_0P_TX BIT(8) 118 #define ACK_RQST_EN BIT(1) 119 #define TEAR_FX_EN BIT(0) 120 121 #define DSI_GEN_HDR 0x6c 122 #define GEN_HDATA(data) (((data) & 0xffff) << 8) 123 #define GEN_HDATA_MASK (0xffff << 8) 124 #define GEN_HTYPE(type) (((type) & 0xff) << 0) 125 #define GEN_HTYPE_MASK 0xff 126 127 #define DSI_GEN_PLD_DATA 0x70 128 129 #define DSI_CMD_PKT_STATUS 0x74 130 #define GEN_CMD_EMPTY BIT(0) 131 #define GEN_CMD_FULL BIT(1) 132 #define GEN_PLD_W_EMPTY BIT(2) 133 #define GEN_PLD_W_FULL BIT(3) 134 #define GEN_PLD_R_EMPTY BIT(4) 135 #define GEN_PLD_R_FULL BIT(5) 136 #define GEN_RD_CMD_BUSY BIT(6) 137 138 #define DSI_TO_CNT_CFG 0x78 139 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16) 140 #define LPRX_TO_CNT(p) ((p) & 0xffff) 141 142 #define DSI_BTA_TO_CNT 0x8c 143 #define DSI_LPCLK_CTRL 0x94 144 #define AUTO_CLKLANE_CTRL BIT(1) 145 #define PHY_TXREQUESTCLKHS BIT(0) 146 147 #define DSI_PHY_TMR_LPCLK_CFG 0x98 148 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16) 149 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff) 150 151 #define DSI_PHY_TMR_CFG 0x9c 152 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24) 153 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16) 154 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff) 155 156 #define DSI_PHY_RSTZ 0xa0 157 #define PHY_ENFORCEPLL BIT(3) 158 #define PHY_ENABLECLK BIT(2) 159 #define PHY_RSTZ BIT(1) 160 #define PHY_SHUTDOWNZ BIT(0) 161 162 #define DSI_PHY_IF_CFG 0xa4 163 #define N_LANES(n) ((((n) - 1) & 0x3) << 0) 164 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 165 166 #define DSI_PHY_STATUS 0xb0 167 #define PHY_STOPSTATE0LANE BIT(4) 168 #define PHY_STOPSTATECLKLANE BIT(2) 169 #define PHY_LOCK BIT(0) 170 #define PHY_STOPSTATELANE (PHY_STOPSTATE0LANE | \ 171 PHY_STOPSTATECLKLANE) 172 173 #define DSI_PHY_TST_CTRL0 0xb4 174 #define PHY_TESTCLK BIT(1) 175 #define PHY_TESTCLR BIT(0) 176 177 #define DSI_PHY_TST_CTRL1 0xb8 178 #define PHY_TESTEN BIT(16) 179 #define PHY_TESTDOUT_SHIFT 8 180 #define PHY_TESTDIN_MASK GENMASK(7, 0) 181 #define PHY_TESTDIN(x) UPDATE(x, 7, 0) 182 183 #define DSI_INT_ST0 0xbc 184 #define DSI_INT_ST1 0xc0 185 #define DSI_INT_MSK0 0xc4 186 #define DSI_INT_MSK1 0xc8 187 188 #define PHY_STATUS_TIMEOUT_US 10000 189 #define CMD_PKT_STATUS_TIMEOUT_US 20000 190 191 /* Test Code: 0x44 (HS RX Control of Lane 0) */ 192 #define HSFREQRANGE(x) UPDATE(x, 6, 1) 193 /* Test Code: 0x17 (PLL Input Divider Ratio) */ 194 #define INPUT_DIV(x) UPDATE(x, 6, 0) 195 /* Test Code: 0x18 (PLL Loop Divider Ratio) */ 196 #define FEEDBACK_DIV_LO(x) UPDATE(x, 4, 0) 197 #define FEEDBACK_DIV_HI(x) (BIT(7) | UPDATE(x, 3, 0)) 198 199 #define GRF_REG_FIELD(reg, lsb, msb) ((reg << 16) | (lsb << 8) | (msb)) 200 201 enum grf_reg_fields { 202 DPIUPDATECFG, 203 DPISHUTDN, 204 DPICOLORM, 205 VOPSEL, 206 TURNREQUEST, 207 TURNDISABLE, 208 FORCETXSTOPMODE, 209 FORCERXMODE, 210 ENABLE_N, 211 MASTERSLAVEZ, 212 ENABLECLK, 213 BASEDIR, 214 MAX_FIELDS, 215 }; 216 217 struct dw_mipi_dsi_plat_data { 218 const u32 *dsi0_grf_reg_fields; 219 const u32 *dsi1_grf_reg_fields; 220 unsigned long max_bit_rate_per_lane; 221 }; 222 223 struct mipi_dphy { 224 /* Non-SNPS PHY */ 225 struct rockchip_phy *phy; 226 227 u16 input_div; 228 u16 feedback_div; 229 }; 230 231 struct dw_mipi_dsi { 232 struct udevice *dev; 233 void *base; 234 void *grf; 235 int id; 236 237 /* for dual-channel */ 238 struct dw_mipi_dsi *master; 239 struct dw_mipi_dsi *slave; 240 241 unsigned int lane_mbps; /* per lane */ 242 u32 channel; 243 u32 lanes; 244 u32 format; 245 u32 mode_flags; 246 struct mipi_dphy dphy; 247 struct drm_display_mode *mode; 248 249 const struct dw_mipi_dsi_plat_data *pdata; 250 }; 251 252 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) 253 { 254 writel(val, dsi->base + reg); 255 } 256 257 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) 258 { 259 return readl(dsi->base + reg); 260 } 261 262 static inline void dsi_update_bits(struct dw_mipi_dsi *dsi, 263 u32 reg, u32 mask, u32 val) 264 { 265 u32 orig, tmp; 266 267 orig = dsi_read(dsi, reg); 268 tmp = orig & ~mask; 269 tmp |= val & mask; 270 dsi_write(dsi, reg, tmp); 271 } 272 273 static void grf_field_write(struct dw_mipi_dsi *dsi, enum grf_reg_fields index, 274 unsigned int val) 275 { 276 const u32 field = dsi->id ? dsi->pdata->dsi1_grf_reg_fields[index] : 277 dsi->pdata->dsi0_grf_reg_fields[index]; 278 u16 reg; 279 u8 msb, lsb; 280 281 if (!field) 282 return; 283 284 reg = (field >> 16) & 0xffff; 285 lsb = (field >> 8) & 0xff; 286 msb = (field >> 0) & 0xff; 287 288 rk_clrsetreg(dsi->grf + reg, GENMASK(msb, lsb), val << lsb); 289 } 290 291 static inline void dpishutdn_assert(struct dw_mipi_dsi *dsi) 292 { 293 grf_field_write(dsi, DPISHUTDN, 1); 294 } 295 296 static inline void dpishutdn_deassert(struct dw_mipi_dsi *dsi) 297 { 298 grf_field_write(dsi, DPISHUTDN, 0); 299 } 300 301 static int genif_wait_w_pld_fifo_not_full(struct dw_mipi_dsi *dsi) 302 { 303 u32 sts; 304 int ret; 305 306 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 307 sts, !(sts & GEN_PLD_W_FULL), 308 CMD_PKT_STATUS_TIMEOUT_US); 309 if (ret < 0) { 310 printf("generic write payload fifo is full\n"); 311 return ret; 312 } 313 314 return 0; 315 } 316 317 static int genif_wait_cmd_fifo_not_full(struct dw_mipi_dsi *dsi) 318 { 319 u32 sts; 320 int ret; 321 322 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 323 sts, !(sts & GEN_CMD_FULL), 324 CMD_PKT_STATUS_TIMEOUT_US); 325 if (ret < 0) { 326 printf("generic write cmd fifo is full\n"); 327 return ret; 328 } 329 330 return 0; 331 } 332 333 static int genif_wait_write_fifo_empty(struct dw_mipi_dsi *dsi) 334 { 335 u32 sts; 336 u32 mask; 337 int ret; 338 339 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 340 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 341 sts, (sts & mask) == mask, 342 CMD_PKT_STATUS_TIMEOUT_US); 343 if (ret < 0) { 344 printf("generic write fifo is full\n"); 345 return ret; 346 } 347 348 return 0; 349 } 350 351 static inline void mipi_dphy_enableclk_assert(struct dw_mipi_dsi *dsi) 352 { 353 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK); 354 udelay(1); 355 } 356 357 static inline void mipi_dphy_enableclk_deassert(struct dw_mipi_dsi *dsi) 358 { 359 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, 0); 360 udelay(1); 361 } 362 363 static inline void mipi_dphy_shutdownz_assert(struct dw_mipi_dsi *dsi) 364 { 365 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, 0); 366 udelay(1); 367 } 368 369 static inline void mipi_dphy_shutdownz_deassert(struct dw_mipi_dsi *dsi) 370 { 371 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, PHY_SHUTDOWNZ); 372 udelay(1); 373 } 374 375 static inline void mipi_dphy_rstz_assert(struct dw_mipi_dsi *dsi) 376 { 377 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, 0); 378 udelay(1); 379 } 380 381 static inline void mipi_dphy_rstz_deassert(struct dw_mipi_dsi *dsi) 382 { 383 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, PHY_RSTZ); 384 udelay(1); 385 } 386 387 static inline void testif_testclk_assert(struct dw_mipi_dsi *dsi) 388 { 389 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK); 390 udelay(1); 391 } 392 393 static inline void testif_testclk_deassert(struct dw_mipi_dsi *dsi) 394 { 395 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK, 0); 396 udelay(1); 397 } 398 399 static inline void testif_testclr_assert(struct dw_mipi_dsi *dsi) 400 { 401 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR, PHY_TESTCLR); 402 udelay(1); 403 } 404 405 static inline void testif_testclr_deassert(struct dw_mipi_dsi *dsi) 406 { 407 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR, 0); 408 udelay(1); 409 } 410 411 static inline void testif_testen_assert(struct dw_mipi_dsi *dsi) 412 { 413 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN, PHY_TESTEN); 414 udelay(1); 415 } 416 417 static inline void testif_testen_deassert(struct dw_mipi_dsi *dsi) 418 { 419 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN, 0); 420 udelay(1); 421 } 422 423 static inline void testif_set_data(struct dw_mipi_dsi *dsi, u8 data) 424 { 425 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, 426 PHY_TESTDIN_MASK, PHY_TESTDIN(data)); 427 udelay(1); 428 } 429 430 static inline u8 testif_get_data(struct dw_mipi_dsi *dsi) 431 { 432 return dsi_read(dsi, DSI_PHY_TST_CTRL1) >> PHY_TESTDOUT_SHIFT; 433 } 434 435 static void testif_test_code_write(struct dw_mipi_dsi *dsi, u8 test_code) 436 { 437 testif_testclk_assert(dsi); 438 testif_set_data(dsi, test_code); 439 testif_testen_assert(dsi); 440 testif_testclk_deassert(dsi); 441 testif_testen_deassert(dsi); 442 } 443 444 static void testif_test_data_write(struct dw_mipi_dsi *dsi, u8 test_data) 445 { 446 testif_testclk_deassert(dsi); 447 testif_set_data(dsi, test_data); 448 testif_testclk_assert(dsi); 449 } 450 451 static void testif_write(struct dw_mipi_dsi *dsi, u8 test_code, u8 test_data) 452 { 453 testif_test_code_write(dsi, test_code); 454 testif_test_data_write(dsi, test_data); 455 456 dev_dbg(dsi->dev, 457 "test_code=0x%02x, test_data=0x%02x, monitor_data=0x%02x\n", 458 test_code, test_data, testif_get_data(dsi)); 459 } 460 461 static int mipi_dphy_power_on(struct dw_mipi_dsi *dsi) 462 { 463 u32 mask, val; 464 int ret; 465 466 mipi_dphy_shutdownz_deassert(dsi); 467 mipi_dphy_rstz_deassert(dsi); 468 mdelay(2); 469 470 if (dsi->dphy.phy) { 471 rockchip_phy_set_mode(dsi->dphy.phy, PHY_MODE_VIDEO_MIPI); 472 rockchip_phy_power_on(dsi->dphy.phy); 473 } 474 475 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 476 val, val & PHY_LOCK, PHY_STATUS_TIMEOUT_US); 477 if (ret < 0) { 478 dev_err(dsi->dev, "PHY is not locked\n"); 479 return ret; 480 } 481 482 udelay(200); 483 484 mask = PHY_STOPSTATELANE; 485 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 486 val, (val & mask) == mask, 487 PHY_STATUS_TIMEOUT_US); 488 if (ret < 0) { 489 dev_err(dsi->dev, "lane module is not in stop state\n"); 490 return ret; 491 } 492 493 udelay(10); 494 495 return 0; 496 } 497 498 static void dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) 499 { 500 /* Table 5-1 Frequency Ranges */ 501 const struct { 502 unsigned long max_lane_mbps; 503 u8 hsfreqrange; 504 } hsfreqrange_table[] = { 505 { 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01}, 506 { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12}, 507 { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23}, 508 { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15}, 509 { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07}, 510 { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09}, 511 { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a}, 512 {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b}, 513 {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c}, 514 {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c} 515 }; 516 u8 hsfreqrange, counter; 517 unsigned int index, txbyteclkhs; 518 u16 n, m; 519 520 for (index = 0; index < ARRAY_SIZE(hsfreqrange_table); index++) 521 if (dsi->lane_mbps <= hsfreqrange_table[index].max_lane_mbps) 522 break; 523 524 if (index == ARRAY_SIZE(hsfreqrange_table)) 525 --index; 526 527 hsfreqrange = hsfreqrange_table[index].hsfreqrange; 528 testif_write(dsi, 0x44, HSFREQRANGE(hsfreqrange)); 529 530 txbyteclkhs = dsi->lane_mbps >> 3; 531 counter = txbyteclkhs * 60 / 1000; 532 testif_write(dsi, 0x60, 0x80 | counter); 533 testif_write(dsi, 0x70, 0x80 | counter); 534 535 n = dsi->dphy.input_div - 1; 536 m = dsi->dphy.feedback_div - 1; 537 testif_write(dsi, 0x19, 0x30); 538 testif_write(dsi, 0x17, INPUT_DIV(n)); 539 testif_write(dsi, 0x18, FEEDBACK_DIV_LO(m)); 540 testif_write(dsi, 0x18, FEEDBACK_DIV_HI(m >> 5)); 541 } 542 543 static unsigned long dw_mipi_dsi_get_lane_rate(struct dw_mipi_dsi *dsi) 544 { 545 const struct drm_display_mode *mode = dsi->mode; 546 unsigned long max_lane_rate = dsi->pdata->max_bit_rate_per_lane; 547 unsigned long lane_rate; 548 unsigned int value; 549 int bpp, lanes; 550 u64 tmp; 551 552 /* optional override of the desired bandwidth */ 553 value = dev_read_u32_default(dsi->dev, "rockchip,lane-rate", 0); 554 if (value > 0) 555 return value * 1000 * 1000; 556 557 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 558 if (bpp < 0) 559 bpp = 24; 560 561 lanes = dsi->slave ? dsi->lanes * 2 : dsi->lanes; 562 tmp = (u64)mode->clock * 1000 * bpp; 563 do_div(tmp, lanes); 564 565 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */ 566 tmp *= 10; 567 do_div(tmp, 9); 568 569 if (tmp > max_lane_rate) 570 lane_rate = max_lane_rate; 571 else 572 lane_rate = tmp; 573 574 return lane_rate; 575 } 576 577 static void dw_mipi_dsi_set_pll(struct dw_mipi_dsi *dsi, unsigned long rate) 578 { 579 unsigned long fin, fout; 580 unsigned long fvco_min, fvco_max, best_freq = 984000000; 581 u8 min_prediv, max_prediv; 582 u8 _prediv, best_prediv = 2; 583 u16 _fbdiv, best_fbdiv = 82; 584 u32 min_delta = ~0U; 585 586 fin = 24000000; 587 fout = rate; 588 589 /* 5Mhz < Fref / N < 40MHz, 80MHz < Fvco < 1500Mhz */ 590 min_prediv = DIV_ROUND_UP(fin, 40000000); 591 max_prediv = fin / 5000000; 592 fvco_min = 80000000; 593 fvco_max = 1500000000; 594 595 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 596 u64 tmp, _fout; 597 u32 delta; 598 599 /* Fvco = Fref * M / N */ 600 tmp = (u64)fout * _prediv; 601 do_div(tmp, fin); 602 _fbdiv = tmp; 603 604 /* 605 * Due to the use of a "by 2 pre-scaler," the range of the 606 * feedback multiplication value M is limited to even division 607 * numbers, and m must be greater than 12, less than 1000. 608 */ 609 if (_fbdiv <= 12 || _fbdiv >= 1000) 610 continue; 611 612 if (_fbdiv % 2) 613 ++_fbdiv; 614 615 _fout = (u64)_fbdiv * fin; 616 do_div(_fout, _prediv); 617 618 if (_fout < fvco_min || _fout > fvco_max) 619 continue; 620 621 delta = abs(fout - _fout); 622 if (!delta) { 623 best_prediv = _prediv; 624 best_fbdiv = _fbdiv; 625 best_freq = _fout; 626 break; 627 } else if (delta < min_delta) { 628 best_prediv = _prediv; 629 best_fbdiv = _fbdiv; 630 best_freq = _fout; 631 min_delta = delta; 632 } 633 } 634 635 dsi->lane_mbps = best_freq / 1000 / 1000; 636 dsi->dphy.input_div = best_prediv; 637 dsi->dphy.feedback_div = best_fbdiv; 638 if (dsi->slave) { 639 dsi->slave->lane_mbps = dsi->lane_mbps; 640 dsi->slave->dphy.input_div = dsi->dphy.input_div; 641 dsi->slave->dphy.feedback_div = dsi->dphy.feedback_div; 642 } 643 } 644 645 static int dw_mipi_dsi_read_from_fifo(struct dw_mipi_dsi *dsi, 646 const struct mipi_dsi_msg *msg) 647 { 648 u8 *payload = msg->rx_buf; 649 u16 length; 650 u32 val; 651 int ret; 652 653 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 654 val, !(val & GEN_RD_CMD_BUSY), 5000); 655 if (ret) { 656 printf("entire response isn't stored in the FIFO\n"); 657 return ret; 658 } 659 660 /* Receive payload */ 661 for (length = msg->rx_len; length; length -= 4) { 662 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 663 val, !(val & GEN_PLD_R_EMPTY), 5000); 664 if (ret) { 665 printf("Read payload FIFO is empty\n"); 666 return ret; 667 } 668 669 val = dsi_read(dsi, DSI_GEN_PLD_DATA); 670 671 switch (length) { 672 case 3: 673 payload[2] = (val >> 16) & 0xff; 674 /* Fall through */ 675 case 2: 676 payload[1] = (val >> 8) & 0xff; 677 /* Fall through */ 678 case 1: 679 payload[0] = val & 0xff; 680 return 0; 681 } 682 683 payload[0] = (val >> 0) & 0xff; 684 payload[1] = (val >> 8) & 0xff; 685 payload[2] = (val >> 16) & 0xff; 686 payload[3] = (val >> 24) & 0xff; 687 payload += 4; 688 } 689 690 return 0; 691 } 692 693 static int dw_mipi_dsi_turn_on_peripheral(struct dw_mipi_dsi *dsi) 694 { 695 dpishutdn_assert(dsi); 696 udelay(20); 697 dpishutdn_deassert(dsi); 698 699 return 0; 700 } 701 702 static int dw_mipi_dsi_shutdown_peripheral(struct dw_mipi_dsi *dsi) 703 { 704 dpishutdn_deassert(dsi); 705 udelay(20); 706 dpishutdn_assert(dsi); 707 708 return 0; 709 } 710 711 static ssize_t dw_mipi_dsi_transfer(struct dw_mipi_dsi *dsi, 712 const struct mipi_dsi_msg *msg) 713 { 714 struct mipi_dsi_packet packet; 715 int ret; 716 int val; 717 718 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { 719 dsi_update_bits(dsi, DSI_VID_MODE_CFG, LP_CMD_EN, LP_CMD_EN); 720 dsi_update_bits(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS, 0); 721 } else { 722 dsi_update_bits(dsi, DSI_VID_MODE_CFG, LP_CMD_EN, 0); 723 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 724 PHY_TXREQUESTCLKHS, PHY_TXREQUESTCLKHS); 725 } 726 727 switch (msg->type) { 728 case MIPI_DSI_SHUTDOWN_PERIPHERAL: 729 return dw_mipi_dsi_shutdown_peripheral(dsi); 730 case MIPI_DSI_TURN_ON_PERIPHERAL: 731 return dw_mipi_dsi_turn_on_peripheral(dsi); 732 case MIPI_DSI_DCS_SHORT_WRITE: 733 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_0P_TX, 734 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 735 DCS_SW_0P_TX : 0); 736 break; 737 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 738 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_1P_TX, 739 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 740 DCS_SW_1P_TX : 0); 741 break; 742 case MIPI_DSI_DCS_LONG_WRITE: 743 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX, 744 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 745 DCS_LW_TX : 0); 746 break; 747 case MIPI_DSI_DCS_READ: 748 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SR_0P_TX, 749 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 750 DCS_SR_0P_TX : 0); 751 break; 752 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: 753 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, MAX_RD_PKT_SIZE, 754 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 755 MAX_RD_PKT_SIZE : 0); 756 break; 757 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 758 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_0P_TX, 759 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 760 GEN_SW_0P_TX : 0); 761 break; 762 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 763 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_1P_TX, 764 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 765 GEN_SW_1P_TX : 0); 766 break; 767 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 768 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_2P_TX, 769 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 770 GEN_SW_2P_TX : 0); 771 break; 772 case MIPI_DSI_GENERIC_LONG_WRITE: 773 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_LW_TX, 774 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 775 GEN_LW_TX : 0); 776 break; 777 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 778 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_0P_TX, 779 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 780 GEN_SR_0P_TX : 0); 781 break; 782 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 783 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_1P_TX, 784 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 785 GEN_SR_1P_TX : 0); 786 break; 787 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 788 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_2P_TX, 789 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 790 GEN_SR_2P_TX : 0); 791 break; 792 default: 793 return -EINVAL; 794 } 795 796 if (msg->flags & MIPI_DSI_MSG_REQ_ACK) 797 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, 798 ACK_RQST_EN, ACK_RQST_EN); 799 800 /* create a packet to the DSI protocol */ 801 ret = mipi_dsi_create_packet(&packet, msg); 802 if (ret) { 803 printf("failed to create packet: %d\n", ret); 804 return ret; 805 } 806 807 /* Send payload */ 808 while (DIV_ROUND_UP(packet.payload_length, 4)) { 809 /* 810 * Alternatively, you can always keep the FIFO 811 * nearly full by monitoring the FIFO state until 812 * it is not full, and then writea single word of data. 813 * This solution is more resource consuming 814 * but it simultaneously avoids FIFO starvation, 815 * making it possible to use FIFO sizes smaller than 816 * the amount of data of the longest packet to be written. 817 */ 818 ret = genif_wait_w_pld_fifo_not_full(dsi); 819 if (ret) 820 return ret; 821 822 if (packet.payload_length < 4) { 823 /* send residu payload */ 824 val = 0; 825 memcpy(&val, packet.payload, packet.payload_length); 826 dsi_write(dsi, DSI_GEN_PLD_DATA, val); 827 packet.payload_length = 0; 828 } else { 829 val = get_unaligned_le32(packet.payload); 830 dsi_write(dsi, DSI_GEN_PLD_DATA, val); 831 packet.payload += 4; 832 packet.payload_length -= 4; 833 } 834 } 835 836 ret = genif_wait_cmd_fifo_not_full(dsi); 837 if (ret) 838 return ret; 839 840 /* Send packet header */ 841 val = get_unaligned_le32(packet.header); 842 dsi_write(dsi, DSI_GEN_HDR, val); 843 844 ret = genif_wait_write_fifo_empty(dsi); 845 if (ret) 846 return ret; 847 848 if (msg->rx_len) { 849 ret = dw_mipi_dsi_read_from_fifo(dsi, msg); 850 if (ret < 0) 851 return ret; 852 } 853 854 if (dsi->slave) { 855 ret = dw_mipi_dsi_transfer(dsi->slave, msg); 856 if (ret < 0) 857 return ret; 858 } 859 860 return msg->rx_len ? msg->rx_len : msg->tx_len; 861 } 862 863 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) 864 { 865 u32 val = LP_VACT_EN | LP_VFP_EN | LP_VBP_EN | LP_VSA_EN | 866 LP_HFP_EN | LP_HBP_EN; 867 868 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) 869 val &= ~LP_HFP_EN; 870 871 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) 872 val &= ~LP_HBP_EN; 873 874 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 875 val |= VID_MODE_TYPE_BURST; 876 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 877 val |= VID_MODE_TYPE_BURST_SYNC_PULSES; 878 else 879 val |= VID_MODE_TYPE_BURST_SYNC_EVENTS; 880 881 dsi_write(dsi, DSI_VID_MODE_CFG, val); 882 883 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 884 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 885 AUTO_CLKLANE_CTRL, AUTO_CLKLANE_CTRL); 886 } 887 888 static void dw_mipi_dsi_enable(struct dw_mipi_dsi *dsi) 889 { 890 const struct drm_display_mode *mode = dsi->mode; 891 892 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 893 PHY_TXREQUESTCLKHS, PHY_TXREQUESTCLKHS); 894 895 dsi_write(dsi, DSI_PWR_UP, RESET); 896 897 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 898 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, VIDEO_MODE); 899 } else { 900 dsi_write(dsi, DSI_DBI_VCID, DBI_VCID(dsi->channel)); 901 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX, 0); 902 dsi_write(dsi, DSI_EDPI_CMD_SIZE, mode->hdisplay); 903 dsi_update_bits(dsi, DSI_MODE_CFG, 904 CMD_VIDEO_MODE, COMMAND_MODE); 905 } 906 907 dsi_write(dsi, DSI_PWR_UP, POWERUP); 908 909 if (dsi->slave) 910 dw_mipi_dsi_enable(dsi->slave); 911 } 912 913 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) 914 { 915 dsi_write(dsi, DSI_PWR_UP, RESET); 916 dsi_write(dsi, DSI_LPCLK_CTRL, 0); 917 dsi_write(dsi, DSI_EDPI_CMD_SIZE, 0); 918 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, COMMAND_MODE); 919 dsi_write(dsi, DSI_PWR_UP, POWERUP); 920 921 if (dsi->slave) 922 dw_mipi_dsi_disable(dsi->slave); 923 } 924 925 static void dw_mipi_dsi_post_disable(struct dw_mipi_dsi *dsi) 926 { 927 dsi_write(dsi, DSI_PWR_UP, RESET); 928 dsi_write(dsi, DSI_PHY_RSTZ, 0); 929 930 if (dsi->slave) 931 dw_mipi_dsi_post_disable(dsi->slave); 932 } 933 934 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) 935 { 936 u32 esc_clk_div; 937 938 dsi_write(dsi, DSI_PWR_UP, RESET); 939 940 /* The maximum value of the escape clock frequency is 20MHz */ 941 esc_clk_div = DIV_ROUND_UP(dsi->lane_mbps >> 3, 20); 942 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) | 943 TX_ESC_CLK_DIVIDSION(esc_clk_div)); 944 } 945 946 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, 947 struct drm_display_mode *mode) 948 { 949 u32 val = 0, color = 0; 950 951 switch (dsi->format) { 952 case MIPI_DSI_FMT_RGB888: 953 color = DPI_COLOR_CODING_24BIT; 954 break; 955 case MIPI_DSI_FMT_RGB666: 956 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY; 957 break; 958 case MIPI_DSI_FMT_RGB666_PACKED: 959 color = DPI_COLOR_CODING_18BIT_1; 960 break; 961 case MIPI_DSI_FMT_RGB565: 962 color = DPI_COLOR_CODING_16BIT_1; 963 break; 964 } 965 966 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 967 val |= VSYNC_ACTIVE_LOW; 968 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 969 val |= HSYNC_ACTIVE_LOW; 970 971 dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel)); 972 dsi_write(dsi, DSI_DPI_COLOR_CODING, color); 973 dsi_write(dsi, DSI_DPI_CFG_POL, val); 974 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4) 975 | INVACT_LPCMD_TIME(4)); 976 } 977 978 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi) 979 { 980 u32 val = CRC_RX_EN | ECC_RX_EN | BTA_EN | EOTP_TX_EN; 981 982 if (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 983 val &= ~EOTP_TX_EN; 984 985 dsi_write(dsi, DSI_PCKHDL_CFG, val); 986 } 987 988 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, 989 struct drm_display_mode *mode) 990 { 991 int pkt_size; 992 993 if (dsi->slave || dsi->master) 994 pkt_size = VID_PKT_SIZE(mode->hdisplay / 2); 995 else 996 pkt_size = VID_PKT_SIZE(mode->hdisplay); 997 998 dsi_write(dsi, DSI_VID_PKT_SIZE, pkt_size); 999 } 1000 1001 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) 1002 { 1003 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000)); 1004 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); 1005 } 1006 1007 /* Get lane byte clock cycles. */ 1008 static int dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, 1009 u32 hcomponent) 1010 { 1011 u32 lbcc; 1012 1013 lbcc = hcomponent * dsi->lane_mbps * 1000 / 8; 1014 1015 if (dsi->mode->clock == 0) { 1016 printf("dsi mode clock is 0!\n"); 1017 return 0; 1018 } 1019 1020 return DIV_ROUND_CLOSEST(lbcc, dsi->mode->clock); 1021 } 1022 1023 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi) 1024 { 1025 int htotal, hsa, hbp, lbcc; 1026 struct drm_display_mode *mode = dsi->mode; 1027 1028 htotal = mode->htotal; 1029 hsa = mode->hsync_end - mode->hsync_start; 1030 hbp = mode->htotal - mode->hsync_end; 1031 1032 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal); 1033 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); 1034 1035 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa); 1036 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); 1037 1038 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp); 1039 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); 1040 } 1041 1042 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi) 1043 { 1044 u32 vactive, vsa, vfp, vbp; 1045 struct drm_display_mode *mode = dsi->mode; 1046 1047 vactive = mode->vdisplay; 1048 vsa = mode->vsync_end - mode->vsync_start; 1049 vfp = mode->vsync_start - mode->vdisplay; 1050 vbp = mode->vtotal - mode->vsync_end; 1051 1052 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); 1053 dsi_write(dsi, DSI_VID_VSA_LINES, vsa); 1054 dsi_write(dsi, DSI_VID_VFP_LINES, vfp); 1055 dsi_write(dsi, DSI_VID_VBP_LINES, vbp); 1056 } 1057 1058 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) 1059 { 1060 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14) 1061 | PHY_LP2HS_TIME(0x10) | MAX_RD_TIME(10000)); 1062 1063 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40) 1064 | PHY_CLKLP2HS_TIME(0x40)); 1065 } 1066 1067 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) 1068 { 1069 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) | 1070 N_LANES(dsi->lanes)); 1071 } 1072 1073 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) 1074 { 1075 dsi_read(dsi, DSI_INT_ST0); 1076 dsi_read(dsi, DSI_INT_ST1); 1077 dsi_write(dsi, DSI_INT_MSK0, 0); 1078 dsi_write(dsi, DSI_INT_MSK1, 0); 1079 } 1080 1081 static int dw_mipi_dsi_connector_init(struct display_state *state) 1082 { 1083 struct connector_state *conn_state = &state->conn_state; 1084 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1085 1086 dsi->dphy.phy = conn_state->phy; 1087 1088 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 1089 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 1090 conn_state->type = DRM_MODE_CONNECTOR_DSI; 1091 1092 if (dsi->slave) { 1093 dsi->lanes /= 2; 1094 dsi->slave->lanes = dsi->lanes; 1095 dsi->slave->format = dsi->format; 1096 dsi->slave->mode_flags = dsi->mode_flags; 1097 dsi->slave->channel = dsi->channel; 1098 conn_state->output_type = ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL; 1099 } 1100 1101 return 0; 1102 } 1103 1104 static void dw_mipi_dsi_set_hs_clk(struct dw_mipi_dsi *dsi, unsigned long rate) 1105 { 1106 rate = rockchip_phy_set_pll(dsi->dphy.phy, rate); 1107 dsi->lane_mbps = rate / 1000 / 1000; 1108 } 1109 1110 static void dw_mipi_dsi_host_init(struct dw_mipi_dsi *dsi) 1111 { 1112 dw_mipi_dsi_init(dsi); 1113 dw_mipi_dsi_dpi_config(dsi, dsi->mode); 1114 dw_mipi_dsi_packet_handler_config(dsi); 1115 dw_mipi_dsi_video_mode_config(dsi); 1116 dw_mipi_dsi_video_packet_config(dsi, dsi->mode); 1117 dw_mipi_dsi_command_mode_config(dsi); 1118 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, COMMAND_MODE); 1119 dw_mipi_dsi_line_timer_config(dsi); 1120 dw_mipi_dsi_vertical_timing_config(dsi); 1121 dw_mipi_dsi_dphy_timing_config(dsi); 1122 dw_mipi_dsi_dphy_interface_config(dsi); 1123 dw_mipi_dsi_clear_err(dsi); 1124 } 1125 1126 static void dw_mipi_dsi_vop_routing(struct dw_mipi_dsi *dsi, int vop_id) 1127 { 1128 grf_field_write(dsi, VOPSEL, vop_id); 1129 1130 if (dsi->slave) 1131 grf_field_write(dsi->slave, VOPSEL, vop_id); 1132 } 1133 1134 static void mipi_dphy_init(struct dw_mipi_dsi *dsi) 1135 { 1136 u32 map[] = {0x1, 0x3, 0x7, 0xf}; 1137 1138 mipi_dphy_enableclk_deassert(dsi); 1139 mipi_dphy_shutdownz_assert(dsi); 1140 mipi_dphy_rstz_assert(dsi); 1141 testif_testclr_assert(dsi); 1142 1143 /* Configures DPHY to work as a Master */ 1144 grf_field_write(dsi, MASTERSLAVEZ, 1); 1145 1146 /* Configures lane as TX */ 1147 grf_field_write(dsi, BASEDIR, 0); 1148 1149 /* Set all REQUEST inputs to zero */ 1150 grf_field_write(dsi, TURNREQUEST, 0); 1151 grf_field_write(dsi, TURNDISABLE, 0); 1152 grf_field_write(dsi, FORCETXSTOPMODE, 0); 1153 grf_field_write(dsi, FORCERXMODE, 0); 1154 udelay(1); 1155 1156 testif_testclr_deassert(dsi); 1157 1158 if (!dsi->dphy.phy) 1159 dw_mipi_dsi_phy_init(dsi); 1160 1161 /* Enable Data Lane Module */ 1162 grf_field_write(dsi, ENABLE_N, map[dsi->lanes - 1]); 1163 1164 /* Enable Clock Lane Module */ 1165 grf_field_write(dsi, ENABLECLK, 1); 1166 1167 mipi_dphy_enableclk_assert(dsi); 1168 } 1169 1170 static void dw_mipi_dsi_pre_enable(struct dw_mipi_dsi *dsi) 1171 { 1172 dw_mipi_dsi_host_init(dsi); 1173 mipi_dphy_init(dsi); 1174 mipi_dphy_power_on(dsi); 1175 dsi_write(dsi, DSI_PWR_UP, POWERUP); 1176 1177 if (dsi->slave) 1178 dw_mipi_dsi_pre_enable(dsi->slave); 1179 } 1180 1181 static int dw_mipi_dsi_connector_prepare(struct display_state *state) 1182 { 1183 struct connector_state *conn_state = &state->conn_state; 1184 struct crtc_state *crtc_state = &state->crtc_state; 1185 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1186 unsigned long lane_rate; 1187 1188 dsi->mode = &conn_state->mode; 1189 if (dsi->slave) 1190 dsi->slave->mode = dsi->mode; 1191 1192 lane_rate = dw_mipi_dsi_get_lane_rate(dsi); 1193 if (dsi->dphy.phy) 1194 dw_mipi_dsi_set_hs_clk(dsi, lane_rate); 1195 else 1196 dw_mipi_dsi_set_pll(dsi, lane_rate); 1197 1198 printf("final DSI-Link bandwidth: %u Mbps x %d\n", 1199 dsi->lane_mbps, dsi->slave ? dsi->lanes * 2 : dsi->lanes); 1200 1201 dw_mipi_dsi_vop_routing(dsi, crtc_state->crtc_id); 1202 dw_mipi_dsi_pre_enable(dsi); 1203 1204 return 0; 1205 } 1206 1207 static void dw_mipi_dsi_connector_unprepare(struct display_state *state) 1208 { 1209 struct connector_state *conn_state = &state->conn_state; 1210 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1211 1212 dw_mipi_dsi_post_disable(dsi); 1213 } 1214 1215 static int dw_mipi_dsi_connector_enable(struct display_state *state) 1216 { 1217 struct connector_state *conn_state = &state->conn_state; 1218 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1219 1220 dw_mipi_dsi_enable(dsi); 1221 1222 return 0; 1223 } 1224 1225 static int dw_mipi_dsi_connector_disable(struct display_state *state) 1226 { 1227 struct connector_state *conn_state = &state->conn_state; 1228 struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev); 1229 1230 dw_mipi_dsi_disable(dsi); 1231 1232 return 0; 1233 } 1234 1235 static const struct rockchip_connector_funcs dw_mipi_dsi_connector_funcs = { 1236 .init = dw_mipi_dsi_connector_init, 1237 .prepare = dw_mipi_dsi_connector_prepare, 1238 .unprepare = dw_mipi_dsi_connector_unprepare, 1239 .enable = dw_mipi_dsi_connector_enable, 1240 .disable = dw_mipi_dsi_connector_disable, 1241 }; 1242 1243 static int dw_mipi_dsi_dual_channel_probe(struct dw_mipi_dsi *master) 1244 { 1245 struct udevice *dev; 1246 struct dw_mipi_dsi *slave; 1247 int ret; 1248 1249 ret = uclass_get_device_by_phandle(UCLASS_DISPLAY, master->dev, 1250 "rockchip,dual-channel", &dev); 1251 if (ret == -ENOENT) { 1252 return 0; 1253 } else if (ret) { 1254 dev_err(dev, "failed to find slave device: %d\n", ret); 1255 return ret; 1256 } 1257 1258 slave = dev_get_priv(dev); 1259 if (!slave) { 1260 dev_err(dev, "failed to get slave channel\n"); 1261 return -ENODEV; 1262 } 1263 1264 master->slave = slave; 1265 slave->master = master; 1266 1267 return 0; 1268 } 1269 1270 static int dw_mipi_dsi_probe(struct udevice *dev) 1271 { 1272 struct dw_mipi_dsi *dsi = dev_get_priv(dev); 1273 const struct rockchip_connector *connector = 1274 (const struct rockchip_connector *)dev_get_driver_data(dev); 1275 const struct dw_mipi_dsi_plat_data *pdata = connector->data; 1276 int id, ret; 1277 1278 dsi->base = dev_read_addr_ptr(dev); 1279 dsi->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1280 if (IS_ERR(dsi->grf)) 1281 return PTR_ERR(dsi->grf); 1282 1283 id = of_alias_get_id(ofnode_to_np(dev->node), "dsi"); 1284 if (id < 0) 1285 id = 0; 1286 1287 dsi->dev = dev; 1288 dsi->pdata = pdata; 1289 dsi->id = id; 1290 1291 ret = dw_mipi_dsi_dual_channel_probe(dsi); 1292 if (ret) 1293 return ret; 1294 1295 return 0; 1296 } 1297 1298 static const u32 px30_dsi_grf_reg_fields[MAX_FIELDS] = { 1299 [DPIUPDATECFG] = GRF_REG_FIELD(0x0434, 7, 7), 1300 [DPICOLORM] = GRF_REG_FIELD(0x0434, 3, 3), 1301 [DPISHUTDN] = GRF_REG_FIELD(0x0434, 2, 2), 1302 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0438, 7, 10), 1303 [TURNDISABLE] = GRF_REG_FIELD(0x0438, 5, 5), 1304 [VOPSEL] = GRF_REG_FIELD(0x0438, 0, 0), 1305 }; 1306 1307 static const struct dw_mipi_dsi_plat_data px30_mipi_dsi_plat_data = { 1308 .dsi0_grf_reg_fields = px30_dsi_grf_reg_fields, 1309 .max_bit_rate_per_lane = 1000000000UL, 1310 }; 1311 1312 static const struct rockchip_connector px30_mipi_dsi_driver_data = { 1313 .funcs = &dw_mipi_dsi_connector_funcs, 1314 .data = &px30_mipi_dsi_plat_data, 1315 }; 1316 1317 static const u32 rk1808_dsi_grf_reg_fields[MAX_FIELDS] = { 1318 [MASTERSLAVEZ] = GRF_REG_FIELD(0x0440, 8, 8), 1319 [DPIUPDATECFG] = GRF_REG_FIELD(0x0440, 7, 7), 1320 [DPICOLORM] = GRF_REG_FIELD(0x0440, 3, 3), 1321 [DPISHUTDN] = GRF_REG_FIELD(0x0440, 2, 2), 1322 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0444, 7, 10), 1323 [FORCERXMODE] = GRF_REG_FIELD(0x0444, 6, 6), 1324 [TURNDISABLE] = GRF_REG_FIELD(0x0444, 5, 5), 1325 }; 1326 1327 static const struct dw_mipi_dsi_plat_data rk1808_mipi_dsi_plat_data = { 1328 .dsi0_grf_reg_fields = rk1808_dsi_grf_reg_fields, 1329 .max_bit_rate_per_lane = 2000000000UL, 1330 }; 1331 1332 static const struct rockchip_connector rk1808_mipi_dsi_driver_data = { 1333 .funcs = &dw_mipi_dsi_connector_funcs, 1334 .data = &rk1808_mipi_dsi_plat_data, 1335 }; 1336 1337 static const u32 rk3128_dsi_grf_reg_fields[MAX_FIELDS] = { 1338 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0150, 10, 13), 1339 [FORCERXMODE] = GRF_REG_FIELD(0x0150, 9, 9), 1340 [TURNDISABLE] = GRF_REG_FIELD(0x0150, 8, 8), 1341 [DPICOLORM] = GRF_REG_FIELD(0x0150, 5, 5), 1342 [DPISHUTDN] = GRF_REG_FIELD(0x0150, 4, 4), 1343 }; 1344 1345 static const struct dw_mipi_dsi_plat_data rk3128_mipi_dsi_plat_data = { 1346 .dsi0_grf_reg_fields = rk3128_dsi_grf_reg_fields, 1347 .max_bit_rate_per_lane = 1000000000UL, 1348 }; 1349 1350 static const struct rockchip_connector rk3128_mipi_dsi_driver_data = { 1351 .funcs = &dw_mipi_dsi_connector_funcs, 1352 .data = &rk3128_mipi_dsi_plat_data, 1353 }; 1354 1355 static const u32 rk3288_dsi0_grf_reg_fields[MAX_FIELDS] = { 1356 [DPICOLORM] = GRF_REG_FIELD(0x025c, 8, 8), 1357 [DPISHUTDN] = GRF_REG_FIELD(0x025c, 7, 7), 1358 [VOPSEL] = GRF_REG_FIELD(0x025c, 6, 6), 1359 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0264, 8, 11), 1360 [FORCERXMODE] = GRF_REG_FIELD(0x0264, 4, 7), 1361 [TURNDISABLE] = GRF_REG_FIELD(0x0264, 0, 3), 1362 [TURNREQUEST] = GRF_REG_FIELD(0x03a4, 8, 10), 1363 [DPIUPDATECFG] = GRF_REG_FIELD(0x03a8, 0, 0), 1364 }; 1365 1366 static const u32 rk3288_dsi1_grf_reg_fields[MAX_FIELDS] = { 1367 [DPICOLORM] = GRF_REG_FIELD(0x025c, 11, 11), 1368 [DPISHUTDN] = GRF_REG_FIELD(0x025c, 10, 10), 1369 [VOPSEL] = GRF_REG_FIELD(0x025c, 9, 9), 1370 [ENABLE_N] = GRF_REG_FIELD(0x0268, 12, 15), 1371 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0268, 8, 11), 1372 [FORCERXMODE] = GRF_REG_FIELD(0x0268, 4, 7), 1373 [TURNDISABLE] = GRF_REG_FIELD(0x0268, 0, 3), 1374 [BASEDIR] = GRF_REG_FIELD(0x027c, 15, 15), 1375 [MASTERSLAVEZ] = GRF_REG_FIELD(0x027c, 14, 14), 1376 [ENABLECLK] = GRF_REG_FIELD(0x027c, 12, 12), 1377 [TURNREQUEST] = GRF_REG_FIELD(0x03a4, 4, 7), 1378 [DPIUPDATECFG] = GRF_REG_FIELD(0x03a8, 1, 1), 1379 }; 1380 1381 static const struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_plat_data = { 1382 .dsi0_grf_reg_fields = rk3288_dsi0_grf_reg_fields, 1383 .dsi1_grf_reg_fields = rk3288_dsi1_grf_reg_fields, 1384 .max_bit_rate_per_lane = 1500000000UL, 1385 }; 1386 1387 static const struct rockchip_connector rk3288_mipi_dsi_driver_data = { 1388 .funcs = &dw_mipi_dsi_connector_funcs, 1389 .data = &rk3288_mipi_dsi_plat_data, 1390 }; 1391 1392 static const u32 rk3366_dsi_grf_reg_fields[MAX_FIELDS] = { 1393 [VOPSEL] = GRF_REG_FIELD(0x0400, 2, 2), 1394 [DPIUPDATECFG] = GRF_REG_FIELD(0x0410, 9, 9), 1395 [DPICOLORM] = GRF_REG_FIELD(0x0410, 3, 3), 1396 [DPISHUTDN] = GRF_REG_FIELD(0x0410, 2, 2), 1397 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0414, 7, 10), 1398 [FORCERXMODE] = GRF_REG_FIELD(0x0414, 6, 6), 1399 [TURNDISABLE] = GRF_REG_FIELD(0x0414, 5, 5), 1400 }; 1401 1402 static const struct dw_mipi_dsi_plat_data rk3366_mipi_dsi_plat_data = { 1403 .dsi0_grf_reg_fields = rk3366_dsi_grf_reg_fields, 1404 .max_bit_rate_per_lane = 1000000000UL, 1405 }; 1406 1407 static const struct rockchip_connector rk3366_mipi_dsi_driver_data = { 1408 .funcs = &dw_mipi_dsi_connector_funcs, 1409 .data = &rk3366_mipi_dsi_plat_data, 1410 }; 1411 1412 static const u32 rk3368_dsi_grf_reg_fields[MAX_FIELDS] = { 1413 [DPIUPDATECFG] = GRF_REG_FIELD(0x0418, 7, 7), 1414 [DPICOLORM] = GRF_REG_FIELD(0x0418, 3, 3), 1415 [DPISHUTDN] = GRF_REG_FIELD(0x0418, 2, 2), 1416 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x041c, 7, 10), 1417 [FORCERXMODE] = GRF_REG_FIELD(0x041c, 6, 6), 1418 [TURNDISABLE] = GRF_REG_FIELD(0x041c, 5, 5), 1419 }; 1420 1421 static const struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_plat_data = { 1422 .dsi0_grf_reg_fields = rk3368_dsi_grf_reg_fields, 1423 .max_bit_rate_per_lane = 1000000000UL, 1424 }; 1425 1426 static const struct rockchip_connector rk3368_mipi_dsi_driver_data = { 1427 .funcs = &dw_mipi_dsi_connector_funcs, 1428 .data = &rk3368_mipi_dsi_plat_data, 1429 }; 1430 1431 static const u32 rk3399_dsi0_grf_reg_fields[MAX_FIELDS] = { 1432 [DPIUPDATECFG] = GRF_REG_FIELD(0x6224, 15, 15), 1433 [DPISHUTDN] = GRF_REG_FIELD(0x6224, 14, 14), 1434 [DPICOLORM] = GRF_REG_FIELD(0x6224, 13, 13), 1435 [VOPSEL] = GRF_REG_FIELD(0x6250, 0, 0), 1436 [TURNREQUEST] = GRF_REG_FIELD(0x6258, 12, 15), 1437 [TURNDISABLE] = GRF_REG_FIELD(0x6258, 8, 11), 1438 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x6258, 4, 7), 1439 [FORCERXMODE] = GRF_REG_FIELD(0x6258, 0, 3), 1440 }; 1441 1442 static const u32 rk3399_dsi1_grf_reg_fields[MAX_FIELDS] = { 1443 [VOPSEL] = GRF_REG_FIELD(0x6250, 4, 4), 1444 [DPIUPDATECFG] = GRF_REG_FIELD(0x6250, 3, 3), 1445 [DPISHUTDN] = GRF_REG_FIELD(0x6250, 2, 2), 1446 [DPICOLORM] = GRF_REG_FIELD(0x6250, 1, 1), 1447 [TURNDISABLE] = GRF_REG_FIELD(0x625c, 12, 15), 1448 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x625c, 8, 11), 1449 [FORCERXMODE] = GRF_REG_FIELD(0x625c, 4, 7), 1450 [ENABLE_N] = GRF_REG_FIELD(0x625c, 0, 3), 1451 [MASTERSLAVEZ] = GRF_REG_FIELD(0x6260, 7, 7), 1452 [ENABLECLK] = GRF_REG_FIELD(0x6260, 6, 6), 1453 [BASEDIR] = GRF_REG_FIELD(0x6260, 5, 5), 1454 [TURNREQUEST] = GRF_REG_FIELD(0x6260, 0, 3), 1455 }; 1456 1457 static const struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_plat_data = { 1458 .dsi0_grf_reg_fields = rk3399_dsi0_grf_reg_fields, 1459 .dsi1_grf_reg_fields = rk3399_dsi1_grf_reg_fields, 1460 .max_bit_rate_per_lane = 1500000000UL, 1461 }; 1462 1463 static const struct rockchip_connector rk3399_mipi_dsi_driver_data = { 1464 .funcs = &dw_mipi_dsi_connector_funcs, 1465 .data = &rk3399_mipi_dsi_plat_data, 1466 }; 1467 1468 static const u32 rv1108_dsi_grf_reg_fields[MAX_FIELDS] = { 1469 [DPICOLORM] = GRF_REG_FIELD(0x0410, 7, 7), 1470 [DPISHUTDN] = GRF_REG_FIELD(0x0410, 6, 6), 1471 [DPIUPDATECFG] = GRF_REG_FIELD(0x0410, 8, 8), 1472 [FORCERXMODE] = GRF_REG_FIELD(0x0414, 5, 5), 1473 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0414, 6, 9), 1474 [TURNDISABLE] = GRF_REG_FIELD(0x0414, 4, 4), 1475 }; 1476 1477 static const struct dw_mipi_dsi_plat_data rv1108_mipi_dsi_plat_data = { 1478 .dsi0_grf_reg_fields = rv1108_dsi_grf_reg_fields, 1479 .max_bit_rate_per_lane = 1000000000UL, 1480 }; 1481 1482 static const struct rockchip_connector rv1108_mipi_dsi_driver_data = { 1483 .funcs = &dw_mipi_dsi_connector_funcs, 1484 .data = &rv1108_mipi_dsi_plat_data, 1485 }; 1486 1487 static const struct udevice_id dw_mipi_dsi_ids[] = { 1488 { 1489 .compatible = "rockchip,px30-mipi-dsi", 1490 .data = (ulong)&px30_mipi_dsi_driver_data, 1491 }, 1492 { 1493 .compatible = "rockchip,rk1808-mipi-dsi", 1494 .data = (ulong)&rk1808_mipi_dsi_driver_data, 1495 }, 1496 { 1497 .compatible = "rockchip,rk3128-mipi-dsi", 1498 .data = (ulong)&rk3128_mipi_dsi_driver_data, 1499 }, 1500 { 1501 .compatible = "rockchip,rk3288-mipi-dsi", 1502 .data = (ulong)&rk3288_mipi_dsi_driver_data, 1503 }, 1504 { 1505 .compatible = "rockchip,rk3366-mipi-dsi", 1506 .data = (ulong)&rk3366_mipi_dsi_driver_data, 1507 }, 1508 { 1509 .compatible = "rockchip,rk3368-mipi-dsi", 1510 .data = (ulong)&rk3368_mipi_dsi_driver_data, 1511 }, 1512 { 1513 .compatible = "rockchip,rk3399-mipi-dsi", 1514 .data = (ulong)&rk3399_mipi_dsi_driver_data, 1515 }, 1516 { 1517 .compatible = "rockchip,rv1108-mipi-dsi", 1518 .data = (ulong)&rv1108_mipi_dsi_driver_data, 1519 }, 1520 {} 1521 }; 1522 1523 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host, 1524 const struct mipi_dsi_msg *msg) 1525 { 1526 struct dw_mipi_dsi *dsi = dev_get_priv(host->dev); 1527 1528 return dw_mipi_dsi_transfer(dsi, msg); 1529 } 1530 1531 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 1532 struct mipi_dsi_device *device) 1533 { 1534 struct dw_mipi_dsi *dsi = dev_get_priv(host->dev); 1535 1536 if (device->lanes < 1 || device->lanes > 8) 1537 return -EINVAL; 1538 1539 dsi->lanes = device->lanes; 1540 dsi->channel = device->channel; 1541 dsi->format = device->format; 1542 dsi->mode_flags = device->mode_flags; 1543 1544 return 0; 1545 } 1546 1547 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = { 1548 .attach = dw_mipi_dsi_host_attach, 1549 .transfer = dw_mipi_dsi_host_transfer, 1550 }; 1551 1552 static int dw_mipi_dsi_bind(struct udevice *dev) 1553 { 1554 struct mipi_dsi_host *host = dev_get_platdata(dev); 1555 1556 host->dev = dev; 1557 host->ops = &dw_mipi_dsi_host_ops; 1558 1559 return dm_scan_fdt_dev(dev); 1560 } 1561 1562 static int dw_mipi_dsi_child_post_bind(struct udevice *dev) 1563 { 1564 struct mipi_dsi_host *host = dev_get_platdata(dev->parent); 1565 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1566 1567 device->dev = dev; 1568 device->host = host; 1569 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4); 1570 device->format = dev_read_u32_default(dev, "dsi,format", 1571 MIPI_DSI_FMT_RGB888); 1572 device->mode_flags = dev_read_u32_default(dev, "dsi,flags", 1573 MIPI_DSI_MODE_VIDEO | 1574 MIPI_DSI_MODE_VIDEO_BURST | 1575 MIPI_DSI_MODE_VIDEO_HBP | 1576 MIPI_DSI_MODE_LPM | 1577 MIPI_DSI_MODE_EOT_PACKET); 1578 device->channel = dev_read_u32_default(dev, "reg", 0); 1579 1580 return 0; 1581 } 1582 1583 static int dw_mipi_dsi_child_pre_probe(struct udevice *dev) 1584 { 1585 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1586 int ret; 1587 1588 ret = mipi_dsi_attach(device); 1589 if (ret) { 1590 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret); 1591 return ret; 1592 } 1593 1594 return 0; 1595 } 1596 1597 U_BOOT_DRIVER(dw_mipi_dsi) = { 1598 .name = "dw_mipi_dsi", 1599 .id = UCLASS_DISPLAY, 1600 .of_match = dw_mipi_dsi_ids, 1601 .probe = dw_mipi_dsi_probe, 1602 .bind = dw_mipi_dsi_bind, 1603 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi), 1604 .per_child_platdata_auto_alloc_size = sizeof(struct mipi_dsi_device), 1605 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_host), 1606 .child_post_bind = dw_mipi_dsi_child_post_bind, 1607 .child_pre_probe = dw_mipi_dsi_child_pre_probe, 1608 }; 1609