1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <drm/drm_mipi_dsi.h> 8 9 #include <config.h> 10 #include <common.h> 11 #include <errno.h> 12 #include <asm/unaligned.h> 13 #include <asm/io.h> 14 #include <asm/hardware.h> 15 #include <dm/device.h> 16 #include <dm/read.h> 17 #include <dm/of_access.h> 18 #include <syscon.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <linux/iopoll.h> 21 22 #include "rockchip_display.h" 23 #include "rockchip_crtc.h" 24 #include "rockchip_connector.h" 25 #include "rockchip_panel.h" 26 #include "rockchip_phy.h" 27 28 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) 29 30 #define DSI_VERSION 0x00 31 #define DSI_PWR_UP 0x04 32 #define RESET 0 33 #define POWERUP BIT(0) 34 35 #define DSI_CLKMGR_CFG 0x08 36 #define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) 37 #define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) 38 39 #define DSI_DPI_VCID 0x0c 40 #define DPI_VID(vid) (((vid) & 0x3) << 0) 41 42 #define DSI_DPI_COLOR_CODING 0x10 43 #define EN18_LOOSELY BIT(8) 44 #define DPI_COLOR_CODING_16BIT_1 0x0 45 #define DPI_COLOR_CODING_16BIT_2 0x1 46 #define DPI_COLOR_CODING_16BIT_3 0x2 47 #define DPI_COLOR_CODING_18BIT_1 0x3 48 #define DPI_COLOR_CODING_18BIT_2 0x4 49 #define DPI_COLOR_CODING_24BIT 0x5 50 51 #define DSI_DPI_CFG_POL 0x14 52 #define COLORM_ACTIVE_LOW BIT(4) 53 #define SHUTD_ACTIVE_LOW BIT(3) 54 #define HSYNC_ACTIVE_LOW BIT(2) 55 #define VSYNC_ACTIVE_LOW BIT(1) 56 #define DATAEN_ACTIVE_LOW BIT(0) 57 58 #define DSI_DPI_LP_CMD_TIM 0x18 59 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) 60 #define INVACT_LPCMD_TIME(p) ((p) & 0xff) 61 62 #define DSI_DBI_VCID 0x1c 63 #define DBI_VCID(x) UPDATE(x, 1, 0) 64 #define DSI_DBI_CFG 0x20 65 #define DSI_DBI_CMDSIZE 0x28 66 67 #define DSI_PCKHDL_CFG 0x2c 68 #define CRC_RX_EN BIT(4) 69 #define ECC_RX_EN BIT(3) 70 #define BTA_EN BIT(2) 71 #define EOTP_RX_EN BIT(1) 72 #define EOTP_TX_EN BIT(0) 73 #define DSI_MODE_CFG 0x34 74 #define CMD_VIDEO_MODE BIT(0) 75 #define COMMAND_MODE BIT(0) 76 #define VIDEO_MODE 0 77 #define DSI_VID_MODE_CFG 0x38 78 #define VPG_EN BIT(16) 79 #define LP_CMD_EN BIT(15) 80 #define FRAME_BTA_ACK BIT(14) 81 #define LP_HFP_EN BIT(13) 82 #define LP_HBP_EN BIT(12) 83 #define LP_VACT_EN BIT(11) 84 #define LP_VFP_EN BIT(10) 85 #define LP_VBP_EN BIT(9) 86 #define LP_VSA_EN BIT(8) 87 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0 88 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1 89 #define VID_MODE_TYPE_BURST 0x2 90 91 #define DSI_VID_PKT_SIZE 0x3c 92 #define VID_PKT_SIZE(p) (((p) & 0x3fff) << 0) 93 #define VID_PKT_MAX_SIZE 0x3fff 94 95 #define DSI_VID_NUM_CHUMKS 0x40 96 #define DSI_VID_NULL_PKT_SIZE 0x44 97 #define DSI_VID_HSA_TIME 0x48 98 #define DSI_VID_HBP_TIME 0x4c 99 #define DSI_VID_HLINE_TIME 0x50 100 #define DSI_VID_VSA_LINES 0x54 101 #define DSI_VID_VBP_LINES 0x58 102 #define DSI_VID_VFP_LINES 0x5c 103 #define DSI_VID_VACTIVE_LINES 0x60 104 #define DSI_EDPI_CMD_SIZE 0x64 105 #define DSI_CMD_MODE_CFG 0x68 106 #define MAX_RD_PKT_SIZE BIT(24) 107 #define DCS_LW_TX BIT(19) 108 #define DCS_SR_0P_TX BIT(18) 109 #define DCS_SW_1P_TX BIT(17) 110 #define DCS_SW_0P_TX BIT(16) 111 #define GEN_LW_TX BIT(14) 112 #define GEN_SR_2P_TX BIT(13) 113 #define GEN_SR_1P_TX BIT(12) 114 #define GEN_SR_0P_TX BIT(11) 115 #define GEN_SW_2P_TX BIT(10) 116 #define GEN_SW_1P_TX BIT(9) 117 #define GEN_SW_0P_TX BIT(8) 118 #define ACK_RQST_EN BIT(1) 119 #define TEAR_FX_EN BIT(0) 120 121 #define DSI_GEN_HDR 0x6c 122 #define GEN_HDATA(data) (((data) & 0xffff) << 8) 123 #define GEN_HDATA_MASK (0xffff << 8) 124 #define GEN_HTYPE(type) (((type) & 0xff) << 0) 125 #define GEN_HTYPE_MASK 0xff 126 127 #define DSI_GEN_PLD_DATA 0x70 128 129 #define DSI_CMD_PKT_STATUS 0x74 130 #define GEN_CMD_EMPTY BIT(0) 131 #define GEN_CMD_FULL BIT(1) 132 #define GEN_PLD_W_EMPTY BIT(2) 133 #define GEN_PLD_W_FULL BIT(3) 134 #define GEN_PLD_R_EMPTY BIT(4) 135 #define GEN_PLD_R_FULL BIT(5) 136 #define GEN_RD_CMD_BUSY BIT(6) 137 138 #define DSI_TO_CNT_CFG 0x78 139 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16) 140 #define LPRX_TO_CNT(p) ((p) & 0xffff) 141 142 #define DSI_BTA_TO_CNT 0x8c 143 #define DSI_LPCLK_CTRL 0x94 144 #define AUTO_CLKLANE_CTRL BIT(1) 145 #define PHY_TXREQUESTCLKHS BIT(0) 146 147 #define DSI_PHY_TMR_LPCLK_CFG 0x98 148 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16) 149 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff) 150 151 #define DSI_PHY_TMR_CFG 0x9c 152 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24) 153 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16) 154 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff) 155 156 #define DSI_PHY_RSTZ 0xa0 157 #define PHY_ENFORCEPLL BIT(3) 158 #define PHY_ENABLECLK BIT(2) 159 #define PHY_RSTZ BIT(1) 160 #define PHY_SHUTDOWNZ BIT(0) 161 162 #define DSI_PHY_IF_CFG 0xa4 163 #define N_LANES(n) ((((n) - 1) & 0x3) << 0) 164 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 165 166 #define DSI_PHY_STATUS 0xb0 167 #define PHY_STOPSTATE0LANE BIT(4) 168 #define PHY_STOPSTATECLKLANE BIT(2) 169 #define PHY_LOCK BIT(0) 170 #define PHY_STOPSTATELANE (PHY_STOPSTATE0LANE | \ 171 PHY_STOPSTATECLKLANE) 172 173 #define DSI_PHY_TST_CTRL0 0xb4 174 #define PHY_TESTCLK BIT(1) 175 #define PHY_TESTCLR BIT(0) 176 177 #define DSI_PHY_TST_CTRL1 0xb8 178 #define PHY_TESTEN BIT(16) 179 #define PHY_TESTDOUT_SHIFT 8 180 #define PHY_TESTDIN_MASK GENMASK(7, 0) 181 #define PHY_TESTDIN(x) UPDATE(x, 7, 0) 182 183 #define DSI_INT_ST0 0xbc 184 #define DSI_INT_ST1 0xc0 185 #define DSI_INT_MSK0 0xc4 186 #define DSI_INT_MSK1 0xc8 187 188 #define PHY_STATUS_TIMEOUT_US 10000 189 #define CMD_PKT_STATUS_TIMEOUT_US 20000 190 191 /* Test Code: 0x44 (HS RX Control of Lane 0) */ 192 #define HSFREQRANGE(x) UPDATE(x, 6, 1) 193 /* Test Code: 0x17 (PLL Input Divider Ratio) */ 194 #define INPUT_DIV(x) UPDATE(x, 6, 0) 195 /* Test Code: 0x18 (PLL Loop Divider Ratio) */ 196 #define FEEDBACK_DIV_LO(x) UPDATE(x, 4, 0) 197 #define FEEDBACK_DIV_HI(x) (BIT(7) | UPDATE(x, 3, 0)) 198 199 #define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 10) | ((lsb) << 5) | (msb)) 200 201 enum grf_reg_fields { 202 DPIUPDATECFG, 203 DPISHUTDN, 204 DPICOLORM, 205 VOPSEL, 206 TURNREQUEST, 207 TURNDISABLE, 208 SKEWCALHS, 209 FORCETXSTOPMODE, 210 FORCERXMODE, 211 ENABLE_N, 212 MASTERSLAVEZ, 213 ENABLECLK, 214 BASEDIR, 215 MAX_FIELDS, 216 }; 217 218 struct dw_mipi_dsi_plat_data { 219 const u32 *dsi0_grf_reg_fields; 220 const u32 *dsi1_grf_reg_fields; 221 unsigned long max_bit_rate_per_lane; 222 }; 223 224 struct mipi_dphy { 225 /* Non-SNPS PHY */ 226 struct rockchip_phy *phy; 227 228 u16 input_div; 229 u16 feedback_div; 230 }; 231 232 struct dw_mipi_dsi { 233 struct rockchip_connector connector; 234 struct udevice *dev; 235 void *base; 236 void *grf; 237 int id; 238 struct dw_mipi_dsi *master; 239 struct dw_mipi_dsi *slave; 240 bool prepared; 241 242 unsigned int lane_mbps; /* per lane */ 243 u32 channel; 244 u32 lanes; 245 u32 format; 246 u32 mode_flags; 247 struct mipi_dphy dphy; 248 struct drm_display_mode mode; 249 bool data_swap; 250 bool dual_channel; 251 bool disable_hold_mode; 252 253 const struct dw_mipi_dsi_plat_data *pdata; 254 }; 255 256 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) 257 { 258 writel(val, dsi->base + reg); 259 } 260 261 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) 262 { 263 return readl(dsi->base + reg); 264 } 265 266 static inline void dsi_update_bits(struct dw_mipi_dsi *dsi, 267 u32 reg, u32 mask, u32 val) 268 { 269 u32 orig, tmp; 270 271 orig = dsi_read(dsi, reg); 272 tmp = orig & ~mask; 273 tmp |= val & mask; 274 dsi_write(dsi, reg, tmp); 275 } 276 277 static void grf_field_write(struct dw_mipi_dsi *dsi, enum grf_reg_fields index, 278 unsigned int val) 279 { 280 const u32 field = dsi->id ? dsi->pdata->dsi1_grf_reg_fields[index] : 281 dsi->pdata->dsi0_grf_reg_fields[index]; 282 u16 reg; 283 u8 msb, lsb; 284 285 if (!field) 286 return; 287 288 reg = (field >> 10) & 0x3ffff; 289 lsb = (field >> 5) & 0x1f; 290 msb = (field >> 0) & 0x1f; 291 292 rk_clrsetreg(dsi->grf + reg, GENMASK(msb, lsb), val << lsb); 293 } 294 295 static inline void dpishutdn_assert(struct dw_mipi_dsi *dsi) 296 { 297 grf_field_write(dsi, DPISHUTDN, 1); 298 } 299 300 static inline void dpishutdn_deassert(struct dw_mipi_dsi *dsi) 301 { 302 grf_field_write(dsi, DPISHUTDN, 0); 303 } 304 305 static int genif_wait_w_pld_fifo_not_full(struct dw_mipi_dsi *dsi) 306 { 307 u32 sts; 308 int ret; 309 310 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 311 sts, !(sts & GEN_PLD_W_FULL), 312 CMD_PKT_STATUS_TIMEOUT_US); 313 if (ret < 0) { 314 printf("generic write payload fifo is full\n"); 315 return ret; 316 } 317 318 return 0; 319 } 320 321 static int genif_wait_cmd_fifo_not_full(struct dw_mipi_dsi *dsi) 322 { 323 u32 sts; 324 int ret; 325 326 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 327 sts, !(sts & GEN_CMD_FULL), 328 CMD_PKT_STATUS_TIMEOUT_US); 329 if (ret < 0) { 330 printf("generic write cmd fifo is full\n"); 331 return ret; 332 } 333 334 return 0; 335 } 336 337 static int genif_wait_write_fifo_empty(struct dw_mipi_dsi *dsi) 338 { 339 u32 sts; 340 u32 mask; 341 int ret; 342 343 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 344 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 345 sts, (sts & mask) == mask, 346 CMD_PKT_STATUS_TIMEOUT_US); 347 if (ret < 0) { 348 printf("generic write fifo is full\n"); 349 return ret; 350 } 351 352 return 0; 353 } 354 355 static inline void mipi_dphy_enableclk_assert(struct dw_mipi_dsi *dsi) 356 { 357 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK); 358 udelay(1); 359 } 360 361 static inline void mipi_dphy_enableclk_deassert(struct dw_mipi_dsi *dsi) 362 { 363 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, 0); 364 udelay(1); 365 } 366 367 static inline void mipi_dphy_shutdownz_assert(struct dw_mipi_dsi *dsi) 368 { 369 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, 0); 370 udelay(1); 371 } 372 373 static inline void mipi_dphy_shutdownz_deassert(struct dw_mipi_dsi *dsi) 374 { 375 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, PHY_SHUTDOWNZ); 376 udelay(1); 377 } 378 379 static inline void mipi_dphy_rstz_assert(struct dw_mipi_dsi *dsi) 380 { 381 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, 0); 382 udelay(1); 383 } 384 385 static inline void mipi_dphy_rstz_deassert(struct dw_mipi_dsi *dsi) 386 { 387 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, PHY_RSTZ); 388 udelay(1); 389 } 390 391 static inline void testif_testclk_assert(struct dw_mipi_dsi *dsi) 392 { 393 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK); 394 udelay(1); 395 } 396 397 static inline void testif_testclk_deassert(struct dw_mipi_dsi *dsi) 398 { 399 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK, 0); 400 udelay(1); 401 } 402 403 static inline void testif_testclr_assert(struct dw_mipi_dsi *dsi) 404 { 405 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR, PHY_TESTCLR); 406 udelay(1); 407 } 408 409 static inline void testif_testclr_deassert(struct dw_mipi_dsi *dsi) 410 { 411 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR, 0); 412 udelay(1); 413 } 414 415 static inline void testif_testen_assert(struct dw_mipi_dsi *dsi) 416 { 417 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN, PHY_TESTEN); 418 udelay(1); 419 } 420 421 static inline void testif_testen_deassert(struct dw_mipi_dsi *dsi) 422 { 423 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN, 0); 424 udelay(1); 425 } 426 427 static inline void testif_set_data(struct dw_mipi_dsi *dsi, u8 data) 428 { 429 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, 430 PHY_TESTDIN_MASK, PHY_TESTDIN(data)); 431 udelay(1); 432 } 433 434 static inline u8 testif_get_data(struct dw_mipi_dsi *dsi) 435 { 436 return dsi_read(dsi, DSI_PHY_TST_CTRL1) >> PHY_TESTDOUT_SHIFT; 437 } 438 439 static void testif_test_code_write(struct dw_mipi_dsi *dsi, u8 test_code) 440 { 441 testif_testclk_assert(dsi); 442 testif_set_data(dsi, test_code); 443 testif_testen_assert(dsi); 444 testif_testclk_deassert(dsi); 445 testif_testen_deassert(dsi); 446 } 447 448 static void testif_test_data_write(struct dw_mipi_dsi *dsi, u8 test_data) 449 { 450 testif_testclk_deassert(dsi); 451 testif_set_data(dsi, test_data); 452 testif_testclk_assert(dsi); 453 } 454 455 static void testif_write(struct dw_mipi_dsi *dsi, u8 test_code, u8 test_data) 456 { 457 testif_test_code_write(dsi, test_code); 458 testif_test_data_write(dsi, test_data); 459 460 dev_dbg(dsi->dev, 461 "test_code=0x%02x, test_data=0x%02x, monitor_data=0x%02x\n", 462 test_code, test_data, testif_get_data(dsi)); 463 } 464 465 static int mipi_dphy_power_on(struct dw_mipi_dsi *dsi) 466 { 467 u32 mask, val; 468 int ret; 469 470 mipi_dphy_shutdownz_deassert(dsi); 471 mipi_dphy_rstz_deassert(dsi); 472 mdelay(2); 473 474 if (dsi->dphy.phy) { 475 rockchip_phy_set_mode(dsi->dphy.phy, PHY_MODE_MIPI_DPHY); 476 rockchip_phy_power_on(dsi->dphy.phy); 477 } 478 479 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 480 val, val & PHY_LOCK, PHY_STATUS_TIMEOUT_US); 481 if (ret < 0) { 482 dev_err(dsi->dev, "PHY is not locked\n"); 483 return ret; 484 } 485 486 udelay(200); 487 488 mask = PHY_STOPSTATELANE; 489 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 490 val, (val & mask) == mask, 491 PHY_STATUS_TIMEOUT_US); 492 if (ret < 0) { 493 dev_err(dsi->dev, "lane module is not in stop state\n"); 494 return ret; 495 } 496 497 udelay(10); 498 499 return 0; 500 } 501 502 static void dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) 503 { 504 /* Table 5-1 Frequency Ranges */ 505 const struct { 506 unsigned long max_lane_mbps; 507 u8 hsfreqrange; 508 } hsfreqrange_table[] = { 509 { 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01}, 510 { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12}, 511 { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23}, 512 { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15}, 513 { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07}, 514 { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09}, 515 { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a}, 516 {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b}, 517 {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c}, 518 {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c} 519 }; 520 u8 hsfreqrange, counter; 521 unsigned int index, txbyteclkhs; 522 u16 n, m; 523 524 for (index = 0; index < ARRAY_SIZE(hsfreqrange_table); index++) 525 if (dsi->lane_mbps <= hsfreqrange_table[index].max_lane_mbps) 526 break; 527 528 if (index == ARRAY_SIZE(hsfreqrange_table)) 529 --index; 530 531 hsfreqrange = hsfreqrange_table[index].hsfreqrange; 532 testif_write(dsi, 0x44, HSFREQRANGE(hsfreqrange)); 533 534 txbyteclkhs = dsi->lane_mbps >> 3; 535 counter = txbyteclkhs * 60 / 1000; 536 testif_write(dsi, 0x60, 0x80 | counter); 537 testif_write(dsi, 0x70, 0x80 | counter); 538 539 n = dsi->dphy.input_div - 1; 540 m = dsi->dphy.feedback_div - 1; 541 testif_write(dsi, 0x19, 0x30); 542 testif_write(dsi, 0x17, INPUT_DIV(n)); 543 testif_write(dsi, 0x18, FEEDBACK_DIV_LO(m)); 544 testif_write(dsi, 0x18, FEEDBACK_DIV_HI(m >> 5)); 545 } 546 547 static unsigned long dw_mipi_dsi_get_lane_rate(struct dw_mipi_dsi *dsi) 548 { 549 const struct drm_display_mode *mode = &dsi->mode; 550 unsigned long max_lane_rate = dsi->pdata->max_bit_rate_per_lane; 551 unsigned long lane_rate; 552 unsigned int value; 553 int bpp, lanes; 554 u64 tmp; 555 556 /* optional override of the desired bandwidth */ 557 value = dev_read_u32_default(dsi->dev, "rockchip,lane-rate", 0); 558 if (value > 0) 559 return value * 1000 * 1000; 560 561 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 562 if (bpp < 0) 563 bpp = 24; 564 565 lanes = dsi->slave ? dsi->lanes * 2 : dsi->lanes; 566 tmp = (u64)mode->clock * 1000 * bpp; 567 do_div(tmp, lanes); 568 569 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */ 570 tmp *= 10; 571 do_div(tmp, 9); 572 573 if (tmp > max_lane_rate) 574 lane_rate = max_lane_rate; 575 else 576 lane_rate = tmp; 577 578 return lane_rate; 579 } 580 581 static void dw_mipi_dsi_set_pll(struct dw_mipi_dsi *dsi, unsigned long rate) 582 { 583 unsigned long fin, fout; 584 unsigned long fvco_min, fvco_max, best_freq = 984000000; 585 u8 min_prediv, max_prediv; 586 u8 _prediv, best_prediv = 2; 587 u16 _fbdiv, best_fbdiv = 82; 588 u32 min_delta = ~0U; 589 590 fin = 24000000; 591 fout = rate; 592 593 /* 5Mhz < Fref / N < 40MHz, 80MHz < Fvco < 1500Mhz */ 594 min_prediv = DIV_ROUND_UP(fin, 40000000); 595 max_prediv = fin / 5000000; 596 fvco_min = 80000000; 597 fvco_max = 1500000000; 598 599 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 600 u64 tmp, _fout; 601 u32 delta; 602 603 /* Fvco = Fref * M / N */ 604 tmp = (u64)fout * _prediv; 605 do_div(tmp, fin); 606 _fbdiv = tmp; 607 608 /* 609 * Due to the use of a "by 2 pre-scaler," the range of the 610 * feedback multiplication value M is limited to even division 611 * numbers, and m must be greater than 12, less than 1000. 612 */ 613 if (_fbdiv <= 12 || _fbdiv >= 1000) 614 continue; 615 616 if (_fbdiv % 2) 617 ++_fbdiv; 618 619 _fout = (u64)_fbdiv * fin; 620 do_div(_fout, _prediv); 621 622 if (_fout < fvco_min || _fout > fvco_max) 623 continue; 624 625 delta = abs(fout - _fout); 626 if (!delta) { 627 best_prediv = _prediv; 628 best_fbdiv = _fbdiv; 629 best_freq = _fout; 630 break; 631 } else if (delta < min_delta) { 632 best_prediv = _prediv; 633 best_fbdiv = _fbdiv; 634 best_freq = _fout; 635 min_delta = delta; 636 } 637 } 638 639 dsi->lane_mbps = best_freq / 1000 / 1000; 640 dsi->dphy.input_div = best_prediv; 641 dsi->dphy.feedback_div = best_fbdiv; 642 if (dsi->slave) { 643 dsi->slave->lane_mbps = dsi->lane_mbps; 644 dsi->slave->dphy.input_div = dsi->dphy.input_div; 645 dsi->slave->dphy.feedback_div = dsi->dphy.feedback_div; 646 } 647 if (dsi->master) { 648 dsi->master->lane_mbps = dsi->lane_mbps; 649 dsi->master->dphy.input_div = dsi->dphy.input_div; 650 dsi->master->dphy.feedback_div = dsi->dphy.feedback_div; 651 } 652 } 653 654 static int dw_mipi_dsi_read_from_fifo(struct dw_mipi_dsi *dsi, 655 const struct mipi_dsi_msg *msg) 656 { 657 u8 *payload = msg->rx_buf; 658 u16 length; 659 u32 val; 660 int ret; 661 662 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 663 val, !(val & GEN_RD_CMD_BUSY), 5000); 664 if (ret) { 665 printf("entire response isn't stored in the FIFO\n"); 666 return ret; 667 } 668 669 /* Receive payload */ 670 for (length = msg->rx_len; length; length -= 4) { 671 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 672 val, !(val & GEN_PLD_R_EMPTY), 5000); 673 if (ret) { 674 printf("Read payload FIFO is empty\n"); 675 return ret; 676 } 677 678 val = dsi_read(dsi, DSI_GEN_PLD_DATA); 679 680 switch (length) { 681 case 3: 682 payload[2] = (val >> 16) & 0xff; 683 /* Fall through */ 684 case 2: 685 payload[1] = (val >> 8) & 0xff; 686 /* Fall through */ 687 case 1: 688 payload[0] = val & 0xff; 689 return 0; 690 } 691 692 payload[0] = (val >> 0) & 0xff; 693 payload[1] = (val >> 8) & 0xff; 694 payload[2] = (val >> 16) & 0xff; 695 payload[3] = (val >> 24) & 0xff; 696 payload += 4; 697 } 698 699 return 0; 700 } 701 702 static int dw_mipi_dsi_turn_on_peripheral(struct dw_mipi_dsi *dsi) 703 { 704 dpishutdn_assert(dsi); 705 udelay(20); 706 dpishutdn_deassert(dsi); 707 708 return 0; 709 } 710 711 static int dw_mipi_dsi_shutdown_peripheral(struct dw_mipi_dsi *dsi) 712 { 713 dpishutdn_deassert(dsi); 714 udelay(20); 715 dpishutdn_assert(dsi); 716 717 return 0; 718 } 719 720 static ssize_t dw_mipi_dsi_transfer(struct dw_mipi_dsi *dsi, 721 const struct mipi_dsi_msg *msg) 722 { 723 struct mipi_dsi_packet packet; 724 int ret; 725 int val; 726 727 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { 728 dsi_update_bits(dsi, DSI_VID_MODE_CFG, LP_CMD_EN, LP_CMD_EN); 729 dsi_update_bits(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS, 0); 730 } else { 731 dsi_update_bits(dsi, DSI_VID_MODE_CFG, LP_CMD_EN, 0); 732 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 733 PHY_TXREQUESTCLKHS, PHY_TXREQUESTCLKHS); 734 } 735 736 switch (msg->type) { 737 case MIPI_DSI_SHUTDOWN_PERIPHERAL: 738 return dw_mipi_dsi_shutdown_peripheral(dsi); 739 case MIPI_DSI_TURN_ON_PERIPHERAL: 740 return dw_mipi_dsi_turn_on_peripheral(dsi); 741 case MIPI_DSI_DCS_SHORT_WRITE: 742 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_0P_TX, 743 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 744 DCS_SW_0P_TX : 0); 745 break; 746 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 747 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_1P_TX, 748 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 749 DCS_SW_1P_TX : 0); 750 break; 751 case MIPI_DSI_DCS_LONG_WRITE: 752 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX, 753 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 754 DCS_LW_TX : 0); 755 break; 756 case MIPI_DSI_DCS_READ: 757 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SR_0P_TX, 758 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 759 DCS_SR_0P_TX : 0); 760 break; 761 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: 762 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, MAX_RD_PKT_SIZE, 763 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 764 MAX_RD_PKT_SIZE : 0); 765 break; 766 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 767 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_0P_TX, 768 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 769 GEN_SW_0P_TX : 0); 770 break; 771 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 772 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_1P_TX, 773 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 774 GEN_SW_1P_TX : 0); 775 break; 776 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 777 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_2P_TX, 778 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 779 GEN_SW_2P_TX : 0); 780 break; 781 case MIPI_DSI_GENERIC_LONG_WRITE: 782 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_LW_TX, 783 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 784 GEN_LW_TX : 0); 785 break; 786 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 787 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_0P_TX, 788 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 789 GEN_SR_0P_TX : 0); 790 break; 791 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 792 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_1P_TX, 793 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 794 GEN_SR_1P_TX : 0); 795 break; 796 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 797 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_2P_TX, 798 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 799 GEN_SR_2P_TX : 0); 800 break; 801 default: 802 return -EINVAL; 803 } 804 805 if (msg->flags & MIPI_DSI_MSG_REQ_ACK) 806 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, 807 ACK_RQST_EN, ACK_RQST_EN); 808 809 /* create a packet to the DSI protocol */ 810 ret = mipi_dsi_create_packet(&packet, msg); 811 if (ret) { 812 printf("failed to create packet: %d\n", ret); 813 return ret; 814 } 815 816 /* Send payload */ 817 while (DIV_ROUND_UP(packet.payload_length, 4)) { 818 /* 819 * Alternatively, you can always keep the FIFO 820 * nearly full by monitoring the FIFO state until 821 * it is not full, and then writea single word of data. 822 * This solution is more resource consuming 823 * but it simultaneously avoids FIFO starvation, 824 * making it possible to use FIFO sizes smaller than 825 * the amount of data of the longest packet to be written. 826 */ 827 ret = genif_wait_w_pld_fifo_not_full(dsi); 828 if (ret) 829 return ret; 830 831 if (packet.payload_length < 4) { 832 /* send residu payload */ 833 val = 0; 834 memcpy(&val, packet.payload, packet.payload_length); 835 dsi_write(dsi, DSI_GEN_PLD_DATA, val); 836 packet.payload_length = 0; 837 } else { 838 val = get_unaligned_le32(packet.payload); 839 dsi_write(dsi, DSI_GEN_PLD_DATA, val); 840 packet.payload += 4; 841 packet.payload_length -= 4; 842 } 843 } 844 845 ret = genif_wait_cmd_fifo_not_full(dsi); 846 if (ret) 847 return ret; 848 849 /* Send packet header */ 850 val = get_unaligned_le32(packet.header); 851 dsi_write(dsi, DSI_GEN_HDR, val); 852 853 ret = genif_wait_write_fifo_empty(dsi); 854 if (ret) 855 return ret; 856 857 if (msg->rx_len) { 858 ret = dw_mipi_dsi_read_from_fifo(dsi, msg); 859 if (ret < 0) 860 return ret; 861 } 862 863 if (dsi->slave) { 864 ret = dw_mipi_dsi_transfer(dsi->slave, msg); 865 if (ret < 0) 866 return ret; 867 } 868 869 return msg->rx_len ? msg->rx_len : msg->tx_len; 870 } 871 872 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) 873 { 874 u32 val = LP_VACT_EN | LP_VFP_EN | LP_VBP_EN | LP_VSA_EN | 875 LP_HFP_EN | LP_HBP_EN; 876 877 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP) 878 val &= ~LP_HFP_EN; 879 880 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP) 881 val &= ~LP_HBP_EN; 882 883 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 884 val |= VID_MODE_TYPE_BURST; 885 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 886 val |= VID_MODE_TYPE_BURST_SYNC_PULSES; 887 else 888 val |= VID_MODE_TYPE_BURST_SYNC_EVENTS; 889 890 dsi_write(dsi, DSI_VID_MODE_CFG, val); 891 892 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 893 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 894 AUTO_CLKLANE_CTRL, AUTO_CLKLANE_CTRL); 895 } 896 897 static void dw_mipi_dsi_enable(struct dw_mipi_dsi *dsi) 898 { 899 const struct drm_display_mode *mode = &dsi->mode; 900 901 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 902 PHY_TXREQUESTCLKHS, PHY_TXREQUESTCLKHS); 903 904 dsi_write(dsi, DSI_PWR_UP, RESET); 905 906 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 907 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, VIDEO_MODE); 908 } else { 909 dsi_write(dsi, DSI_DBI_VCID, DBI_VCID(dsi->channel)); 910 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX, 0); 911 dsi_write(dsi, DSI_EDPI_CMD_SIZE, mode->hdisplay); 912 dsi_update_bits(dsi, DSI_MODE_CFG, 913 CMD_VIDEO_MODE, COMMAND_MODE); 914 } 915 916 dsi_write(dsi, DSI_PWR_UP, POWERUP); 917 918 if (dsi->slave) 919 dw_mipi_dsi_enable(dsi->slave); 920 } 921 922 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) 923 { 924 dsi_write(dsi, DSI_PWR_UP, RESET); 925 dsi_write(dsi, DSI_LPCLK_CTRL, 0); 926 dsi_write(dsi, DSI_EDPI_CMD_SIZE, 0); 927 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, COMMAND_MODE); 928 dsi_write(dsi, DSI_PWR_UP, POWERUP); 929 930 if (dsi->slave) 931 dw_mipi_dsi_disable(dsi->slave); 932 } 933 934 static void dw_mipi_dsi_post_disable(struct dw_mipi_dsi *dsi) 935 { 936 if (!dsi->prepared) 937 return; 938 939 if (dsi->master) 940 dw_mipi_dsi_post_disable(dsi->master); 941 942 dsi_write(dsi, DSI_PWR_UP, RESET); 943 dsi_write(dsi, DSI_PHY_RSTZ, 0); 944 945 if (dsi->dphy.phy) 946 rockchip_phy_power_off(dsi->dphy.phy); 947 948 dsi->prepared = false; 949 950 if (dsi->slave) 951 dw_mipi_dsi_post_disable(dsi->slave); 952 } 953 954 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) 955 { 956 u32 esc_clk_div; 957 958 dsi_write(dsi, DSI_PWR_UP, RESET); 959 960 /* The maximum value of the escape clock frequency is 20MHz */ 961 esc_clk_div = DIV_ROUND_UP(dsi->lane_mbps >> 3, 20); 962 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) | 963 TX_ESC_CLK_DIVIDSION(esc_clk_div)); 964 } 965 966 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, 967 struct drm_display_mode *mode) 968 { 969 u32 val = 0, color = 0; 970 971 switch (dsi->format) { 972 case MIPI_DSI_FMT_RGB888: 973 color = DPI_COLOR_CODING_24BIT; 974 break; 975 case MIPI_DSI_FMT_RGB666: 976 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY; 977 break; 978 case MIPI_DSI_FMT_RGB666_PACKED: 979 color = DPI_COLOR_CODING_18BIT_1; 980 break; 981 case MIPI_DSI_FMT_RGB565: 982 color = DPI_COLOR_CODING_16BIT_1; 983 break; 984 } 985 986 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 987 val |= VSYNC_ACTIVE_LOW; 988 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 989 val |= HSYNC_ACTIVE_LOW; 990 991 dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel)); 992 dsi_write(dsi, DSI_DPI_COLOR_CODING, color); 993 dsi_write(dsi, DSI_DPI_CFG_POL, val); 994 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4) 995 | INVACT_LPCMD_TIME(4)); 996 } 997 998 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi) 999 { 1000 u32 val = CRC_RX_EN | ECC_RX_EN | BTA_EN | EOTP_TX_EN; 1001 1002 if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) 1003 val &= ~EOTP_TX_EN; 1004 1005 dsi_write(dsi, DSI_PCKHDL_CFG, val); 1006 } 1007 1008 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, 1009 struct drm_display_mode *mode) 1010 { 1011 dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay)); 1012 } 1013 1014 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) 1015 { 1016 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000)); 1017 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); 1018 } 1019 1020 /* Get lane byte clock cycles. */ 1021 static int dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, 1022 u32 hcomponent) 1023 { 1024 u32 lbcc; 1025 1026 lbcc = hcomponent * dsi->lane_mbps * 1000 / 8; 1027 1028 if (!dsi->mode.clock) 1029 return 0; 1030 1031 return DIV_ROUND_CLOSEST(lbcc, dsi->mode.clock); 1032 } 1033 1034 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi) 1035 { 1036 int htotal, hsa, hbp, lbcc; 1037 struct drm_display_mode *mode = &dsi->mode; 1038 1039 htotal = mode->htotal; 1040 hsa = mode->hsync_end - mode->hsync_start; 1041 hbp = mode->htotal - mode->hsync_end; 1042 1043 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal); 1044 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); 1045 1046 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa); 1047 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); 1048 1049 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp); 1050 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); 1051 } 1052 1053 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi) 1054 { 1055 u32 vactive, vsa, vfp, vbp; 1056 struct drm_display_mode *mode = &dsi->mode; 1057 1058 vactive = mode->vdisplay; 1059 vsa = mode->vsync_end - mode->vsync_start; 1060 vfp = mode->vsync_start - mode->vdisplay; 1061 vbp = mode->vtotal - mode->vsync_end; 1062 1063 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); 1064 dsi_write(dsi, DSI_VID_VSA_LINES, vsa); 1065 dsi_write(dsi, DSI_VID_VFP_LINES, vfp); 1066 dsi_write(dsi, DSI_VID_VBP_LINES, vbp); 1067 } 1068 1069 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) 1070 { 1071 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14) 1072 | PHY_LP2HS_TIME(0x10) | MAX_RD_TIME(10000)); 1073 1074 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40) 1075 | PHY_CLKLP2HS_TIME(0x40)); 1076 } 1077 1078 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) 1079 { 1080 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) | 1081 N_LANES(dsi->lanes)); 1082 } 1083 1084 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) 1085 { 1086 dsi_read(dsi, DSI_INT_ST0); 1087 dsi_read(dsi, DSI_INT_ST1); 1088 dsi_write(dsi, DSI_INT_MSK0, 0); 1089 dsi_write(dsi, DSI_INT_MSK1, 0); 1090 } 1091 1092 static int dw_mipi_dsi_connector_init(struct rockchip_connector *conn, struct display_state *state) 1093 { 1094 struct connector_state *conn_state = &state->conn_state; 1095 struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev); 1096 1097 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dsi->id); 1098 dsi->dphy.phy = conn->phy; 1099 1100 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 1101 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709; 1102 conn_state->color_range = DRM_COLOR_YCBCR_FULL_RANGE; 1103 conn_state->output_if |= 1104 dsi->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0; 1105 1106 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { 1107 conn_state->output_flags |= ROCKCHIP_OUTPUT_MIPI_DS_MODE; 1108 conn_state->hold_mode = dsi->disable_hold_mode ? false : true; 1109 } 1110 1111 #ifndef CONFIG_ROCKCHIP_RK3568 1112 if (dsi->id) { 1113 struct udevice *dev; 1114 int ret; 1115 1116 ret = uclass_get_device_by_name(UCLASS_DISPLAY, "dsi@ff960000", 1117 &dev); 1118 if (ret) 1119 return ret; 1120 1121 dsi->master = dev_get_priv(dev); 1122 if (!dsi->master) 1123 return -ENODEV; 1124 1125 conn_state->output_flags = ROCKCHIP_OUTPUT_DATA_SWAP; 1126 } 1127 #endif 1128 1129 if (dsi->dual_channel) { 1130 struct udevice *dev; 1131 int ret; 1132 1133 ret = uclass_get_device_by_name(UCLASS_DISPLAY, 1134 #if defined(CONFIG_ROCKCHIP_RK3288) 1135 "dsi@ff964000", 1136 #elif defined(CONFIG_ROCKCHIP_RK3399) 1137 "dsi@ff968000", 1138 #else 1139 "dsi@fe070000", 1140 #endif 1141 &dev); 1142 if (ret) 1143 return ret; 1144 1145 dsi->slave = dev_get_priv(dev); 1146 if (!dsi->slave) 1147 return -ENODEV; 1148 1149 dsi->lanes /= 2; 1150 dsi->slave->lanes = dsi->lanes; 1151 dsi->slave->format = dsi->format; 1152 dsi->slave->mode_flags = dsi->mode_flags; 1153 dsi->slave->channel = dsi->channel; 1154 conn_state->output_flags = 1155 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; 1156 if (dsi->data_swap) 1157 conn_state->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP; 1158 1159 conn_state->output_if |= VOP_OUTPUT_IF_MIPI1; 1160 1161 #if defined(CONFIG_ROCKCHIP_RK3568) 1162 struct rockchip_phy *phy = NULL; 1163 struct udevice *phy_dev; 1164 1165 ret = uclass_get_device_by_phandle(UCLASS_PHY, dev, 1166 "phys", &phy_dev); 1167 if (ret) 1168 return -ENODEV; 1169 1170 phy = (struct rockchip_phy *)dev_get_driver_data(phy_dev); 1171 if (!phy) 1172 return -ENODEV; 1173 1174 dsi->slave->dphy.phy = phy; 1175 if (phy->funcs && phy->funcs->init) 1176 return phy->funcs->init(phy); 1177 #endif 1178 1179 } 1180 1181 return 0; 1182 } 1183 1184 static void dw_mipi_dsi_set_hs_clk(struct dw_mipi_dsi *dsi, unsigned long rate) 1185 { 1186 rate = rockchip_phy_set_pll(dsi->dphy.phy, rate); 1187 dsi->lane_mbps = rate / 1000 / 1000; 1188 } 1189 1190 static void dw_mipi_dsi_host_init(struct dw_mipi_dsi *dsi) 1191 { 1192 dw_mipi_dsi_init(dsi); 1193 dw_mipi_dsi_dpi_config(dsi, &dsi->mode); 1194 dw_mipi_dsi_packet_handler_config(dsi); 1195 dw_mipi_dsi_video_mode_config(dsi); 1196 dw_mipi_dsi_video_packet_config(dsi, &dsi->mode); 1197 dw_mipi_dsi_command_mode_config(dsi); 1198 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, COMMAND_MODE); 1199 dw_mipi_dsi_line_timer_config(dsi); 1200 dw_mipi_dsi_vertical_timing_config(dsi); 1201 dw_mipi_dsi_dphy_timing_config(dsi); 1202 dw_mipi_dsi_dphy_interface_config(dsi); 1203 dw_mipi_dsi_clear_err(dsi); 1204 } 1205 1206 static void dw_mipi_dsi_vop_routing(struct dw_mipi_dsi *dsi, int vop_id) 1207 { 1208 grf_field_write(dsi, VOPSEL, vop_id); 1209 1210 if (dsi->slave) 1211 grf_field_write(dsi->slave, VOPSEL, vop_id); 1212 } 1213 1214 static void mipi_dphy_init(struct dw_mipi_dsi *dsi) 1215 { 1216 u32 map[] = {0x0, 0x1, 0x3, 0x7, 0xf}; 1217 1218 mipi_dphy_enableclk_deassert(dsi); 1219 mipi_dphy_shutdownz_assert(dsi); 1220 mipi_dphy_rstz_assert(dsi); 1221 testif_testclr_assert(dsi); 1222 1223 /* Configures DPHY to work as a Master */ 1224 grf_field_write(dsi, MASTERSLAVEZ, 1); 1225 1226 /* Configures lane as TX */ 1227 grf_field_write(dsi, BASEDIR, 0); 1228 1229 /* Set all REQUEST inputs to zero */ 1230 grf_field_write(dsi, TURNREQUEST, 0); 1231 grf_field_write(dsi, TURNDISABLE, 0); 1232 grf_field_write(dsi, FORCETXSTOPMODE, 0); 1233 grf_field_write(dsi, FORCERXMODE, 0); 1234 udelay(1); 1235 1236 testif_testclr_deassert(dsi); 1237 1238 if (!dsi->dphy.phy) 1239 dw_mipi_dsi_phy_init(dsi); 1240 1241 /* Enable Data Lane Module */ 1242 grf_field_write(dsi, ENABLE_N, map[dsi->lanes]); 1243 1244 /* Enable Clock Lane Module */ 1245 grf_field_write(dsi, ENABLECLK, 1); 1246 1247 mipi_dphy_enableclk_assert(dsi); 1248 } 1249 1250 static void dw_mipi_dsi_pre_enable(struct dw_mipi_dsi *dsi) 1251 { 1252 if (dsi->prepared) 1253 return; 1254 1255 if (dsi->master) 1256 dw_mipi_dsi_pre_enable(dsi->master); 1257 1258 dw_mipi_dsi_host_init(dsi); 1259 mipi_dphy_init(dsi); 1260 mipi_dphy_power_on(dsi); 1261 dsi_write(dsi, DSI_PWR_UP, POWERUP); 1262 1263 dsi->prepared = true; 1264 1265 if (dsi->slave) 1266 dw_mipi_dsi_pre_enable(dsi->slave); 1267 } 1268 1269 static int dw_mipi_dsi_connector_prepare(struct rockchip_connector *conn, 1270 struct display_state *state) 1271 { 1272 struct connector_state *conn_state = &state->conn_state; 1273 struct crtc_state *crtc_state = &state->crtc_state; 1274 struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev); 1275 unsigned long lane_rate; 1276 1277 memcpy(&dsi->mode, &conn_state->mode, sizeof(struct drm_display_mode)); 1278 if (dsi->slave) { 1279 dsi->mode.hdisplay /= 2; 1280 memcpy(&dsi->slave->mode, &dsi->mode, 1281 sizeof(struct drm_display_mode)); 1282 } 1283 1284 lane_rate = dw_mipi_dsi_get_lane_rate(dsi); 1285 if (dsi->dphy.phy) 1286 dw_mipi_dsi_set_hs_clk(dsi, lane_rate); 1287 else 1288 dw_mipi_dsi_set_pll(dsi, lane_rate); 1289 1290 if (dsi->slave && dsi->slave->dphy.phy) 1291 dw_mipi_dsi_set_hs_clk(dsi->slave, lane_rate); 1292 1293 printf("final DSI-Link bandwidth: %u Mbps x %d\n", 1294 dsi->lane_mbps, dsi->slave ? dsi->lanes * 2 : dsi->lanes); 1295 1296 dw_mipi_dsi_vop_routing(dsi, crtc_state->crtc_id); 1297 dw_mipi_dsi_pre_enable(dsi); 1298 1299 return 0; 1300 } 1301 1302 static void dw_mipi_dsi_connector_unprepare(struct rockchip_connector *conn, 1303 struct display_state *state) 1304 { 1305 struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev); 1306 1307 dw_mipi_dsi_post_disable(dsi); 1308 } 1309 1310 static int dw_mipi_dsi_connector_enable(struct rockchip_connector *conn, 1311 struct display_state *state) 1312 { 1313 struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev); 1314 1315 dw_mipi_dsi_enable(dsi); 1316 1317 return 0; 1318 } 1319 1320 static int dw_mipi_dsi_connector_disable(struct rockchip_connector *conn, 1321 struct display_state *state) 1322 { 1323 struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev); 1324 1325 dw_mipi_dsi_disable(dsi); 1326 1327 return 0; 1328 } 1329 1330 static const struct rockchip_connector_funcs dw_mipi_dsi_connector_funcs = { 1331 .init = dw_mipi_dsi_connector_init, 1332 .prepare = dw_mipi_dsi_connector_prepare, 1333 .unprepare = dw_mipi_dsi_connector_unprepare, 1334 .enable = dw_mipi_dsi_connector_enable, 1335 .disable = dw_mipi_dsi_connector_disable, 1336 }; 1337 1338 static int dw_mipi_dsi_probe(struct udevice *dev) 1339 { 1340 struct dw_mipi_dsi *dsi = dev_get_priv(dev); 1341 const struct dw_mipi_dsi_plat_data *pdata = 1342 (const struct dw_mipi_dsi_plat_data *)dev_get_driver_data(dev); 1343 int id; 1344 1345 dsi->base = dev_read_addr_ptr(dev); 1346 dsi->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1347 if (IS_ERR(dsi->grf)) 1348 return PTR_ERR(dsi->grf); 1349 1350 id = of_alias_get_id(ofnode_to_np(dev->node), "dsi"); 1351 if (id < 0) 1352 id = 0; 1353 1354 dsi->dev = dev; 1355 dsi->pdata = pdata; 1356 dsi->id = id; 1357 dsi->dual_channel = dev_read_bool(dsi->dev, "rockchip,dual-channel"); 1358 dsi->data_swap = dev_read_bool(dsi->dev, "rockchip,data-swap"); 1359 dsi->disable_hold_mode = dev_read_bool(dsi->dev, "disable-hold-mode"); 1360 1361 rockchip_connector_bind(&dsi->connector, dev, dsi->id, &dw_mipi_dsi_connector_funcs, NULL, 1362 DRM_MODE_CONNECTOR_DSI); 1363 1364 return 0; 1365 } 1366 1367 static const u32 px30_dsi_grf_reg_fields[MAX_FIELDS] = { 1368 [DPIUPDATECFG] = GRF_REG_FIELD(0x0434, 7, 7), 1369 [DPICOLORM] = GRF_REG_FIELD(0x0434, 3, 3), 1370 [DPISHUTDN] = GRF_REG_FIELD(0x0434, 2, 2), 1371 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0438, 7, 10), 1372 [TURNDISABLE] = GRF_REG_FIELD(0x0438, 5, 5), 1373 [VOPSEL] = GRF_REG_FIELD(0x0438, 0, 0), 1374 }; 1375 1376 static const struct dw_mipi_dsi_plat_data px30_mipi_dsi_plat_data = { 1377 .dsi0_grf_reg_fields = px30_dsi_grf_reg_fields, 1378 .max_bit_rate_per_lane = 1000000000UL, 1379 }; 1380 1381 static const u32 rk1808_dsi_grf_reg_fields[MAX_FIELDS] = { 1382 [MASTERSLAVEZ] = GRF_REG_FIELD(0x0440, 8, 8), 1383 [DPIUPDATECFG] = GRF_REG_FIELD(0x0440, 7, 7), 1384 [DPICOLORM] = GRF_REG_FIELD(0x0440, 3, 3), 1385 [DPISHUTDN] = GRF_REG_FIELD(0x0440, 2, 2), 1386 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0444, 7, 10), 1387 [FORCERXMODE] = GRF_REG_FIELD(0x0444, 6, 6), 1388 [TURNDISABLE] = GRF_REG_FIELD(0x0444, 5, 5), 1389 }; 1390 1391 static const struct dw_mipi_dsi_plat_data rk1808_mipi_dsi_plat_data = { 1392 .dsi0_grf_reg_fields = rk1808_dsi_grf_reg_fields, 1393 .max_bit_rate_per_lane = 2000000000UL, 1394 }; 1395 1396 static const u32 rk3128_dsi_grf_reg_fields[MAX_FIELDS] = { 1397 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0150, 10, 13), 1398 [FORCERXMODE] = GRF_REG_FIELD(0x0150, 9, 9), 1399 [TURNDISABLE] = GRF_REG_FIELD(0x0150, 8, 8), 1400 [DPICOLORM] = GRF_REG_FIELD(0x0150, 5, 5), 1401 [DPISHUTDN] = GRF_REG_FIELD(0x0150, 4, 4), 1402 }; 1403 1404 static const struct dw_mipi_dsi_plat_data rk3128_mipi_dsi_plat_data = { 1405 .dsi0_grf_reg_fields = rk3128_dsi_grf_reg_fields, 1406 .max_bit_rate_per_lane = 1000000000UL, 1407 }; 1408 1409 static const u32 rk3288_dsi0_grf_reg_fields[MAX_FIELDS] = { 1410 [DPICOLORM] = GRF_REG_FIELD(0x025c, 8, 8), 1411 [DPISHUTDN] = GRF_REG_FIELD(0x025c, 7, 7), 1412 [VOPSEL] = GRF_REG_FIELD(0x025c, 6, 6), 1413 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0264, 8, 11), 1414 [FORCERXMODE] = GRF_REG_FIELD(0x0264, 4, 7), 1415 [TURNDISABLE] = GRF_REG_FIELD(0x0264, 0, 3), 1416 [TURNREQUEST] = GRF_REG_FIELD(0x03a4, 8, 10), 1417 [DPIUPDATECFG] = GRF_REG_FIELD(0x03a8, 0, 0), 1418 }; 1419 1420 static const u32 rk3288_dsi1_grf_reg_fields[MAX_FIELDS] = { 1421 [DPICOLORM] = GRF_REG_FIELD(0x025c, 11, 11), 1422 [DPISHUTDN] = GRF_REG_FIELD(0x025c, 10, 10), 1423 [VOPSEL] = GRF_REG_FIELD(0x025c, 9, 9), 1424 [ENABLE_N] = GRF_REG_FIELD(0x0268, 12, 15), 1425 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0268, 8, 11), 1426 [FORCERXMODE] = GRF_REG_FIELD(0x0268, 4, 7), 1427 [TURNDISABLE] = GRF_REG_FIELD(0x0268, 0, 3), 1428 [BASEDIR] = GRF_REG_FIELD(0x027c, 15, 15), 1429 [MASTERSLAVEZ] = GRF_REG_FIELD(0x027c, 14, 14), 1430 [ENABLECLK] = GRF_REG_FIELD(0x027c, 12, 12), 1431 [TURNREQUEST] = GRF_REG_FIELD(0x03a4, 4, 7), 1432 [DPIUPDATECFG] = GRF_REG_FIELD(0x03a8, 1, 1), 1433 }; 1434 1435 static const struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_plat_data = { 1436 .dsi0_grf_reg_fields = rk3288_dsi0_grf_reg_fields, 1437 .dsi1_grf_reg_fields = rk3288_dsi1_grf_reg_fields, 1438 .max_bit_rate_per_lane = 1500000000UL, 1439 }; 1440 1441 static const u32 rk3366_dsi_grf_reg_fields[MAX_FIELDS] = { 1442 [VOPSEL] = GRF_REG_FIELD(0x0400, 2, 2), 1443 [DPIUPDATECFG] = GRF_REG_FIELD(0x0410, 9, 9), 1444 [DPICOLORM] = GRF_REG_FIELD(0x0410, 3, 3), 1445 [DPISHUTDN] = GRF_REG_FIELD(0x0410, 2, 2), 1446 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0414, 7, 10), 1447 [FORCERXMODE] = GRF_REG_FIELD(0x0414, 6, 6), 1448 [TURNDISABLE] = GRF_REG_FIELD(0x0414, 5, 5), 1449 }; 1450 1451 static const struct dw_mipi_dsi_plat_data rk3366_mipi_dsi_plat_data = { 1452 .dsi0_grf_reg_fields = rk3366_dsi_grf_reg_fields, 1453 .max_bit_rate_per_lane = 1000000000UL, 1454 }; 1455 1456 static const u32 rk3368_dsi_grf_reg_fields[MAX_FIELDS] = { 1457 [DPIUPDATECFG] = GRF_REG_FIELD(0x0418, 7, 7), 1458 [DPICOLORM] = GRF_REG_FIELD(0x0418, 3, 3), 1459 [DPISHUTDN] = GRF_REG_FIELD(0x0418, 2, 2), 1460 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x041c, 7, 10), 1461 [FORCERXMODE] = GRF_REG_FIELD(0x041c, 6, 6), 1462 [TURNDISABLE] = GRF_REG_FIELD(0x041c, 5, 5), 1463 }; 1464 1465 static const struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_plat_data = { 1466 .dsi0_grf_reg_fields = rk3368_dsi_grf_reg_fields, 1467 .max_bit_rate_per_lane = 1000000000UL, 1468 }; 1469 1470 static const u32 rk3399_dsi0_grf_reg_fields[MAX_FIELDS] = { 1471 [DPIUPDATECFG] = GRF_REG_FIELD(0x6224, 15, 15), 1472 [DPISHUTDN] = GRF_REG_FIELD(0x6224, 14, 14), 1473 [DPICOLORM] = GRF_REG_FIELD(0x6224, 13, 13), 1474 [VOPSEL] = GRF_REG_FIELD(0x6250, 0, 0), 1475 [TURNREQUEST] = GRF_REG_FIELD(0x6258, 12, 15), 1476 [TURNDISABLE] = GRF_REG_FIELD(0x6258, 8, 11), 1477 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x6258, 4, 7), 1478 [FORCERXMODE] = GRF_REG_FIELD(0x6258, 0, 3), 1479 }; 1480 1481 static const u32 rk3399_dsi1_grf_reg_fields[MAX_FIELDS] = { 1482 [VOPSEL] = GRF_REG_FIELD(0x6250, 4, 4), 1483 [DPIUPDATECFG] = GRF_REG_FIELD(0x6250, 3, 3), 1484 [DPISHUTDN] = GRF_REG_FIELD(0x6250, 2, 2), 1485 [DPICOLORM] = GRF_REG_FIELD(0x6250, 1, 1), 1486 [TURNDISABLE] = GRF_REG_FIELD(0x625c, 12, 15), 1487 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x625c, 8, 11), 1488 [FORCERXMODE] = GRF_REG_FIELD(0x625c, 4, 7), 1489 [ENABLE_N] = GRF_REG_FIELD(0x625c, 0, 3), 1490 [MASTERSLAVEZ] = GRF_REG_FIELD(0x6260, 7, 7), 1491 [ENABLECLK] = GRF_REG_FIELD(0x6260, 6, 6), 1492 [BASEDIR] = GRF_REG_FIELD(0x6260, 5, 5), 1493 [TURNREQUEST] = GRF_REG_FIELD(0x6260, 0, 3), 1494 }; 1495 1496 static const struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_plat_data = { 1497 .dsi0_grf_reg_fields = rk3399_dsi0_grf_reg_fields, 1498 .dsi1_grf_reg_fields = rk3399_dsi1_grf_reg_fields, 1499 .max_bit_rate_per_lane = 1500000000UL, 1500 }; 1501 1502 static const u32 rk3506_dsi_grf_reg_fields[MAX_FIELDS] = { 1503 [DPIUPDATECFG] = GRF_REG_FIELD(0x0014, 2, 2), 1504 [DPICOLORM] = GRF_REG_FIELD(0x0014, 1, 1), 1505 [DPISHUTDN] = GRF_REG_FIELD(0x0014, 0, 0), 1506 [SKEWCALHS] = GRF_REG_FIELD(0x0018, 11, 15), 1507 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0018, 4, 7), 1508 [TURNDISABLE] = GRF_REG_FIELD(0x0018, 2, 2), 1509 [FORCERXMODE] = GRF_REG_FIELD(0x0018, 0, 0), 1510 [ENABLE_N] = GRF_REG_FIELD(0x0018, 8, 9), 1511 }; 1512 1513 static const struct dw_mipi_dsi_plat_data rk3506_mipi_dsi_plat_data = { 1514 .dsi0_grf_reg_fields = rk3506_dsi_grf_reg_fields, 1515 .max_bit_rate_per_lane = 1500000000UL, 1516 }; 1517 1518 static const u32 rk3562_dsi_grf_reg_fields[MAX_FIELDS] = { 1519 [DPIUPDATECFG] = GRF_REG_FIELD(0x05d0, 2, 2), 1520 [DPICOLORM] = GRF_REG_FIELD(0x05d0, 1, 1), 1521 [DPISHUTDN] = GRF_REG_FIELD(0x05d0, 0, 0), 1522 [SKEWCALHS] = GRF_REG_FIELD(0x05d4, 11, 15), 1523 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x05d4, 4, 7), 1524 [TURNDISABLE] = GRF_REG_FIELD(0x05d4, 2, 2), 1525 [FORCERXMODE] = GRF_REG_FIELD(0x05d4, 0, 0), 1526 }; 1527 1528 static const struct dw_mipi_dsi_plat_data rk3562_mipi_dsi_plat_data = { 1529 .dsi0_grf_reg_fields = rk3562_dsi_grf_reg_fields, 1530 .max_bit_rate_per_lane = 1200000000UL, 1531 }; 1532 1533 static const u32 rk3568_dsi0_grf_reg_fields[MAX_FIELDS] = { 1534 [DPIUPDATECFG] = GRF_REG_FIELD(0x0360, 2, 2), 1535 [DPICOLORM] = GRF_REG_FIELD(0x0360, 1, 1), 1536 [DPISHUTDN] = GRF_REG_FIELD(0x0360, 0, 0), 1537 [SKEWCALHS] = GRF_REG_FIELD(0x0368, 11, 15), 1538 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0368, 4, 7), 1539 [TURNDISABLE] = GRF_REG_FIELD(0x0368, 2, 2), 1540 [FORCERXMODE] = GRF_REG_FIELD(0x0368, 0, 0), 1541 }; 1542 1543 static const u32 rk3568_dsi1_grf_reg_fields[MAX_FIELDS] = { 1544 [DPIUPDATECFG] = GRF_REG_FIELD(0x0360, 10, 10), 1545 [DPICOLORM] = GRF_REG_FIELD(0x0360, 9, 9), 1546 [DPISHUTDN] = GRF_REG_FIELD(0x0360, 8, 8), 1547 [SKEWCALHS] = GRF_REG_FIELD(0x036c, 11, 15), 1548 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x036c, 4, 7), 1549 [TURNDISABLE] = GRF_REG_FIELD(0x036c, 2, 2), 1550 [FORCERXMODE] = GRF_REG_FIELD(0x036c, 0, 0), 1551 }; 1552 1553 static const struct dw_mipi_dsi_plat_data rk3568_mipi_dsi_plat_data = { 1554 .dsi0_grf_reg_fields = rk3568_dsi0_grf_reg_fields, 1555 .dsi1_grf_reg_fields = rk3568_dsi1_grf_reg_fields, 1556 .max_bit_rate_per_lane = 1200000000UL, 1557 }; 1558 1559 static const u32 rv1108_dsi_grf_reg_fields[MAX_FIELDS] = { 1560 [DPICOLORM] = GRF_REG_FIELD(0x0410, 7, 7), 1561 [DPISHUTDN] = GRF_REG_FIELD(0x0410, 6, 6), 1562 [DPIUPDATECFG] = GRF_REG_FIELD(0x0410, 8, 8), 1563 [FORCERXMODE] = GRF_REG_FIELD(0x0414, 5, 5), 1564 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0414, 6, 9), 1565 [TURNDISABLE] = GRF_REG_FIELD(0x0414, 4, 4), 1566 }; 1567 1568 static const struct dw_mipi_dsi_plat_data rv1108_mipi_dsi_plat_data = { 1569 .dsi0_grf_reg_fields = rv1108_dsi_grf_reg_fields, 1570 .max_bit_rate_per_lane = 1000000000UL, 1571 }; 1572 1573 static const u32 rv1126_dsi_grf_reg_fields[MAX_FIELDS] = { 1574 [DPIUPDATECFG] = GRF_REG_FIELD(0x0008, 5, 5), 1575 [DPISHUTDN] = GRF_REG_FIELD(0x0008, 4, 4), 1576 [DPICOLORM] = GRF_REG_FIELD(0x0008, 3, 3), 1577 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x10220, 4, 7), 1578 [TURNDISABLE] = GRF_REG_FIELD(0x10220, 2, 2), 1579 [FORCERXMODE] = GRF_REG_FIELD(0x10220, 0, 0), 1580 }; 1581 1582 static const struct dw_mipi_dsi_plat_data rv1126_mipi_dsi_plat_data = { 1583 .dsi0_grf_reg_fields = rv1126_dsi_grf_reg_fields, 1584 .max_bit_rate_per_lane = 1000000000UL, 1585 }; 1586 1587 static const struct udevice_id dw_mipi_dsi_ids[] = { 1588 { 1589 .compatible = "rockchip,px30-mipi-dsi", 1590 .data = (ulong)&px30_mipi_dsi_plat_data, 1591 }, 1592 { 1593 .compatible = "rockchip,rk1808-mipi-dsi", 1594 .data = (ulong)&rk1808_mipi_dsi_plat_data, 1595 }, 1596 { 1597 .compatible = "rockchip,rk3128-mipi-dsi", 1598 .data = (ulong)&rk3128_mipi_dsi_plat_data, 1599 }, 1600 { 1601 .compatible = "rockchip,rk3288-mipi-dsi", 1602 .data = (ulong)&rk3288_mipi_dsi_plat_data, 1603 }, 1604 { 1605 .compatible = "rockchip,rk3366-mipi-dsi", 1606 .data = (ulong)&rk3366_mipi_dsi_plat_data, 1607 }, 1608 { 1609 .compatible = "rockchip,rk3368-mipi-dsi", 1610 .data = (ulong)&rk3368_mipi_dsi_plat_data, 1611 }, 1612 { 1613 .compatible = "rockchip,rk3399-mipi-dsi", 1614 .data = (ulong)&rk3399_mipi_dsi_plat_data, 1615 }, 1616 { 1617 .compatible = "rockchip,rk3506-mipi-dsi", 1618 .data = (ulong)&rk3506_mipi_dsi_plat_data, 1619 }, 1620 { 1621 .compatible = "rockchip,rk3562-mipi-dsi", 1622 .data = (ulong)&rk3562_mipi_dsi_plat_data, 1623 }, 1624 { 1625 .compatible = "rockchip,rk3568-mipi-dsi", 1626 .data = (ulong)&rk3568_mipi_dsi_plat_data, 1627 }, 1628 { 1629 .compatible = "rockchip,rv1108-mipi-dsi", 1630 .data = (ulong)&rv1108_mipi_dsi_plat_data, 1631 }, 1632 { 1633 .compatible = "rockchip,rv1126-mipi-dsi", 1634 .data = (ulong)&rv1126_mipi_dsi_plat_data, 1635 }, 1636 {} 1637 }; 1638 1639 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host, 1640 const struct mipi_dsi_msg *msg) 1641 { 1642 struct dw_mipi_dsi *dsi = dev_get_priv(host->dev); 1643 1644 return dw_mipi_dsi_transfer(dsi, msg); 1645 } 1646 1647 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 1648 struct mipi_dsi_device *device) 1649 { 1650 struct dw_mipi_dsi *dsi = dev_get_priv(host->dev); 1651 1652 if (device->lanes < 1 || device->lanes > 8) 1653 return -EINVAL; 1654 1655 dsi->lanes = device->lanes; 1656 dsi->channel = device->channel; 1657 dsi->format = device->format; 1658 dsi->mode_flags = device->mode_flags; 1659 1660 return 0; 1661 } 1662 1663 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = { 1664 .attach = dw_mipi_dsi_host_attach, 1665 .transfer = dw_mipi_dsi_host_transfer, 1666 }; 1667 1668 static int dw_mipi_dsi_bind(struct udevice *dev) 1669 { 1670 struct mipi_dsi_host *host = dev_get_platdata(dev); 1671 1672 host->dev = dev; 1673 host->ops = &dw_mipi_dsi_host_ops; 1674 1675 return dm_scan_fdt_dev(dev); 1676 } 1677 1678 static int dw_mipi_dsi_child_post_bind(struct udevice *dev) 1679 { 1680 struct mipi_dsi_host *host = dev_get_platdata(dev->parent); 1681 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1682 char name[20]; 1683 1684 sprintf(name, "%s.%d", host->dev->name, device->channel); 1685 device_set_name(dev, name); 1686 1687 device->dev = dev; 1688 device->host = host; 1689 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4); 1690 device->format = dev_read_u32_default(dev, "dsi,format", 1691 MIPI_DSI_FMT_RGB888); 1692 device->mode_flags = dev_read_u32_default(dev, "dsi,flags", 1693 MIPI_DSI_MODE_VIDEO | 1694 MIPI_DSI_MODE_VIDEO_BURST | 1695 MIPI_DSI_MODE_VIDEO_NO_HBP | 1696 MIPI_DSI_MODE_LPM | 1697 MIPI_DSI_MODE_NO_EOT_PACKET); 1698 device->channel = dev_read_u32_default(dev, "reg", 0); 1699 1700 return 0; 1701 } 1702 1703 static int dw_mipi_dsi_child_pre_probe(struct udevice *dev) 1704 { 1705 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1706 int ret; 1707 1708 ret = mipi_dsi_attach(device); 1709 if (ret) { 1710 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret); 1711 return ret; 1712 } 1713 1714 return 0; 1715 } 1716 1717 U_BOOT_DRIVER(dw_mipi_dsi) = { 1718 .name = "dw_mipi_dsi", 1719 .id = UCLASS_DISPLAY, 1720 .of_match = dw_mipi_dsi_ids, 1721 .probe = dw_mipi_dsi_probe, 1722 .bind = dw_mipi_dsi_bind, 1723 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi), 1724 .per_child_platdata_auto_alloc_size = sizeof(struct mipi_dsi_device), 1725 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_host), 1726 .child_post_bind = dw_mipi_dsi_child_post_bind, 1727 .child_pre_probe = dw_mipi_dsi_child_pre_probe, 1728 }; 1729