1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <drm/drm_mipi_dsi.h> 8 9 #include <config.h> 10 #include <common.h> 11 #include <errno.h> 12 #include <asm/unaligned.h> 13 #include <asm/io.h> 14 #include <asm/hardware.h> 15 #include <dm/device.h> 16 #include <dm/read.h> 17 #include <dm/of_access.h> 18 #include <syscon.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <linux/iopoll.h> 21 22 #include "rockchip_display.h" 23 #include "rockchip_crtc.h" 24 #include "rockchip_connector.h" 25 #include "rockchip_panel.h" 26 #include "rockchip_phy.h" 27 28 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) 29 30 #define DSI_VERSION 0x00 31 #define DSI_PWR_UP 0x04 32 #define RESET 0 33 #define POWERUP BIT(0) 34 35 #define DSI_CLKMGR_CFG 0x08 36 #define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) 37 #define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) 38 39 #define DSI_DPI_VCID 0x0c 40 #define DPI_VID(vid) (((vid) & 0x3) << 0) 41 42 #define DSI_DPI_COLOR_CODING 0x10 43 #define EN18_LOOSELY BIT(8) 44 #define DPI_COLOR_CODING_16BIT_1 0x0 45 #define DPI_COLOR_CODING_16BIT_2 0x1 46 #define DPI_COLOR_CODING_16BIT_3 0x2 47 #define DPI_COLOR_CODING_18BIT_1 0x3 48 #define DPI_COLOR_CODING_18BIT_2 0x4 49 #define DPI_COLOR_CODING_24BIT 0x5 50 51 #define DSI_DPI_CFG_POL 0x14 52 #define COLORM_ACTIVE_LOW BIT(4) 53 #define SHUTD_ACTIVE_LOW BIT(3) 54 #define HSYNC_ACTIVE_LOW BIT(2) 55 #define VSYNC_ACTIVE_LOW BIT(1) 56 #define DATAEN_ACTIVE_LOW BIT(0) 57 58 #define DSI_DPI_LP_CMD_TIM 0x18 59 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) 60 #define INVACT_LPCMD_TIME(p) ((p) & 0xff) 61 62 #define DSI_DBI_VCID 0x1c 63 #define DBI_VCID(x) UPDATE(x, 1, 0) 64 #define DSI_DBI_CFG 0x20 65 #define DSI_DBI_CMDSIZE 0x28 66 67 #define DSI_PCKHDL_CFG 0x2c 68 #define CRC_RX_EN BIT(4) 69 #define ECC_RX_EN BIT(3) 70 #define BTA_EN BIT(2) 71 #define EOTP_RX_EN BIT(1) 72 #define EOTP_TX_EN BIT(0) 73 #define DSI_MODE_CFG 0x34 74 #define CMD_VIDEO_MODE BIT(0) 75 #define COMMAND_MODE BIT(0) 76 #define VIDEO_MODE 0 77 #define DSI_VID_MODE_CFG 0x38 78 #define VPG_EN BIT(16) 79 #define LP_CMD_EN BIT(15) 80 #define FRAME_BTA_ACK BIT(14) 81 #define LP_HFP_EN BIT(13) 82 #define LP_HBP_EN BIT(12) 83 #define LP_VACT_EN BIT(11) 84 #define LP_VFP_EN BIT(10) 85 #define LP_VBP_EN BIT(9) 86 #define LP_VSA_EN BIT(8) 87 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0 88 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1 89 #define VID_MODE_TYPE_BURST 0x2 90 91 #define DSI_VID_PKT_SIZE 0x3c 92 #define VID_PKT_SIZE(p) (((p) & 0x3fff) << 0) 93 #define VID_PKT_MAX_SIZE 0x3fff 94 95 #define DSI_VID_NUM_CHUMKS 0x40 96 #define DSI_VID_NULL_PKT_SIZE 0x44 97 #define DSI_VID_HSA_TIME 0x48 98 #define DSI_VID_HBP_TIME 0x4c 99 #define DSI_VID_HLINE_TIME 0x50 100 #define DSI_VID_VSA_LINES 0x54 101 #define DSI_VID_VBP_LINES 0x58 102 #define DSI_VID_VFP_LINES 0x5c 103 #define DSI_VID_VACTIVE_LINES 0x60 104 #define DSI_EDPI_CMD_SIZE 0x64 105 #define DSI_CMD_MODE_CFG 0x68 106 #define MAX_RD_PKT_SIZE BIT(24) 107 #define DCS_LW_TX BIT(19) 108 #define DCS_SR_0P_TX BIT(18) 109 #define DCS_SW_1P_TX BIT(17) 110 #define DCS_SW_0P_TX BIT(16) 111 #define GEN_LW_TX BIT(14) 112 #define GEN_SR_2P_TX BIT(13) 113 #define GEN_SR_1P_TX BIT(12) 114 #define GEN_SR_0P_TX BIT(11) 115 #define GEN_SW_2P_TX BIT(10) 116 #define GEN_SW_1P_TX BIT(9) 117 #define GEN_SW_0P_TX BIT(8) 118 #define ACK_RQST_EN BIT(1) 119 #define TEAR_FX_EN BIT(0) 120 121 #define DSI_GEN_HDR 0x6c 122 #define GEN_HDATA(data) (((data) & 0xffff) << 8) 123 #define GEN_HDATA_MASK (0xffff << 8) 124 #define GEN_HTYPE(type) (((type) & 0xff) << 0) 125 #define GEN_HTYPE_MASK 0xff 126 127 #define DSI_GEN_PLD_DATA 0x70 128 129 #define DSI_CMD_PKT_STATUS 0x74 130 #define GEN_CMD_EMPTY BIT(0) 131 #define GEN_CMD_FULL BIT(1) 132 #define GEN_PLD_W_EMPTY BIT(2) 133 #define GEN_PLD_W_FULL BIT(3) 134 #define GEN_PLD_R_EMPTY BIT(4) 135 #define GEN_PLD_R_FULL BIT(5) 136 #define GEN_RD_CMD_BUSY BIT(6) 137 138 #define DSI_TO_CNT_CFG 0x78 139 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16) 140 #define LPRX_TO_CNT(p) ((p) & 0xffff) 141 142 #define DSI_BTA_TO_CNT 0x8c 143 #define DSI_LPCLK_CTRL 0x94 144 #define AUTO_CLKLANE_CTRL BIT(1) 145 #define PHY_TXREQUESTCLKHS BIT(0) 146 147 #define DSI_PHY_TMR_LPCLK_CFG 0x98 148 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16) 149 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff) 150 151 #define DSI_PHY_TMR_CFG 0x9c 152 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24) 153 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16) 154 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff) 155 156 #define DSI_PHY_RSTZ 0xa0 157 #define PHY_ENFORCEPLL BIT(3) 158 #define PHY_ENABLECLK BIT(2) 159 #define PHY_RSTZ BIT(1) 160 #define PHY_SHUTDOWNZ BIT(0) 161 162 #define DSI_PHY_IF_CFG 0xa4 163 #define N_LANES(n) ((((n) - 1) & 0x3) << 0) 164 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 165 166 #define DSI_PHY_STATUS 0xb0 167 #define PHY_STOPSTATE0LANE BIT(4) 168 #define PHY_STOPSTATECLKLANE BIT(2) 169 #define PHY_LOCK BIT(0) 170 #define PHY_STOPSTATELANE (PHY_STOPSTATE0LANE | \ 171 PHY_STOPSTATECLKLANE) 172 173 #define DSI_PHY_TST_CTRL0 0xb4 174 #define PHY_TESTCLK BIT(1) 175 #define PHY_TESTCLR BIT(0) 176 177 #define DSI_PHY_TST_CTRL1 0xb8 178 #define PHY_TESTEN BIT(16) 179 #define PHY_TESTDOUT_SHIFT 8 180 #define PHY_TESTDIN_MASK GENMASK(7, 0) 181 #define PHY_TESTDIN(x) UPDATE(x, 7, 0) 182 183 #define DSI_INT_ST0 0xbc 184 #define DSI_INT_ST1 0xc0 185 #define DSI_INT_MSK0 0xc4 186 #define DSI_INT_MSK1 0xc8 187 188 #define PHY_STATUS_TIMEOUT_US 10000 189 #define CMD_PKT_STATUS_TIMEOUT_US 20000 190 191 /* Test Code: 0x44 (HS RX Control of Lane 0) */ 192 #define HSFREQRANGE(x) UPDATE(x, 6, 1) 193 /* Test Code: 0x17 (PLL Input Divider Ratio) */ 194 #define INPUT_DIV(x) UPDATE(x, 6, 0) 195 /* Test Code: 0x18 (PLL Loop Divider Ratio) */ 196 #define FEEDBACK_DIV_LO(x) UPDATE(x, 4, 0) 197 #define FEEDBACK_DIV_HI(x) (BIT(7) | UPDATE(x, 3, 0)) 198 199 #define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 10) | ((lsb) << 5) | (msb)) 200 201 enum grf_reg_fields { 202 DPIUPDATECFG, 203 DPISHUTDN, 204 DPICOLORM, 205 VOPSEL, 206 TURNREQUEST, 207 TURNDISABLE, 208 SKEWCALHS, 209 FORCETXSTOPMODE, 210 FORCERXMODE, 211 ENABLE_N, 212 MASTERSLAVEZ, 213 ENABLECLK, 214 BASEDIR, 215 MAX_FIELDS, 216 }; 217 218 struct dw_mipi_dsi_plat_data { 219 const u32 *dsi0_grf_reg_fields; 220 const u32 *dsi1_grf_reg_fields; 221 unsigned long max_bit_rate_per_lane; 222 }; 223 224 struct mipi_dphy { 225 /* Non-SNPS PHY */ 226 struct rockchip_phy *phy; 227 228 u16 input_div; 229 u16 feedback_div; 230 }; 231 232 struct dw_mipi_dsi { 233 struct rockchip_connector connector; 234 struct udevice *dev; 235 void *base; 236 void *grf; 237 int id; 238 struct dw_mipi_dsi *master; 239 struct dw_mipi_dsi *slave; 240 bool prepared; 241 242 unsigned int lane_mbps; /* per lane */ 243 u32 channel; 244 u32 lanes; 245 u32 format; 246 u32 mode_flags; 247 struct mipi_dphy dphy; 248 struct drm_display_mode mode; 249 bool data_swap; 250 251 const struct dw_mipi_dsi_plat_data *pdata; 252 }; 253 254 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) 255 { 256 writel(val, dsi->base + reg); 257 } 258 259 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) 260 { 261 return readl(dsi->base + reg); 262 } 263 264 static inline void dsi_update_bits(struct dw_mipi_dsi *dsi, 265 u32 reg, u32 mask, u32 val) 266 { 267 u32 orig, tmp; 268 269 orig = dsi_read(dsi, reg); 270 tmp = orig & ~mask; 271 tmp |= val & mask; 272 dsi_write(dsi, reg, tmp); 273 } 274 275 static void grf_field_write(struct dw_mipi_dsi *dsi, enum grf_reg_fields index, 276 unsigned int val) 277 { 278 const u32 field = dsi->id ? dsi->pdata->dsi1_grf_reg_fields[index] : 279 dsi->pdata->dsi0_grf_reg_fields[index]; 280 u16 reg; 281 u8 msb, lsb; 282 283 if (!field) 284 return; 285 286 reg = (field >> 10) & 0x3ffff; 287 lsb = (field >> 5) & 0x1f; 288 msb = (field >> 0) & 0x1f; 289 290 rk_clrsetreg(dsi->grf + reg, GENMASK(msb, lsb), val << lsb); 291 } 292 293 static inline void dpishutdn_assert(struct dw_mipi_dsi *dsi) 294 { 295 grf_field_write(dsi, DPISHUTDN, 1); 296 } 297 298 static inline void dpishutdn_deassert(struct dw_mipi_dsi *dsi) 299 { 300 grf_field_write(dsi, DPISHUTDN, 0); 301 } 302 303 static int genif_wait_w_pld_fifo_not_full(struct dw_mipi_dsi *dsi) 304 { 305 u32 sts; 306 int ret; 307 308 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 309 sts, !(sts & GEN_PLD_W_FULL), 310 CMD_PKT_STATUS_TIMEOUT_US); 311 if (ret < 0) { 312 printf("generic write payload fifo is full\n"); 313 return ret; 314 } 315 316 return 0; 317 } 318 319 static int genif_wait_cmd_fifo_not_full(struct dw_mipi_dsi *dsi) 320 { 321 u32 sts; 322 int ret; 323 324 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 325 sts, !(sts & GEN_CMD_FULL), 326 CMD_PKT_STATUS_TIMEOUT_US); 327 if (ret < 0) { 328 printf("generic write cmd fifo is full\n"); 329 return ret; 330 } 331 332 return 0; 333 } 334 335 static int genif_wait_write_fifo_empty(struct dw_mipi_dsi *dsi) 336 { 337 u32 sts; 338 u32 mask; 339 int ret; 340 341 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 342 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 343 sts, (sts & mask) == mask, 344 CMD_PKT_STATUS_TIMEOUT_US); 345 if (ret < 0) { 346 printf("generic write fifo is full\n"); 347 return ret; 348 } 349 350 return 0; 351 } 352 353 static inline void mipi_dphy_enableclk_assert(struct dw_mipi_dsi *dsi) 354 { 355 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK); 356 udelay(1); 357 } 358 359 static inline void mipi_dphy_enableclk_deassert(struct dw_mipi_dsi *dsi) 360 { 361 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, 0); 362 udelay(1); 363 } 364 365 static inline void mipi_dphy_shutdownz_assert(struct dw_mipi_dsi *dsi) 366 { 367 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, 0); 368 udelay(1); 369 } 370 371 static inline void mipi_dphy_shutdownz_deassert(struct dw_mipi_dsi *dsi) 372 { 373 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, PHY_SHUTDOWNZ); 374 udelay(1); 375 } 376 377 static inline void mipi_dphy_rstz_assert(struct dw_mipi_dsi *dsi) 378 { 379 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, 0); 380 udelay(1); 381 } 382 383 static inline void mipi_dphy_rstz_deassert(struct dw_mipi_dsi *dsi) 384 { 385 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, PHY_RSTZ); 386 udelay(1); 387 } 388 389 static inline void testif_testclk_assert(struct dw_mipi_dsi *dsi) 390 { 391 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK); 392 udelay(1); 393 } 394 395 static inline void testif_testclk_deassert(struct dw_mipi_dsi *dsi) 396 { 397 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK, 0); 398 udelay(1); 399 } 400 401 static inline void testif_testclr_assert(struct dw_mipi_dsi *dsi) 402 { 403 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR, PHY_TESTCLR); 404 udelay(1); 405 } 406 407 static inline void testif_testclr_deassert(struct dw_mipi_dsi *dsi) 408 { 409 dsi_update_bits(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR, 0); 410 udelay(1); 411 } 412 413 static inline void testif_testen_assert(struct dw_mipi_dsi *dsi) 414 { 415 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN, PHY_TESTEN); 416 udelay(1); 417 } 418 419 static inline void testif_testen_deassert(struct dw_mipi_dsi *dsi) 420 { 421 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN, 0); 422 udelay(1); 423 } 424 425 static inline void testif_set_data(struct dw_mipi_dsi *dsi, u8 data) 426 { 427 dsi_update_bits(dsi, DSI_PHY_TST_CTRL1, 428 PHY_TESTDIN_MASK, PHY_TESTDIN(data)); 429 udelay(1); 430 } 431 432 static inline u8 testif_get_data(struct dw_mipi_dsi *dsi) 433 { 434 return dsi_read(dsi, DSI_PHY_TST_CTRL1) >> PHY_TESTDOUT_SHIFT; 435 } 436 437 static void testif_test_code_write(struct dw_mipi_dsi *dsi, u8 test_code) 438 { 439 testif_testclk_assert(dsi); 440 testif_set_data(dsi, test_code); 441 testif_testen_assert(dsi); 442 testif_testclk_deassert(dsi); 443 testif_testen_deassert(dsi); 444 } 445 446 static void testif_test_data_write(struct dw_mipi_dsi *dsi, u8 test_data) 447 { 448 testif_testclk_deassert(dsi); 449 testif_set_data(dsi, test_data); 450 testif_testclk_assert(dsi); 451 } 452 453 static void testif_write(struct dw_mipi_dsi *dsi, u8 test_code, u8 test_data) 454 { 455 testif_test_code_write(dsi, test_code); 456 testif_test_data_write(dsi, test_data); 457 458 dev_dbg(dsi->dev, 459 "test_code=0x%02x, test_data=0x%02x, monitor_data=0x%02x\n", 460 test_code, test_data, testif_get_data(dsi)); 461 } 462 463 static int mipi_dphy_power_on(struct dw_mipi_dsi *dsi) 464 { 465 u32 mask, val; 466 int ret; 467 468 mipi_dphy_shutdownz_deassert(dsi); 469 mipi_dphy_rstz_deassert(dsi); 470 mdelay(2); 471 472 if (dsi->dphy.phy) { 473 rockchip_phy_set_mode(dsi->dphy.phy, PHY_MODE_MIPI_DPHY); 474 rockchip_phy_power_on(dsi->dphy.phy); 475 } 476 477 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 478 val, val & PHY_LOCK, PHY_STATUS_TIMEOUT_US); 479 if (ret < 0) { 480 dev_err(dsi->dev, "PHY is not locked\n"); 481 return ret; 482 } 483 484 udelay(200); 485 486 mask = PHY_STOPSTATELANE; 487 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 488 val, (val & mask) == mask, 489 PHY_STATUS_TIMEOUT_US); 490 if (ret < 0) { 491 dev_err(dsi->dev, "lane module is not in stop state\n"); 492 return ret; 493 } 494 495 udelay(10); 496 497 return 0; 498 } 499 500 static void dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) 501 { 502 /* Table 5-1 Frequency Ranges */ 503 const struct { 504 unsigned long max_lane_mbps; 505 u8 hsfreqrange; 506 } hsfreqrange_table[] = { 507 { 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01}, 508 { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12}, 509 { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23}, 510 { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15}, 511 { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07}, 512 { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09}, 513 { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a}, 514 {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b}, 515 {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c}, 516 {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c} 517 }; 518 u8 hsfreqrange, counter; 519 unsigned int index, txbyteclkhs; 520 u16 n, m; 521 522 for (index = 0; index < ARRAY_SIZE(hsfreqrange_table); index++) 523 if (dsi->lane_mbps <= hsfreqrange_table[index].max_lane_mbps) 524 break; 525 526 if (index == ARRAY_SIZE(hsfreqrange_table)) 527 --index; 528 529 hsfreqrange = hsfreqrange_table[index].hsfreqrange; 530 testif_write(dsi, 0x44, HSFREQRANGE(hsfreqrange)); 531 532 txbyteclkhs = dsi->lane_mbps >> 3; 533 counter = txbyteclkhs * 60 / 1000; 534 testif_write(dsi, 0x60, 0x80 | counter); 535 testif_write(dsi, 0x70, 0x80 | counter); 536 537 n = dsi->dphy.input_div - 1; 538 m = dsi->dphy.feedback_div - 1; 539 testif_write(dsi, 0x19, 0x30); 540 testif_write(dsi, 0x17, INPUT_DIV(n)); 541 testif_write(dsi, 0x18, FEEDBACK_DIV_LO(m)); 542 testif_write(dsi, 0x18, FEEDBACK_DIV_HI(m >> 5)); 543 } 544 545 static unsigned long dw_mipi_dsi_get_lane_rate(struct dw_mipi_dsi *dsi) 546 { 547 const struct drm_display_mode *mode = &dsi->mode; 548 unsigned long max_lane_rate = dsi->pdata->max_bit_rate_per_lane; 549 unsigned long lane_rate; 550 unsigned int value; 551 int bpp, lanes; 552 u64 tmp; 553 554 /* optional override of the desired bandwidth */ 555 value = dev_read_u32_default(dsi->dev, "rockchip,lane-rate", 0); 556 if (value > 0) 557 return value * 1000 * 1000; 558 559 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 560 if (bpp < 0) 561 bpp = 24; 562 563 lanes = dsi->slave ? dsi->lanes * 2 : dsi->lanes; 564 tmp = (u64)mode->clock * 1000 * bpp; 565 do_div(tmp, lanes); 566 567 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */ 568 tmp *= 10; 569 do_div(tmp, 9); 570 571 if (tmp > max_lane_rate) 572 lane_rate = max_lane_rate; 573 else 574 lane_rate = tmp; 575 576 return lane_rate; 577 } 578 579 static void dw_mipi_dsi_set_pll(struct dw_mipi_dsi *dsi, unsigned long rate) 580 { 581 unsigned long fin, fout; 582 unsigned long fvco_min, fvco_max, best_freq = 984000000; 583 u8 min_prediv, max_prediv; 584 u8 _prediv, best_prediv = 2; 585 u16 _fbdiv, best_fbdiv = 82; 586 u32 min_delta = ~0U; 587 588 fin = 24000000; 589 fout = rate; 590 591 /* 5Mhz < Fref / N < 40MHz, 80MHz < Fvco < 1500Mhz */ 592 min_prediv = DIV_ROUND_UP(fin, 40000000); 593 max_prediv = fin / 5000000; 594 fvco_min = 80000000; 595 fvco_max = 1500000000; 596 597 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 598 u64 tmp, _fout; 599 u32 delta; 600 601 /* Fvco = Fref * M / N */ 602 tmp = (u64)fout * _prediv; 603 do_div(tmp, fin); 604 _fbdiv = tmp; 605 606 /* 607 * Due to the use of a "by 2 pre-scaler," the range of the 608 * feedback multiplication value M is limited to even division 609 * numbers, and m must be greater than 12, less than 1000. 610 */ 611 if (_fbdiv <= 12 || _fbdiv >= 1000) 612 continue; 613 614 if (_fbdiv % 2) 615 ++_fbdiv; 616 617 _fout = (u64)_fbdiv * fin; 618 do_div(_fout, _prediv); 619 620 if (_fout < fvco_min || _fout > fvco_max) 621 continue; 622 623 delta = abs(fout - _fout); 624 if (!delta) { 625 best_prediv = _prediv; 626 best_fbdiv = _fbdiv; 627 best_freq = _fout; 628 break; 629 } else if (delta < min_delta) { 630 best_prediv = _prediv; 631 best_fbdiv = _fbdiv; 632 best_freq = _fout; 633 min_delta = delta; 634 } 635 } 636 637 dsi->lane_mbps = best_freq / 1000 / 1000; 638 dsi->dphy.input_div = best_prediv; 639 dsi->dphy.feedback_div = best_fbdiv; 640 if (dsi->slave) { 641 dsi->slave->lane_mbps = dsi->lane_mbps; 642 dsi->slave->dphy.input_div = dsi->dphy.input_div; 643 dsi->slave->dphy.feedback_div = dsi->dphy.feedback_div; 644 } 645 if (dsi->master) { 646 dsi->master->lane_mbps = dsi->lane_mbps; 647 dsi->master->dphy.input_div = dsi->dphy.input_div; 648 dsi->master->dphy.feedback_div = dsi->dphy.feedback_div; 649 } 650 } 651 652 static int dw_mipi_dsi_read_from_fifo(struct dw_mipi_dsi *dsi, 653 const struct mipi_dsi_msg *msg) 654 { 655 u8 *payload = msg->rx_buf; 656 u16 length; 657 u32 val; 658 int ret; 659 660 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 661 val, !(val & GEN_RD_CMD_BUSY), 5000); 662 if (ret) { 663 printf("entire response isn't stored in the FIFO\n"); 664 return ret; 665 } 666 667 /* Receive payload */ 668 for (length = msg->rx_len; length; length -= 4) { 669 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 670 val, !(val & GEN_PLD_R_EMPTY), 5000); 671 if (ret) { 672 printf("Read payload FIFO is empty\n"); 673 return ret; 674 } 675 676 val = dsi_read(dsi, DSI_GEN_PLD_DATA); 677 678 switch (length) { 679 case 3: 680 payload[2] = (val >> 16) & 0xff; 681 /* Fall through */ 682 case 2: 683 payload[1] = (val >> 8) & 0xff; 684 /* Fall through */ 685 case 1: 686 payload[0] = val & 0xff; 687 return 0; 688 } 689 690 payload[0] = (val >> 0) & 0xff; 691 payload[1] = (val >> 8) & 0xff; 692 payload[2] = (val >> 16) & 0xff; 693 payload[3] = (val >> 24) & 0xff; 694 payload += 4; 695 } 696 697 return 0; 698 } 699 700 static int dw_mipi_dsi_turn_on_peripheral(struct dw_mipi_dsi *dsi) 701 { 702 dpishutdn_assert(dsi); 703 udelay(20); 704 dpishutdn_deassert(dsi); 705 706 return 0; 707 } 708 709 static int dw_mipi_dsi_shutdown_peripheral(struct dw_mipi_dsi *dsi) 710 { 711 dpishutdn_deassert(dsi); 712 udelay(20); 713 dpishutdn_assert(dsi); 714 715 return 0; 716 } 717 718 static ssize_t dw_mipi_dsi_transfer(struct dw_mipi_dsi *dsi, 719 const struct mipi_dsi_msg *msg) 720 { 721 struct mipi_dsi_packet packet; 722 int ret; 723 int val; 724 725 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { 726 dsi_update_bits(dsi, DSI_VID_MODE_CFG, LP_CMD_EN, LP_CMD_EN); 727 dsi_update_bits(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS, 0); 728 } else { 729 dsi_update_bits(dsi, DSI_VID_MODE_CFG, LP_CMD_EN, 0); 730 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 731 PHY_TXREQUESTCLKHS, PHY_TXREQUESTCLKHS); 732 } 733 734 switch (msg->type) { 735 case MIPI_DSI_SHUTDOWN_PERIPHERAL: 736 return dw_mipi_dsi_shutdown_peripheral(dsi); 737 case MIPI_DSI_TURN_ON_PERIPHERAL: 738 return dw_mipi_dsi_turn_on_peripheral(dsi); 739 case MIPI_DSI_DCS_SHORT_WRITE: 740 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_0P_TX, 741 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 742 DCS_SW_0P_TX : 0); 743 break; 744 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 745 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_1P_TX, 746 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 747 DCS_SW_1P_TX : 0); 748 break; 749 case MIPI_DSI_DCS_LONG_WRITE: 750 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX, 751 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 752 DCS_LW_TX : 0); 753 break; 754 case MIPI_DSI_DCS_READ: 755 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SR_0P_TX, 756 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 757 DCS_SR_0P_TX : 0); 758 break; 759 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: 760 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, MAX_RD_PKT_SIZE, 761 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 762 MAX_RD_PKT_SIZE : 0); 763 break; 764 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 765 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_0P_TX, 766 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 767 GEN_SW_0P_TX : 0); 768 break; 769 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 770 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_1P_TX, 771 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 772 GEN_SW_1P_TX : 0); 773 break; 774 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 775 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_2P_TX, 776 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 777 GEN_SW_2P_TX : 0); 778 break; 779 case MIPI_DSI_GENERIC_LONG_WRITE: 780 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_LW_TX, 781 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 782 GEN_LW_TX : 0); 783 break; 784 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 785 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_0P_TX, 786 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 787 GEN_SR_0P_TX : 0); 788 break; 789 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 790 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_1P_TX, 791 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 792 GEN_SR_1P_TX : 0); 793 break; 794 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 795 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_2P_TX, 796 dsi->mode_flags & MIPI_DSI_MODE_LPM ? 797 GEN_SR_2P_TX : 0); 798 break; 799 default: 800 return -EINVAL; 801 } 802 803 if (msg->flags & MIPI_DSI_MSG_REQ_ACK) 804 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, 805 ACK_RQST_EN, ACK_RQST_EN); 806 807 /* create a packet to the DSI protocol */ 808 ret = mipi_dsi_create_packet(&packet, msg); 809 if (ret) { 810 printf("failed to create packet: %d\n", ret); 811 return ret; 812 } 813 814 /* Send payload */ 815 while (DIV_ROUND_UP(packet.payload_length, 4)) { 816 /* 817 * Alternatively, you can always keep the FIFO 818 * nearly full by monitoring the FIFO state until 819 * it is not full, and then writea single word of data. 820 * This solution is more resource consuming 821 * but it simultaneously avoids FIFO starvation, 822 * making it possible to use FIFO sizes smaller than 823 * the amount of data of the longest packet to be written. 824 */ 825 ret = genif_wait_w_pld_fifo_not_full(dsi); 826 if (ret) 827 return ret; 828 829 if (packet.payload_length < 4) { 830 /* send residu payload */ 831 val = 0; 832 memcpy(&val, packet.payload, packet.payload_length); 833 dsi_write(dsi, DSI_GEN_PLD_DATA, val); 834 packet.payload_length = 0; 835 } else { 836 val = get_unaligned_le32(packet.payload); 837 dsi_write(dsi, DSI_GEN_PLD_DATA, val); 838 packet.payload += 4; 839 packet.payload_length -= 4; 840 } 841 } 842 843 ret = genif_wait_cmd_fifo_not_full(dsi); 844 if (ret) 845 return ret; 846 847 /* Send packet header */ 848 val = get_unaligned_le32(packet.header); 849 dsi_write(dsi, DSI_GEN_HDR, val); 850 851 ret = genif_wait_write_fifo_empty(dsi); 852 if (ret) 853 return ret; 854 855 if (msg->rx_len) { 856 ret = dw_mipi_dsi_read_from_fifo(dsi, msg); 857 if (ret < 0) 858 return ret; 859 } 860 861 if (dsi->slave) { 862 ret = dw_mipi_dsi_transfer(dsi->slave, msg); 863 if (ret < 0) 864 return ret; 865 } 866 867 return msg->rx_len ? msg->rx_len : msg->tx_len; 868 } 869 870 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) 871 { 872 u32 val = LP_VACT_EN | LP_VFP_EN | LP_VBP_EN | LP_VSA_EN | 873 LP_HFP_EN | LP_HBP_EN; 874 875 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) 876 val &= ~LP_HFP_EN; 877 878 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) 879 val &= ~LP_HBP_EN; 880 881 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 882 val |= VID_MODE_TYPE_BURST; 883 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 884 val |= VID_MODE_TYPE_BURST_SYNC_PULSES; 885 else 886 val |= VID_MODE_TYPE_BURST_SYNC_EVENTS; 887 888 dsi_write(dsi, DSI_VID_MODE_CFG, val); 889 890 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 891 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 892 AUTO_CLKLANE_CTRL, AUTO_CLKLANE_CTRL); 893 } 894 895 static void dw_mipi_dsi_enable(struct dw_mipi_dsi *dsi) 896 { 897 const struct drm_display_mode *mode = &dsi->mode; 898 899 dsi_update_bits(dsi, DSI_LPCLK_CTRL, 900 PHY_TXREQUESTCLKHS, PHY_TXREQUESTCLKHS); 901 902 dsi_write(dsi, DSI_PWR_UP, RESET); 903 904 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 905 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, VIDEO_MODE); 906 } else { 907 dsi_write(dsi, DSI_DBI_VCID, DBI_VCID(dsi->channel)); 908 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX, 0); 909 dsi_write(dsi, DSI_EDPI_CMD_SIZE, mode->hdisplay); 910 dsi_update_bits(dsi, DSI_MODE_CFG, 911 CMD_VIDEO_MODE, COMMAND_MODE); 912 } 913 914 dsi_write(dsi, DSI_PWR_UP, POWERUP); 915 916 if (dsi->slave) 917 dw_mipi_dsi_enable(dsi->slave); 918 } 919 920 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) 921 { 922 dsi_write(dsi, DSI_PWR_UP, RESET); 923 dsi_write(dsi, DSI_LPCLK_CTRL, 0); 924 dsi_write(dsi, DSI_EDPI_CMD_SIZE, 0); 925 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, COMMAND_MODE); 926 dsi_write(dsi, DSI_PWR_UP, POWERUP); 927 928 if (dsi->slave) 929 dw_mipi_dsi_disable(dsi->slave); 930 } 931 932 static void dw_mipi_dsi_post_disable(struct dw_mipi_dsi *dsi) 933 { 934 if (!dsi->prepared) 935 return; 936 937 if (dsi->master) 938 dw_mipi_dsi_post_disable(dsi->master); 939 940 dsi_write(dsi, DSI_PWR_UP, RESET); 941 dsi_write(dsi, DSI_PHY_RSTZ, 0); 942 943 if (dsi->dphy.phy) 944 rockchip_phy_power_off(dsi->dphy.phy); 945 946 dsi->prepared = false; 947 948 if (dsi->slave) 949 dw_mipi_dsi_post_disable(dsi->slave); 950 } 951 952 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) 953 { 954 u32 esc_clk_div; 955 956 dsi_write(dsi, DSI_PWR_UP, RESET); 957 958 /* The maximum value of the escape clock frequency is 20MHz */ 959 esc_clk_div = DIV_ROUND_UP(dsi->lane_mbps >> 3, 20); 960 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) | 961 TX_ESC_CLK_DIVIDSION(esc_clk_div)); 962 } 963 964 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, 965 struct drm_display_mode *mode) 966 { 967 u32 val = 0, color = 0; 968 969 switch (dsi->format) { 970 case MIPI_DSI_FMT_RGB888: 971 color = DPI_COLOR_CODING_24BIT; 972 break; 973 case MIPI_DSI_FMT_RGB666: 974 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY; 975 break; 976 case MIPI_DSI_FMT_RGB666_PACKED: 977 color = DPI_COLOR_CODING_18BIT_1; 978 break; 979 case MIPI_DSI_FMT_RGB565: 980 color = DPI_COLOR_CODING_16BIT_1; 981 break; 982 } 983 984 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 985 val |= VSYNC_ACTIVE_LOW; 986 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 987 val |= HSYNC_ACTIVE_LOW; 988 989 dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel)); 990 dsi_write(dsi, DSI_DPI_COLOR_CODING, color); 991 dsi_write(dsi, DSI_DPI_CFG_POL, val); 992 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4) 993 | INVACT_LPCMD_TIME(4)); 994 } 995 996 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi) 997 { 998 u32 val = CRC_RX_EN | ECC_RX_EN | BTA_EN | EOTP_TX_EN; 999 1000 if (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 1001 val &= ~EOTP_TX_EN; 1002 1003 dsi_write(dsi, DSI_PCKHDL_CFG, val); 1004 } 1005 1006 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, 1007 struct drm_display_mode *mode) 1008 { 1009 dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay)); 1010 } 1011 1012 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) 1013 { 1014 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000)); 1015 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); 1016 } 1017 1018 /* Get lane byte clock cycles. */ 1019 static int dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, 1020 u32 hcomponent) 1021 { 1022 u32 lbcc; 1023 1024 lbcc = hcomponent * dsi->lane_mbps * 1000 / 8; 1025 1026 if (!dsi->mode.clock) 1027 return 0; 1028 1029 return DIV_ROUND_CLOSEST(lbcc, dsi->mode.clock); 1030 } 1031 1032 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi) 1033 { 1034 int htotal, hsa, hbp, lbcc; 1035 struct drm_display_mode *mode = &dsi->mode; 1036 1037 htotal = mode->htotal; 1038 hsa = mode->hsync_end - mode->hsync_start; 1039 hbp = mode->htotal - mode->hsync_end; 1040 1041 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal); 1042 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); 1043 1044 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa); 1045 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); 1046 1047 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp); 1048 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); 1049 } 1050 1051 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi) 1052 { 1053 u32 vactive, vsa, vfp, vbp; 1054 struct drm_display_mode *mode = &dsi->mode; 1055 1056 vactive = mode->vdisplay; 1057 vsa = mode->vsync_end - mode->vsync_start; 1058 vfp = mode->vsync_start - mode->vdisplay; 1059 vbp = mode->vtotal - mode->vsync_end; 1060 1061 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); 1062 dsi_write(dsi, DSI_VID_VSA_LINES, vsa); 1063 dsi_write(dsi, DSI_VID_VFP_LINES, vfp); 1064 dsi_write(dsi, DSI_VID_VBP_LINES, vbp); 1065 } 1066 1067 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) 1068 { 1069 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14) 1070 | PHY_LP2HS_TIME(0x10) | MAX_RD_TIME(10000)); 1071 1072 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40) 1073 | PHY_CLKLP2HS_TIME(0x40)); 1074 } 1075 1076 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) 1077 { 1078 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) | 1079 N_LANES(dsi->lanes)); 1080 } 1081 1082 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) 1083 { 1084 dsi_read(dsi, DSI_INT_ST0); 1085 dsi_read(dsi, DSI_INT_ST1); 1086 dsi_write(dsi, DSI_INT_MSK0, 0); 1087 dsi_write(dsi, DSI_INT_MSK1, 0); 1088 } 1089 1090 static int dw_mipi_dsi_connector_init(struct rockchip_connector *conn, struct display_state *state) 1091 { 1092 struct connector_state *conn_state = &state->conn_state; 1093 struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev); 1094 1095 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dsi->id); 1096 dsi->dphy.phy = conn->phy; 1097 1098 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 1099 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 1100 conn_state->output_if |= 1101 dsi->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0; 1102 1103 #ifndef CONFIG_ROCKCHIP_RK3568 1104 if (dsi->id) { 1105 struct udevice *dev; 1106 int ret; 1107 1108 ret = uclass_get_device_by_name(UCLASS_DISPLAY, "dsi@ff960000", 1109 &dev); 1110 if (ret) 1111 return ret; 1112 1113 dsi->master = dev_get_priv(dev); 1114 if (!dsi->master) 1115 return -ENODEV; 1116 1117 conn_state->output_flags = ROCKCHIP_OUTPUT_DATA_SWAP; 1118 } 1119 #endif 1120 1121 if (dsi->lanes > 4) { 1122 struct udevice *dev; 1123 int ret; 1124 1125 ret = uclass_get_device_by_name(UCLASS_DISPLAY, 1126 #if defined(CONFIG_ROCKCHIP_RK3288) 1127 "dsi@ff964000", 1128 #elif defined(CONFIG_ROCKCHIP_RK3399) 1129 "dsi@ff968000", 1130 #else 1131 "dsi@fe070000", 1132 #endif 1133 &dev); 1134 if (ret) 1135 return ret; 1136 1137 dsi->slave = dev_get_priv(dev); 1138 if (!dsi->slave) 1139 return -ENODEV; 1140 1141 dsi->lanes /= 2; 1142 dsi->slave->lanes = dsi->lanes; 1143 dsi->slave->format = dsi->format; 1144 dsi->slave->mode_flags = dsi->mode_flags; 1145 dsi->slave->channel = dsi->channel; 1146 conn_state->output_flags = 1147 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; 1148 if (dsi->data_swap) 1149 conn_state->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP; 1150 1151 conn_state->output_if |= VOP_OUTPUT_IF_MIPI1; 1152 1153 #if defined(CONFIG_ROCKCHIP_RK3568) 1154 struct rockchip_phy *phy = NULL; 1155 struct udevice *phy_dev; 1156 1157 ret = uclass_get_device_by_phandle(UCLASS_PHY, dev, 1158 "phys", &phy_dev); 1159 if (ret) 1160 return -ENODEV; 1161 1162 phy = (struct rockchip_phy *)dev_get_driver_data(phy_dev); 1163 if (!phy) 1164 return -ENODEV; 1165 1166 dsi->slave->dphy.phy = phy; 1167 if (phy->funcs && phy->funcs->init) 1168 return phy->funcs->init(phy); 1169 #endif 1170 1171 } 1172 1173 return 0; 1174 } 1175 1176 static void dw_mipi_dsi_set_hs_clk(struct dw_mipi_dsi *dsi, unsigned long rate) 1177 { 1178 rate = rockchip_phy_set_pll(dsi->dphy.phy, rate); 1179 dsi->lane_mbps = rate / 1000 / 1000; 1180 } 1181 1182 static void dw_mipi_dsi_host_init(struct dw_mipi_dsi *dsi) 1183 { 1184 dw_mipi_dsi_init(dsi); 1185 dw_mipi_dsi_dpi_config(dsi, &dsi->mode); 1186 dw_mipi_dsi_packet_handler_config(dsi); 1187 dw_mipi_dsi_video_mode_config(dsi); 1188 dw_mipi_dsi_video_packet_config(dsi, &dsi->mode); 1189 dw_mipi_dsi_command_mode_config(dsi); 1190 dsi_update_bits(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE, COMMAND_MODE); 1191 dw_mipi_dsi_line_timer_config(dsi); 1192 dw_mipi_dsi_vertical_timing_config(dsi); 1193 dw_mipi_dsi_dphy_timing_config(dsi); 1194 dw_mipi_dsi_dphy_interface_config(dsi); 1195 dw_mipi_dsi_clear_err(dsi); 1196 } 1197 1198 static void dw_mipi_dsi_vop_routing(struct dw_mipi_dsi *dsi, int vop_id) 1199 { 1200 grf_field_write(dsi, VOPSEL, vop_id); 1201 1202 if (dsi->slave) 1203 grf_field_write(dsi->slave, VOPSEL, vop_id); 1204 } 1205 1206 static void mipi_dphy_init(struct dw_mipi_dsi *dsi) 1207 { 1208 u32 map[] = {0x0, 0x1, 0x3, 0x7, 0xf}; 1209 1210 mipi_dphy_enableclk_deassert(dsi); 1211 mipi_dphy_shutdownz_assert(dsi); 1212 mipi_dphy_rstz_assert(dsi); 1213 testif_testclr_assert(dsi); 1214 1215 /* Configures DPHY to work as a Master */ 1216 grf_field_write(dsi, MASTERSLAVEZ, 1); 1217 1218 /* Configures lane as TX */ 1219 grf_field_write(dsi, BASEDIR, 0); 1220 1221 /* Set all REQUEST inputs to zero */ 1222 grf_field_write(dsi, TURNREQUEST, 0); 1223 grf_field_write(dsi, TURNDISABLE, 0); 1224 grf_field_write(dsi, FORCETXSTOPMODE, 0); 1225 grf_field_write(dsi, FORCERXMODE, 0); 1226 udelay(1); 1227 1228 testif_testclr_deassert(dsi); 1229 1230 if (!dsi->dphy.phy) 1231 dw_mipi_dsi_phy_init(dsi); 1232 1233 /* Enable Data Lane Module */ 1234 grf_field_write(dsi, ENABLE_N, map[dsi->lanes]); 1235 1236 /* Enable Clock Lane Module */ 1237 grf_field_write(dsi, ENABLECLK, 1); 1238 1239 mipi_dphy_enableclk_assert(dsi); 1240 } 1241 1242 static void dw_mipi_dsi_pre_enable(struct dw_mipi_dsi *dsi) 1243 { 1244 if (dsi->prepared) 1245 return; 1246 1247 if (dsi->master) 1248 dw_mipi_dsi_pre_enable(dsi->master); 1249 1250 dw_mipi_dsi_host_init(dsi); 1251 mipi_dphy_init(dsi); 1252 mipi_dphy_power_on(dsi); 1253 dsi_write(dsi, DSI_PWR_UP, POWERUP); 1254 1255 dsi->prepared = true; 1256 1257 if (dsi->slave) 1258 dw_mipi_dsi_pre_enable(dsi->slave); 1259 } 1260 1261 static int dw_mipi_dsi_connector_prepare(struct rockchip_connector *conn, 1262 struct display_state *state) 1263 { 1264 struct connector_state *conn_state = &state->conn_state; 1265 struct crtc_state *crtc_state = &state->crtc_state; 1266 struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev); 1267 unsigned long lane_rate; 1268 1269 memcpy(&dsi->mode, &conn_state->mode, sizeof(struct drm_display_mode)); 1270 if (dsi->slave) { 1271 dsi->mode.hdisplay /= 2; 1272 memcpy(&dsi->slave->mode, &dsi->mode, 1273 sizeof(struct drm_display_mode)); 1274 } 1275 1276 lane_rate = dw_mipi_dsi_get_lane_rate(dsi); 1277 if (dsi->dphy.phy) 1278 dw_mipi_dsi_set_hs_clk(dsi, lane_rate); 1279 else 1280 dw_mipi_dsi_set_pll(dsi, lane_rate); 1281 1282 if (dsi->slave && dsi->slave->dphy.phy) 1283 dw_mipi_dsi_set_hs_clk(dsi->slave, lane_rate); 1284 1285 printf("final DSI-Link bandwidth: %u Mbps x %d\n", 1286 dsi->lane_mbps, dsi->slave ? dsi->lanes * 2 : dsi->lanes); 1287 1288 dw_mipi_dsi_vop_routing(dsi, crtc_state->crtc_id); 1289 dw_mipi_dsi_pre_enable(dsi); 1290 1291 return 0; 1292 } 1293 1294 static void dw_mipi_dsi_connector_unprepare(struct rockchip_connector *conn, 1295 struct display_state *state) 1296 { 1297 struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev); 1298 1299 dw_mipi_dsi_post_disable(dsi); 1300 } 1301 1302 static int dw_mipi_dsi_connector_enable(struct rockchip_connector *conn, 1303 struct display_state *state) 1304 { 1305 struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev); 1306 1307 dw_mipi_dsi_enable(dsi); 1308 1309 return 0; 1310 } 1311 1312 static int dw_mipi_dsi_connector_disable(struct rockchip_connector *conn, 1313 struct display_state *state) 1314 { 1315 struct dw_mipi_dsi *dsi = dev_get_priv(conn->dev); 1316 1317 dw_mipi_dsi_disable(dsi); 1318 1319 return 0; 1320 } 1321 1322 static const struct rockchip_connector_funcs dw_mipi_dsi_connector_funcs = { 1323 .init = dw_mipi_dsi_connector_init, 1324 .prepare = dw_mipi_dsi_connector_prepare, 1325 .unprepare = dw_mipi_dsi_connector_unprepare, 1326 .enable = dw_mipi_dsi_connector_enable, 1327 .disable = dw_mipi_dsi_connector_disable, 1328 }; 1329 1330 static int dw_mipi_dsi_probe(struct udevice *dev) 1331 { 1332 struct dw_mipi_dsi *dsi = dev_get_priv(dev); 1333 const struct dw_mipi_dsi_plat_data *pdata = 1334 (const struct dw_mipi_dsi_plat_data *)dev_get_driver_data(dev); 1335 int id; 1336 1337 dsi->base = dev_read_addr_ptr(dev); 1338 dsi->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1339 if (IS_ERR(dsi->grf)) 1340 return PTR_ERR(dsi->grf); 1341 1342 id = of_alias_get_id(ofnode_to_np(dev->node), "dsi"); 1343 if (id < 0) 1344 id = 0; 1345 1346 dsi->dev = dev; 1347 dsi->pdata = pdata; 1348 dsi->id = id; 1349 dsi->data_swap = dev_read_bool(dsi->dev, "rockchip,data-swap"); 1350 1351 rockchip_connector_bind(&dsi->connector, dev, dsi->id, &dw_mipi_dsi_connector_funcs, NULL, 1352 DRM_MODE_CONNECTOR_DSI); 1353 1354 return 0; 1355 } 1356 1357 static const u32 px30_dsi_grf_reg_fields[MAX_FIELDS] = { 1358 [DPIUPDATECFG] = GRF_REG_FIELD(0x0434, 7, 7), 1359 [DPICOLORM] = GRF_REG_FIELD(0x0434, 3, 3), 1360 [DPISHUTDN] = GRF_REG_FIELD(0x0434, 2, 2), 1361 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0438, 7, 10), 1362 [TURNDISABLE] = GRF_REG_FIELD(0x0438, 5, 5), 1363 [VOPSEL] = GRF_REG_FIELD(0x0438, 0, 0), 1364 }; 1365 1366 static const struct dw_mipi_dsi_plat_data px30_mipi_dsi_plat_data = { 1367 .dsi0_grf_reg_fields = px30_dsi_grf_reg_fields, 1368 .max_bit_rate_per_lane = 1000000000UL, 1369 }; 1370 1371 static const u32 rk1808_dsi_grf_reg_fields[MAX_FIELDS] = { 1372 [MASTERSLAVEZ] = GRF_REG_FIELD(0x0440, 8, 8), 1373 [DPIUPDATECFG] = GRF_REG_FIELD(0x0440, 7, 7), 1374 [DPICOLORM] = GRF_REG_FIELD(0x0440, 3, 3), 1375 [DPISHUTDN] = GRF_REG_FIELD(0x0440, 2, 2), 1376 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0444, 7, 10), 1377 [FORCERXMODE] = GRF_REG_FIELD(0x0444, 6, 6), 1378 [TURNDISABLE] = GRF_REG_FIELD(0x0444, 5, 5), 1379 }; 1380 1381 static const struct dw_mipi_dsi_plat_data rk1808_mipi_dsi_plat_data = { 1382 .dsi0_grf_reg_fields = rk1808_dsi_grf_reg_fields, 1383 .max_bit_rate_per_lane = 2000000000UL, 1384 }; 1385 1386 static const u32 rk3128_dsi_grf_reg_fields[MAX_FIELDS] = { 1387 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0150, 10, 13), 1388 [FORCERXMODE] = GRF_REG_FIELD(0x0150, 9, 9), 1389 [TURNDISABLE] = GRF_REG_FIELD(0x0150, 8, 8), 1390 [DPICOLORM] = GRF_REG_FIELD(0x0150, 5, 5), 1391 [DPISHUTDN] = GRF_REG_FIELD(0x0150, 4, 4), 1392 }; 1393 1394 static const struct dw_mipi_dsi_plat_data rk3128_mipi_dsi_plat_data = { 1395 .dsi0_grf_reg_fields = rk3128_dsi_grf_reg_fields, 1396 .max_bit_rate_per_lane = 1000000000UL, 1397 }; 1398 1399 static const u32 rk3288_dsi0_grf_reg_fields[MAX_FIELDS] = { 1400 [DPICOLORM] = GRF_REG_FIELD(0x025c, 8, 8), 1401 [DPISHUTDN] = GRF_REG_FIELD(0x025c, 7, 7), 1402 [VOPSEL] = GRF_REG_FIELD(0x025c, 6, 6), 1403 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0264, 8, 11), 1404 [FORCERXMODE] = GRF_REG_FIELD(0x0264, 4, 7), 1405 [TURNDISABLE] = GRF_REG_FIELD(0x0264, 0, 3), 1406 [TURNREQUEST] = GRF_REG_FIELD(0x03a4, 8, 10), 1407 [DPIUPDATECFG] = GRF_REG_FIELD(0x03a8, 0, 0), 1408 }; 1409 1410 static const u32 rk3288_dsi1_grf_reg_fields[MAX_FIELDS] = { 1411 [DPICOLORM] = GRF_REG_FIELD(0x025c, 11, 11), 1412 [DPISHUTDN] = GRF_REG_FIELD(0x025c, 10, 10), 1413 [VOPSEL] = GRF_REG_FIELD(0x025c, 9, 9), 1414 [ENABLE_N] = GRF_REG_FIELD(0x0268, 12, 15), 1415 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0268, 8, 11), 1416 [FORCERXMODE] = GRF_REG_FIELD(0x0268, 4, 7), 1417 [TURNDISABLE] = GRF_REG_FIELD(0x0268, 0, 3), 1418 [BASEDIR] = GRF_REG_FIELD(0x027c, 15, 15), 1419 [MASTERSLAVEZ] = GRF_REG_FIELD(0x027c, 14, 14), 1420 [ENABLECLK] = GRF_REG_FIELD(0x027c, 12, 12), 1421 [TURNREQUEST] = GRF_REG_FIELD(0x03a4, 4, 7), 1422 [DPIUPDATECFG] = GRF_REG_FIELD(0x03a8, 1, 1), 1423 }; 1424 1425 static const struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_plat_data = { 1426 .dsi0_grf_reg_fields = rk3288_dsi0_grf_reg_fields, 1427 .dsi1_grf_reg_fields = rk3288_dsi1_grf_reg_fields, 1428 .max_bit_rate_per_lane = 1500000000UL, 1429 }; 1430 1431 static const u32 rk3366_dsi_grf_reg_fields[MAX_FIELDS] = { 1432 [VOPSEL] = GRF_REG_FIELD(0x0400, 2, 2), 1433 [DPIUPDATECFG] = GRF_REG_FIELD(0x0410, 9, 9), 1434 [DPICOLORM] = GRF_REG_FIELD(0x0410, 3, 3), 1435 [DPISHUTDN] = GRF_REG_FIELD(0x0410, 2, 2), 1436 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0414, 7, 10), 1437 [FORCERXMODE] = GRF_REG_FIELD(0x0414, 6, 6), 1438 [TURNDISABLE] = GRF_REG_FIELD(0x0414, 5, 5), 1439 }; 1440 1441 static const struct dw_mipi_dsi_plat_data rk3366_mipi_dsi_plat_data = { 1442 .dsi0_grf_reg_fields = rk3366_dsi_grf_reg_fields, 1443 .max_bit_rate_per_lane = 1000000000UL, 1444 }; 1445 1446 static const u32 rk3368_dsi_grf_reg_fields[MAX_FIELDS] = { 1447 [DPIUPDATECFG] = GRF_REG_FIELD(0x0418, 7, 7), 1448 [DPICOLORM] = GRF_REG_FIELD(0x0418, 3, 3), 1449 [DPISHUTDN] = GRF_REG_FIELD(0x0418, 2, 2), 1450 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x041c, 7, 10), 1451 [FORCERXMODE] = GRF_REG_FIELD(0x041c, 6, 6), 1452 [TURNDISABLE] = GRF_REG_FIELD(0x041c, 5, 5), 1453 }; 1454 1455 static const struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_plat_data = { 1456 .dsi0_grf_reg_fields = rk3368_dsi_grf_reg_fields, 1457 .max_bit_rate_per_lane = 1000000000UL, 1458 }; 1459 1460 static const u32 rk3399_dsi0_grf_reg_fields[MAX_FIELDS] = { 1461 [DPIUPDATECFG] = GRF_REG_FIELD(0x6224, 15, 15), 1462 [DPISHUTDN] = GRF_REG_FIELD(0x6224, 14, 14), 1463 [DPICOLORM] = GRF_REG_FIELD(0x6224, 13, 13), 1464 [VOPSEL] = GRF_REG_FIELD(0x6250, 0, 0), 1465 [TURNREQUEST] = GRF_REG_FIELD(0x6258, 12, 15), 1466 [TURNDISABLE] = GRF_REG_FIELD(0x6258, 8, 11), 1467 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x6258, 4, 7), 1468 [FORCERXMODE] = GRF_REG_FIELD(0x6258, 0, 3), 1469 }; 1470 1471 static const u32 rk3399_dsi1_grf_reg_fields[MAX_FIELDS] = { 1472 [VOPSEL] = GRF_REG_FIELD(0x6250, 4, 4), 1473 [DPIUPDATECFG] = GRF_REG_FIELD(0x6250, 3, 3), 1474 [DPISHUTDN] = GRF_REG_FIELD(0x6250, 2, 2), 1475 [DPICOLORM] = GRF_REG_FIELD(0x6250, 1, 1), 1476 [TURNDISABLE] = GRF_REG_FIELD(0x625c, 12, 15), 1477 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x625c, 8, 11), 1478 [FORCERXMODE] = GRF_REG_FIELD(0x625c, 4, 7), 1479 [ENABLE_N] = GRF_REG_FIELD(0x625c, 0, 3), 1480 [MASTERSLAVEZ] = GRF_REG_FIELD(0x6260, 7, 7), 1481 [ENABLECLK] = GRF_REG_FIELD(0x6260, 6, 6), 1482 [BASEDIR] = GRF_REG_FIELD(0x6260, 5, 5), 1483 [TURNREQUEST] = GRF_REG_FIELD(0x6260, 0, 3), 1484 }; 1485 1486 static const struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_plat_data = { 1487 .dsi0_grf_reg_fields = rk3399_dsi0_grf_reg_fields, 1488 .dsi1_grf_reg_fields = rk3399_dsi1_grf_reg_fields, 1489 .max_bit_rate_per_lane = 1500000000UL, 1490 }; 1491 1492 static const u32 rk3568_dsi0_grf_reg_fields[MAX_FIELDS] = { 1493 [DPIUPDATECFG] = GRF_REG_FIELD(0x0360, 2, 2), 1494 [DPICOLORM] = GRF_REG_FIELD(0x0360, 1, 1), 1495 [DPISHUTDN] = GRF_REG_FIELD(0x0360, 0, 0), 1496 [SKEWCALHS] = GRF_REG_FIELD(0x0368, 11, 15), 1497 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0368, 4, 7), 1498 [TURNDISABLE] = GRF_REG_FIELD(0x0368, 2, 2), 1499 [FORCERXMODE] = GRF_REG_FIELD(0x0368, 0, 0), 1500 }; 1501 1502 static const u32 rk3568_dsi1_grf_reg_fields[MAX_FIELDS] = { 1503 [DPIUPDATECFG] = GRF_REG_FIELD(0x0360, 10, 10), 1504 [DPICOLORM] = GRF_REG_FIELD(0x0360, 9, 9), 1505 [DPISHUTDN] = GRF_REG_FIELD(0x0360, 8, 8), 1506 [SKEWCALHS] = GRF_REG_FIELD(0x036c, 11, 15), 1507 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x036c, 4, 7), 1508 [TURNDISABLE] = GRF_REG_FIELD(0x036c, 2, 2), 1509 [FORCERXMODE] = GRF_REG_FIELD(0x036c, 0, 0), 1510 }; 1511 1512 static const struct dw_mipi_dsi_plat_data rk3568_mipi_dsi_plat_data = { 1513 .dsi0_grf_reg_fields = rk3568_dsi0_grf_reg_fields, 1514 .dsi1_grf_reg_fields = rk3568_dsi1_grf_reg_fields, 1515 .max_bit_rate_per_lane = 1200000000UL, 1516 }; 1517 1518 static const u32 rv1108_dsi_grf_reg_fields[MAX_FIELDS] = { 1519 [DPICOLORM] = GRF_REG_FIELD(0x0410, 7, 7), 1520 [DPISHUTDN] = GRF_REG_FIELD(0x0410, 6, 6), 1521 [DPIUPDATECFG] = GRF_REG_FIELD(0x0410, 8, 8), 1522 [FORCERXMODE] = GRF_REG_FIELD(0x0414, 5, 5), 1523 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x0414, 6, 9), 1524 [TURNDISABLE] = GRF_REG_FIELD(0x0414, 4, 4), 1525 }; 1526 1527 static const struct dw_mipi_dsi_plat_data rv1108_mipi_dsi_plat_data = { 1528 .dsi0_grf_reg_fields = rv1108_dsi_grf_reg_fields, 1529 .max_bit_rate_per_lane = 1000000000UL, 1530 }; 1531 1532 static const u32 rv1126_dsi_grf_reg_fields[MAX_FIELDS] = { 1533 [DPIUPDATECFG] = GRF_REG_FIELD(0x0008, 5, 5), 1534 [DPISHUTDN] = GRF_REG_FIELD(0x0008, 4, 4), 1535 [DPICOLORM] = GRF_REG_FIELD(0x0008, 3, 3), 1536 [FORCETXSTOPMODE] = GRF_REG_FIELD(0x10220, 4, 7), 1537 [TURNDISABLE] = GRF_REG_FIELD(0x10220, 2, 2), 1538 [FORCERXMODE] = GRF_REG_FIELD(0x10220, 0, 0), 1539 }; 1540 1541 static const struct dw_mipi_dsi_plat_data rv1126_mipi_dsi_plat_data = { 1542 .dsi0_grf_reg_fields = rv1126_dsi_grf_reg_fields, 1543 .max_bit_rate_per_lane = 1000000000UL, 1544 }; 1545 1546 static const struct udevice_id dw_mipi_dsi_ids[] = { 1547 { 1548 .compatible = "rockchip,px30-mipi-dsi", 1549 .data = (ulong)&px30_mipi_dsi_plat_data, 1550 }, 1551 { 1552 .compatible = "rockchip,rk1808-mipi-dsi", 1553 .data = (ulong)&rk1808_mipi_dsi_plat_data, 1554 }, 1555 { 1556 .compatible = "rockchip,rk3128-mipi-dsi", 1557 .data = (ulong)&rk3128_mipi_dsi_plat_data, 1558 }, 1559 { 1560 .compatible = "rockchip,rk3288-mipi-dsi", 1561 .data = (ulong)&rk3288_mipi_dsi_plat_data, 1562 }, 1563 { 1564 .compatible = "rockchip,rk3366-mipi-dsi", 1565 .data = (ulong)&rk3366_mipi_dsi_plat_data, 1566 }, 1567 { 1568 .compatible = "rockchip,rk3368-mipi-dsi", 1569 .data = (ulong)&rk3368_mipi_dsi_plat_data, 1570 }, 1571 { 1572 .compatible = "rockchip,rk3399-mipi-dsi", 1573 .data = (ulong)&rk3399_mipi_dsi_plat_data, 1574 }, 1575 { 1576 .compatible = "rockchip,rk3568-mipi-dsi", 1577 .data = (ulong)&rk3568_mipi_dsi_plat_data, 1578 }, 1579 { 1580 .compatible = "rockchip,rv1108-mipi-dsi", 1581 .data = (ulong)&rv1108_mipi_dsi_plat_data, 1582 }, 1583 { 1584 .compatible = "rockchip,rv1126-mipi-dsi", 1585 .data = (ulong)&rv1126_mipi_dsi_plat_data, 1586 }, 1587 {} 1588 }; 1589 1590 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host, 1591 const struct mipi_dsi_msg *msg) 1592 { 1593 struct dw_mipi_dsi *dsi = dev_get_priv(host->dev); 1594 1595 return dw_mipi_dsi_transfer(dsi, msg); 1596 } 1597 1598 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 1599 struct mipi_dsi_device *device) 1600 { 1601 struct dw_mipi_dsi *dsi = dev_get_priv(host->dev); 1602 1603 if (device->lanes < 1 || device->lanes > 8) 1604 return -EINVAL; 1605 1606 dsi->lanes = device->lanes; 1607 dsi->channel = device->channel; 1608 dsi->format = device->format; 1609 dsi->mode_flags = device->mode_flags; 1610 1611 return 0; 1612 } 1613 1614 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = { 1615 .attach = dw_mipi_dsi_host_attach, 1616 .transfer = dw_mipi_dsi_host_transfer, 1617 }; 1618 1619 static int dw_mipi_dsi_bind(struct udevice *dev) 1620 { 1621 struct mipi_dsi_host *host = dev_get_platdata(dev); 1622 1623 host->dev = dev; 1624 host->ops = &dw_mipi_dsi_host_ops; 1625 1626 return dm_scan_fdt_dev(dev); 1627 } 1628 1629 static int dw_mipi_dsi_child_post_bind(struct udevice *dev) 1630 { 1631 struct mipi_dsi_host *host = dev_get_platdata(dev->parent); 1632 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1633 char name[20]; 1634 1635 sprintf(name, "%s.%d", host->dev->name, device->channel); 1636 device_set_name(dev, name); 1637 1638 device->dev = dev; 1639 device->host = host; 1640 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4); 1641 device->format = dev_read_u32_default(dev, "dsi,format", 1642 MIPI_DSI_FMT_RGB888); 1643 device->mode_flags = dev_read_u32_default(dev, "dsi,flags", 1644 MIPI_DSI_MODE_VIDEO | 1645 MIPI_DSI_MODE_VIDEO_BURST | 1646 MIPI_DSI_MODE_VIDEO_HBP | 1647 MIPI_DSI_MODE_LPM | 1648 MIPI_DSI_MODE_EOT_PACKET); 1649 device->channel = dev_read_u32_default(dev, "reg", 0); 1650 1651 return 0; 1652 } 1653 1654 static int dw_mipi_dsi_child_pre_probe(struct udevice *dev) 1655 { 1656 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1657 int ret; 1658 1659 ret = mipi_dsi_attach(device); 1660 if (ret) { 1661 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret); 1662 return ret; 1663 } 1664 1665 return 0; 1666 } 1667 1668 U_BOOT_DRIVER(dw_mipi_dsi) = { 1669 .name = "dw_mipi_dsi", 1670 .id = UCLASS_DISPLAY, 1671 .of_match = dw_mipi_dsi_ids, 1672 .probe = dw_mipi_dsi_probe, 1673 .bind = dw_mipi_dsi_bind, 1674 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi), 1675 .per_child_platdata_auto_alloc_size = sizeof(struct mipi_dsi_device), 1676 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_host), 1677 .child_post_bind = dw_mipi_dsi_child_post_bind, 1678 .child_pre_probe = dw_mipi_dsi_child_pre_probe, 1679 }; 1680