1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <syscon.h> 10 #include <asm/gpio.h> 11 #include <asm/arch-rockchip/clock.h> 12 #include <asm/arch/vendor.h> 13 #include <edid.h> 14 #include <dm/device.h> 15 #include <dm/of_access.h> 16 #include <dm/ofnode.h> 17 #include <dm/read.h> 18 #include <linux/hdmi.h> 19 #include <linux/media-bus-format.h> 20 #include <linux/dw_hdmi.h> 21 #include <asm/io.h> 22 #include "rockchip_display.h" 23 #include "rockchip_crtc.h" 24 #include "rockchip_connector.h" 25 #include "dw_hdmi.h" 26 #include "rockchip_phy.h" 27 28 #define HDCP_PRIVATE_KEY_SIZE 280 29 #define HDCP_KEY_SHA_SIZE 20 30 #define HDMI_HDCP1X_ID 5 31 #define HDMI_EDID_BLOCK_LEN 128 32 /* 33 * Unless otherwise noted, entries in this table are 100% optimization. 34 * Values can be obtained from hdmi_compute_n() but that function is 35 * slow so we pre-compute values we expect to see. 36 * 37 * All 32k and 48k values are expected to be the same (due to the way 38 * the math works) for any rate that's an exact kHz. 39 */ 40 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = { 41 { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, }, 42 { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, }, 43 { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 44 { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, }, 45 { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, }, 46 { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, 47 { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, 48 { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 49 { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 50 { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, 51 { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 52 { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, 53 { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 54 { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 55 { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, }, 56 { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 57 { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, }, 58 { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 59 { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 60 { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, }, 61 { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, 62 { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, 63 { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, 64 { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 65 { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 66 { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 67 { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 68 { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 69 { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, 70 { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 71 { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, }, 72 { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, 73 { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 74 { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 75 { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 76 { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, 77 { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 78 79 /* For 297 MHz+ HDMI spec have some other rule for setting N */ 80 { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, }, 81 { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, }, 82 83 /* End of table */ 84 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, }, 85 }; 86 87 static const u16 csc_coeff_default[3][4] = { 88 { 0x2000, 0x0000, 0x0000, 0x0000 }, 89 { 0x0000, 0x2000, 0x0000, 0x0000 }, 90 { 0x0000, 0x0000, 0x2000, 0x0000 } 91 }; 92 93 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 94 { 0x2000, 0x6926, 0x74fd, 0x010e }, 95 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 96 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 97 }; 98 99 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 100 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 101 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 102 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 103 }; 104 105 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 106 { 0x2591, 0x1322, 0x074b, 0x0000 }, 107 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 108 { 0x6acd, 0x7534, 0x2000, 0x0200 } 109 }; 110 111 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 112 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 113 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 114 { 0x6756, 0x78ab, 0x2000, 0x0200 } 115 }; 116 117 static const u16 csc_coeff_full_to_limited[3][4] = { 118 { 0x36f7, 0x0000, 0x0000, 0x0040 }, 119 { 0x0000, 0x36f7, 0x0000, 0x0040 }, 120 { 0x0000, 0x0000, 0x36f7, 0x0040 } 121 }; 122 123 struct hdmi_vmode { 124 bool mdataenablepolarity; 125 126 unsigned int mpixelclock; 127 unsigned int mpixelrepetitioninput; 128 unsigned int mpixelrepetitionoutput; 129 unsigned int mtmdsclock; 130 }; 131 132 struct hdmi_data_info { 133 unsigned int enc_in_bus_format; 134 unsigned int enc_out_bus_format; 135 unsigned int enc_in_encoding; 136 unsigned int enc_out_encoding; 137 unsigned int quant_range; 138 unsigned int pix_repet_factor; 139 struct hdmi_vmode video_mode; 140 }; 141 142 struct dw_hdmi_phy_data { 143 enum dw_hdmi_phy_type type; 144 const char *name; 145 unsigned int gen; 146 bool has_svsret; 147 int (*configure)(struct dw_hdmi *hdmi, 148 const struct dw_hdmi_plat_data *pdata, 149 unsigned long mpixelclock); 150 }; 151 152 struct hdcp_keys { 153 u8 KSV[8]; 154 u8 devicekey[HDCP_PRIVATE_KEY_SIZE]; 155 u8 sha1[HDCP_KEY_SHA_SIZE]; 156 u8 seeds[2]; 157 }; 158 159 struct dw_hdmi_i2c { 160 u8 slave_reg; 161 bool is_regaddr; 162 bool is_segment; 163 164 unsigned int scl_high_ns; 165 unsigned int scl_low_ns; 166 }; 167 168 struct dw_hdmi { 169 int id; 170 enum dw_hdmi_devtype dev_type; 171 unsigned int version; 172 struct hdmi_data_info hdmi_data; 173 struct hdmi_edid_data edid_data; 174 const struct dw_hdmi_plat_data *plat_data; 175 struct ddc_adapter adap; 176 177 int vic; 178 int io_width; 179 180 unsigned long bus_format; 181 bool cable_plugin; 182 bool sink_is_hdmi; 183 bool sink_has_audio; 184 bool force_output; 185 void *regs; 186 void *grf; 187 void *gpio_base; 188 struct dw_hdmi_i2c *i2c; 189 190 struct { 191 const struct dw_hdmi_phy_ops *ops; 192 const char *name; 193 void *data; 194 bool enabled; 195 } phy; 196 197 struct drm_display_mode previous_mode; 198 199 unsigned int sample_rate; 200 unsigned int audio_cts; 201 unsigned int audio_n; 202 bool audio_enable; 203 bool scramble_low_rates; 204 205 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset); 206 u8 (*read)(struct dw_hdmi *hdmi, int offset); 207 208 bool hdcp1x_enable; 209 bool output_bus_format_rgb; 210 211 struct gpio_desc hpd_gpiod; 212 }; 213 214 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset) 215 { 216 writel(val, hdmi->regs + (offset << 2)); 217 } 218 219 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset) 220 { 221 return readl(hdmi->regs + (offset << 2)); 222 } 223 224 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 225 { 226 writeb(val, hdmi->regs + offset); 227 } 228 229 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset) 230 { 231 return readb(hdmi->regs + offset); 232 } 233 234 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 235 { 236 hdmi->write(hdmi, val, offset); 237 } 238 239 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 240 { 241 return hdmi->read(hdmi, offset); 242 } 243 244 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 245 { 246 u8 val = hdmi_readb(hdmi, reg) & ~mask; 247 248 val |= data & mask; 249 hdmi_writeb(hdmi, val, reg); 250 } 251 252 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 253 u8 shift, u8 mask) 254 { 255 hdmi_modb(hdmi, data << shift, mask, reg); 256 } 257 258 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 259 { 260 switch (bus_format) { 261 case MEDIA_BUS_FMT_RGB888_1X24: 262 case MEDIA_BUS_FMT_RGB101010_1X30: 263 case MEDIA_BUS_FMT_RGB121212_1X36: 264 case MEDIA_BUS_FMT_RGB161616_1X48: 265 return true; 266 267 default: 268 return false; 269 } 270 } 271 272 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 273 { 274 switch (bus_format) { 275 case MEDIA_BUS_FMT_YUV8_1X24: 276 case MEDIA_BUS_FMT_YUV10_1X30: 277 case MEDIA_BUS_FMT_YUV12_1X36: 278 case MEDIA_BUS_FMT_YUV16_1X48: 279 return true; 280 281 default: 282 return false; 283 } 284 } 285 286 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 287 { 288 switch (bus_format) { 289 case MEDIA_BUS_FMT_UYVY8_1X16: 290 case MEDIA_BUS_FMT_UYVY10_1X20: 291 case MEDIA_BUS_FMT_UYVY12_1X24: 292 return true; 293 294 default: 295 return false; 296 } 297 } 298 299 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 300 { 301 switch (bus_format) { 302 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 303 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 304 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 305 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 306 return true; 307 308 default: 309 return false; 310 } 311 } 312 313 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 314 { 315 switch (bus_format) { 316 case MEDIA_BUS_FMT_RGB888_1X24: 317 case MEDIA_BUS_FMT_YUV8_1X24: 318 case MEDIA_BUS_FMT_UYVY8_1X16: 319 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 320 return 8; 321 322 case MEDIA_BUS_FMT_RGB101010_1X30: 323 case MEDIA_BUS_FMT_YUV10_1X30: 324 case MEDIA_BUS_FMT_UYVY10_1X20: 325 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 326 return 10; 327 328 case MEDIA_BUS_FMT_RGB121212_1X36: 329 case MEDIA_BUS_FMT_YUV12_1X36: 330 case MEDIA_BUS_FMT_UYVY12_1X24: 331 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 332 return 12; 333 334 case MEDIA_BUS_FMT_RGB161616_1X48: 335 case MEDIA_BUS_FMT_YUV16_1X48: 336 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 337 return 16; 338 339 default: 340 return 0; 341 } 342 } 343 344 static int is_color_space_conversion(struct dw_hdmi *hdmi) 345 { 346 struct drm_display_mode *mode = 347 hdmi->edid_data.preferred_mode; 348 bool is_cea_default; 349 350 is_cea_default = (drm_match_cea_mode(mode) > 1) && 351 (hdmi->hdmi_data.quant_range == 352 HDMI_QUANTIZATION_RANGE_DEFAULT); 353 354 /* 355 * When output is rgb limited range or default range with 356 * cea mode, csc should be enabled. 357 */ 358 if (hdmi->hdmi_data.enc_in_bus_format != 359 hdmi->hdmi_data.enc_out_bus_format || 360 ((hdmi->hdmi_data.quant_range == HDMI_QUANTIZATION_RANGE_LIMITED || 361 is_cea_default) && 362 hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format))) 363 return 1; 364 365 return 0; 366 } 367 368 static int is_color_space_decimation(struct dw_hdmi *hdmi) 369 { 370 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 371 return 0; 372 373 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 374 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 375 return 1; 376 377 return 0; 378 } 379 380 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 381 unsigned char bit) 382 { 383 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 384 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 385 } 386 387 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi, 388 unsigned char bit) 389 { 390 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET, 391 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0); 392 } 393 394 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi, 395 unsigned char bit) 396 { 397 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET, 398 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0); 399 } 400 401 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi, 402 unsigned char bit) 403 { 404 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1); 405 } 406 407 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi, 408 unsigned char bit) 409 { 410 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2); 411 } 412 413 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 414 unsigned char *buf, unsigned int length) 415 { 416 struct dw_hdmi_i2c *i2c = hdmi->i2c; 417 int interrupt = 0, i = 20; 418 bool read_edid = false; 419 420 if (!i2c->is_regaddr) { 421 printf("set read register address to 0\n"); 422 i2c->slave_reg = 0x00; 423 i2c->is_regaddr = true; 424 } 425 426 /* edid reads are in 128 bytes. scdc reads are in 1 byte */ 427 if (length == HDMI_EDID_BLOCK_LEN) 428 read_edid = true; 429 430 while (length > 0) { 431 hdmi_writeb(hdmi, i2c->slave_reg, HDMI_I2CM_ADDRESS); 432 433 if (read_edid) { 434 i2c->slave_reg += 8; 435 length -= 8; 436 } else { 437 i2c->slave_reg++; 438 length--; 439 } 440 441 if (i2c->is_segment) { 442 if (read_edid) 443 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ8_EXT, 444 HDMI_I2CM_OPERATION); 445 else 446 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 447 HDMI_I2CM_OPERATION); 448 } else { 449 if (read_edid) 450 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ8, 451 HDMI_I2CM_OPERATION); 452 else 453 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 454 HDMI_I2CM_OPERATION); 455 } 456 457 while (i--) { 458 udelay(1000); 459 interrupt = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 460 if (interrupt) 461 hdmi_writeb(hdmi, interrupt, 462 HDMI_IH_I2CM_STAT0); 463 if (interrupt & (m_SCDC_READREQ | m_I2CM_DONE | 464 m_I2CM_ERROR)) 465 break; 466 } 467 468 if (!interrupt) { 469 printf("[%s] i2c read reg[0x%02x] no interrupt\n", 470 __func__, i2c->slave_reg); 471 hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ); 472 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR, 473 HDMI_I2CM_OPERATION); 474 udelay(1000); 475 return -EAGAIN; 476 } 477 478 /* Check for error condition on the bus */ 479 if (interrupt & HDMI_IH_I2CM_STAT0_ERROR) { 480 printf("[%s] read reg[0x%02x] data error:0x%02x\n", 481 __func__, i2c->slave_reg, interrupt); 482 hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ); 483 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR, 484 HDMI_I2CM_OPERATION); 485 udelay(1000); 486 return -EIO; 487 } 488 489 i = 20; 490 if (read_edid) 491 for (i = 0; i < 8; i++) 492 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_READ_BUFF0 + i); 493 else 494 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 495 } 496 i2c->is_segment = false; 497 498 return 0; 499 } 500 501 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 502 unsigned char *buf, unsigned int length) 503 { 504 struct dw_hdmi_i2c *i2c = hdmi->i2c; 505 int i = 20; 506 u8 interrupt = 0; 507 508 if (!i2c->is_regaddr) { 509 /* Use the first write byte as register address */ 510 i2c->slave_reg = buf[0]; 511 length--; 512 buf++; 513 i2c->is_regaddr = true; 514 } 515 516 while (length--) { 517 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 518 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 519 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 520 HDMI_I2CM_OPERATION); 521 522 while (i--) { 523 udelay(1000); 524 interrupt = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 525 if (interrupt) 526 hdmi_writeb(hdmi, 527 interrupt, HDMI_IH_I2CM_STAT0); 528 529 if (interrupt & (m_SCDC_READREQ | 530 m_I2CM_DONE | m_I2CM_ERROR)) 531 break; 532 } 533 534 if (!interrupt) { 535 printf("[%s] i2c write reg[0x%02x] no interrupt\n", 536 __func__, i2c->slave_reg); 537 hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ); 538 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR, 539 HDMI_I2CM_OPERATION); 540 udelay(1000); 541 return -EAGAIN; 542 } 543 544 if ((interrupt & m_I2CM_ERROR) || (i == -1)) { 545 printf("[%s] write data error\n", __func__); 546 hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ); 547 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR, 548 HDMI_I2CM_OPERATION); 549 udelay(1000); 550 return -EIO; 551 } else if (interrupt & m_I2CM_DONE) { 552 printf("[%s] write offset %02x success\n", 553 __func__, i2c->slave_reg); 554 return -EAGAIN; 555 } 556 557 i = 20; 558 } 559 560 return 0; 561 } 562 563 static int dw_hdmi_i2c_xfer(struct ddc_adapter *adap, 564 struct i2c_msg *msgs, int num) 565 { 566 struct dw_hdmi *hdmi = container_of(adap, struct dw_hdmi, adap); 567 struct dw_hdmi_i2c *i2c = hdmi->i2c; 568 u8 addr = msgs[0].addr; 569 int i, ret = 0; 570 571 printf("xfer: num: %d, addr: %#x\n", num, addr); 572 for (i = 0; i < num; i++) { 573 if (msgs[i].len == 0) { 574 printf("unsupported transfer %d/%d, no data\n", 575 i + 1, num); 576 return -EOPNOTSUPP; 577 } 578 } 579 580 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 581 582 /* Set slave device address taken from the first I2C message */ 583 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1) 584 addr = DDC_ADDR; 585 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 586 587 /* Set slave device register address on transfer */ 588 i2c->is_regaddr = false; 589 590 /* Set segment pointer for I2C extended read mode operation */ 591 i2c->is_segment = false; 592 593 for (i = 0; i < num; i++) { 594 debug("xfer: num: %d/%d, len: %d, flags: %#x\n", 595 i + 1, num, msgs[i].len, msgs[i].flags); 596 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 597 i2c->is_segment = true; 598 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 599 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 600 } else { 601 if (msgs[i].flags & I2C_M_RD) 602 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 603 msgs[i].len); 604 else 605 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 606 msgs[i].len); 607 } 608 if (ret < 0) 609 break; 610 } 611 612 if (!ret) 613 ret = num; 614 615 /* Mute DONE and ERROR interrupts */ 616 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 617 HDMI_IH_MUTE_I2CM_STAT0); 618 619 return ret; 620 } 621 622 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 623 { 624 u32 val; 625 626 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 627 if (msec-- == 0) 628 return false; 629 udelay(1000); 630 } 631 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 632 633 return true; 634 } 635 636 static void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 637 unsigned char addr) 638 { 639 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 640 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 641 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 642 HDMI_PHY_I2CM_DATAO_1_ADDR); 643 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 644 HDMI_PHY_I2CM_DATAO_0_ADDR); 645 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 646 HDMI_PHY_I2CM_OPERATION_ADDR); 647 hdmi_phy_wait_i2c_done(hdmi, 1000); 648 } 649 650 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 651 { 652 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 653 HDMI_PHY_CONF0_PDZ_OFFSET, 654 HDMI_PHY_CONF0_PDZ_MASK); 655 } 656 657 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 658 { 659 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 660 HDMI_PHY_CONF0_ENTMDS_OFFSET, 661 HDMI_PHY_CONF0_ENTMDS_MASK); 662 } 663 664 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 665 { 666 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 667 HDMI_PHY_CONF0_SVSRET_OFFSET, 668 HDMI_PHY_CONF0_SVSRET_MASK); 669 } 670 671 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 672 { 673 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 674 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 675 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 676 } 677 678 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 679 { 680 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 681 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 682 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 683 } 684 685 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 686 { 687 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 688 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 689 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 690 } 691 692 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 693 { 694 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 695 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 696 HDMI_PHY_CONF0_SELDIPIF_MASK); 697 } 698 699 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 700 { 701 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 702 unsigned int i; 703 u16 val; 704 705 if (phy->gen == 1) { 706 dw_hdmi_phy_enable_tmds(hdmi, 0); 707 dw_hdmi_phy_enable_powerdown(hdmi, true); 708 return; 709 } 710 711 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 712 713 /* 714 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 715 * to low power mode. 716 */ 717 for (i = 0; i < 5; ++i) { 718 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 719 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 720 break; 721 722 udelay(2000); 723 } 724 725 if (val & HDMI_PHY_TX_PHY_LOCK) 726 printf("PHY failed to power down\n"); 727 else 728 printf("PHY powered down in %u iterations\n", i); 729 730 dw_hdmi_phy_gen2_pddq(hdmi, 1); 731 } 732 733 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 734 { 735 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 736 unsigned int i; 737 u8 val; 738 739 if (phy->gen == 1) { 740 dw_hdmi_phy_enable_powerdown(hdmi, false); 741 742 /* Toggle TMDS enable. */ 743 dw_hdmi_phy_enable_tmds(hdmi, 0); 744 dw_hdmi_phy_enable_tmds(hdmi, 1); 745 return 0; 746 } 747 748 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 749 dw_hdmi_phy_gen2_pddq(hdmi, 0); 750 751 /* Wait for PHY PLL lock */ 752 for (i = 0; i < 5; ++i) { 753 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 754 if (val) 755 break; 756 757 udelay(2000); 758 } 759 760 if (!val) { 761 printf("PHY PLL failed to lock\n"); 762 return -ETIMEDOUT; 763 } 764 printf("PHY PLL locked %u iterations\n", i); 765 766 return 0; 767 } 768 769 /* 770 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 771 * information the DWC MHL PHY has the same register layout and is thus also 772 * supported by this function. 773 */ 774 static 775 int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 776 const struct dw_hdmi_plat_data *pdata, 777 unsigned long mpixelclock) 778 { 779 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 780 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 781 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 782 unsigned int tmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 783 unsigned int depth = 784 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 785 786 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) && 787 pdata->mpll_cfg_420) 788 mpll_config = pdata->mpll_cfg_420; 789 790 /* PLL/MPLL Cfg - always match on final entry */ 791 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 792 if (mpixelclock <= mpll_config->mpixelclock) 793 break; 794 795 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 796 if (tmdsclock <= curr_ctrl->mpixelclock) 797 break; 798 799 for (; phy_config->mpixelclock != ~0UL; phy_config++) 800 if (tmdsclock <= phy_config->mpixelclock) 801 break; 802 803 if (mpll_config->mpixelclock == ~0UL || 804 curr_ctrl->mpixelclock == ~0UL || 805 phy_config->mpixelclock == ~0UL) 806 return -EINVAL; 807 808 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 809 depth = fls(depth - 8); 810 else 811 depth = 0; 812 if (depth) 813 depth--; 814 815 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].cpce, 816 HDMI_3D_TX_PHY_CPCE_CTRL); 817 818 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].gmp, 819 HDMI_3D_TX_PHY_GMPCTRL); 820 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[depth], 821 HDMI_3D_TX_PHY_CURRCTRL); 822 823 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 824 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 825 HDMI_3D_TX_PHY_MSM_CTRL); 826 827 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 828 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 829 HDMI_3D_TX_PHY_CKSYMTXCTRL); 830 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 831 HDMI_3D_TX_PHY_VLEVCTRL); 832 833 return 0; 834 } 835 836 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 837 { 838 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 839 .name = "DWC HDMI TX PHY", 840 .gen = 1, 841 }, { 842 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 843 .name = "DWC MHL PHY + HEAC PHY", 844 .gen = 2, 845 .has_svsret = true, 846 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 847 }, { 848 .type = DW_HDMI_PHY_DWC_MHL_PHY, 849 .name = "DWC MHL PHY", 850 .gen = 2, 851 .has_svsret = true, 852 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 853 }, { 854 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 855 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 856 .gen = 2, 857 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 858 }, { 859 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 860 .name = "DWC HDMI 3D TX PHY", 861 .gen = 2, 862 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 863 }, { 864 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 865 .name = "DWC HDMI 2.0 TX PHY", 866 .gen = 2, 867 .has_svsret = true, 868 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 869 }, { 870 .type = DW_HDMI_PHY_VENDOR_PHY, 871 .name = "Vendor PHY", 872 } 873 }; 874 875 static int rockchip_dw_hdmi_scrambling_enable(struct dw_hdmi *hdmi, 876 int enable) 877 { 878 u8 stat; 879 880 drm_scdc_readb(&hdmi->adap, SCDC_TMDS_CONFIG, &stat); 881 882 if (stat < 0 && !hdmi->force_output) { 883 debug("Failed to read tmds config\n"); 884 return false; 885 } 886 887 if (enable == 1) { 888 /* Write on Rx the bit Scrambling_Enable, register 0x20 */ 889 stat |= SCDC_SCRAMBLING_ENABLE; 890 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 891 /* TMDS software reset request */ 892 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 893 HDMI_MC_SWRSTZ); 894 /* Enable/Disable Scrambling */ 895 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); 896 } else { 897 /* Enable/Disable Scrambling */ 898 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); 899 /* TMDS software reset request */ 900 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 901 HDMI_MC_SWRSTZ); 902 /* Write on Rx the bit Scrambling_Enable, register 0x20 */ 903 stat &= ~SCDC_SCRAMBLING_ENABLE; 904 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 905 } 906 907 return 0; 908 } 909 910 static void rockchip_dw_hdmi_scdc_set_tmds_rate(struct dw_hdmi *hdmi) 911 { 912 u8 stat; 913 914 drm_scdc_readb(&hdmi->adap, SCDC_TMDS_CONFIG, &stat); 915 if (hdmi->hdmi_data.video_mode.mtmdsclock > 340000000) 916 stat |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 917 else 918 stat &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 919 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 920 } 921 922 static int hdmi_phy_configure(struct dw_hdmi *hdmi) 923 { 924 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 925 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 926 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 927 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 928 int ret; 929 930 dw_hdmi_phy_power_off(hdmi); 931 932 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ 933 if (hdmi->edid_data.display_info.hdmi.scdc.supported) 934 rockchip_dw_hdmi_scdc_set_tmds_rate(hdmi); 935 936 /* Leave low power consumption mode by asserting SVSRET. */ 937 if (phy->has_svsret) 938 dw_hdmi_phy_enable_svsret(hdmi, 1); 939 940 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 941 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 942 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 943 944 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 945 946 hdmi_phy_test_clear(hdmi, 1); 947 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, 948 HDMI_PHY_I2CM_SLAVE_ADDR); 949 hdmi_phy_test_clear(hdmi, 0); 950 951 /* Write to the PHY as configured by the platform */ 952 if (pdata->configure_phy) 953 ret = pdata->configure_phy(hdmi, pdata, mpixelclock); 954 else 955 ret = phy->configure(hdmi, pdata, mpixelclock); 956 if (ret) { 957 printf("PHY configuration failed (clock %lu)\n", 958 mpixelclock); 959 return ret; 960 } 961 962 /* Wait for resuming transmission of TMDS clock and data */ 963 if (mtmdsclock > 340000000) 964 mdelay(100); 965 966 return dw_hdmi_phy_power_on(hdmi); 967 } 968 969 static int dw_hdmi_phy_init(struct rockchip_connector *conn, struct dw_hdmi *hdmi, 970 void *data) 971 { 972 int i, ret; 973 974 /* HDMI Phy spec says to do the phy initialization sequence twice */ 975 for (i = 0; i < 2; i++) { 976 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 977 dw_hdmi_phy_sel_interface_control(hdmi, 0); 978 ret = hdmi_phy_configure(hdmi); 979 if (ret) 980 return ret; 981 } 982 983 return 0; 984 } 985 986 static void dw_hdmi_phy_disable(struct rockchip_connector *conn, struct dw_hdmi *hdmi, 987 void *data) 988 { 989 dw_hdmi_phy_power_off(hdmi); 990 } 991 992 static enum drm_connector_status 993 dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data) 994 { 995 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 996 connector_status_connected : connector_status_disconnected; 997 } 998 999 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 1000 .init = dw_hdmi_phy_init, 1001 .disable = dw_hdmi_phy_disable, 1002 .read_hpd = dw_hdmi_phy_read_hpd, 1003 }; 1004 1005 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 1006 { 1007 unsigned int i; 1008 u8 phy_type; 1009 1010 phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID); 1011 1012 /* 1013 * RK3228 and RK3328 phy_type is DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 1014 * but it has a vedor phy. 1015 */ 1016 if (phy_type == DW_HDMI_PHY_VENDOR_PHY || 1017 hdmi->dev_type == RK3528_HDMI || 1018 hdmi->dev_type == RK3328_HDMI || 1019 hdmi->dev_type == RK3228_HDMI) { 1020 /* Vendor PHYs require support from the glue layer. */ 1021 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 1022 printf( 1023 "Vendor HDMI PHY not supported by glue layer\n"); 1024 return -ENODEV; 1025 } 1026 1027 hdmi->phy.ops = hdmi->plat_data->phy_ops; 1028 hdmi->phy.data = hdmi->plat_data->phy_data; 1029 hdmi->phy.name = hdmi->plat_data->phy_name; 1030 return 0; 1031 } 1032 1033 /* Synopsys PHYs are handled internally. */ 1034 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 1035 if (dw_hdmi_phys[i].type == phy_type) { 1036 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 1037 hdmi->phy.name = dw_hdmi_phys[i].name; 1038 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 1039 1040 if (!dw_hdmi_phys[i].configure && 1041 !hdmi->plat_data->configure_phy) { 1042 printf("%s requires platform support\n", 1043 hdmi->phy.name); 1044 return -ENODEV; 1045 } 1046 1047 return 0; 1048 } 1049 } 1050 1051 printf("Unsupported HDMI PHY type (%02x)\n", phy_type); 1052 return -ENODEV; 1053 } 1054 1055 static unsigned int 1056 hdmi_get_tmdsclock(struct dw_hdmi *hdmi, unsigned long mpixelclock) 1057 { 1058 unsigned int tmdsclock = mpixelclock; 1059 unsigned int depth = 1060 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 1061 1062 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1063 switch (depth) { 1064 case 16: 1065 tmdsclock = mpixelclock * 2; 1066 break; 1067 case 12: 1068 tmdsclock = mpixelclock * 3 / 2; 1069 break; 1070 case 10: 1071 tmdsclock = mpixelclock * 5 / 4; 1072 break; 1073 default: 1074 break; 1075 } 1076 } 1077 1078 return tmdsclock; 1079 } 1080 1081 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1082 const struct drm_display_mode *mode) 1083 { 1084 u8 bytes = 0, inv_val = 0; 1085 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1086 struct drm_hdmi_info *hdmi_info = &hdmi->edid_data.display_info.hdmi; 1087 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1088 unsigned int hdisplay, vdisplay; 1089 1090 vmode->mpixelclock = mode->crtc_clock * 1000; 1091 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == 1092 DRM_MODE_FLAG_3D_FRAME_PACKING) 1093 vmode->mpixelclock *= 2; 1094 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock); 1095 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1096 vmode->mtmdsclock /= 2; 1097 printf("final pixclk = %d tmdsclk = %d\n", 1098 vmode->mpixelclock, vmode->mtmdsclock); 1099 1100 /* Set up HDMI_FC_INVIDCONF 1101 * Some display equipments require that the interval 1102 * between Video Data and Data island must be at least 58 pixels, 1103 * and fc_invidconf.HDCP_keepout set (1'b1) can meet the requirement. 1104 */ 1105 inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE; 1106 1107 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 1108 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 1109 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 1110 1111 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 1112 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 1113 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 1114 1115 inv_val |= (vmode->mdataenablepolarity ? 1116 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 1117 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 1118 1119 if (hdmi->vic == 39) 1120 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 1121 else 1122 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1123 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 1124 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 1125 1126 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1127 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 1128 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 1129 1130 inv_val |= hdmi->sink_is_hdmi ? 1131 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 1132 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 1133 1134 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 1135 1136 hdisplay = mode->hdisplay; 1137 hblank = mode->htotal - mode->hdisplay; 1138 h_de_hs = mode->hsync_start - mode->hdisplay; 1139 hsync_len = mode->hsync_end - mode->hsync_start; 1140 1141 /* 1142 * When we're setting a YCbCr420 mode, we need 1143 * to adjust the horizontal timing to suit. 1144 */ 1145 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1146 hdisplay /= 2; 1147 hblank /= 2; 1148 h_de_hs /= 2; 1149 hsync_len /= 2; 1150 } 1151 1152 vdisplay = mode->vdisplay; 1153 vblank = mode->vtotal - mode->vdisplay; 1154 v_de_vs = mode->vsync_start - mode->vdisplay; 1155 vsync_len = mode->vsync_end - mode->vsync_start; 1156 1157 /* 1158 * When we're setting an interlaced mode, we need 1159 * to adjust the vertical timing to suit. 1160 */ 1161 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1162 vdisplay /= 2; 1163 vblank /= 2; 1164 v_de_vs /= 2; 1165 vsync_len /= 2; 1166 } else if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == 1167 DRM_MODE_FLAG_3D_FRAME_PACKING) { 1168 vdisplay += mode->vtotal; 1169 } 1170 1171 /* Scrambling Control */ 1172 if (hdmi_info->scdc.supported || hdmi->force_output) { 1173 if (vmode->mtmdsclock > 340000000 || 1174 (hdmi_info->scdc.scrambling.low_rates && 1175 hdmi->scramble_low_rates)) { 1176 drm_scdc_readb(&hdmi->adap, SCDC_SINK_VERSION, &bytes); 1177 drm_scdc_writeb(&hdmi->adap, SCDC_SOURCE_VERSION, 1178 bytes); 1179 rockchip_dw_hdmi_scrambling_enable(hdmi, 1); 1180 } else { 1181 rockchip_dw_hdmi_scrambling_enable(hdmi, 0); 1182 } 1183 } 1184 1185 /* Set up horizontal active pixel width */ 1186 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1); 1187 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0); 1188 1189 /* Set up vertical active lines */ 1190 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 1191 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 1192 1193 /* Set up horizontal blanking pixel region width */ 1194 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 1195 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 1196 1197 /* Set up vertical blanking pixel region width */ 1198 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 1199 1200 /* Set up HSYNC active edge delay width (in pixel clks) */ 1201 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 1202 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 1203 1204 /* Set up VSYNC active edge delay (in lines) */ 1205 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 1206 1207 /* Set up HSYNC active pulse width (in pixel clks) */ 1208 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 1209 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 1210 1211 /* Set up VSYNC active edge delay (in lines) */ 1212 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 1213 } 1214 1215 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 1216 { 1217 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 1218 unsigned i; 1219 u32 csc_scale = 1; 1220 int enc_out_rgb, enc_in_rgb; 1221 1222 enc_out_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format); 1223 enc_in_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format); 1224 1225 if (is_color_space_conversion(hdmi)) { 1226 if (enc_out_rgb && enc_in_rgb) { 1227 csc_coeff = &csc_coeff_full_to_limited; 1228 csc_scale = 0; 1229 } else if (enc_out_rgb) { 1230 if (hdmi->hdmi_data.enc_out_encoding == 1231 V4L2_YCBCR_ENC_601) 1232 csc_coeff = &csc_coeff_rgb_out_eitu601; 1233 else 1234 csc_coeff = &csc_coeff_rgb_out_eitu709; 1235 } else if (enc_in_rgb) { 1236 if (hdmi->hdmi_data.enc_out_encoding == 1237 V4L2_YCBCR_ENC_601) 1238 csc_coeff = &csc_coeff_rgb_in_eitu601; 1239 else 1240 csc_coeff = &csc_coeff_rgb_in_eitu709; 1241 csc_scale = 0; 1242 } 1243 } 1244 1245 /* The CSC registers are sequential, alternating MSB then LSB */ 1246 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 1247 u16 coeff_a = (*csc_coeff)[0][i]; 1248 u16 coeff_b = (*csc_coeff)[1][i]; 1249 u16 coeff_c = (*csc_coeff)[2][i]; 1250 1251 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 1252 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 1253 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 1254 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 1255 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 1256 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 1257 } 1258 1259 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 1260 HDMI_CSC_SCALE); 1261 } 1262 1263 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 1264 { 1265 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 1266 return 0; 1267 1268 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1269 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1270 return 1; 1271 1272 return 0; 1273 } 1274 1275 static void hdmi_video_csc(struct dw_hdmi *hdmi) 1276 { 1277 int color_depth = 0; 1278 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 1279 int decimation = 0; 1280 1281 /* YCC422 interpolation to 444 mode */ 1282 if (is_color_space_interpolation(hdmi)) 1283 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 1284 else if (is_color_space_decimation(hdmi)) 1285 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 1286 1287 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 1288 case 8: 1289 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 1290 break; 1291 case 10: 1292 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 1293 break; 1294 case 12: 1295 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 1296 break; 1297 case 16: 1298 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 1299 break; 1300 1301 default: 1302 return; 1303 } 1304 1305 /* Configure the CSC registers */ 1306 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 1307 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 1308 HDMI_CSC_SCALE); 1309 1310 dw_hdmi_update_csc_coeffs(hdmi); 1311 } 1312 1313 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 1314 { 1315 u8 clkdis; 1316 1317 /* control period minimum duration */ 1318 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 1319 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 1320 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 1321 1322 /* Set to fill TMDS data channels */ 1323 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 1324 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 1325 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 1326 1327 /* Enable pixel clock and tmds data path */ 1328 clkdis = 0x7F; 1329 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 1330 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1331 1332 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1333 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1334 1335 /* Enable csc path */ 1336 if (is_color_space_conversion(hdmi)) { 1337 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 1338 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1339 } 1340 1341 /* Enable pixel repetition path */ 1342 if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) { 1343 clkdis &= ~HDMI_MC_CLKDIS_PREPCLK_DISABLE; 1344 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1345 } 1346 1347 /* Enable color space conversion if needed */ 1348 if (is_color_space_conversion(hdmi)) 1349 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 1350 HDMI_MC_FLOWCTRL); 1351 else 1352 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 1353 HDMI_MC_FLOWCTRL); 1354 } 1355 1356 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 1357 { 1358 unsigned int count; 1359 unsigned int i; 1360 u8 val; 1361 1362 /* 1363 * Under some circumstances the Frame Composer arithmetic unit can miss 1364 * an FC register write due to being busy processing the previous one. 1365 * The issue can be worked around by issuing a TMDS software reset and 1366 * then write one of the FC registers several times. 1367 * 1368 * The number of iterations matters and depends on the HDMI TX revision 1369 * (and possibly on the platform). So far only i.MX6Q (v1.30a) and 1370 * i.MX6DL (v1.31a) have been identified as needing the workaround, with 1371 * 4 and 1 iterations respectively. 1372 */ 1373 1374 switch (hdmi->version) { 1375 case 0x130a: 1376 count = 4; 1377 break; 1378 case 0x131a: 1379 case 0x200a: 1380 case 0x201a: 1381 case 0x211a: 1382 count = 1; 1383 break; 1384 default: 1385 return; 1386 } 1387 1388 /* TMDS software reset */ 1389 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 1390 1391 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 1392 for (i = 0; i < count; i++) 1393 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 1394 } 1395 1396 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 1397 { 1398 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 1399 HDMI_IH_MUTE_FC_STAT2); 1400 } 1401 1402 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 1403 { 1404 unsigned int color_depth = 0; 1405 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 1406 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 1407 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1408 u8 val, vp_conf; 1409 1410 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1411 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) || 1412 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1413 switch (hdmi_bus_fmt_color_depth( 1414 hdmi->hdmi_data.enc_out_bus_format)) { 1415 case 8: 1416 color_depth = 0; 1417 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1418 break; 1419 case 10: 1420 color_depth = 5; 1421 break; 1422 case 12: 1423 color_depth = 6; 1424 break; 1425 case 16: 1426 color_depth = 7; 1427 break; 1428 default: 1429 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1430 } 1431 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1432 switch (hdmi_bus_fmt_color_depth( 1433 hdmi->hdmi_data.enc_out_bus_format)) { 1434 case 0: 1435 case 8: 1436 remap_size = HDMI_VP_REMAP_YCC422_16bit; 1437 break; 1438 case 10: 1439 remap_size = HDMI_VP_REMAP_YCC422_20bit; 1440 break; 1441 case 12: 1442 remap_size = HDMI_VP_REMAP_YCC422_24bit; 1443 break; 1444 1445 default: 1446 return; 1447 } 1448 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 1449 } else { 1450 return; 1451 } 1452 1453 /* set the packetizer registers */ 1454 val = (color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 1455 HDMI_VP_PR_CD_COLOR_DEPTH_MASK; 1456 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 1457 1458 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 1459 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 1460 1461 /* Data from pixel repeater block */ 1462 if (hdmi_data->pix_repet_factor > 0) { 1463 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 1464 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 1465 } else { /* data from packetizer block */ 1466 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 1467 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 1468 } 1469 1470 hdmi_modb(hdmi, vp_conf, 1471 HDMI_VP_CONF_PR_EN_MASK | 1472 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 1473 1474 hdmi_modb(hdmi, 0, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, 1475 HDMI_VP_STUFF); 1476 1477 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 1478 1479 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 1480 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1481 HDMI_VP_CONF_PP_EN_ENABLE | 1482 HDMI_VP_CONF_YCC422_EN_DISABLE; 1483 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 1484 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1485 HDMI_VP_CONF_PP_EN_DISABLE | 1486 HDMI_VP_CONF_YCC422_EN_ENABLE; 1487 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 1488 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 1489 HDMI_VP_CONF_PP_EN_DISABLE | 1490 HDMI_VP_CONF_YCC422_EN_DISABLE; 1491 } else { 1492 return; 1493 } 1494 1495 hdmi_modb(hdmi, vp_conf, 1496 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 1497 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 1498 1499 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 1500 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 1501 HDMI_VP_STUFF_PP_STUFFING_MASK | 1502 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 1503 1504 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 1505 HDMI_VP_CONF); 1506 } 1507 1508 static void hdmi_video_sample(struct dw_hdmi *hdmi) 1509 { 1510 int color_format = 0; 1511 u8 val; 1512 1513 switch (hdmi->hdmi_data.enc_in_bus_format) { 1514 case MEDIA_BUS_FMT_RGB888_1X24: 1515 color_format = 0x01; 1516 break; 1517 case MEDIA_BUS_FMT_RGB101010_1X30: 1518 color_format = 0x03; 1519 break; 1520 case MEDIA_BUS_FMT_RGB121212_1X36: 1521 color_format = 0x05; 1522 break; 1523 case MEDIA_BUS_FMT_RGB161616_1X48: 1524 color_format = 0x07; 1525 break; 1526 1527 case MEDIA_BUS_FMT_YUV8_1X24: 1528 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1529 color_format = 0x09; 1530 break; 1531 case MEDIA_BUS_FMT_YUV10_1X30: 1532 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1533 color_format = 0x0B; 1534 break; 1535 case MEDIA_BUS_FMT_YUV12_1X36: 1536 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 1537 color_format = 0x0D; 1538 break; 1539 case MEDIA_BUS_FMT_YUV16_1X48: 1540 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 1541 color_format = 0x0F; 1542 break; 1543 1544 case MEDIA_BUS_FMT_UYVY8_1X16: 1545 color_format = 0x16; 1546 break; 1547 case MEDIA_BUS_FMT_UYVY10_1X20: 1548 color_format = 0x14; 1549 break; 1550 case MEDIA_BUS_FMT_UYVY12_1X24: 1551 color_format = 0x12; 1552 break; 1553 1554 default: 1555 return; 1556 } 1557 1558 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 1559 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 1560 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 1561 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 1562 1563 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 1564 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 1565 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 1566 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 1567 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 1568 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 1569 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 1570 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 1571 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 1572 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 1573 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 1574 } 1575 1576 static void dw_hdmi_disable(struct rockchip_connector *conn, struct dw_hdmi *hdmi, 1577 struct display_state *state) 1578 { 1579 if (hdmi->phy.enabled) { 1580 hdmi->phy.ops->disable(conn, hdmi, state); 1581 hdmi->phy.enabled = false; 1582 } 1583 } 1584 1585 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1586 { 1587 struct hdmi_avi_infoframe frame; 1588 u8 val; 1589 bool is_hdmi2 = false; 1590 enum hdmi_quantization_range rgb_quant_range = 1591 hdmi->hdmi_data.quant_range; 1592 1593 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) || 1594 hdmi->edid_data.display_info.hdmi.scdc.supported) 1595 is_hdmi2 = true; 1596 /* Initialise info frame from DRM mode */ 1597 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2); 1598 1599 /* 1600 * Ignore monitor selectable quantization, use quantization set 1601 * by the user 1602 */ 1603 drm_hdmi_avi_infoframe_quant_range(&frame, mode, rgb_quant_range, 1604 true); 1605 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1606 frame.colorspace = HDMI_COLORSPACE_YUV444; 1607 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1608 frame.colorspace = HDMI_COLORSPACE_YUV422; 1609 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1610 frame.colorspace = HDMI_COLORSPACE_YUV420; 1611 else 1612 frame.colorspace = HDMI_COLORSPACE_RGB; 1613 1614 /* Set up colorimetry */ 1615 switch (hdmi->hdmi_data.enc_out_encoding) { 1616 case V4L2_YCBCR_ENC_601: 1617 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1618 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1619 else 1620 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1621 frame.extended_colorimetry = 1622 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1623 break; 1624 case V4L2_YCBCR_ENC_709: 1625 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1626 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1627 else 1628 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1629 frame.extended_colorimetry = 1630 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1631 break; 1632 default: /* Carries no data */ 1633 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1634 frame.extended_colorimetry = 1635 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1636 break; 1637 } 1638 1639 frame.scan_mode = HDMI_SCAN_MODE_NONE; 1640 1641 /* 1642 * The Designware IP uses a different byte format from standard 1643 * AVI info frames, though generally the bits are in the correct 1644 * bytes. 1645 */ 1646 1647 /* 1648 * AVI data byte 1 differences: Colorspace in bits 0,1,7 rather than 1649 * 5,6,7, active aspect present in bit 6 rather than 4. 1650 */ 1651 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 0x3); 1652 if (frame.active_aspect & 15) 1653 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1654 if (frame.top_bar || frame.bottom_bar) 1655 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1656 if (frame.left_bar || frame.right_bar) 1657 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1658 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1659 1660 /* AVI data byte 2 differences: none */ 1661 val = ((frame.colorimetry & 0x3) << 6) | 1662 ((frame.picture_aspect & 0x3) << 4) | 1663 (frame.active_aspect & 0xf); 1664 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1665 1666 /* AVI data byte 3 differences: none */ 1667 val = ((frame.extended_colorimetry & 0x7) << 4) | 1668 ((frame.quantization_range & 0x3) << 2) | 1669 (frame.nups & 0x3); 1670 if (frame.itc) 1671 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1672 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1673 1674 /* AVI data byte 4 differences: none */ 1675 val = frame.video_code & 0x7f; 1676 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1677 1678 /* AVI Data Byte 5- set up input and output pixel repetition */ 1679 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1680 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1681 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1682 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1683 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1684 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1685 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1686 1687 /* 1688 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1689 * ycc range in bits 2,3 rather than 6,7 1690 */ 1691 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1692 (frame.content_type & 0x3); 1693 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1694 1695 /* AVI Data Bytes 6-13 */ 1696 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1697 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1698 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1699 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1700 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1701 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1702 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1703 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1704 } 1705 1706 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1707 struct drm_display_mode *mode) 1708 { 1709 struct hdmi_vendor_infoframe frame; 1710 u8 buffer[10]; 1711 ssize_t err; 1712 1713 /* Disable HDMI vendor specific infoframe send */ 1714 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1715 HDMI_FC_DATAUTO0_VSD_MASK); 1716 1717 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode); 1718 if (err < 0) 1719 /* 1720 * Going into that statement does not means vendor infoframe 1721 * fails. It just informed us that vendor infoframe is not 1722 * needed for the selected mode. Only 4k or stereoscopic 3D 1723 * mode requires vendor infoframe. So just simply return. 1724 */ 1725 return; 1726 1727 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1728 if (err < 0) { 1729 printf("Failed to pack vendor infoframe: %zd\n", err); 1730 return; 1731 } 1732 1733 /* Set the length of HDMI vendor specific InfoFrame payload */ 1734 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1735 1736 /* Set 24bit IEEE Registration Identifier */ 1737 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1738 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1739 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1740 1741 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1742 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1743 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1744 1745 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1746 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1747 1748 /* Packet frame interpolation */ 1749 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1750 1751 /* Auto packets per frame and line spacing */ 1752 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1753 1754 /* Configures the Frame Composer On RDRB mode */ 1755 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1756 HDMI_FC_DATAUTO0_VSD_MASK); 1757 } 1758 1759 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 1760 unsigned int n) 1761 { 1762 /* Must be set/cleared first */ 1763 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 1764 1765 /* nshift factor = 0 */ 1766 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 1767 1768 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 1769 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 1770 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 1771 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 1772 1773 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 1774 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 1775 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 1776 } 1777 1778 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi, 1779 unsigned long pixel_clk, 1780 unsigned long freq) 1781 { 1782 const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data; 1783 const struct dw_hdmi_audio_tmds_n *tmds_n = NULL; 1784 int i; 1785 1786 if (plat_data->tmds_n_table) { 1787 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) { 1788 if (pixel_clk == plat_data->tmds_n_table[i].tmds) { 1789 tmds_n = &plat_data->tmds_n_table[i]; 1790 break; 1791 } 1792 } 1793 } 1794 1795 if (!tmds_n) { 1796 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) { 1797 if (pixel_clk == common_tmds_n_table[i].tmds) { 1798 tmds_n = &common_tmds_n_table[i]; 1799 break; 1800 } 1801 } 1802 } 1803 1804 if (!tmds_n) 1805 return -ENOENT; 1806 1807 switch (freq) { 1808 case 32000: 1809 return tmds_n->n_32k; 1810 case 44100: 1811 case 88200: 1812 case 176400: 1813 return (freq / 44100) * tmds_n->n_44k1; 1814 case 48000: 1815 case 96000: 1816 case 192000: 1817 return (freq / 48000) * tmds_n->n_48k; 1818 default: 1819 return -ENOENT; 1820 } 1821 } 1822 1823 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n, 1824 unsigned int pixel_clk) 1825 { 1826 u64 final, diff; 1827 u64 cts; 1828 1829 final = (u64)pixel_clk * n; 1830 1831 cts = final; 1832 do_div(cts, 128 * freq); 1833 1834 diff = final - (u64)cts * (128 * freq); 1835 1836 return diff; 1837 } 1838 1839 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi, 1840 unsigned long pixel_clk, 1841 unsigned long freq) 1842 { 1843 unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500); 1844 unsigned int max_n = (128 * freq) / 300; 1845 unsigned int ideal_n = (128 * freq) / 1000; 1846 unsigned int best_n_distance = ideal_n; 1847 unsigned int best_n = 0; 1848 u64 best_diff = U64_MAX; 1849 int n; 1850 1851 /* If the ideal N could satisfy the audio math, then just take it */ 1852 if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0) 1853 return ideal_n; 1854 1855 for (n = min_n; n <= max_n; n++) { 1856 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk); 1857 1858 if (diff < best_diff || (diff == best_diff && 1859 abs(n - ideal_n) < best_n_distance)) { 1860 best_n = n; 1861 best_diff = diff; 1862 best_n_distance = abs(best_n - ideal_n); 1863 } 1864 1865 /* 1866 * The best N already satisfy the audio math, and also be 1867 * the closest value to ideal N, so just cut the loop. 1868 */ 1869 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance)) 1870 break; 1871 } 1872 1873 return best_n; 1874 } 1875 1876 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk, 1877 unsigned long sample_rate) 1878 { 1879 int n; 1880 1881 n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate); 1882 if (n > 0) 1883 return n; 1884 1885 printf("Rate %lu missing; compute N dynamically\n", 1886 pixel_clk); 1887 1888 return hdmi_compute_n(hdmi, pixel_clk, sample_rate); 1889 } 1890 1891 static 1892 void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, unsigned long pixel_clk, 1893 unsigned int sample_rate) 1894 { 1895 unsigned long ftdms = pixel_clk; 1896 unsigned int n, cts; 1897 u64 tmp; 1898 1899 n = hdmi_find_n(hdmi, pixel_clk, sample_rate); 1900 1901 /* 1902 * Compute the CTS value from the N value. Note that CTS and N 1903 * can be up to 20 bits in total, so we need 64-bit math. Also 1904 * note that our TDMS clock is not fully accurate; it is accurate 1905 * to kHz. This can introduce an unnecessary remainder in the 1906 * calculation below, so we don't try to warn about that. 1907 */ 1908 tmp = (u64)ftdms * n; 1909 do_div(tmp, 128 * sample_rate); 1910 cts = tmp; 1911 1912 printf("%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", __func__, 1913 sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000, n, cts); 1914 1915 hdmi->audio_n = n; 1916 hdmi->audio_cts = cts; 1917 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 1918 } 1919 1920 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 1921 { 1922 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 1923 hdmi->sample_rate); 1924 } 1925 1926 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi) 1927 { 1928 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS); 1929 } 1930 1931 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 1932 { 1933 hdmi->sample_rate = rate; 1934 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 1935 hdmi->sample_rate); 1936 } 1937 1938 #ifndef CONFIG_SPL_BUILD 1939 static int dw_hdmi_hdcp_load_key(struct dw_hdmi *hdmi) 1940 { 1941 int i, j, ret, val; 1942 struct hdcp_keys *hdcp_keys; 1943 1944 val = sizeof(*hdcp_keys); 1945 hdcp_keys = malloc(val); 1946 if (!hdcp_keys) 1947 return -ENOMEM; 1948 1949 memset(hdcp_keys, 0, val); 1950 1951 ret = vendor_storage_read(HDMI_HDCP1X_ID, hdcp_keys, val); 1952 if (ret < val) { 1953 printf("HDCP: read size %d\n", ret); 1954 free(hdcp_keys); 1955 return -EINVAL; 1956 } 1957 1958 if (hdcp_keys->KSV[0] == 0x00 && 1959 hdcp_keys->KSV[1] == 0x00 && 1960 hdcp_keys->KSV[2] == 0x00 && 1961 hdcp_keys->KSV[3] == 0x00 && 1962 hdcp_keys->KSV[4] == 0x00) { 1963 printf("HDCP: Invalid hdcp key\n"); 1964 free(hdcp_keys); 1965 return -EINVAL; 1966 } 1967 1968 /* Disable decryption logic */ 1969 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_RMCTL); 1970 /* Poll untile DPK write is allowed */ 1971 do { 1972 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1973 } while ((val & DPK_WR_OK_STS) == 0); 1974 1975 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_DPK6); 1976 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_DPK5); 1977 1978 /* The useful data in ksv should be 5 byte */ 1979 for (i = 4; i >= 0; i--) 1980 hdmi_writeb(hdmi, hdcp_keys->KSV[i], HDMI_HDCPREG_DPK0 + i); 1981 /* Poll untile DPK write is allowed */ 1982 do { 1983 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1984 } while ((val & DPK_WR_OK_STS) == 0); 1985 1986 /* Enable decryption logic */ 1987 hdmi_writeb(hdmi, 1, HDMI_HDCPREG_RMCTL); 1988 hdmi_writeb(hdmi, hdcp_keys->seeds[0], HDMI_HDCPREG_SEED1); 1989 hdmi_writeb(hdmi, hdcp_keys->seeds[1], HDMI_HDCPREG_SEED0); 1990 1991 /* Write encrypt device private key */ 1992 for (i = 0; i < DW_HDMI_HDCP_DPK_LEN - 6; i += 7) { 1993 for (j = 6; j >= 0; j--) 1994 hdmi_writeb(hdmi, hdcp_keys->devicekey[i + j], 1995 HDMI_HDCPREG_DPK0 + j); 1996 do { 1997 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1998 } while ((val & DPK_WR_OK_STS) == 0); 1999 } 2000 2001 free(hdcp_keys); 2002 return 0; 2003 } 2004 #endif 2005 2006 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi, 2007 const struct drm_display_mode *mode) 2008 { 2009 u8 vsync_pol, hsync_pol, data_pol, hdmi_dvi; 2010 2011 if (!hdmi->hdcp1x_enable) 2012 return; 2013 2014 /* Configure the video polarity */ 2015 vsync_pol = mode->flags & DRM_MODE_FLAG_PVSYNC ? 2016 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH : 2017 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW; 2018 hsync_pol = mode->flags & DRM_MODE_FLAG_PHSYNC ? 2019 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH : 2020 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW; 2021 data_pol = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 2022 hdmi_modb(hdmi, vsync_pol | hsync_pol | data_pol, 2023 HDMI_A_VIDPOLCFG_VSYNCPOL_MASK | 2024 HDMI_A_VIDPOLCFG_HSYNCPOL_MASK | 2025 HDMI_A_VIDPOLCFG_DATAENPOL_MASK, 2026 HDMI_A_VIDPOLCFG); 2027 2028 /* Config the display mode */ 2029 hdmi_dvi = hdmi->sink_is_hdmi ? HDMI_A_HDCPCFG0_HDMIDVI_HDMI : 2030 HDMI_A_HDCPCFG0_HDMIDVI_DVI; 2031 hdmi_modb(hdmi, hdmi_dvi, HDMI_A_HDCPCFG0_HDMIDVI_MASK, 2032 HDMI_A_HDCPCFG0); 2033 2034 #ifndef CONFIG_SPL_BUILD 2035 if (!(hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS) & 0x3f)) 2036 dw_hdmi_hdcp_load_key(hdmi); 2037 #endif 2038 2039 hdmi_modb(hdmi, HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE, 2040 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK, 2041 HDMI_FC_INVIDCONF); 2042 2043 if (hdmi_readb(hdmi, HDMI_CONFIG1_ID) & HDMI_A_HDCP22_MASK) { 2044 hdmi_modb(hdmi, HDMI_HDCP2_OVR_ENABLE | 2045 HDMI_HDCP2_FORCE_DISABLE, 2046 HDMI_HDCP2_OVR_EN_MASK | 2047 HDMI_HDCP2_FORCE_MASK, 2048 HDMI_HDCP2REG_CTRL); 2049 hdmi_writeb(hdmi, 0xff, HDMI_HDCP2REG_MASK); 2050 hdmi_writeb(hdmi, 0xff, HDMI_HDCP2REG_MUTE); 2051 } 2052 2053 hdmi_writeb(hdmi, 0x40, HDMI_A_OESSWCFG); 2054 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE | 2055 HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE | 2056 HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE, 2057 HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK | 2058 HDMI_A_HDCPCFG0_EN11FEATURE_MASK | 2059 HDMI_A_HDCPCFG0_SYNCRICHECK_MASK, HDMI_A_HDCPCFG0); 2060 2061 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE | 2062 HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE, 2063 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK | 2064 HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK, HDMI_A_HDCPCFG1); 2065 2066 /* Reset HDCP Engine */ 2067 if (hdmi_readb(hdmi, HDMI_MC_CLKDIS) & HDMI_MC_CLKDIS_HDCPCLK_MASK) { 2068 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_SWRESET_ASSERT, 2069 HDMI_A_HDCPCFG1_SWRESET_MASK, HDMI_A_HDCPCFG1); 2070 } 2071 2072 hdmi_writeb(hdmi, 0x00, HDMI_A_APIINTMSK); 2073 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_ENABLE, 2074 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 2075 2076 hdmi_modb(hdmi, HDMI_MC_CLKDIS_HDCPCLK_ENABLE, 2077 HDMI_MC_CLKDIS_HDCPCLK_MASK, HDMI_MC_CLKDIS); 2078 2079 printf("%s success\n", __func__); 2080 } 2081 2082 static int dw_hdmi_setup(struct dw_hdmi *hdmi, 2083 struct rockchip_connector *conn, 2084 struct drm_display_mode *mode, 2085 struct display_state *state) 2086 { 2087 int ret; 2088 void *data = hdmi->plat_data->phy_data; 2089 2090 hdmi_disable_overflow_interrupts(hdmi); 2091 if (!hdmi->vic) 2092 printf("Non-CEA mode used in HDMI\n"); 2093 else 2094 printf("CEA mode used vic=%d\n", hdmi->vic); 2095 2096 if (hdmi->plat_data->get_enc_out_encoding) 2097 hdmi->hdmi_data.enc_out_encoding = 2098 hdmi->plat_data->get_enc_out_encoding(data); 2099 else if (hdmi->vic == 6 || hdmi->vic == 7 || 2100 hdmi->vic == 21 || hdmi->vic == 22 || 2101 hdmi->vic == 2 || hdmi->vic == 3 || 2102 hdmi->vic == 17 || hdmi->vic == 18) 2103 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 2104 else 2105 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 2106 2107 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2108 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1; 2109 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1; 2110 } else { 2111 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 2112 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 2113 } 2114 2115 /* TOFIX: Get input encoding from plat data or fallback to none */ 2116 if (hdmi->plat_data->get_enc_in_encoding) 2117 hdmi->hdmi_data.enc_in_encoding = 2118 hdmi->plat_data->get_enc_in_encoding(data); 2119 else if (hdmi->plat_data->input_bus_encoding) 2120 hdmi->hdmi_data.enc_in_encoding = 2121 hdmi->plat_data->input_bus_encoding; 2122 else 2123 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 2124 2125 if (hdmi->plat_data->get_quant_range) 2126 hdmi->hdmi_data.quant_range = 2127 hdmi->plat_data->get_quant_range(data); 2128 else 2129 hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 2130 2131 /* 2132 * According to the dw-hdmi specification 6.4.2 2133 * vp_pr_cd[3:0]: 2134 * 0000b: No pixel repetition (pixel sent only once) 2135 * 0001b: Pixel sent two times (pixel repeated once) 2136 */ 2137 hdmi->hdmi_data.pix_repet_factor = 2138 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0; 2139 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 2140 2141 /* HDMI Initialization Step B.1 */ 2142 hdmi_av_composer(hdmi, mode); 2143 2144 /* HDMI Initialization Step B.2 */ 2145 ret = hdmi->phy.ops->init(conn, hdmi, state); 2146 if (ret) 2147 return ret; 2148 hdmi->phy.enabled = true; 2149 2150 /* HDMI Initializateion Step B.3 */ 2151 dw_hdmi_enable_video_path(hdmi); 2152 2153 /* HDMI Initialization Step E - Configure audio */ 2154 if (hdmi->sink_has_audio) { 2155 printf("sink has audio support\n"); 2156 hdmi_clk_regenerator_update_pixel_clock(hdmi); 2157 hdmi_enable_audio_clk(hdmi); 2158 } 2159 2160 /* not for DVI mode */ 2161 if (hdmi->sink_is_hdmi) { 2162 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 2163 hdmi_config_AVI(hdmi, mode); 2164 hdmi_config_vendor_specific_infoframe(hdmi, mode); 2165 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_HDMIDVI_HDMI, 2166 HDMI_A_HDCPCFG0_HDMIDVI_MASK, 2167 HDMI_A_HDCPCFG0); 2168 } else { 2169 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_HDMIDVI_DVI, 2170 HDMI_A_HDCPCFG0_HDMIDVI_MASK, 2171 HDMI_A_HDCPCFG0); 2172 printf("%s DVI mode\n", __func__); 2173 } 2174 2175 hdmi_video_packetize(hdmi); 2176 hdmi_video_csc(hdmi); 2177 hdmi_video_sample(hdmi); 2178 hdmi_tx_hdcp_config(hdmi, mode); 2179 dw_hdmi_clear_overflow(hdmi); 2180 2181 return 0; 2182 } 2183 2184 int dw_hdmi_detect_hotplug(struct dw_hdmi *hdmi, 2185 struct display_state *state) 2186 { 2187 return hdmi->phy.ops->read_hpd(hdmi, state); 2188 } 2189 2190 static int dw_hdmi_set_reg_wr(struct dw_hdmi *hdmi) 2191 { 2192 switch (hdmi->io_width) { 2193 case 4: 2194 hdmi->write = dw_hdmi_writel; 2195 hdmi->read = dw_hdmi_readl; 2196 break; 2197 case 1: 2198 hdmi->write = dw_hdmi_writeb; 2199 hdmi->read = dw_hdmi_readb; 2200 break; 2201 default: 2202 printf("reg-io-width must be 1 or 4\n"); 2203 return -EINVAL; 2204 } 2205 2206 return 0; 2207 } 2208 2209 static void initialize_hdmi_mutes(struct dw_hdmi *hdmi) 2210 { 2211 /*mute unnecessary interrupt, only enable hpd */ 2212 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 2213 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 2214 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 2215 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 2216 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 2217 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 2218 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 2219 hdmi_writeb(hdmi, 0xfe, HDMI_IH_MUTE_PHY_STAT0); 2220 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 2221 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 2222 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 2223 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 2224 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 2225 hdmi_writeb(hdmi, 0xf1, HDMI_PHY_MASK0); 2226 2227 /*Force output black*/ 2228 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS2); 2229 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS1); 2230 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS0); 2231 } 2232 2233 static void dw_hdmi_dev_init(struct dw_hdmi *hdmi) 2234 { 2235 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 2236 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 2237 2238 initialize_hdmi_mutes(hdmi); 2239 } 2240 2241 static void dw_hdmi_i2c_set_divs(struct dw_hdmi *hdmi) 2242 { 2243 unsigned long low_ns, high_ns; 2244 unsigned long div_low, div_high; 2245 2246 /* Standard-mode */ 2247 if (hdmi->i2c->scl_high_ns < 4000) 2248 high_ns = 4708; 2249 else 2250 high_ns = hdmi->i2c->scl_high_ns; 2251 2252 if (hdmi->i2c->scl_low_ns < 4700) 2253 low_ns = 4916; 2254 else 2255 low_ns = hdmi->i2c->scl_low_ns; 2256 2257 div_low = (24000 * low_ns) / 1000000; 2258 if ((24000 * low_ns) % 1000000) 2259 div_low++; 2260 2261 div_high = (24000 * high_ns) / 1000000; 2262 if ((24000 * high_ns) % 1000000) 2263 div_high++; 2264 2265 /* Maximum divider supported by hw is 0xffff */ 2266 if (div_low > 0xffff) 2267 div_low = 0xffff; 2268 2269 if (div_high > 0xffff) 2270 div_high = 0xffff; 2271 2272 hdmi_writeb(hdmi, div_high & 0xff, HDMI_I2CM_SS_SCL_HCNT_0_ADDR); 2273 hdmi_writeb(hdmi, (div_high >> 8) & 0xff, 2274 HDMI_I2CM_SS_SCL_HCNT_1_ADDR); 2275 hdmi_writeb(hdmi, div_low & 0xff, HDMI_I2CM_SS_SCL_LCNT_0_ADDR); 2276 hdmi_writeb(hdmi, (div_low >> 8) & 0xff, 2277 HDMI_I2CM_SS_SCL_LCNT_1_ADDR); 2278 } 2279 2280 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 2281 { 2282 /* Software reset */ 2283 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 2284 2285 /* Set Standard Mode speed */ 2286 hdmi_modb(hdmi, HDMI_I2CM_DIV_STD_MODE, 2287 HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV); 2288 2289 /* Set done, not acknowledged and arbitration interrupt polarities */ 2290 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 2291 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 2292 HDMI_I2CM_CTLINT); 2293 2294 /* Clear DONE and ERROR interrupts */ 2295 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 2296 HDMI_IH_I2CM_STAT0); 2297 2298 /* Mute DONE and ERROR interrupts */ 2299 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 2300 HDMI_IH_MUTE_I2CM_STAT0); 2301 2302 /* set SDA high level holding time */ 2303 hdmi_writeb(hdmi, 0x48, HDMI_I2CM_SDA_HOLD); 2304 2305 dw_hdmi_i2c_set_divs(hdmi); 2306 } 2307 2308 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 2309 { 2310 hdmi->audio_enable = true; 2311 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 2312 } 2313 2314 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 2315 { 2316 hdmi->audio_enable = false; 2317 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 2318 } 2319 2320 int rockchip_dw_hdmi_init(struct rockchip_connector *conn, struct display_state *state) 2321 { 2322 struct connector_state *conn_state = &state->conn_state; 2323 const struct dw_hdmi_plat_data *pdata = 2324 #ifdef CONFIG_SPL_BUILD 2325 (const struct dw_hdmi_plat_data *)conn->data; 2326 #else 2327 (const struct dw_hdmi_plat_data *)dev_get_driver_data(conn->dev); 2328 ofnode hdmi_node = conn->dev->node; 2329 struct device_node *ddc_node; 2330 int ret; 2331 #endif 2332 struct crtc_state *crtc_state = &state->crtc_state; 2333 struct dw_hdmi *hdmi; 2334 struct drm_display_mode *mode_buf; 2335 u32 val; 2336 2337 hdmi = malloc(sizeof(struct dw_hdmi)); 2338 if (!hdmi) 2339 return -ENOMEM; 2340 2341 memset(hdmi, 0, sizeof(struct dw_hdmi)); 2342 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 2343 if (!mode_buf) 2344 return -ENOMEM; 2345 2346 #ifdef CONFIG_SPL_BUILD 2347 hdmi->id = 0; 2348 hdmi->regs = (void *)RK3528_HDMI_BASE; 2349 hdmi->io_width = 4; 2350 hdmi->scramble_low_rates = false; 2351 hdmi->hdcp1x_enable = false; 2352 hdmi->output_bus_format_rgb = false; 2353 conn_state->type = DRM_MODE_CONNECTOR_HDMIA; 2354 #else 2355 hdmi->id = of_alias_get_id(ofnode_to_np(hdmi_node), "hdmi"); 2356 if (hdmi->id < 0) 2357 hdmi->id = 0; 2358 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, hdmi->id); 2359 #endif 2360 2361 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 2362 2363 hdmi->dev_type = pdata->dev_type; 2364 hdmi->plat_data = pdata; 2365 2366 #ifndef CONFIG_SPL_BUILD 2367 hdmi->regs = dev_read_addr_ptr(conn->dev); 2368 hdmi->io_width = ofnode_read_s32_default(hdmi_node, "reg-io-width", -1); 2369 2370 if (ofnode_read_bool(hdmi_node, "scramble-low-rates")) 2371 hdmi->scramble_low_rates = true; 2372 2373 if (ofnode_read_bool(hdmi_node, "hdcp1x-enable")) 2374 hdmi->hdcp1x_enable = true; 2375 else 2376 hdmi->hdcp1x_enable = false; 2377 2378 if (ofnode_read_bool(hdmi_node, "force_output_bus_format_RGB") || 2379 ofnode_read_bool(hdmi_node, "unsupported-yuv-input")) 2380 hdmi->output_bus_format_rgb = true; 2381 else 2382 hdmi->output_bus_format_rgb = false; 2383 2384 ret = dev_read_size(conn->dev, "rockchip,phy-table"); 2385 if (ret > 0 && hdmi->plat_data->phy_config) { 2386 u32 phy_config[ret / 4]; 2387 int i; 2388 2389 dev_read_u32_array(conn->dev, "rockchip,phy-table", phy_config, ret / 4); 2390 2391 for (i = 0; i < ret / 16; i++) { 2392 if (phy_config[i * 4] != 0) 2393 hdmi->plat_data->phy_config[i].mpixelclock = (u64)phy_config[i * 4]; 2394 else 2395 hdmi->plat_data->phy_config[i].mpixelclock = ~0UL; 2396 hdmi->plat_data->phy_config[i].sym_ctr = (u16)phy_config[i * 4 + 1]; 2397 hdmi->plat_data->phy_config[i].term = (u16)phy_config[i * 4 + 2]; 2398 hdmi->plat_data->phy_config[i].vlev_ctr = (u16)phy_config[i * 4 + 3]; 2399 } 2400 } 2401 2402 ddc_node = of_parse_phandle(ofnode_to_np(hdmi_node), "ddc-i2c-bus", 0); 2403 if (ddc_node) { 2404 uclass_get_device_by_ofnode(UCLASS_I2C, np_to_ofnode(ddc_node), 2405 &hdmi->adap.i2c_bus); 2406 if (hdmi->adap.i2c_bus) 2407 hdmi->adap.ops = i2c_get_ops(hdmi->adap.i2c_bus); 2408 } 2409 #endif 2410 2411 hdmi->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 2412 if (hdmi->grf <= 0) { 2413 printf("%s: Get syscon grf failed (ret=%p)\n", 2414 __func__, hdmi->grf); 2415 return -ENXIO; 2416 } 2417 2418 #ifdef CONFIG_SPL_BUILD 2419 hdmi->gpio_base = (void *)RK3528_GPIO_BASE; 2420 #else 2421 ret = gpio_request_by_name(conn->dev, "hpd-gpios", 0, 2422 &hdmi->hpd_gpiod, GPIOD_IS_IN); 2423 if (ret && ret != -ENOENT) { 2424 printf("%s: Cannot get HPD GPIO: %d\n", __func__, ret); 2425 return ret; 2426 } 2427 hdmi->gpio_base = (void *)dev_read_addr_index(conn->dev, 1); 2428 #endif 2429 if (!hdmi->gpio_base) 2430 return -ENODEV; 2431 2432 dw_hdmi_set_reg_wr(hdmi); 2433 2434 if (pdata->grf_vop_sel_reg) { 2435 if (crtc_state->crtc_id) 2436 val = ((1 << pdata->vop_sel_bit) | 2437 (1 << (16 + pdata->vop_sel_bit))); 2438 else 2439 val = ((0 << pdata->vop_sel_bit) | 2440 (1 << (16 + pdata->vop_sel_bit))); 2441 writel(val, hdmi->grf + pdata->grf_vop_sel_reg); 2442 } 2443 2444 hdmi->i2c = malloc(sizeof(struct dw_hdmi_i2c)); 2445 if (!hdmi->i2c) 2446 return -ENOMEM; 2447 hdmi->adap.ddc_xfer = dw_hdmi_i2c_xfer; 2448 2449 /* 2450 * Read high and low time from device tree. If not available use 2451 * the default timing scl clock rate is about 99.6KHz. 2452 */ 2453 #ifdef CONFIG_SPL_BUILD 2454 hdmi->i2c->scl_high_ns = 9625; 2455 hdmi->i2c->scl_low_ns = 10000; 2456 #else 2457 hdmi->i2c->scl_high_ns = 2458 ofnode_read_s32_default(hdmi_node, 2459 "ddc-i2c-scl-high-time-ns", 4708); 2460 hdmi->i2c->scl_low_ns = 2461 ofnode_read_s32_default(hdmi_node, 2462 "ddc-i2c-scl-low-time-ns", 4916); 2463 #endif 2464 2465 dw_hdmi_i2c_init(hdmi); 2466 conn_state->output_if |= VOP_OUTPUT_IF_HDMI0; 2467 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 2468 2469 hdmi->edid_data.mode_buf = mode_buf; 2470 hdmi->sample_rate = 48000; 2471 2472 conn->data = hdmi; 2473 dw_hdmi_set_iomux(hdmi->grf, hdmi->gpio_base, 2474 &hdmi->hpd_gpiod, hdmi->dev_type); 2475 dw_hdmi_detect_phy(hdmi); 2476 dw_hdmi_dev_init(hdmi); 2477 2478 return 0; 2479 } 2480 2481 void rockchip_dw_hdmi_deinit(struct rockchip_connector *conn, struct display_state *state) 2482 { 2483 struct dw_hdmi *hdmi = conn->data; 2484 2485 if (hdmi->i2c) 2486 free(hdmi->i2c); 2487 if (hdmi->edid_data.mode_buf) 2488 free(hdmi->edid_data.mode_buf); 2489 if (hdmi) 2490 free(hdmi); 2491 } 2492 2493 int rockchip_dw_hdmi_prepare(struct rockchip_connector *conn, struct display_state *state) 2494 { 2495 return 0; 2496 } 2497 2498 int rockchip_dw_hdmi_enable(struct rockchip_connector *conn, struct display_state *state) 2499 { 2500 struct connector_state *conn_state = &state->conn_state; 2501 struct drm_display_mode *mode = &conn_state->mode; 2502 struct dw_hdmi *hdmi = conn->data; 2503 2504 if (!hdmi) 2505 return -EFAULT; 2506 2507 /* Store the display mode for plugin/DKMS poweron events */ 2508 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 2509 2510 dw_hdmi_setup(hdmi, conn, mode, state); 2511 2512 return 0; 2513 } 2514 2515 int rockchip_dw_hdmi_disable(struct rockchip_connector *conn, struct display_state *state) 2516 { 2517 struct dw_hdmi *hdmi = conn->data; 2518 2519 dw_hdmi_disable(conn, hdmi, state); 2520 return 0; 2521 } 2522 2523 static void rockchip_dw_hdmi_mode_valid(struct dw_hdmi *hdmi) 2524 { 2525 struct hdmi_edid_data *edid_data = &hdmi->edid_data; 2526 int i; 2527 2528 for (i = 0; i < edid_data->modes; i++) { 2529 if (edid_data->mode_buf[i].invalid) 2530 continue; 2531 2532 if (edid_data->mode_buf[i].clock > 600000) 2533 edid_data->mode_buf[i].invalid = true; 2534 } 2535 } 2536 2537 int rockchip_dw_hdmi_get_timing(struct rockchip_connector *conn, struct display_state *state) 2538 { 2539 int ret, i, vic; 2540 struct connector_state *conn_state = &state->conn_state; 2541 struct drm_display_mode *mode = &conn_state->mode; 2542 struct dw_hdmi *hdmi = conn->data; 2543 struct edid *edid = (struct edid *)conn_state->edid; 2544 unsigned int bus_format; 2545 unsigned long enc_out_encoding; 2546 struct overscan *overscan = &conn_state->overscan; 2547 const u8 def_modes_vic[6] = {4, 16, 2, 17, 31, 19}; 2548 2549 if (!hdmi) 2550 return -EFAULT; 2551 2552 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 2553 2554 if (!ret) { 2555 hdmi->sink_is_hdmi = 2556 drm_detect_hdmi_monitor(edid); 2557 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 2558 ret = drm_add_edid_modes(&hdmi->edid_data, conn_state->edid); 2559 } 2560 if (ret < 0) { 2561 hdmi->sink_is_hdmi = true; 2562 hdmi->sink_has_audio = true; 2563 do_cea_modes(&hdmi->edid_data, def_modes_vic, 2564 sizeof(def_modes_vic)); 2565 hdmi->edid_data.mode_buf[0].type |= DRM_MODE_TYPE_PREFERRED; 2566 hdmi->edid_data.preferred_mode = &hdmi->edid_data.mode_buf[0]; 2567 printf("failed to get edid\n"); 2568 } 2569 #ifdef CONFIG_SPL_BUILD 2570 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, hdmi->id); 2571 #endif 2572 drm_rk_filter_whitelist(&hdmi->edid_data); 2573 rockchip_dw_hdmi_mode_valid(hdmi); 2574 if (hdmi->phy.ops->mode_valid) 2575 hdmi->phy.ops->mode_valid(conn, hdmi, state); 2576 drm_mode_max_resolution_filter(&hdmi->edid_data, 2577 &state->crtc_state.max_output); 2578 if (!drm_mode_prune_invalid(&hdmi->edid_data)) { 2579 printf("can't find valid hdmi mode\n"); 2580 return -EINVAL; 2581 } 2582 2583 for (i = 0; i < hdmi->edid_data.modes; i++) { 2584 hdmi->edid_data.mode_buf[i].vrefresh = 2585 drm_mode_vrefresh(&hdmi->edid_data.mode_buf[i]); 2586 2587 vic = drm_match_cea_mode(&hdmi->edid_data.mode_buf[i]); 2588 if (hdmi->edid_data.mode_buf[i].picture_aspect_ratio == HDMI_PICTURE_ASPECT_NONE) { 2589 if (vic >= 93 && vic <= 95) 2590 hdmi->edid_data.mode_buf[i].picture_aspect_ratio = 2591 HDMI_PICTURE_ASPECT_16_9; 2592 else if (vic == 98) 2593 hdmi->edid_data.mode_buf[i].picture_aspect_ratio = 2594 HDMI_PICTURE_ASPECT_256_135; 2595 } 2596 } 2597 2598 drm_mode_sort(&hdmi->edid_data); 2599 drm_rk_selete_output(&hdmi->edid_data, conn_state, &bus_format, 2600 overscan, hdmi->dev_type, hdmi->output_bus_format_rgb); 2601 2602 *mode = *hdmi->edid_data.preferred_mode; 2603 hdmi->vic = drm_match_cea_mode(mode); 2604 2605 if (state->force_output) { 2606 hdmi->force_output = state->force_output; 2607 hdmi->sink_is_hdmi = true; 2608 hdmi->sink_has_audio = true; 2609 bus_format = state->force_bus_format; 2610 } 2611 conn_state->bus_format = bus_format; 2612 hdmi->hdmi_data.enc_in_bus_format = bus_format; 2613 hdmi->hdmi_data.enc_out_bus_format = bus_format; 2614 2615 switch (bus_format) { 2616 case MEDIA_BUS_FMT_UYVY10_1X20: 2617 conn_state->bus_format = MEDIA_BUS_FMT_YUV10_1X30; 2618 hdmi->hdmi_data.enc_in_bus_format = 2619 MEDIA_BUS_FMT_YUV10_1X30; 2620 break; 2621 case MEDIA_BUS_FMT_UYVY8_1X16: 2622 conn_state->bus_format = MEDIA_BUS_FMT_YUV8_1X24; 2623 hdmi->hdmi_data.enc_in_bus_format = 2624 MEDIA_BUS_FMT_YUV8_1X24; 2625 break; 2626 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 2627 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 2628 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420; 2629 break; 2630 } 2631 2632 if (hdmi->vic == 6 || hdmi->vic == 7 || hdmi->vic == 21 || 2633 hdmi->vic == 22 || hdmi->vic == 2 || hdmi->vic == 3 || 2634 hdmi->vic == 17 || hdmi->vic == 18) 2635 enc_out_encoding = V4L2_YCBCR_ENC_601; 2636 else 2637 enc_out_encoding = V4L2_YCBCR_ENC_709; 2638 2639 if (enc_out_encoding == V4L2_YCBCR_ENC_BT2020) 2640 conn_state->color_space = V4L2_COLORSPACE_BT2020; 2641 else if (bus_format == MEDIA_BUS_FMT_RGB888_1X24 || 2642 bus_format == MEDIA_BUS_FMT_RGB101010_1X30) 2643 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 2644 else if (enc_out_encoding == V4L2_YCBCR_ENC_709) 2645 conn_state->color_space = V4L2_COLORSPACE_REC709; 2646 else 2647 conn_state->color_space = V4L2_COLORSPACE_SMPTE170M; 2648 2649 return 0; 2650 } 2651 2652 int rockchip_dw_hdmi_detect(struct rockchip_connector *conn, struct display_state *state) 2653 { 2654 int ret; 2655 struct dw_hdmi *hdmi = conn->data; 2656 2657 if (!hdmi) 2658 return -EFAULT; 2659 2660 ret = dw_hdmi_detect_hotplug(hdmi, state); 2661 2662 return ret; 2663 } 2664 2665 int rockchip_dw_hdmi_get_edid(struct rockchip_connector *conn, struct display_state *state) 2666 { 2667 int ret; 2668 struct connector_state *conn_state = &state->conn_state; 2669 struct dw_hdmi *hdmi = conn->data; 2670 2671 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 2672 2673 return ret; 2674 } 2675 2676 int inno_dw_hdmi_phy_init(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data) 2677 { 2678 struct display_state *state = (struct display_state *)data; 2679 struct connector_state *conn_state = &state->conn_state; 2680 u32 color_depth, bus_width; 2681 2682 color_depth = 2683 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 2684 2685 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 2686 bus_width = color_depth / 2; 2687 else if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 2688 bus_width = color_depth; 2689 else 2690 bus_width = 8; 2691 rockchip_phy_set_bus_width(conn->phy, bus_width); 2692 rockchip_phy_set_pll(conn->phy, 2693 conn_state->mode.crtc_clock * 1000); 2694 if (hdmi->edid_data.display_info.hdmi.scdc.supported) 2695 rockchip_dw_hdmi_scdc_set_tmds_rate(hdmi); 2696 rockchip_phy_power_on(conn->phy); 2697 2698 return 0; 2699 } 2700 2701 void inno_dw_hdmi_phy_disable(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data) 2702 { 2703 } 2704 2705 enum drm_connector_status 2706 inno_dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data) 2707 { 2708 enum drm_connector_status status; 2709 struct display_state *state = (struct display_state *)data; 2710 2711 status = dw_hdmi_phy_read_hpd(hdmi, state); 2712 2713 if (hdmi->dev_type == RK3328_HDMI) { 2714 if (status == connector_status_connected) 2715 inno_dw_hdmi_set_domain(hdmi->grf, 1); 2716 else 2717 inno_dw_hdmi_set_domain(hdmi->grf, 0); 2718 } 2719 2720 return status; 2721 } 2722 2723 void inno_dw_hdmi_mode_valid(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data) 2724 { 2725 struct hdmi_edid_data *edid_data = &hdmi->edid_data; 2726 unsigned long rate; 2727 int i, ret; 2728 struct drm_display_mode *mode_buf = edid_data->mode_buf; 2729 2730 for (i = 0; i < edid_data->modes; i++) { 2731 if (edid_data->mode_buf[i].invalid) 2732 continue; 2733 if (edid_data->mode_buf[i].flags & DRM_MODE_FLAG_DBLCLK) 2734 rate = mode_buf[i].clock * 1000 * 2; 2735 else 2736 rate = mode_buf[i].clock * 1000; 2737 2738 /* Check whether mode is out of phy cfg range. */ 2739 ret = rockchip_phy_round_rate(conn->phy, rate); 2740 2741 if (ret < 0) 2742 edid_data->mode_buf[i].invalid = true; 2743 } 2744 } 2745