1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <syscon.h> 10 #include <asm/arch-rockchip/clock.h> 11 #include <asm/arch/vendor.h> 12 #include <edid.h> 13 #include <dm/device.h> 14 #include <dm/of_access.h> 15 #include <dm/ofnode.h> 16 #include <dm/read.h> 17 #include <linux/hdmi.h> 18 #include <linux/media-bus-format.h> 19 #include <linux/dw_hdmi.h> 20 #include <asm/io.h> 21 #include "rockchip_display.h" 22 #include "rockchip_crtc.h" 23 #include "rockchip_connector.h" 24 #include "dw_hdmi.h" 25 #include "rockchip_phy.h" 26 27 #define HDCP_PRIVATE_KEY_SIZE 280 28 #define HDCP_KEY_SHA_SIZE 20 29 #define HDMI_HDCP1X_ID 5 30 /* 31 * Unless otherwise noted, entries in this table are 100% optimization. 32 * Values can be obtained from hdmi_compute_n() but that function is 33 * slow so we pre-compute values we expect to see. 34 * 35 * All 32k and 48k values are expected to be the same (due to the way 36 * the math works) for any rate that's an exact kHz. 37 */ 38 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = { 39 { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, }, 40 { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, }, 41 { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 42 { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, }, 43 { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, }, 44 { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, 45 { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, 46 { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 47 { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 48 { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, 49 { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 50 { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, 51 { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 52 { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 53 { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, }, 54 { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 55 { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, }, 56 { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 57 { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 58 { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, }, 59 { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, 60 { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, 61 { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, 62 { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 63 { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 64 { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 65 { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 66 { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 67 { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, 68 { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 69 { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, }, 70 { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, 71 { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 72 { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 73 { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 74 { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, 75 { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 76 77 /* For 297 MHz+ HDMI spec have some other rule for setting N */ 78 { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, }, 79 { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, }, 80 81 /* End of table */ 82 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, }, 83 }; 84 85 static const u16 csc_coeff_default[3][4] = { 86 { 0x2000, 0x0000, 0x0000, 0x0000 }, 87 { 0x0000, 0x2000, 0x0000, 0x0000 }, 88 { 0x0000, 0x0000, 0x2000, 0x0000 } 89 }; 90 91 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 92 { 0x2000, 0x6926, 0x74fd, 0x010e }, 93 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 94 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 95 }; 96 97 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 98 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 99 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 100 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 101 }; 102 103 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 104 { 0x2591, 0x1322, 0x074b, 0x0000 }, 105 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 106 { 0x6acd, 0x7534, 0x2000, 0x0200 } 107 }; 108 109 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 110 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 111 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 112 { 0x6756, 0x78ab, 0x2000, 0x0200 } 113 }; 114 115 static const u16 csc_coeff_full_to_limited[3][4] = { 116 { 0x36f7, 0x0000, 0x0000, 0x0040 }, 117 { 0x0000, 0x36f7, 0x0000, 0x0040 }, 118 { 0x0000, 0x0000, 0x36f7, 0x0040 } 119 }; 120 121 struct hdmi_vmode { 122 bool mdataenablepolarity; 123 124 unsigned int mpixelclock; 125 unsigned int mpixelrepetitioninput; 126 unsigned int mpixelrepetitionoutput; 127 unsigned int mtmdsclock; 128 }; 129 130 struct hdmi_data_info { 131 unsigned int enc_in_bus_format; 132 unsigned int enc_out_bus_format; 133 unsigned int enc_in_encoding; 134 unsigned int enc_out_encoding; 135 unsigned int quant_range; 136 unsigned int pix_repet_factor; 137 struct hdmi_vmode video_mode; 138 }; 139 140 struct dw_hdmi_phy_data { 141 enum dw_hdmi_phy_type type; 142 const char *name; 143 unsigned int gen; 144 bool has_svsret; 145 int (*configure)(struct dw_hdmi *hdmi, 146 const struct dw_hdmi_plat_data *pdata, 147 unsigned long mpixelclock); 148 }; 149 150 struct hdcp_keys { 151 u8 KSV[8]; 152 u8 devicekey[HDCP_PRIVATE_KEY_SIZE]; 153 u8 sha1[HDCP_KEY_SHA_SIZE]; 154 u8 seeds[2]; 155 }; 156 157 struct dw_hdmi_i2c { 158 u8 slave_reg; 159 bool is_regaddr; 160 bool is_segment; 161 162 unsigned int scl_high_ns; 163 unsigned int scl_low_ns; 164 }; 165 166 struct dw_hdmi { 167 enum dw_hdmi_devtype dev_type; 168 unsigned int version; 169 struct hdmi_data_info hdmi_data; 170 struct hdmi_edid_data edid_data; 171 const struct dw_hdmi_plat_data *plat_data; 172 struct ddc_adapter adap; 173 174 int vic; 175 int io_width; 176 177 unsigned long bus_format; 178 bool cable_plugin; 179 bool sink_is_hdmi; 180 bool sink_has_audio; 181 void *regs; 182 void *grf; 183 struct dw_hdmi_i2c *i2c; 184 185 struct { 186 const struct dw_hdmi_phy_ops *ops; 187 const char *name; 188 void *data; 189 bool enabled; 190 } phy; 191 192 struct drm_display_mode previous_mode; 193 194 unsigned int sample_rate; 195 unsigned int audio_cts; 196 unsigned int audio_n; 197 bool audio_enable; 198 bool scramble_low_rates; 199 200 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset); 201 u8 (*read)(struct dw_hdmi *hdmi, int offset); 202 203 bool hdcp1x_enable; 204 }; 205 206 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset) 207 { 208 writel(val, hdmi->regs + (offset << 2)); 209 } 210 211 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset) 212 { 213 return readl(hdmi->regs + (offset << 2)); 214 } 215 216 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 217 { 218 writeb(val, hdmi->regs + offset); 219 } 220 221 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset) 222 { 223 return readb(hdmi->regs + offset); 224 } 225 226 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 227 { 228 hdmi->write(hdmi, val, offset); 229 } 230 231 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 232 { 233 return hdmi->read(hdmi, offset); 234 } 235 236 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 237 { 238 u8 val = hdmi_readb(hdmi, reg) & ~mask; 239 240 val |= data & mask; 241 hdmi_writeb(hdmi, val, reg); 242 } 243 244 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 245 u8 shift, u8 mask) 246 { 247 hdmi_modb(hdmi, data << shift, mask, reg); 248 } 249 250 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 251 { 252 switch (bus_format) { 253 case MEDIA_BUS_FMT_RGB888_1X24: 254 case MEDIA_BUS_FMT_RGB101010_1X30: 255 case MEDIA_BUS_FMT_RGB121212_1X36: 256 case MEDIA_BUS_FMT_RGB161616_1X48: 257 return true; 258 259 default: 260 return false; 261 } 262 } 263 264 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 265 { 266 switch (bus_format) { 267 case MEDIA_BUS_FMT_YUV8_1X24: 268 case MEDIA_BUS_FMT_YUV10_1X30: 269 case MEDIA_BUS_FMT_YUV12_1X36: 270 case MEDIA_BUS_FMT_YUV16_1X48: 271 return true; 272 273 default: 274 return false; 275 } 276 } 277 278 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 279 { 280 switch (bus_format) { 281 case MEDIA_BUS_FMT_UYVY8_1X16: 282 case MEDIA_BUS_FMT_UYVY10_1X20: 283 case MEDIA_BUS_FMT_UYVY12_1X24: 284 return true; 285 286 default: 287 return false; 288 } 289 } 290 291 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 292 { 293 switch (bus_format) { 294 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 295 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 296 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 297 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 298 return true; 299 300 default: 301 return false; 302 } 303 } 304 305 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 306 { 307 switch (bus_format) { 308 case MEDIA_BUS_FMT_RGB888_1X24: 309 case MEDIA_BUS_FMT_YUV8_1X24: 310 case MEDIA_BUS_FMT_UYVY8_1X16: 311 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 312 return 8; 313 314 case MEDIA_BUS_FMT_RGB101010_1X30: 315 case MEDIA_BUS_FMT_YUV10_1X30: 316 case MEDIA_BUS_FMT_UYVY10_1X20: 317 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 318 return 10; 319 320 case MEDIA_BUS_FMT_RGB121212_1X36: 321 case MEDIA_BUS_FMT_YUV12_1X36: 322 case MEDIA_BUS_FMT_UYVY12_1X24: 323 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 324 return 12; 325 326 case MEDIA_BUS_FMT_RGB161616_1X48: 327 case MEDIA_BUS_FMT_YUV16_1X48: 328 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 329 return 16; 330 331 default: 332 return 0; 333 } 334 } 335 336 static int is_color_space_conversion(struct dw_hdmi *hdmi) 337 { 338 struct drm_display_mode *mode = 339 hdmi->edid_data.preferred_mode; 340 bool is_cea_default; 341 342 is_cea_default = (drm_match_cea_mode(mode) > 1) && 343 (hdmi->hdmi_data.quant_range == 344 HDMI_QUANTIZATION_RANGE_DEFAULT); 345 346 /* 347 * When output is rgb limited range or default range with 348 * cea mode, csc should be enabled. 349 */ 350 if (hdmi->hdmi_data.enc_in_bus_format != 351 hdmi->hdmi_data.enc_out_bus_format || 352 ((hdmi->hdmi_data.quant_range == HDMI_QUANTIZATION_RANGE_LIMITED || 353 is_cea_default) && 354 hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format))) 355 return 1; 356 357 return 0; 358 } 359 360 static int is_color_space_decimation(struct dw_hdmi *hdmi) 361 { 362 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 363 return 0; 364 365 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 366 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 367 return 1; 368 369 return 0; 370 } 371 372 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 373 unsigned char bit) 374 { 375 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 376 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 377 } 378 379 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi, 380 unsigned char bit) 381 { 382 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET, 383 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0); 384 } 385 386 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi, 387 unsigned char bit) 388 { 389 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET, 390 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0); 391 } 392 393 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi, 394 unsigned char bit) 395 { 396 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1); 397 } 398 399 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi, 400 unsigned char bit) 401 { 402 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2); 403 } 404 405 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 406 unsigned char *buf, unsigned int length) 407 { 408 struct dw_hdmi_i2c *i2c = hdmi->i2c; 409 int interrupt = 0, i = 20; 410 411 if (!i2c->is_regaddr) { 412 printf("set read register address to 0\n"); 413 i2c->slave_reg = 0x00; 414 i2c->is_regaddr = true; 415 } 416 417 while (length--) { 418 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 419 if (i2c->is_segment) 420 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 421 HDMI_I2CM_OPERATION); 422 else 423 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 424 HDMI_I2CM_OPERATION); 425 426 while (i--) { 427 udelay(1000); 428 interrupt = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 429 if (interrupt) 430 hdmi_writeb(hdmi, interrupt, 431 HDMI_IH_I2CM_STAT0); 432 if (interrupt & (m_SCDC_READREQ | m_I2CM_DONE | 433 m_I2CM_ERROR)) 434 break; 435 } 436 437 if (!interrupt) { 438 printf("[%s] i2c read reg[0x%02x] no interrupt\n", 439 __func__, i2c->slave_reg); 440 return -EAGAIN; 441 } 442 443 /* Check for error condition on the bus */ 444 if (interrupt & HDMI_IH_I2CM_STAT0_ERROR) { 445 printf("[%s] read reg[0x%02x] data error:0x%02x\n", 446 __func__, i2c->slave_reg, interrupt); 447 return -EIO; 448 } 449 450 i = 20; 451 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 452 } 453 i2c->is_segment = false; 454 455 return 0; 456 } 457 458 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 459 unsigned char *buf, unsigned int length) 460 { 461 struct dw_hdmi_i2c *i2c = hdmi->i2c; 462 int i = 20; 463 u8 interrupt = 0; 464 465 if (!i2c->is_regaddr) { 466 /* Use the first write byte as register address */ 467 i2c->slave_reg = buf[0]; 468 length--; 469 buf++; 470 i2c->is_regaddr = true; 471 } 472 473 while (length--) { 474 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 475 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 476 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 477 HDMI_I2CM_OPERATION); 478 479 while (i--) { 480 udelay(1000); 481 interrupt = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 482 if (interrupt) 483 hdmi_writeb(hdmi, 484 interrupt, HDMI_IH_I2CM_STAT0); 485 486 if (interrupt & (m_SCDC_READREQ | 487 m_I2CM_DONE | m_I2CM_ERROR)) 488 break; 489 } 490 491 if ((interrupt & m_I2CM_ERROR) || (i == -1)) { 492 printf("[%s] write data error\n", __func__); 493 return -EIO; 494 } else if (interrupt & m_I2CM_DONE) { 495 printf("[%s] write offset %02x success\n", 496 __func__, i2c->slave_reg); 497 return -EAGAIN; 498 } 499 500 i = 20; 501 } 502 503 return 0; 504 } 505 506 static int dw_hdmi_i2c_xfer(struct ddc_adapter *adap, 507 struct i2c_msg *msgs, int num) 508 { 509 struct dw_hdmi *hdmi = container_of(adap, struct dw_hdmi, adap); 510 struct dw_hdmi_i2c *i2c = hdmi->i2c; 511 u8 addr = msgs[0].addr; 512 int i, ret = 0; 513 514 printf("xfer: num: %d, addr: %#x\n", num, addr); 515 for (i = 0; i < num; i++) { 516 if (msgs[i].len == 0) { 517 printf("unsupported transfer %d/%d, no data\n", 518 i + 1, num); 519 return -EOPNOTSUPP; 520 } 521 } 522 523 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 524 525 /* Set slave device address taken from the first I2C message */ 526 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1) 527 addr = DDC_ADDR; 528 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 529 530 /* Set slave device register address on transfer */ 531 i2c->is_regaddr = false; 532 533 /* Set segment pointer for I2C extended read mode operation */ 534 i2c->is_segment = false; 535 536 for (i = 0; i < num; i++) { 537 debug("xfer: num: %d/%d, len: %d, flags: %#x\n", 538 i + 1, num, msgs[i].len, msgs[i].flags); 539 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 540 i2c->is_segment = true; 541 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 542 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 543 } else { 544 if (msgs[i].flags & I2C_M_RD) 545 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 546 msgs[i].len); 547 else 548 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 549 msgs[i].len); 550 } 551 if (ret < 0) 552 break; 553 } 554 555 if (!ret) 556 ret = num; 557 558 /* Mute DONE and ERROR interrupts */ 559 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 560 HDMI_IH_MUTE_I2CM_STAT0); 561 562 return ret; 563 } 564 565 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 566 { 567 u32 val; 568 569 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 570 if (msec-- == 0) 571 return false; 572 udelay(1000); 573 } 574 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 575 576 return true; 577 } 578 579 static void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 580 unsigned char addr) 581 { 582 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 583 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 584 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 585 HDMI_PHY_I2CM_DATAO_1_ADDR); 586 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 587 HDMI_PHY_I2CM_DATAO_0_ADDR); 588 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 589 HDMI_PHY_I2CM_OPERATION_ADDR); 590 hdmi_phy_wait_i2c_done(hdmi, 1000); 591 } 592 593 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 594 { 595 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 596 HDMI_PHY_CONF0_PDZ_OFFSET, 597 HDMI_PHY_CONF0_PDZ_MASK); 598 } 599 600 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 601 { 602 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 603 HDMI_PHY_CONF0_ENTMDS_OFFSET, 604 HDMI_PHY_CONF0_ENTMDS_MASK); 605 } 606 607 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 608 { 609 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 610 HDMI_PHY_CONF0_SVSRET_OFFSET, 611 HDMI_PHY_CONF0_SVSRET_MASK); 612 } 613 614 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 615 { 616 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 617 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 618 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 619 } 620 621 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 622 { 623 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 624 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 625 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 626 } 627 628 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 629 { 630 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 631 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 632 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 633 } 634 635 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 636 { 637 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 638 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 639 HDMI_PHY_CONF0_SELDIPIF_MASK); 640 } 641 642 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 643 { 644 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 645 unsigned int i; 646 u16 val; 647 648 if (phy->gen == 1) { 649 dw_hdmi_phy_enable_tmds(hdmi, 0); 650 dw_hdmi_phy_enable_powerdown(hdmi, true); 651 return; 652 } 653 654 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 655 656 /* 657 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 658 * to low power mode. 659 */ 660 for (i = 0; i < 5; ++i) { 661 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 662 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 663 break; 664 665 udelay(2000); 666 } 667 668 if (val & HDMI_PHY_TX_PHY_LOCK) 669 printf("PHY failed to power down\n"); 670 else 671 printf("PHY powered down in %u iterations\n", i); 672 673 dw_hdmi_phy_gen2_pddq(hdmi, 1); 674 } 675 676 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 677 { 678 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 679 unsigned int i; 680 u8 val; 681 682 if (phy->gen == 1) { 683 dw_hdmi_phy_enable_powerdown(hdmi, false); 684 685 /* Toggle TMDS enable. */ 686 dw_hdmi_phy_enable_tmds(hdmi, 0); 687 dw_hdmi_phy_enable_tmds(hdmi, 1); 688 return 0; 689 } 690 691 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 692 dw_hdmi_phy_gen2_pddq(hdmi, 0); 693 694 /* Wait for PHY PLL lock */ 695 for (i = 0; i < 5; ++i) { 696 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 697 if (val) 698 break; 699 700 udelay(2000); 701 } 702 703 if (!val) { 704 printf("PHY PLL failed to lock\n"); 705 return -ETIMEDOUT; 706 } 707 printf("PHY PLL locked %u iterations\n", i); 708 709 return 0; 710 } 711 712 /* 713 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 714 * information the DWC MHL PHY has the same register layout and is thus also 715 * supported by this function. 716 */ 717 static 718 int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 719 const struct dw_hdmi_plat_data *pdata, 720 unsigned long mpixelclock) 721 { 722 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 723 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 724 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 725 unsigned int tmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 726 unsigned int depth = 727 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 728 729 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) && 730 pdata->mpll_cfg_420) 731 mpll_config = pdata->mpll_cfg_420; 732 733 /* PLL/MPLL Cfg - always match on final entry */ 734 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 735 if (mpixelclock <= mpll_config->mpixelclock) 736 break; 737 738 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 739 if (tmdsclock <= curr_ctrl->mpixelclock) 740 break; 741 742 for (; phy_config->mpixelclock != ~0UL; phy_config++) 743 if (tmdsclock <= phy_config->mpixelclock) 744 break; 745 746 if (mpll_config->mpixelclock == ~0UL || 747 curr_ctrl->mpixelclock == ~0UL || 748 phy_config->mpixelclock == ~0UL) 749 return -EINVAL; 750 751 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 752 depth = fls(depth - 8); 753 else 754 depth = 0; 755 if (depth) 756 depth--; 757 758 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].cpce, 759 HDMI_3D_TX_PHY_CPCE_CTRL); 760 761 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].gmp, 762 HDMI_3D_TX_PHY_GMPCTRL); 763 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[depth], 764 HDMI_3D_TX_PHY_CURRCTRL); 765 766 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 767 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 768 HDMI_3D_TX_PHY_MSM_CTRL); 769 770 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 771 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 772 HDMI_3D_TX_PHY_CKSYMTXCTRL); 773 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 774 HDMI_3D_TX_PHY_VLEVCTRL); 775 776 return 0; 777 } 778 779 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 780 { 781 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 782 .name = "DWC HDMI TX PHY", 783 .gen = 1, 784 }, { 785 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 786 .name = "DWC MHL PHY + HEAC PHY", 787 .gen = 2, 788 .has_svsret = true, 789 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 790 }, { 791 .type = DW_HDMI_PHY_DWC_MHL_PHY, 792 .name = "DWC MHL PHY", 793 .gen = 2, 794 .has_svsret = true, 795 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 796 }, { 797 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 798 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 799 .gen = 2, 800 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 801 }, { 802 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 803 .name = "DWC HDMI 3D TX PHY", 804 .gen = 2, 805 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 806 }, { 807 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 808 .name = "DWC HDMI 2.0 TX PHY", 809 .gen = 2, 810 .has_svsret = true, 811 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 812 }, { 813 .type = DW_HDMI_PHY_VENDOR_PHY, 814 .name = "Vendor PHY", 815 } 816 }; 817 818 static int rockchip_dw_hdmi_scrambling_enable(struct dw_hdmi *hdmi, 819 int enable) 820 { 821 u8 stat; 822 823 drm_scdc_readb(&hdmi->adap, SCDC_TMDS_CONFIG, &stat); 824 825 if (stat < 0) { 826 debug("Failed to read tmds config\n"); 827 return false; 828 } 829 830 if (enable == 1) { 831 /* Write on Rx the bit Scrambling_Enable, register 0x20 */ 832 stat |= SCDC_SCRAMBLING_ENABLE; 833 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 834 /* TMDS software reset request */ 835 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 836 HDMI_MC_SWRSTZ); 837 /* Enable/Disable Scrambling */ 838 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); 839 } else { 840 /* Enable/Disable Scrambling */ 841 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); 842 /* TMDS software reset request */ 843 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 844 HDMI_MC_SWRSTZ); 845 /* Write on Rx the bit Scrambling_Enable, register 0x20 */ 846 stat &= ~SCDC_SCRAMBLING_ENABLE; 847 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 848 } 849 850 return 0; 851 } 852 853 static void rockchip_dw_hdmi_scdc_set_tmds_rate(struct dw_hdmi *hdmi) 854 { 855 u8 stat; 856 857 drm_scdc_readb(&hdmi->adap, SCDC_TMDS_CONFIG, &stat); 858 if (hdmi->hdmi_data.video_mode.mtmdsclock > 340000000) 859 stat |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 860 else 861 stat &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 862 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 863 } 864 865 static int hdmi_phy_configure(struct dw_hdmi *hdmi) 866 { 867 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 868 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 869 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 870 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 871 int ret; 872 873 dw_hdmi_phy_power_off(hdmi); 874 875 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ 876 if (hdmi->edid_data.display_info.hdmi.scdc.supported) 877 rockchip_dw_hdmi_scdc_set_tmds_rate(hdmi); 878 879 /* Leave low power consumption mode by asserting SVSRET. */ 880 if (phy->has_svsret) 881 dw_hdmi_phy_enable_svsret(hdmi, 1); 882 883 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 884 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 885 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 886 887 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 888 889 hdmi_phy_test_clear(hdmi, 1); 890 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, 891 HDMI_PHY_I2CM_SLAVE_ADDR); 892 hdmi_phy_test_clear(hdmi, 0); 893 894 /* Write to the PHY as configured by the platform */ 895 if (pdata->configure_phy) 896 ret = pdata->configure_phy(hdmi, pdata, mpixelclock); 897 else 898 ret = phy->configure(hdmi, pdata, mpixelclock); 899 if (ret) { 900 printf("PHY configuration failed (clock %lu)\n", 901 mpixelclock); 902 return ret; 903 } 904 905 /* Wait for resuming transmission of TMDS clock and data */ 906 if (mtmdsclock > 340000000) 907 mdelay(100); 908 909 return dw_hdmi_phy_power_on(hdmi); 910 } 911 912 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, 913 void *data) 914 { 915 int i, ret; 916 917 /* HDMI Phy spec says to do the phy initialization sequence twice */ 918 for (i = 0; i < 2; i++) { 919 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 920 dw_hdmi_phy_sel_interface_control(hdmi, 0); 921 ret = hdmi_phy_configure(hdmi); 922 if (ret) 923 return ret; 924 } 925 926 return 0; 927 } 928 929 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, 930 void *data) 931 { 932 dw_hdmi_phy_power_off(hdmi); 933 } 934 935 static enum drm_connector_status 936 dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data) 937 { 938 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 939 connector_status_connected : connector_status_disconnected; 940 } 941 942 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 943 .init = dw_hdmi_phy_init, 944 .disable = dw_hdmi_phy_disable, 945 .read_hpd = dw_hdmi_phy_read_hpd, 946 }; 947 948 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 949 { 950 unsigned int i; 951 u8 phy_type; 952 953 phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID); 954 955 /* 956 * RK3228 and RK3328 phy_type is DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 957 * but it has a vedor phy. 958 */ 959 if (phy_type == DW_HDMI_PHY_VENDOR_PHY || 960 hdmi->dev_type == RK3328_HDMI || 961 hdmi->dev_type == RK3228_HDMI) { 962 /* Vendor PHYs require support from the glue layer. */ 963 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 964 printf( 965 "Vendor HDMI PHY not supported by glue layer\n"); 966 return -ENODEV; 967 } 968 969 hdmi->phy.ops = hdmi->plat_data->phy_ops; 970 hdmi->phy.data = hdmi->plat_data->phy_data; 971 hdmi->phy.name = hdmi->plat_data->phy_name; 972 return 0; 973 } 974 975 /* Synopsys PHYs are handled internally. */ 976 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 977 if (dw_hdmi_phys[i].type == phy_type) { 978 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 979 hdmi->phy.name = dw_hdmi_phys[i].name; 980 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 981 982 if (!dw_hdmi_phys[i].configure && 983 !hdmi->plat_data->configure_phy) { 984 printf("%s requires platform support\n", 985 hdmi->phy.name); 986 return -ENODEV; 987 } 988 989 return 0; 990 } 991 } 992 993 printf("Unsupported HDMI PHY type (%02x)\n", phy_type); 994 return -ENODEV; 995 } 996 997 static unsigned int 998 hdmi_get_tmdsclock(struct dw_hdmi *hdmi, unsigned long mpixelclock) 999 { 1000 unsigned int tmdsclock = mpixelclock; 1001 unsigned int depth = 1002 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 1003 1004 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1005 switch (depth) { 1006 case 16: 1007 tmdsclock = mpixelclock * 2; 1008 break; 1009 case 12: 1010 tmdsclock = mpixelclock * 3 / 2; 1011 break; 1012 case 10: 1013 tmdsclock = mpixelclock * 5 / 4; 1014 break; 1015 default: 1016 break; 1017 } 1018 } 1019 1020 return tmdsclock; 1021 } 1022 1023 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1024 const struct drm_display_mode *mode) 1025 { 1026 u8 bytes = 0, inv_val = 0; 1027 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1028 struct drm_hdmi_info *hdmi_info = &hdmi->edid_data.display_info.hdmi; 1029 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1030 unsigned int hdisplay, vdisplay; 1031 1032 vmode->mpixelclock = mode->crtc_clock * 1000; 1033 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == 1034 DRM_MODE_FLAG_3D_FRAME_PACKING) 1035 vmode->mpixelclock *= 2; 1036 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock); 1037 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1038 vmode->mtmdsclock /= 2; 1039 printf("final pixclk = %d tmdsclk = %d\n", 1040 vmode->mpixelclock, vmode->mtmdsclock); 1041 1042 /* Set up HDMI_FC_INVIDCONF 1043 * fc_invidconf.HDCP_keepout must be set (1'b1) 1044 * when activate the scrambler feature. 1045 */ 1046 inv_val = (vmode->mtmdsclock > 340000000 || 1047 (hdmi_info->scdc.scrambling.low_rates && 1048 hdmi->scramble_low_rates) ? 1049 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 1050 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 1051 1052 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 1053 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 1054 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 1055 1056 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 1057 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 1058 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 1059 1060 inv_val |= (vmode->mdataenablepolarity ? 1061 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 1062 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 1063 1064 if (hdmi->vic == 39) 1065 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 1066 else 1067 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1068 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 1069 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 1070 1071 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1072 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 1073 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 1074 1075 inv_val |= hdmi->sink_is_hdmi ? 1076 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 1077 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 1078 1079 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 1080 1081 hdisplay = mode->hdisplay; 1082 hblank = mode->htotal - mode->hdisplay; 1083 h_de_hs = mode->hsync_start - mode->hdisplay; 1084 hsync_len = mode->hsync_end - mode->hsync_start; 1085 1086 /* 1087 * When we're setting a YCbCr420 mode, we need 1088 * to adjust the horizontal timing to suit. 1089 */ 1090 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1091 hdisplay /= 2; 1092 hblank /= 2; 1093 h_de_hs /= 2; 1094 hsync_len /= 2; 1095 } 1096 1097 vdisplay = mode->vdisplay; 1098 vblank = mode->vtotal - mode->vdisplay; 1099 v_de_vs = mode->vsync_start - mode->vdisplay; 1100 vsync_len = mode->vsync_end - mode->vsync_start; 1101 1102 /* 1103 * When we're setting an interlaced mode, we need 1104 * to adjust the vertical timing to suit. 1105 */ 1106 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1107 vdisplay /= 2; 1108 vblank /= 2; 1109 v_de_vs /= 2; 1110 vsync_len /= 2; 1111 } else if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == 1112 DRM_MODE_FLAG_3D_FRAME_PACKING) { 1113 vdisplay += mode->vtotal; 1114 } 1115 1116 /* Scrambling Control */ 1117 if (hdmi_info->scdc.supported) { 1118 if (vmode->mtmdsclock > 340000000 || 1119 (hdmi_info->scdc.scrambling.low_rates && 1120 hdmi->scramble_low_rates)) { 1121 drm_scdc_readb(&hdmi->adap, SCDC_SINK_VERSION, &bytes); 1122 drm_scdc_writeb(&hdmi->adap, SCDC_SOURCE_VERSION, 1123 bytes); 1124 rockchip_dw_hdmi_scrambling_enable(hdmi, 1); 1125 } else { 1126 rockchip_dw_hdmi_scrambling_enable(hdmi, 0); 1127 } 1128 } 1129 1130 /* Set up horizontal active pixel width */ 1131 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1); 1132 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0); 1133 1134 /* Set up vertical active lines */ 1135 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 1136 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 1137 1138 /* Set up horizontal blanking pixel region width */ 1139 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 1140 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 1141 1142 /* Set up vertical blanking pixel region width */ 1143 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 1144 1145 /* Set up HSYNC active edge delay width (in pixel clks) */ 1146 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 1147 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 1148 1149 /* Set up VSYNC active edge delay (in lines) */ 1150 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 1151 1152 /* Set up HSYNC active pulse width (in pixel clks) */ 1153 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 1154 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 1155 1156 /* Set up VSYNC active edge delay (in lines) */ 1157 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 1158 } 1159 1160 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 1161 { 1162 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 1163 unsigned i; 1164 u32 csc_scale = 1; 1165 int enc_out_rgb, enc_in_rgb; 1166 1167 enc_out_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format); 1168 enc_in_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format); 1169 1170 if (is_color_space_conversion(hdmi)) { 1171 if (enc_out_rgb && enc_in_rgb) { 1172 csc_coeff = &csc_coeff_full_to_limited; 1173 csc_scale = 0; 1174 } else if (enc_out_rgb) { 1175 if (hdmi->hdmi_data.enc_out_encoding == 1176 V4L2_YCBCR_ENC_601) 1177 csc_coeff = &csc_coeff_rgb_out_eitu601; 1178 else 1179 csc_coeff = &csc_coeff_rgb_out_eitu709; 1180 } else if (enc_in_rgb) { 1181 if (hdmi->hdmi_data.enc_out_encoding == 1182 V4L2_YCBCR_ENC_601) 1183 csc_coeff = &csc_coeff_rgb_in_eitu601; 1184 else 1185 csc_coeff = &csc_coeff_rgb_in_eitu709; 1186 csc_scale = 0; 1187 } 1188 } 1189 1190 /* The CSC registers are sequential, alternating MSB then LSB */ 1191 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 1192 u16 coeff_a = (*csc_coeff)[0][i]; 1193 u16 coeff_b = (*csc_coeff)[1][i]; 1194 u16 coeff_c = (*csc_coeff)[2][i]; 1195 1196 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 1197 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 1198 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 1199 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 1200 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 1201 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 1202 } 1203 1204 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 1205 HDMI_CSC_SCALE); 1206 } 1207 1208 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 1209 { 1210 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 1211 return 0; 1212 1213 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1214 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1215 return 1; 1216 1217 return 0; 1218 } 1219 1220 static void hdmi_video_csc(struct dw_hdmi *hdmi) 1221 { 1222 int color_depth = 0; 1223 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 1224 int decimation = 0; 1225 1226 /* YCC422 interpolation to 444 mode */ 1227 if (is_color_space_interpolation(hdmi)) 1228 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 1229 else if (is_color_space_decimation(hdmi)) 1230 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 1231 1232 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 1233 case 8: 1234 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 1235 break; 1236 case 10: 1237 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 1238 break; 1239 case 12: 1240 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 1241 break; 1242 case 16: 1243 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 1244 break; 1245 1246 default: 1247 return; 1248 } 1249 1250 /* Configure the CSC registers */ 1251 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 1252 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 1253 HDMI_CSC_SCALE); 1254 1255 dw_hdmi_update_csc_coeffs(hdmi); 1256 } 1257 1258 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 1259 { 1260 u8 clkdis; 1261 1262 /* control period minimum duration */ 1263 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 1264 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 1265 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 1266 1267 /* Set to fill TMDS data channels */ 1268 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 1269 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 1270 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 1271 1272 /* Enable pixel clock and tmds data path */ 1273 clkdis = 0x7F; 1274 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 1275 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1276 1277 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1278 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1279 1280 /* Enable csc path */ 1281 if (is_color_space_conversion(hdmi)) { 1282 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 1283 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1284 } 1285 1286 /* Enable pixel repetition path */ 1287 if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) { 1288 clkdis &= ~HDMI_MC_CLKDIS_PREPCLK_DISABLE; 1289 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1290 } 1291 1292 /* Enable color space conversion if needed */ 1293 if (is_color_space_conversion(hdmi)) 1294 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 1295 HDMI_MC_FLOWCTRL); 1296 else 1297 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 1298 HDMI_MC_FLOWCTRL); 1299 } 1300 1301 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 1302 { 1303 unsigned int count; 1304 unsigned int i; 1305 u8 val; 1306 1307 /* 1308 * Under some circumstances the Frame Composer arithmetic unit can miss 1309 * an FC register write due to being busy processing the previous one. 1310 * The issue can be worked around by issuing a TMDS software reset and 1311 * then write one of the FC registers several times. 1312 * 1313 * The number of iterations matters and depends on the HDMI TX revision 1314 * (and possibly on the platform). So far only i.MX6Q (v1.30a) and 1315 * i.MX6DL (v1.31a) have been identified as needing the workaround, with 1316 * 4 and 1 iterations respectively. 1317 */ 1318 1319 switch (hdmi->version) { 1320 case 0x130a: 1321 count = 4; 1322 break; 1323 case 0x131a: 1324 case 0x200a: 1325 case 0x201a: 1326 case 0x211a: 1327 count = 1; 1328 break; 1329 default: 1330 return; 1331 } 1332 1333 /* TMDS software reset */ 1334 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 1335 1336 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 1337 for (i = 0; i < count; i++) 1338 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 1339 } 1340 1341 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 1342 { 1343 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 1344 HDMI_IH_MUTE_FC_STAT2); 1345 } 1346 1347 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 1348 { 1349 unsigned int color_depth = 0; 1350 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 1351 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 1352 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1353 u8 val, vp_conf; 1354 1355 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1356 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) || 1357 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1358 switch (hdmi_bus_fmt_color_depth( 1359 hdmi->hdmi_data.enc_out_bus_format)) { 1360 case 8: 1361 color_depth = 0; 1362 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1363 break; 1364 case 10: 1365 color_depth = 5; 1366 break; 1367 case 12: 1368 color_depth = 6; 1369 break; 1370 case 16: 1371 color_depth = 7; 1372 break; 1373 default: 1374 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1375 } 1376 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1377 switch (hdmi_bus_fmt_color_depth( 1378 hdmi->hdmi_data.enc_out_bus_format)) { 1379 case 0: 1380 case 8: 1381 remap_size = HDMI_VP_REMAP_YCC422_16bit; 1382 break; 1383 case 10: 1384 remap_size = HDMI_VP_REMAP_YCC422_20bit; 1385 break; 1386 case 12: 1387 remap_size = HDMI_VP_REMAP_YCC422_24bit; 1388 break; 1389 1390 default: 1391 return; 1392 } 1393 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 1394 } else { 1395 return; 1396 } 1397 1398 /* set the packetizer registers */ 1399 val = (color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 1400 HDMI_VP_PR_CD_COLOR_DEPTH_MASK; 1401 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 1402 1403 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 1404 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 1405 1406 /* Data from pixel repeater block */ 1407 if (hdmi_data->pix_repet_factor > 0) { 1408 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 1409 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 1410 } else { /* data from packetizer block */ 1411 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 1412 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 1413 } 1414 1415 hdmi_modb(hdmi, vp_conf, 1416 HDMI_VP_CONF_PR_EN_MASK | 1417 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 1418 1419 if ((color_depth == 5 && hdmi->previous_mode.htotal % 4) || 1420 (color_depth == 6 && hdmi->previous_mode.htotal % 2)) 1421 hdmi_modb(hdmi, 0, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, 1422 HDMI_VP_STUFF); 1423 else 1424 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 1425 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 1426 1427 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 1428 1429 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 1430 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1431 HDMI_VP_CONF_PP_EN_ENABLE | 1432 HDMI_VP_CONF_YCC422_EN_DISABLE; 1433 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 1434 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1435 HDMI_VP_CONF_PP_EN_DISABLE | 1436 HDMI_VP_CONF_YCC422_EN_ENABLE; 1437 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 1438 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 1439 HDMI_VP_CONF_PP_EN_DISABLE | 1440 HDMI_VP_CONF_YCC422_EN_DISABLE; 1441 } else { 1442 return; 1443 } 1444 1445 hdmi_modb(hdmi, vp_conf, 1446 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 1447 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 1448 1449 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 1450 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 1451 HDMI_VP_STUFF_PP_STUFFING_MASK | 1452 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 1453 1454 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 1455 HDMI_VP_CONF); 1456 } 1457 1458 static void hdmi_video_sample(struct dw_hdmi *hdmi) 1459 { 1460 int color_format = 0; 1461 u8 val; 1462 1463 switch (hdmi->hdmi_data.enc_in_bus_format) { 1464 case MEDIA_BUS_FMT_RGB888_1X24: 1465 color_format = 0x01; 1466 break; 1467 case MEDIA_BUS_FMT_RGB101010_1X30: 1468 color_format = 0x03; 1469 break; 1470 case MEDIA_BUS_FMT_RGB121212_1X36: 1471 color_format = 0x05; 1472 break; 1473 case MEDIA_BUS_FMT_RGB161616_1X48: 1474 color_format = 0x07; 1475 break; 1476 1477 case MEDIA_BUS_FMT_YUV8_1X24: 1478 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1479 color_format = 0x09; 1480 break; 1481 case MEDIA_BUS_FMT_YUV10_1X30: 1482 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1483 color_format = 0x0B; 1484 break; 1485 case MEDIA_BUS_FMT_YUV12_1X36: 1486 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 1487 color_format = 0x0D; 1488 break; 1489 case MEDIA_BUS_FMT_YUV16_1X48: 1490 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 1491 color_format = 0x0F; 1492 break; 1493 1494 case MEDIA_BUS_FMT_UYVY8_1X16: 1495 color_format = 0x16; 1496 break; 1497 case MEDIA_BUS_FMT_UYVY10_1X20: 1498 color_format = 0x14; 1499 break; 1500 case MEDIA_BUS_FMT_UYVY12_1X24: 1501 color_format = 0x12; 1502 break; 1503 1504 default: 1505 return; 1506 } 1507 1508 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 1509 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 1510 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 1511 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 1512 1513 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 1514 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 1515 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 1516 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 1517 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 1518 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 1519 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 1520 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 1521 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 1522 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 1523 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 1524 } 1525 1526 static void dw_hdmi_disable(struct dw_hdmi *hdmi, struct display_state *state) 1527 { 1528 if (hdmi->phy.enabled) { 1529 hdmi->phy.ops->disable(hdmi, state); 1530 hdmi->phy.enabled = false; 1531 } 1532 } 1533 1534 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1535 { 1536 struct hdmi_avi_infoframe frame; 1537 u8 val; 1538 bool is_hdmi2 = false; 1539 enum hdmi_quantization_range rgb_quant_range = 1540 hdmi->hdmi_data.quant_range; 1541 1542 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) || 1543 hdmi->edid_data.display_info.hdmi.scdc.supported) 1544 is_hdmi2 = true; 1545 /* Initialise info frame from DRM mode */ 1546 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2); 1547 1548 /* 1549 * Ignore monitor selectable quantization, use quantization set 1550 * by the user 1551 */ 1552 drm_hdmi_avi_infoframe_quant_range(&frame, mode, rgb_quant_range, 1553 true); 1554 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1555 frame.colorspace = HDMI_COLORSPACE_YUV444; 1556 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1557 frame.colorspace = HDMI_COLORSPACE_YUV422; 1558 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1559 frame.colorspace = HDMI_COLORSPACE_YUV420; 1560 else 1561 frame.colorspace = HDMI_COLORSPACE_RGB; 1562 1563 /* Set up colorimetry */ 1564 switch (hdmi->hdmi_data.enc_out_encoding) { 1565 case V4L2_YCBCR_ENC_601: 1566 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1567 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1568 else 1569 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1570 frame.extended_colorimetry = 1571 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1572 break; 1573 case V4L2_YCBCR_ENC_709: 1574 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1575 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1576 else 1577 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1578 frame.extended_colorimetry = 1579 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1580 break; 1581 default: /* Carries no data */ 1582 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1583 frame.extended_colorimetry = 1584 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1585 break; 1586 } 1587 1588 frame.scan_mode = HDMI_SCAN_MODE_NONE; 1589 1590 /* 1591 * The Designware IP uses a different byte format from standard 1592 * AVI info frames, though generally the bits are in the correct 1593 * bytes. 1594 */ 1595 1596 /* 1597 * AVI data byte 1 differences: Colorspace in bits 0,1,7 rather than 1598 * 5,6,7, active aspect present in bit 6 rather than 4. 1599 */ 1600 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 0x3); 1601 if (frame.active_aspect & 15) 1602 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1603 if (frame.top_bar || frame.bottom_bar) 1604 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1605 if (frame.left_bar || frame.right_bar) 1606 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1607 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1608 1609 /* AVI data byte 2 differences: none */ 1610 val = ((frame.colorimetry & 0x3) << 6) | 1611 ((frame.picture_aspect & 0x3) << 4) | 1612 (frame.active_aspect & 0xf); 1613 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1614 1615 /* AVI data byte 3 differences: none */ 1616 val = ((frame.extended_colorimetry & 0x7) << 4) | 1617 ((frame.quantization_range & 0x3) << 2) | 1618 (frame.nups & 0x3); 1619 if (frame.itc) 1620 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1621 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1622 1623 /* AVI data byte 4 differences: none */ 1624 val = frame.video_code & 0x7f; 1625 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1626 1627 /* AVI Data Byte 5- set up input and output pixel repetition */ 1628 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1629 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1630 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1631 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1632 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1633 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1634 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1635 1636 /* 1637 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1638 * ycc range in bits 2,3 rather than 6,7 1639 */ 1640 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1641 (frame.content_type & 0x3); 1642 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1643 1644 /* AVI Data Bytes 6-13 */ 1645 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1646 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1647 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1648 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1649 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1650 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1651 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1652 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1653 } 1654 1655 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1656 struct drm_display_mode *mode) 1657 { 1658 struct hdmi_vendor_infoframe frame; 1659 u8 buffer[10]; 1660 ssize_t err; 1661 1662 /* Disable HDMI vendor specific infoframe send */ 1663 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1664 HDMI_FC_DATAUTO0_VSD_MASK); 1665 1666 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode); 1667 if (err < 0) 1668 /* 1669 * Going into that statement does not means vendor infoframe 1670 * fails. It just informed us that vendor infoframe is not 1671 * needed for the selected mode. Only 4k or stereoscopic 3D 1672 * mode requires vendor infoframe. So just simply return. 1673 */ 1674 return; 1675 1676 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1677 if (err < 0) { 1678 printf("Failed to pack vendor infoframe: %zd\n", err); 1679 return; 1680 } 1681 1682 /* Set the length of HDMI vendor specific InfoFrame payload */ 1683 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1684 1685 /* Set 24bit IEEE Registration Identifier */ 1686 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1687 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1688 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1689 1690 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1691 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1692 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1693 1694 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1695 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1696 1697 /* Packet frame interpolation */ 1698 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1699 1700 /* Auto packets per frame and line spacing */ 1701 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1702 1703 /* Configures the Frame Composer On RDRB mode */ 1704 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1705 HDMI_FC_DATAUTO0_VSD_MASK); 1706 } 1707 1708 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 1709 unsigned int n) 1710 { 1711 /* Must be set/cleared first */ 1712 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 1713 1714 /* nshift factor = 0 */ 1715 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 1716 1717 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 1718 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 1719 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 1720 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 1721 1722 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 1723 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 1724 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 1725 } 1726 1727 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi, 1728 unsigned long pixel_clk, 1729 unsigned long freq) 1730 { 1731 const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data; 1732 const struct dw_hdmi_audio_tmds_n *tmds_n = NULL; 1733 int i; 1734 1735 if (plat_data->tmds_n_table) { 1736 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) { 1737 if (pixel_clk == plat_data->tmds_n_table[i].tmds) { 1738 tmds_n = &plat_data->tmds_n_table[i]; 1739 break; 1740 } 1741 } 1742 } 1743 1744 if (!tmds_n) { 1745 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) { 1746 if (pixel_clk == common_tmds_n_table[i].tmds) { 1747 tmds_n = &common_tmds_n_table[i]; 1748 break; 1749 } 1750 } 1751 } 1752 1753 if (!tmds_n) 1754 return -ENOENT; 1755 1756 switch (freq) { 1757 case 32000: 1758 return tmds_n->n_32k; 1759 case 44100: 1760 case 88200: 1761 case 176400: 1762 return (freq / 44100) * tmds_n->n_44k1; 1763 case 48000: 1764 case 96000: 1765 case 192000: 1766 return (freq / 48000) * tmds_n->n_48k; 1767 default: 1768 return -ENOENT; 1769 } 1770 } 1771 1772 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n, 1773 unsigned int pixel_clk) 1774 { 1775 u64 final, diff; 1776 u64 cts; 1777 1778 final = (u64)pixel_clk * n; 1779 1780 cts = final; 1781 do_div(cts, 128 * freq); 1782 1783 diff = final - (u64)cts * (128 * freq); 1784 1785 return diff; 1786 } 1787 1788 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi, 1789 unsigned long pixel_clk, 1790 unsigned long freq) 1791 { 1792 unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500); 1793 unsigned int max_n = (128 * freq) / 300; 1794 unsigned int ideal_n = (128 * freq) / 1000; 1795 unsigned int best_n_distance = ideal_n; 1796 unsigned int best_n = 0; 1797 u64 best_diff = U64_MAX; 1798 int n; 1799 1800 /* If the ideal N could satisfy the audio math, then just take it */ 1801 if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0) 1802 return ideal_n; 1803 1804 for (n = min_n; n <= max_n; n++) { 1805 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk); 1806 1807 if (diff < best_diff || (diff == best_diff && 1808 abs(n - ideal_n) < best_n_distance)) { 1809 best_n = n; 1810 best_diff = diff; 1811 best_n_distance = abs(best_n - ideal_n); 1812 } 1813 1814 /* 1815 * The best N already satisfy the audio math, and also be 1816 * the closest value to ideal N, so just cut the loop. 1817 */ 1818 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance)) 1819 break; 1820 } 1821 1822 return best_n; 1823 } 1824 1825 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk, 1826 unsigned long sample_rate) 1827 { 1828 int n; 1829 1830 n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate); 1831 if (n > 0) 1832 return n; 1833 1834 printf("Rate %lu missing; compute N dynamically\n", 1835 pixel_clk); 1836 1837 return hdmi_compute_n(hdmi, pixel_clk, sample_rate); 1838 } 1839 1840 static 1841 void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, unsigned long pixel_clk, 1842 unsigned int sample_rate) 1843 { 1844 unsigned long ftdms = pixel_clk; 1845 unsigned int n, cts; 1846 u64 tmp; 1847 1848 n = hdmi_find_n(hdmi, pixel_clk, sample_rate); 1849 1850 /* 1851 * Compute the CTS value from the N value. Note that CTS and N 1852 * can be up to 20 bits in total, so we need 64-bit math. Also 1853 * note that our TDMS clock is not fully accurate; it is accurate 1854 * to kHz. This can introduce an unnecessary remainder in the 1855 * calculation below, so we don't try to warn about that. 1856 */ 1857 tmp = (u64)ftdms * n; 1858 do_div(tmp, 128 * sample_rate); 1859 cts = tmp; 1860 1861 printf("%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", __func__, 1862 sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000, n, cts); 1863 1864 hdmi->audio_n = n; 1865 hdmi->audio_cts = cts; 1866 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 1867 } 1868 1869 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 1870 { 1871 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 1872 hdmi->sample_rate); 1873 } 1874 1875 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi) 1876 { 1877 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS); 1878 } 1879 1880 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 1881 { 1882 hdmi->sample_rate = rate; 1883 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 1884 hdmi->sample_rate); 1885 } 1886 1887 static int dw_hdmi_hdcp_load_key(struct dw_hdmi *hdmi) 1888 { 1889 int i, j, ret, val; 1890 struct hdcp_keys *hdcp_keys; 1891 1892 val = sizeof(*hdcp_keys); 1893 hdcp_keys = malloc(val); 1894 if (!hdcp_keys) 1895 return -ENOMEM; 1896 1897 memset(hdcp_keys, 0, val); 1898 1899 ret = vendor_storage_read(HDMI_HDCP1X_ID, hdcp_keys, val); 1900 if (ret < val) { 1901 printf("HDCP: read size %d\n", ret); 1902 free(hdcp_keys); 1903 return -EINVAL; 1904 } 1905 1906 if (hdcp_keys->KSV[0] == 0x00 && 1907 hdcp_keys->KSV[1] == 0x00 && 1908 hdcp_keys->KSV[2] == 0x00 && 1909 hdcp_keys->KSV[3] == 0x00 && 1910 hdcp_keys->KSV[4] == 0x00) { 1911 printf("HDCP: Invalid hdcp key\n"); 1912 free(hdcp_keys); 1913 return -EINVAL; 1914 } 1915 1916 /* Disable decryption logic */ 1917 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_RMCTL); 1918 /* Poll untile DPK write is allowed */ 1919 do { 1920 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1921 } while ((val & DPK_WR_OK_STS) == 0); 1922 1923 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_DPK6); 1924 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_DPK5); 1925 1926 /* The useful data in ksv should be 5 byte */ 1927 for (i = 4; i >= 0; i--) 1928 hdmi_writeb(hdmi, hdcp_keys->KSV[i], HDMI_HDCPREG_DPK0 + i); 1929 /* Poll untile DPK write is allowed */ 1930 do { 1931 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1932 } while ((val & DPK_WR_OK_STS) == 0); 1933 1934 /* Enable decryption logic */ 1935 hdmi_writeb(hdmi, 1, HDMI_HDCPREG_RMCTL); 1936 hdmi_writeb(hdmi, hdcp_keys->seeds[0], HDMI_HDCPREG_SEED1); 1937 hdmi_writeb(hdmi, hdcp_keys->seeds[1], HDMI_HDCPREG_SEED0); 1938 1939 /* Write encrypt device private key */ 1940 for (i = 0; i < DW_HDMI_HDCP_DPK_LEN - 6; i += 7) { 1941 for (j = 6; j >= 0; j--) 1942 hdmi_writeb(hdmi, hdcp_keys->devicekey[i + j], 1943 HDMI_HDCPREG_DPK0 + j); 1944 do { 1945 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1946 } while ((val & DPK_WR_OK_STS) == 0); 1947 } 1948 1949 free(hdcp_keys); 1950 return 0; 1951 } 1952 1953 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi, 1954 const struct drm_display_mode *mode) 1955 { 1956 u8 vsync_pol, hsync_pol, data_pol, hdmi_dvi; 1957 1958 if (!hdmi->hdcp1x_enable) 1959 return; 1960 1961 /* Configure the video polarity */ 1962 vsync_pol = mode->flags & DRM_MODE_FLAG_PVSYNC ? 1963 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH : 1964 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW; 1965 hsync_pol = mode->flags & DRM_MODE_FLAG_PHSYNC ? 1966 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH : 1967 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW; 1968 data_pol = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1969 hdmi_modb(hdmi, vsync_pol | hsync_pol | data_pol, 1970 HDMI_A_VIDPOLCFG_VSYNCPOL_MASK | 1971 HDMI_A_VIDPOLCFG_HSYNCPOL_MASK | 1972 HDMI_A_VIDPOLCFG_DATAENPOL_MASK, 1973 HDMI_A_VIDPOLCFG); 1974 1975 /* Config the display mode */ 1976 hdmi_dvi = hdmi->sink_is_hdmi ? HDMI_A_HDCPCFG0_HDMIDVI_HDMI : 1977 HDMI_A_HDCPCFG0_HDMIDVI_DVI; 1978 hdmi_modb(hdmi, hdmi_dvi, HDMI_A_HDCPCFG0_HDMIDVI_MASK, 1979 HDMI_A_HDCPCFG0); 1980 1981 if (!(hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS) & 0x3f)) 1982 dw_hdmi_hdcp_load_key(hdmi); 1983 1984 hdmi_modb(hdmi, HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE, 1985 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK, 1986 HDMI_FC_INVIDCONF); 1987 1988 if (hdmi_readb(hdmi, HDMI_CONFIG1_ID) & HDMI_A_HDCP22_MASK) { 1989 hdmi_modb(hdmi, HDMI_HDCP2_OVR_ENABLE | 1990 HDMI_HDCP2_FORCE_DISABLE, 1991 HDMI_HDCP2_OVR_EN_MASK | 1992 HDMI_HDCP2_FORCE_MASK, 1993 HDMI_HDCP2REG_CTRL); 1994 hdmi_writeb(hdmi, 0xff, HDMI_HDCP2REG_MASK); 1995 hdmi_writeb(hdmi, 0xff, HDMI_HDCP2REG_MUTE); 1996 } 1997 1998 hdmi_writeb(hdmi, 0x40, HDMI_A_OESSWCFG); 1999 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE | 2000 HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE | 2001 HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE, 2002 HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK | 2003 HDMI_A_HDCPCFG0_EN11FEATURE_MASK | 2004 HDMI_A_HDCPCFG0_SYNCRICHECK_MASK, HDMI_A_HDCPCFG0); 2005 2006 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE | 2007 HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE, 2008 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK | 2009 HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK, HDMI_A_HDCPCFG1); 2010 2011 /* Reset HDCP Engine */ 2012 if (hdmi_readb(hdmi, HDMI_MC_CLKDIS) & HDMI_MC_CLKDIS_HDCPCLK_MASK) { 2013 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_SWRESET_ASSERT, 2014 HDMI_A_HDCPCFG1_SWRESET_MASK, HDMI_A_HDCPCFG1); 2015 } 2016 2017 hdmi_writeb(hdmi, 0x00, HDMI_A_APIINTMSK); 2018 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_ENABLE, 2019 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 2020 2021 hdmi_modb(hdmi, HDMI_MC_CLKDIS_HDCPCLK_ENABLE, 2022 HDMI_MC_CLKDIS_HDCPCLK_MASK, HDMI_MC_CLKDIS); 2023 2024 printf("%s success\n", __func__); 2025 } 2026 2027 static int dw_hdmi_setup(struct dw_hdmi *hdmi, 2028 struct drm_display_mode *mode, 2029 struct display_state *state) 2030 { 2031 int ret; 2032 void *data = hdmi->plat_data->phy_data; 2033 2034 hdmi_disable_overflow_interrupts(hdmi); 2035 if (!hdmi->vic) 2036 printf("Non-CEA mode used in HDMI\n"); 2037 else 2038 printf("CEA mode used vic=%d\n", hdmi->vic); 2039 2040 if (hdmi->plat_data->get_enc_out_encoding) 2041 hdmi->hdmi_data.enc_out_encoding = 2042 hdmi->plat_data->get_enc_out_encoding(data); 2043 else if (hdmi->vic == 6 || hdmi->vic == 7 || 2044 hdmi->vic == 21 || hdmi->vic == 22 || 2045 hdmi->vic == 2 || hdmi->vic == 3 || 2046 hdmi->vic == 17 || hdmi->vic == 18) 2047 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 2048 else 2049 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 2050 2051 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2052 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1; 2053 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1; 2054 } else { 2055 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 2056 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 2057 } 2058 2059 /* TOFIX: Get input encoding from plat data or fallback to none */ 2060 if (hdmi->plat_data->get_enc_in_encoding) 2061 hdmi->hdmi_data.enc_in_encoding = 2062 hdmi->plat_data->get_enc_in_encoding(data); 2063 else if (hdmi->plat_data->input_bus_encoding) 2064 hdmi->hdmi_data.enc_in_encoding = 2065 hdmi->plat_data->input_bus_encoding; 2066 else 2067 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 2068 2069 if (hdmi->plat_data->get_quant_range) 2070 hdmi->hdmi_data.quant_range = 2071 hdmi->plat_data->get_quant_range(data); 2072 else 2073 hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 2074 2075 /* 2076 * According to the dw-hdmi specification 6.4.2 2077 * vp_pr_cd[3:0]: 2078 * 0000b: No pixel repetition (pixel sent only once) 2079 * 0001b: Pixel sent two times (pixel repeated once) 2080 */ 2081 hdmi->hdmi_data.pix_repet_factor = 2082 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0; 2083 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 2084 2085 /* HDMI Initialization Step B.1 */ 2086 hdmi_av_composer(hdmi, mode); 2087 2088 /* HDMI Initialization Step B.2 */ 2089 ret = hdmi->phy.ops->init(hdmi, state); 2090 if (ret) 2091 return ret; 2092 hdmi->phy.enabled = true; 2093 2094 /* HDMI Initializateion Step B.3 */ 2095 dw_hdmi_enable_video_path(hdmi); 2096 2097 /* HDMI Initialization Step E - Configure audio */ 2098 if (hdmi->sink_has_audio) { 2099 printf("sink has audio support\n"); 2100 hdmi_clk_regenerator_update_pixel_clock(hdmi); 2101 hdmi_enable_audio_clk(hdmi); 2102 } 2103 2104 /* not for DVI mode */ 2105 if (hdmi->sink_is_hdmi) { 2106 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 2107 hdmi_config_AVI(hdmi, mode); 2108 hdmi_config_vendor_specific_infoframe(hdmi, mode); 2109 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_HDMIDVI_HDMI, 2110 HDMI_A_HDCPCFG0_HDMIDVI_MASK, 2111 HDMI_A_HDCPCFG0); 2112 } else { 2113 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_HDMIDVI_DVI, 2114 HDMI_A_HDCPCFG0_HDMIDVI_MASK, 2115 HDMI_A_HDCPCFG0); 2116 printf("%s DVI mode\n", __func__); 2117 } 2118 2119 hdmi_video_packetize(hdmi); 2120 hdmi_video_csc(hdmi); 2121 hdmi_video_sample(hdmi); 2122 hdmi_tx_hdcp_config(hdmi, mode); 2123 dw_hdmi_clear_overflow(hdmi); 2124 2125 return 0; 2126 } 2127 2128 int dw_hdmi_detect_hotplug(struct dw_hdmi *hdmi, 2129 struct display_state *state) 2130 { 2131 return hdmi->phy.ops->read_hpd(hdmi, state); 2132 } 2133 2134 static int dw_hdmi_set_reg_wr(struct dw_hdmi *hdmi) 2135 { 2136 switch (hdmi->io_width) { 2137 case 4: 2138 hdmi->write = dw_hdmi_writel; 2139 hdmi->read = dw_hdmi_readl; 2140 break; 2141 case 1: 2142 hdmi->write = dw_hdmi_writeb; 2143 hdmi->read = dw_hdmi_readb; 2144 break; 2145 default: 2146 printf("reg-io-width must be 1 or 4\n"); 2147 return -EINVAL; 2148 } 2149 2150 return 0; 2151 } 2152 2153 static void initialize_hdmi_mutes(struct dw_hdmi *hdmi) 2154 { 2155 /*mute unnecessary interrupt, only enable hpd */ 2156 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 2157 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 2158 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 2159 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 2160 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 2161 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 2162 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 2163 hdmi_writeb(hdmi, 0xfe, HDMI_IH_MUTE_PHY_STAT0); 2164 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 2165 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 2166 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 2167 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 2168 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 2169 hdmi_writeb(hdmi, 0xf1, HDMI_PHY_MASK0); 2170 2171 /*Force output black*/ 2172 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS2); 2173 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS1); 2174 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS0); 2175 } 2176 2177 static void dw_hdmi_dev_init(struct dw_hdmi *hdmi) 2178 { 2179 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 2180 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 2181 2182 initialize_hdmi_mutes(hdmi); 2183 } 2184 2185 static void dw_hdmi_i2c_set_divs(struct dw_hdmi *hdmi) 2186 { 2187 unsigned long low_ns, high_ns; 2188 unsigned long div_low, div_high; 2189 2190 /* Standard-mode */ 2191 if (hdmi->i2c->scl_high_ns < 4000) 2192 high_ns = 4708; 2193 else 2194 high_ns = hdmi->i2c->scl_high_ns; 2195 2196 if (hdmi->i2c->scl_low_ns < 4700) 2197 low_ns = 4916; 2198 else 2199 low_ns = hdmi->i2c->scl_low_ns; 2200 2201 div_low = (24000 * low_ns) / 1000000; 2202 if ((24000 * low_ns) % 1000000) 2203 div_low++; 2204 2205 div_high = (24000 * high_ns) / 1000000; 2206 if ((24000 * high_ns) % 1000000) 2207 div_high++; 2208 2209 /* Maximum divider supported by hw is 0xffff */ 2210 if (div_low > 0xffff) 2211 div_low = 0xffff; 2212 2213 if (div_high > 0xffff) 2214 div_high = 0xffff; 2215 2216 hdmi_writeb(hdmi, div_high & 0xff, HDMI_I2CM_SS_SCL_HCNT_0_ADDR); 2217 hdmi_writeb(hdmi, (div_high >> 8) & 0xff, 2218 HDMI_I2CM_SS_SCL_HCNT_1_ADDR); 2219 hdmi_writeb(hdmi, div_low & 0xff, HDMI_I2CM_SS_SCL_LCNT_0_ADDR); 2220 hdmi_writeb(hdmi, (div_low >> 8) & 0xff, 2221 HDMI_I2CM_SS_SCL_LCNT_1_ADDR); 2222 } 2223 2224 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 2225 { 2226 /* Software reset */ 2227 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 2228 2229 /* Set Standard Mode speed */ 2230 hdmi_modb(hdmi, HDMI_I2CM_DIV_STD_MODE, 2231 HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV); 2232 2233 /* Set done, not acknowledged and arbitration interrupt polarities */ 2234 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 2235 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 2236 HDMI_I2CM_CTLINT); 2237 2238 /* Clear DONE and ERROR interrupts */ 2239 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 2240 HDMI_IH_I2CM_STAT0); 2241 2242 /* Mute DONE and ERROR interrupts */ 2243 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 2244 HDMI_IH_MUTE_I2CM_STAT0); 2245 2246 /* set SDA high level holding time */ 2247 hdmi_writeb(hdmi, 0x48, HDMI_I2CM_SDA_HOLD); 2248 2249 dw_hdmi_i2c_set_divs(hdmi); 2250 } 2251 2252 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 2253 { 2254 hdmi->audio_enable = true; 2255 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 2256 } 2257 2258 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 2259 { 2260 hdmi->audio_enable = false; 2261 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 2262 } 2263 2264 int rockchip_dw_hdmi_init(struct display_state *state) 2265 { 2266 struct connector_state *conn_state = &state->conn_state; 2267 const struct rockchip_connector *connector = conn_state->connector; 2268 const struct dw_hdmi_plat_data *pdata = connector->data; 2269 struct crtc_state *crtc_state = &state->crtc_state; 2270 struct dw_hdmi *hdmi; 2271 struct drm_display_mode *mode_buf; 2272 ofnode hdmi_node = conn_state->node; 2273 u32 val; 2274 struct device_node *ddc_node; 2275 2276 hdmi = malloc(sizeof(struct dw_hdmi)); 2277 if (!hdmi) 2278 return -ENOMEM; 2279 2280 memset(hdmi, 0, sizeof(struct dw_hdmi)); 2281 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 2282 if (!mode_buf) 2283 return -ENOMEM; 2284 2285 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 2286 2287 hdmi->regs = dev_read_addr_ptr(conn_state->dev); 2288 hdmi->io_width = ofnode_read_s32_default(hdmi_node, "reg-io-width", -1); 2289 2290 if (ofnode_read_bool(hdmi_node, "scramble-low-rates")) 2291 hdmi->scramble_low_rates = true; 2292 2293 if (ofnode_read_bool(hdmi_node, "hdcp1x-enable")) 2294 hdmi->hdcp1x_enable = true; 2295 else 2296 hdmi->hdcp1x_enable = false; 2297 2298 ddc_node = of_parse_phandle(ofnode_to_np(hdmi_node), "ddc-i2c-bus", 0); 2299 if (ddc_node) { 2300 uclass_get_device_by_ofnode(UCLASS_I2C, np_to_ofnode(ddc_node), 2301 &hdmi->adap.i2c_bus); 2302 if (hdmi->adap.i2c_bus) 2303 hdmi->adap.ops = i2c_get_ops(hdmi->adap.i2c_bus); 2304 } 2305 2306 hdmi->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 2307 if (hdmi->grf <= 0) { 2308 printf("%s: Get syscon grf failed (ret=%p)\n", 2309 __func__, hdmi->grf); 2310 return -ENXIO; 2311 } 2312 2313 dw_hdmi_set_reg_wr(hdmi); 2314 2315 if (pdata->grf_vop_sel_reg) { 2316 if (crtc_state->crtc_id) 2317 val = ((1 << pdata->vop_sel_bit) | 2318 (1 << (16 + pdata->vop_sel_bit))); 2319 else 2320 val = ((0 << pdata->vop_sel_bit) | 2321 (1 << (16 + pdata->vop_sel_bit))); 2322 writel(val, hdmi->grf + pdata->grf_vop_sel_reg); 2323 } 2324 2325 hdmi->i2c = malloc(sizeof(struct dw_hdmi_i2c)); 2326 if (!hdmi->i2c) 2327 return -ENOMEM; 2328 hdmi->adap.ddc_xfer = dw_hdmi_i2c_xfer; 2329 2330 /* 2331 * Read high and low time from device tree. If not available use 2332 * the default timing scl clock rate is about 99.6KHz. 2333 */ 2334 hdmi->i2c->scl_high_ns = 2335 ofnode_read_s32_default(hdmi_node, 2336 "ddc-i2c-scl-high-time-ns", 4708); 2337 hdmi->i2c->scl_low_ns = 2338 ofnode_read_s32_default(hdmi_node, 2339 "ddc-i2c-scl-low-time-ns", 4916); 2340 2341 dw_hdmi_i2c_init(hdmi); 2342 conn_state->type = DRM_MODE_CONNECTOR_HDMIA; 2343 conn_state->output_if |= VOP_OUTPUT_IF_HDMI0; 2344 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 2345 2346 hdmi->dev_type = pdata->dev_type; 2347 hdmi->plat_data = pdata; 2348 hdmi->edid_data.mode_buf = mode_buf; 2349 hdmi->sample_rate = 48000; 2350 2351 conn_state->private = hdmi; 2352 dw_hdmi_set_iomux(hdmi->grf, hdmi->dev_type); 2353 dw_hdmi_detect_phy(hdmi); 2354 dw_hdmi_dev_init(hdmi); 2355 2356 return 0; 2357 } 2358 2359 void rockchip_dw_hdmi_deinit(struct display_state *state) 2360 { 2361 struct connector_state *conn_state = &state->conn_state; 2362 struct dw_hdmi *hdmi = conn_state->private; 2363 2364 if (hdmi->i2c) 2365 free(hdmi->i2c); 2366 if (hdmi->edid_data.mode_buf) 2367 free(hdmi->edid_data.mode_buf); 2368 if (hdmi) 2369 free(hdmi); 2370 } 2371 2372 int rockchip_dw_hdmi_prepare(struct display_state *state) 2373 { 2374 return 0; 2375 } 2376 2377 int rockchip_dw_hdmi_enable(struct display_state *state) 2378 { 2379 struct connector_state *conn_state = &state->conn_state; 2380 struct drm_display_mode *mode = &conn_state->mode; 2381 struct dw_hdmi *hdmi = conn_state->private; 2382 2383 if (!hdmi) 2384 return -EFAULT; 2385 2386 /* Store the display mode for plugin/DKMS poweron events */ 2387 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 2388 2389 dw_hdmi_setup(hdmi, mode, state); 2390 2391 return 0; 2392 } 2393 2394 int rockchip_dw_hdmi_disable(struct display_state *state) 2395 { 2396 struct connector_state *conn_state = &state->conn_state; 2397 struct dw_hdmi *hdmi = conn_state->private; 2398 2399 dw_hdmi_disable(hdmi, state); 2400 return 0; 2401 } 2402 2403 int rockchip_dw_hdmi_get_timing(struct display_state *state) 2404 { 2405 int ret, i; 2406 struct connector_state *conn_state = &state->conn_state; 2407 struct drm_display_mode *mode = &conn_state->mode; 2408 struct dw_hdmi *hdmi = conn_state->private; 2409 struct edid *edid = (struct edid *)conn_state->edid; 2410 unsigned int bus_format; 2411 unsigned long enc_out_encoding; 2412 struct overscan *overscan = &conn_state->overscan; 2413 const u8 def_modes_vic[6] = {4, 16, 2, 17, 31, 19}; 2414 2415 if (!hdmi) 2416 return -EFAULT; 2417 2418 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 2419 2420 if (!ret) { 2421 hdmi->sink_is_hdmi = 2422 drm_detect_hdmi_monitor(edid); 2423 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 2424 ret = drm_add_edid_modes(&hdmi->edid_data, conn_state->edid); 2425 } 2426 if (ret < 0) { 2427 hdmi->sink_is_hdmi = true; 2428 hdmi->sink_has_audio = true; 2429 do_cea_modes(&hdmi->edid_data, def_modes_vic, 2430 sizeof(def_modes_vic)); 2431 hdmi->edid_data.preferred_mode = &hdmi->edid_data.mode_buf[0]; 2432 printf("failed to get edid\n"); 2433 } 2434 drm_rk_filter_whitelist(&hdmi->edid_data); 2435 if (hdmi->phy.ops->mode_valid) 2436 hdmi->phy.ops->mode_valid(hdmi, state); 2437 drm_mode_max_resolution_filter(&hdmi->edid_data, 2438 &state->crtc_state.max_output); 2439 if (!drm_mode_prune_invalid(&hdmi->edid_data)) { 2440 printf("can't find valid hdmi mode\n"); 2441 return -EINVAL; 2442 } 2443 2444 for (i = 0; i < hdmi->edid_data.modes; i++) 2445 hdmi->edid_data.mode_buf[i].vrefresh = 2446 drm_mode_vrefresh(&hdmi->edid_data.mode_buf[i]); 2447 2448 drm_mode_sort(&hdmi->edid_data); 2449 drm_rk_selete_output(&hdmi->edid_data, &bus_format, 2450 overscan, hdmi->dev_type); 2451 2452 *mode = *hdmi->edid_data.preferred_mode; 2453 hdmi->vic = drm_match_cea_mode(mode); 2454 2455 printf("mode:%dx%d\n", mode->hdisplay, mode->vdisplay); 2456 conn_state->bus_format = bus_format; 2457 hdmi->hdmi_data.enc_in_bus_format = bus_format; 2458 hdmi->hdmi_data.enc_out_bus_format = bus_format; 2459 2460 switch (bus_format) { 2461 case MEDIA_BUS_FMT_UYVY10_1X20: 2462 conn_state->bus_format = MEDIA_BUS_FMT_YUV10_1X30; 2463 hdmi->hdmi_data.enc_in_bus_format = 2464 MEDIA_BUS_FMT_YUV10_1X30; 2465 break; 2466 case MEDIA_BUS_FMT_UYVY8_1X16: 2467 conn_state->bus_format = MEDIA_BUS_FMT_YUV8_1X24; 2468 hdmi->hdmi_data.enc_in_bus_format = 2469 MEDIA_BUS_FMT_YUV8_1X24; 2470 break; 2471 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 2472 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 2473 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420; 2474 break; 2475 } 2476 2477 if (hdmi->vic == 6 || hdmi->vic == 7 || hdmi->vic == 21 || 2478 hdmi->vic == 22 || hdmi->vic == 2 || hdmi->vic == 3 || 2479 hdmi->vic == 17 || hdmi->vic == 18) 2480 enc_out_encoding = V4L2_YCBCR_ENC_601; 2481 else 2482 enc_out_encoding = V4L2_YCBCR_ENC_709; 2483 2484 if (enc_out_encoding == V4L2_YCBCR_ENC_BT2020) 2485 conn_state->color_space = V4L2_COLORSPACE_BT2020; 2486 else if (bus_format == MEDIA_BUS_FMT_RGB888_1X24 || 2487 bus_format == MEDIA_BUS_FMT_RGB101010_1X30) 2488 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 2489 else if (enc_out_encoding == V4L2_YCBCR_ENC_709) 2490 conn_state->color_space = V4L2_COLORSPACE_REC709; 2491 else 2492 conn_state->color_space = V4L2_COLORSPACE_SMPTE170M; 2493 2494 return 0; 2495 } 2496 2497 int rockchip_dw_hdmi_detect(struct display_state *state) 2498 { 2499 int ret; 2500 struct connector_state *conn_state = &state->conn_state; 2501 struct dw_hdmi *hdmi = conn_state->private; 2502 2503 if (!hdmi) 2504 return -EFAULT; 2505 2506 ret = dw_hdmi_detect_hotplug(hdmi, state); 2507 2508 return ret; 2509 } 2510 2511 int rockchip_dw_hdmi_get_edid(struct display_state *state) 2512 { 2513 int ret; 2514 struct connector_state *conn_state = &state->conn_state; 2515 struct dw_hdmi *hdmi = conn_state->private; 2516 2517 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 2518 2519 return ret; 2520 } 2521 2522 int inno_dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data) 2523 { 2524 struct display_state *state = (struct display_state *)data; 2525 struct connector_state *conn_state = &state->conn_state; 2526 u32 color_depth, bus_width; 2527 2528 color_depth = 2529 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 2530 2531 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 2532 bus_width = color_depth / 2; 2533 else if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 2534 bus_width = color_depth; 2535 else 2536 bus_width = 8; 2537 rockchip_phy_set_bus_width(conn_state->phy, bus_width); 2538 rockchip_phy_set_pll(conn_state->phy, 2539 conn_state->mode.crtc_clock * 1000); 2540 if (hdmi->edid_data.display_info.hdmi.scdc.supported) 2541 rockchip_dw_hdmi_scdc_set_tmds_rate(hdmi); 2542 rockchip_phy_power_on(conn_state->phy); 2543 2544 return 0; 2545 } 2546 2547 void inno_dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 2548 { 2549 } 2550 2551 enum drm_connector_status 2552 inno_dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data) 2553 { 2554 enum drm_connector_status status; 2555 struct display_state *state = (struct display_state *)data; 2556 2557 status = dw_hdmi_phy_read_hpd(hdmi, state); 2558 2559 if (hdmi->dev_type == RK3328_HDMI) { 2560 if (status == connector_status_connected) 2561 inno_dw_hdmi_set_domain(hdmi->grf, 1); 2562 else 2563 inno_dw_hdmi_set_domain(hdmi->grf, 0); 2564 } 2565 2566 return status; 2567 } 2568 2569 void inno_dw_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data) 2570 { 2571 struct display_state *state = (struct display_state *)data; 2572 struct connector_state *conn_state = &state->conn_state; 2573 struct hdmi_edid_data *edid_data = &hdmi->edid_data; 2574 unsigned long rate; 2575 int i, ret; 2576 struct drm_display_mode *mode_buf = edid_data->mode_buf; 2577 2578 for (i = 0; i < edid_data->modes; i++) { 2579 if (edid_data->mode_buf[i].invalid) 2580 continue; 2581 if (edid_data->mode_buf[i].flags & DRM_MODE_FLAG_DBLCLK) 2582 rate = mode_buf[i].clock * 1000 * 2; 2583 else 2584 rate = mode_buf[i].clock * 1000; 2585 2586 /* Check whether mode is out of phy cfg range. */ 2587 ret = rockchip_phy_round_rate(conn_state->phy, rate); 2588 2589 if (ret < 0) 2590 edid_data->mode_buf[i].invalid = true; 2591 } 2592 } 2593