1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <syscon.h> 10 #include <asm/arch-rockchip/clock.h> 11 #include <asm/arch/vendor.h> 12 #include <edid.h> 13 #include <dm/device.h> 14 #include <dm/of_access.h> 15 #include <dm/ofnode.h> 16 #include <dm/read.h> 17 #include <linux/hdmi.h> 18 #include <linux/media-bus-format.h> 19 #include <linux/dw_hdmi.h> 20 #include <asm/io.h> 21 #include "rockchip_display.h" 22 #include "rockchip_crtc.h" 23 #include "rockchip_connector.h" 24 #include "dw_hdmi.h" 25 #include "rockchip_phy.h" 26 27 #define HDCP_PRIVATE_KEY_SIZE 280 28 #define HDCP_KEY_SHA_SIZE 20 29 #define HDMI_HDCP1X_ID 5 30 /* 31 * Unless otherwise noted, entries in this table are 100% optimization. 32 * Values can be obtained from hdmi_compute_n() but that function is 33 * slow so we pre-compute values we expect to see. 34 * 35 * All 32k and 48k values are expected to be the same (due to the way 36 * the math works) for any rate that's an exact kHz. 37 */ 38 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = { 39 { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, }, 40 { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, }, 41 { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 42 { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, }, 43 { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, }, 44 { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, 45 { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, 46 { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 47 { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 48 { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, 49 { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 50 { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, 51 { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 52 { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 53 { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, }, 54 { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 55 { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, }, 56 { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 57 { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 58 { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, }, 59 { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, 60 { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, 61 { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, 62 { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 63 { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 64 { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 65 { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 66 { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 67 { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, 68 { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 69 { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, }, 70 { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, 71 { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 72 { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 73 { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 74 { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, 75 { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 76 77 /* For 297 MHz+ HDMI spec have some other rule for setting N */ 78 { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, }, 79 { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, }, 80 81 /* End of table */ 82 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, }, 83 }; 84 85 static const u16 csc_coeff_default[3][4] = { 86 { 0x2000, 0x0000, 0x0000, 0x0000 }, 87 { 0x0000, 0x2000, 0x0000, 0x0000 }, 88 { 0x0000, 0x0000, 0x2000, 0x0000 } 89 }; 90 91 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 92 { 0x2000, 0x6926, 0x74fd, 0x010e }, 93 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 94 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 95 }; 96 97 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 98 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 99 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 100 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 101 }; 102 103 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 104 { 0x2591, 0x1322, 0x074b, 0x0000 }, 105 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 106 { 0x6acd, 0x7534, 0x2000, 0x0200 } 107 }; 108 109 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 110 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 111 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 112 { 0x6756, 0x78ab, 0x2000, 0x0200 } 113 }; 114 115 static const u16 csc_coeff_full_to_limited[3][4] = { 116 { 0x36f7, 0x0000, 0x0000, 0x0040 }, 117 { 0x0000, 0x36f7, 0x0000, 0x0040 }, 118 { 0x0000, 0x0000, 0x36f7, 0x0040 } 119 }; 120 121 struct hdmi_vmode { 122 bool mdataenablepolarity; 123 124 unsigned int mpixelclock; 125 unsigned int mpixelrepetitioninput; 126 unsigned int mpixelrepetitionoutput; 127 unsigned int mtmdsclock; 128 }; 129 130 struct hdmi_data_info { 131 unsigned int enc_in_bus_format; 132 unsigned int enc_out_bus_format; 133 unsigned int enc_in_encoding; 134 unsigned int enc_out_encoding; 135 unsigned int quant_range; 136 unsigned int pix_repet_factor; 137 struct hdmi_vmode video_mode; 138 }; 139 140 struct dw_hdmi_phy_data { 141 enum dw_hdmi_phy_type type; 142 const char *name; 143 unsigned int gen; 144 bool has_svsret; 145 int (*configure)(struct dw_hdmi *hdmi, 146 const struct dw_hdmi_plat_data *pdata, 147 unsigned long mpixelclock); 148 }; 149 150 struct hdcp_keys { 151 u8 KSV[8]; 152 u8 devicekey[HDCP_PRIVATE_KEY_SIZE]; 153 u8 sha1[HDCP_KEY_SHA_SIZE]; 154 u8 seeds[2]; 155 }; 156 157 struct dw_hdmi_i2c { 158 u8 slave_reg; 159 bool is_regaddr; 160 bool is_segment; 161 162 unsigned int scl_high_ns; 163 unsigned int scl_low_ns; 164 }; 165 166 struct dw_hdmi { 167 int id; 168 enum dw_hdmi_devtype dev_type; 169 unsigned int version; 170 struct hdmi_data_info hdmi_data; 171 struct hdmi_edid_data edid_data; 172 const struct dw_hdmi_plat_data *plat_data; 173 struct ddc_adapter adap; 174 175 int vic; 176 int io_width; 177 178 unsigned long bus_format; 179 bool cable_plugin; 180 bool sink_is_hdmi; 181 bool sink_has_audio; 182 void *regs; 183 void *grf; 184 struct dw_hdmi_i2c *i2c; 185 186 struct { 187 const struct dw_hdmi_phy_ops *ops; 188 const char *name; 189 void *data; 190 bool enabled; 191 } phy; 192 193 struct drm_display_mode previous_mode; 194 195 unsigned int sample_rate; 196 unsigned int audio_cts; 197 unsigned int audio_n; 198 bool audio_enable; 199 bool scramble_low_rates; 200 201 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset); 202 u8 (*read)(struct dw_hdmi *hdmi, int offset); 203 204 bool hdcp1x_enable; 205 }; 206 207 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset) 208 { 209 writel(val, hdmi->regs + (offset << 2)); 210 } 211 212 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset) 213 { 214 return readl(hdmi->regs + (offset << 2)); 215 } 216 217 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 218 { 219 writeb(val, hdmi->regs + offset); 220 } 221 222 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset) 223 { 224 return readb(hdmi->regs + offset); 225 } 226 227 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 228 { 229 hdmi->write(hdmi, val, offset); 230 } 231 232 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 233 { 234 return hdmi->read(hdmi, offset); 235 } 236 237 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 238 { 239 u8 val = hdmi_readb(hdmi, reg) & ~mask; 240 241 val |= data & mask; 242 hdmi_writeb(hdmi, val, reg); 243 } 244 245 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 246 u8 shift, u8 mask) 247 { 248 hdmi_modb(hdmi, data << shift, mask, reg); 249 } 250 251 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 252 { 253 switch (bus_format) { 254 case MEDIA_BUS_FMT_RGB888_1X24: 255 case MEDIA_BUS_FMT_RGB101010_1X30: 256 case MEDIA_BUS_FMT_RGB121212_1X36: 257 case MEDIA_BUS_FMT_RGB161616_1X48: 258 return true; 259 260 default: 261 return false; 262 } 263 } 264 265 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 266 { 267 switch (bus_format) { 268 case MEDIA_BUS_FMT_YUV8_1X24: 269 case MEDIA_BUS_FMT_YUV10_1X30: 270 case MEDIA_BUS_FMT_YUV12_1X36: 271 case MEDIA_BUS_FMT_YUV16_1X48: 272 return true; 273 274 default: 275 return false; 276 } 277 } 278 279 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 280 { 281 switch (bus_format) { 282 case MEDIA_BUS_FMT_UYVY8_1X16: 283 case MEDIA_BUS_FMT_UYVY10_1X20: 284 case MEDIA_BUS_FMT_UYVY12_1X24: 285 return true; 286 287 default: 288 return false; 289 } 290 } 291 292 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 293 { 294 switch (bus_format) { 295 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 296 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 297 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 298 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 299 return true; 300 301 default: 302 return false; 303 } 304 } 305 306 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 307 { 308 switch (bus_format) { 309 case MEDIA_BUS_FMT_RGB888_1X24: 310 case MEDIA_BUS_FMT_YUV8_1X24: 311 case MEDIA_BUS_FMT_UYVY8_1X16: 312 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 313 return 8; 314 315 case MEDIA_BUS_FMT_RGB101010_1X30: 316 case MEDIA_BUS_FMT_YUV10_1X30: 317 case MEDIA_BUS_FMT_UYVY10_1X20: 318 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 319 return 10; 320 321 case MEDIA_BUS_FMT_RGB121212_1X36: 322 case MEDIA_BUS_FMT_YUV12_1X36: 323 case MEDIA_BUS_FMT_UYVY12_1X24: 324 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 325 return 12; 326 327 case MEDIA_BUS_FMT_RGB161616_1X48: 328 case MEDIA_BUS_FMT_YUV16_1X48: 329 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 330 return 16; 331 332 default: 333 return 0; 334 } 335 } 336 337 static int is_color_space_conversion(struct dw_hdmi *hdmi) 338 { 339 struct drm_display_mode *mode = 340 hdmi->edid_data.preferred_mode; 341 bool is_cea_default; 342 343 is_cea_default = (drm_match_cea_mode(mode) > 1) && 344 (hdmi->hdmi_data.quant_range == 345 HDMI_QUANTIZATION_RANGE_DEFAULT); 346 347 /* 348 * When output is rgb limited range or default range with 349 * cea mode, csc should be enabled. 350 */ 351 if (hdmi->hdmi_data.enc_in_bus_format != 352 hdmi->hdmi_data.enc_out_bus_format || 353 ((hdmi->hdmi_data.quant_range == HDMI_QUANTIZATION_RANGE_LIMITED || 354 is_cea_default) && 355 hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format))) 356 return 1; 357 358 return 0; 359 } 360 361 static int is_color_space_decimation(struct dw_hdmi *hdmi) 362 { 363 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 364 return 0; 365 366 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 367 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 368 return 1; 369 370 return 0; 371 } 372 373 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 374 unsigned char bit) 375 { 376 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 377 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 378 } 379 380 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi, 381 unsigned char bit) 382 { 383 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET, 384 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0); 385 } 386 387 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi, 388 unsigned char bit) 389 { 390 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET, 391 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0); 392 } 393 394 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi, 395 unsigned char bit) 396 { 397 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1); 398 } 399 400 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi, 401 unsigned char bit) 402 { 403 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2); 404 } 405 406 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 407 unsigned char *buf, unsigned int length) 408 { 409 struct dw_hdmi_i2c *i2c = hdmi->i2c; 410 int interrupt = 0, i = 20; 411 412 if (!i2c->is_regaddr) { 413 printf("set read register address to 0\n"); 414 i2c->slave_reg = 0x00; 415 i2c->is_regaddr = true; 416 } 417 418 while (length--) { 419 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 420 if (i2c->is_segment) 421 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 422 HDMI_I2CM_OPERATION); 423 else 424 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 425 HDMI_I2CM_OPERATION); 426 427 while (i--) { 428 udelay(1000); 429 interrupt = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 430 if (interrupt) 431 hdmi_writeb(hdmi, interrupt, 432 HDMI_IH_I2CM_STAT0); 433 if (interrupt & (m_SCDC_READREQ | m_I2CM_DONE | 434 m_I2CM_ERROR)) 435 break; 436 } 437 438 if (!interrupt) { 439 printf("[%s] i2c read reg[0x%02x] no interrupt\n", 440 __func__, i2c->slave_reg); 441 return -EAGAIN; 442 } 443 444 /* Check for error condition on the bus */ 445 if (interrupt & HDMI_IH_I2CM_STAT0_ERROR) { 446 printf("[%s] read reg[0x%02x] data error:0x%02x\n", 447 __func__, i2c->slave_reg, interrupt); 448 return -EIO; 449 } 450 451 i = 20; 452 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 453 } 454 i2c->is_segment = false; 455 456 return 0; 457 } 458 459 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 460 unsigned char *buf, unsigned int length) 461 { 462 struct dw_hdmi_i2c *i2c = hdmi->i2c; 463 int i = 20; 464 u8 interrupt = 0; 465 466 if (!i2c->is_regaddr) { 467 /* Use the first write byte as register address */ 468 i2c->slave_reg = buf[0]; 469 length--; 470 buf++; 471 i2c->is_regaddr = true; 472 } 473 474 while (length--) { 475 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 476 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 477 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 478 HDMI_I2CM_OPERATION); 479 480 while (i--) { 481 udelay(1000); 482 interrupt = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 483 if (interrupt) 484 hdmi_writeb(hdmi, 485 interrupt, HDMI_IH_I2CM_STAT0); 486 487 if (interrupt & (m_SCDC_READREQ | 488 m_I2CM_DONE | m_I2CM_ERROR)) 489 break; 490 } 491 492 if ((interrupt & m_I2CM_ERROR) || (i == -1)) { 493 printf("[%s] write data error\n", __func__); 494 return -EIO; 495 } else if (interrupt & m_I2CM_DONE) { 496 printf("[%s] write offset %02x success\n", 497 __func__, i2c->slave_reg); 498 return -EAGAIN; 499 } 500 501 i = 20; 502 } 503 504 return 0; 505 } 506 507 static int dw_hdmi_i2c_xfer(struct ddc_adapter *adap, 508 struct i2c_msg *msgs, int num) 509 { 510 struct dw_hdmi *hdmi = container_of(adap, struct dw_hdmi, adap); 511 struct dw_hdmi_i2c *i2c = hdmi->i2c; 512 u8 addr = msgs[0].addr; 513 int i, ret = 0; 514 515 printf("xfer: num: %d, addr: %#x\n", num, addr); 516 for (i = 0; i < num; i++) { 517 if (msgs[i].len == 0) { 518 printf("unsupported transfer %d/%d, no data\n", 519 i + 1, num); 520 return -EOPNOTSUPP; 521 } 522 } 523 524 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 525 526 /* Set slave device address taken from the first I2C message */ 527 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1) 528 addr = DDC_ADDR; 529 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 530 531 /* Set slave device register address on transfer */ 532 i2c->is_regaddr = false; 533 534 /* Set segment pointer for I2C extended read mode operation */ 535 i2c->is_segment = false; 536 537 for (i = 0; i < num; i++) { 538 debug("xfer: num: %d/%d, len: %d, flags: %#x\n", 539 i + 1, num, msgs[i].len, msgs[i].flags); 540 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 541 i2c->is_segment = true; 542 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 543 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 544 } else { 545 if (msgs[i].flags & I2C_M_RD) 546 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 547 msgs[i].len); 548 else 549 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 550 msgs[i].len); 551 } 552 if (ret < 0) 553 break; 554 } 555 556 if (!ret) 557 ret = num; 558 559 /* Mute DONE and ERROR interrupts */ 560 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 561 HDMI_IH_MUTE_I2CM_STAT0); 562 563 return ret; 564 } 565 566 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 567 { 568 u32 val; 569 570 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 571 if (msec-- == 0) 572 return false; 573 udelay(1000); 574 } 575 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 576 577 return true; 578 } 579 580 static void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 581 unsigned char addr) 582 { 583 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 584 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 585 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 586 HDMI_PHY_I2CM_DATAO_1_ADDR); 587 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 588 HDMI_PHY_I2CM_DATAO_0_ADDR); 589 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 590 HDMI_PHY_I2CM_OPERATION_ADDR); 591 hdmi_phy_wait_i2c_done(hdmi, 1000); 592 } 593 594 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 595 { 596 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 597 HDMI_PHY_CONF0_PDZ_OFFSET, 598 HDMI_PHY_CONF0_PDZ_MASK); 599 } 600 601 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 602 { 603 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 604 HDMI_PHY_CONF0_ENTMDS_OFFSET, 605 HDMI_PHY_CONF0_ENTMDS_MASK); 606 } 607 608 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 609 { 610 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 611 HDMI_PHY_CONF0_SVSRET_OFFSET, 612 HDMI_PHY_CONF0_SVSRET_MASK); 613 } 614 615 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 616 { 617 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 618 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 619 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 620 } 621 622 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 623 { 624 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 625 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 626 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 627 } 628 629 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 630 { 631 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 632 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 633 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 634 } 635 636 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 637 { 638 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 639 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 640 HDMI_PHY_CONF0_SELDIPIF_MASK); 641 } 642 643 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 644 { 645 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 646 unsigned int i; 647 u16 val; 648 649 if (phy->gen == 1) { 650 dw_hdmi_phy_enable_tmds(hdmi, 0); 651 dw_hdmi_phy_enable_powerdown(hdmi, true); 652 return; 653 } 654 655 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 656 657 /* 658 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 659 * to low power mode. 660 */ 661 for (i = 0; i < 5; ++i) { 662 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 663 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 664 break; 665 666 udelay(2000); 667 } 668 669 if (val & HDMI_PHY_TX_PHY_LOCK) 670 printf("PHY failed to power down\n"); 671 else 672 printf("PHY powered down in %u iterations\n", i); 673 674 dw_hdmi_phy_gen2_pddq(hdmi, 1); 675 } 676 677 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 678 { 679 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 680 unsigned int i; 681 u8 val; 682 683 if (phy->gen == 1) { 684 dw_hdmi_phy_enable_powerdown(hdmi, false); 685 686 /* Toggle TMDS enable. */ 687 dw_hdmi_phy_enable_tmds(hdmi, 0); 688 dw_hdmi_phy_enable_tmds(hdmi, 1); 689 return 0; 690 } 691 692 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 693 dw_hdmi_phy_gen2_pddq(hdmi, 0); 694 695 /* Wait for PHY PLL lock */ 696 for (i = 0; i < 5; ++i) { 697 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 698 if (val) 699 break; 700 701 udelay(2000); 702 } 703 704 if (!val) { 705 printf("PHY PLL failed to lock\n"); 706 return -ETIMEDOUT; 707 } 708 printf("PHY PLL locked %u iterations\n", i); 709 710 return 0; 711 } 712 713 /* 714 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 715 * information the DWC MHL PHY has the same register layout and is thus also 716 * supported by this function. 717 */ 718 static 719 int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 720 const struct dw_hdmi_plat_data *pdata, 721 unsigned long mpixelclock) 722 { 723 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 724 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 725 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 726 unsigned int tmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 727 unsigned int depth = 728 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 729 730 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) && 731 pdata->mpll_cfg_420) 732 mpll_config = pdata->mpll_cfg_420; 733 734 /* PLL/MPLL Cfg - always match on final entry */ 735 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 736 if (mpixelclock <= mpll_config->mpixelclock) 737 break; 738 739 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 740 if (tmdsclock <= curr_ctrl->mpixelclock) 741 break; 742 743 for (; phy_config->mpixelclock != ~0UL; phy_config++) 744 if (tmdsclock <= phy_config->mpixelclock) 745 break; 746 747 if (mpll_config->mpixelclock == ~0UL || 748 curr_ctrl->mpixelclock == ~0UL || 749 phy_config->mpixelclock == ~0UL) 750 return -EINVAL; 751 752 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 753 depth = fls(depth - 8); 754 else 755 depth = 0; 756 if (depth) 757 depth--; 758 759 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].cpce, 760 HDMI_3D_TX_PHY_CPCE_CTRL); 761 762 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].gmp, 763 HDMI_3D_TX_PHY_GMPCTRL); 764 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[depth], 765 HDMI_3D_TX_PHY_CURRCTRL); 766 767 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 768 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 769 HDMI_3D_TX_PHY_MSM_CTRL); 770 771 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 772 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 773 HDMI_3D_TX_PHY_CKSYMTXCTRL); 774 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 775 HDMI_3D_TX_PHY_VLEVCTRL); 776 777 return 0; 778 } 779 780 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 781 { 782 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 783 .name = "DWC HDMI TX PHY", 784 .gen = 1, 785 }, { 786 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 787 .name = "DWC MHL PHY + HEAC PHY", 788 .gen = 2, 789 .has_svsret = true, 790 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 791 }, { 792 .type = DW_HDMI_PHY_DWC_MHL_PHY, 793 .name = "DWC MHL PHY", 794 .gen = 2, 795 .has_svsret = true, 796 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 797 }, { 798 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 799 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 800 .gen = 2, 801 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 802 }, { 803 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 804 .name = "DWC HDMI 3D TX PHY", 805 .gen = 2, 806 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 807 }, { 808 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 809 .name = "DWC HDMI 2.0 TX PHY", 810 .gen = 2, 811 .has_svsret = true, 812 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 813 }, { 814 .type = DW_HDMI_PHY_VENDOR_PHY, 815 .name = "Vendor PHY", 816 } 817 }; 818 819 static int rockchip_dw_hdmi_scrambling_enable(struct dw_hdmi *hdmi, 820 int enable) 821 { 822 u8 stat; 823 824 drm_scdc_readb(&hdmi->adap, SCDC_TMDS_CONFIG, &stat); 825 826 if (stat < 0) { 827 debug("Failed to read tmds config\n"); 828 return false; 829 } 830 831 if (enable == 1) { 832 /* Write on Rx the bit Scrambling_Enable, register 0x20 */ 833 stat |= SCDC_SCRAMBLING_ENABLE; 834 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 835 /* TMDS software reset request */ 836 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 837 HDMI_MC_SWRSTZ); 838 /* Enable/Disable Scrambling */ 839 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); 840 } else { 841 /* Enable/Disable Scrambling */ 842 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); 843 /* TMDS software reset request */ 844 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 845 HDMI_MC_SWRSTZ); 846 /* Write on Rx the bit Scrambling_Enable, register 0x20 */ 847 stat &= ~SCDC_SCRAMBLING_ENABLE; 848 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 849 } 850 851 return 0; 852 } 853 854 static void rockchip_dw_hdmi_scdc_set_tmds_rate(struct dw_hdmi *hdmi) 855 { 856 u8 stat; 857 858 drm_scdc_readb(&hdmi->adap, SCDC_TMDS_CONFIG, &stat); 859 if (hdmi->hdmi_data.video_mode.mtmdsclock > 340000000) 860 stat |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 861 else 862 stat &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 863 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 864 } 865 866 static int hdmi_phy_configure(struct dw_hdmi *hdmi) 867 { 868 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 869 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 870 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 871 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 872 int ret; 873 874 dw_hdmi_phy_power_off(hdmi); 875 876 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ 877 if (hdmi->edid_data.display_info.hdmi.scdc.supported) 878 rockchip_dw_hdmi_scdc_set_tmds_rate(hdmi); 879 880 /* Leave low power consumption mode by asserting SVSRET. */ 881 if (phy->has_svsret) 882 dw_hdmi_phy_enable_svsret(hdmi, 1); 883 884 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 885 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 886 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 887 888 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 889 890 hdmi_phy_test_clear(hdmi, 1); 891 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, 892 HDMI_PHY_I2CM_SLAVE_ADDR); 893 hdmi_phy_test_clear(hdmi, 0); 894 895 /* Write to the PHY as configured by the platform */ 896 if (pdata->configure_phy) 897 ret = pdata->configure_phy(hdmi, pdata, mpixelclock); 898 else 899 ret = phy->configure(hdmi, pdata, mpixelclock); 900 if (ret) { 901 printf("PHY configuration failed (clock %lu)\n", 902 mpixelclock); 903 return ret; 904 } 905 906 /* Wait for resuming transmission of TMDS clock and data */ 907 if (mtmdsclock > 340000000) 908 mdelay(100); 909 910 return dw_hdmi_phy_power_on(hdmi); 911 } 912 913 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, 914 void *data) 915 { 916 int i, ret; 917 918 /* HDMI Phy spec says to do the phy initialization sequence twice */ 919 for (i = 0; i < 2; i++) { 920 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 921 dw_hdmi_phy_sel_interface_control(hdmi, 0); 922 ret = hdmi_phy_configure(hdmi); 923 if (ret) 924 return ret; 925 } 926 927 return 0; 928 } 929 930 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, 931 void *data) 932 { 933 dw_hdmi_phy_power_off(hdmi); 934 } 935 936 static enum drm_connector_status 937 dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data) 938 { 939 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 940 connector_status_connected : connector_status_disconnected; 941 } 942 943 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 944 .init = dw_hdmi_phy_init, 945 .disable = dw_hdmi_phy_disable, 946 .read_hpd = dw_hdmi_phy_read_hpd, 947 }; 948 949 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 950 { 951 unsigned int i; 952 u8 phy_type; 953 954 phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID); 955 956 /* 957 * RK3228 and RK3328 phy_type is DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 958 * but it has a vedor phy. 959 */ 960 if (phy_type == DW_HDMI_PHY_VENDOR_PHY || 961 hdmi->dev_type == RK3328_HDMI || 962 hdmi->dev_type == RK3228_HDMI) { 963 /* Vendor PHYs require support from the glue layer. */ 964 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 965 printf( 966 "Vendor HDMI PHY not supported by glue layer\n"); 967 return -ENODEV; 968 } 969 970 hdmi->phy.ops = hdmi->plat_data->phy_ops; 971 hdmi->phy.data = hdmi->plat_data->phy_data; 972 hdmi->phy.name = hdmi->plat_data->phy_name; 973 return 0; 974 } 975 976 /* Synopsys PHYs are handled internally. */ 977 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 978 if (dw_hdmi_phys[i].type == phy_type) { 979 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 980 hdmi->phy.name = dw_hdmi_phys[i].name; 981 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 982 983 if (!dw_hdmi_phys[i].configure && 984 !hdmi->plat_data->configure_phy) { 985 printf("%s requires platform support\n", 986 hdmi->phy.name); 987 return -ENODEV; 988 } 989 990 return 0; 991 } 992 } 993 994 printf("Unsupported HDMI PHY type (%02x)\n", phy_type); 995 return -ENODEV; 996 } 997 998 static unsigned int 999 hdmi_get_tmdsclock(struct dw_hdmi *hdmi, unsigned long mpixelclock) 1000 { 1001 unsigned int tmdsclock = mpixelclock; 1002 unsigned int depth = 1003 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 1004 1005 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1006 switch (depth) { 1007 case 16: 1008 tmdsclock = mpixelclock * 2; 1009 break; 1010 case 12: 1011 tmdsclock = mpixelclock * 3 / 2; 1012 break; 1013 case 10: 1014 tmdsclock = mpixelclock * 5 / 4; 1015 break; 1016 default: 1017 break; 1018 } 1019 } 1020 1021 return tmdsclock; 1022 } 1023 1024 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1025 const struct drm_display_mode *mode) 1026 { 1027 u8 bytes = 0, inv_val = 0; 1028 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1029 struct drm_hdmi_info *hdmi_info = &hdmi->edid_data.display_info.hdmi; 1030 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1031 unsigned int hdisplay, vdisplay; 1032 1033 vmode->mpixelclock = mode->crtc_clock * 1000; 1034 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == 1035 DRM_MODE_FLAG_3D_FRAME_PACKING) 1036 vmode->mpixelclock *= 2; 1037 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock); 1038 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1039 vmode->mtmdsclock /= 2; 1040 printf("final pixclk = %d tmdsclk = %d\n", 1041 vmode->mpixelclock, vmode->mtmdsclock); 1042 1043 /* Set up HDMI_FC_INVIDCONF 1044 * fc_invidconf.HDCP_keepout must be set (1'b1) 1045 * when activate the scrambler feature. 1046 */ 1047 inv_val = (vmode->mtmdsclock > 340000000 || 1048 (hdmi_info->scdc.scrambling.low_rates && 1049 hdmi->scramble_low_rates) ? 1050 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 1051 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 1052 1053 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 1054 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 1055 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 1056 1057 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 1058 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 1059 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 1060 1061 inv_val |= (vmode->mdataenablepolarity ? 1062 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 1063 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 1064 1065 if (hdmi->vic == 39) 1066 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 1067 else 1068 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1069 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 1070 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 1071 1072 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1073 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 1074 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 1075 1076 inv_val |= hdmi->sink_is_hdmi ? 1077 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 1078 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 1079 1080 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 1081 1082 hdisplay = mode->hdisplay; 1083 hblank = mode->htotal - mode->hdisplay; 1084 h_de_hs = mode->hsync_start - mode->hdisplay; 1085 hsync_len = mode->hsync_end - mode->hsync_start; 1086 1087 /* 1088 * When we're setting a YCbCr420 mode, we need 1089 * to adjust the horizontal timing to suit. 1090 */ 1091 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1092 hdisplay /= 2; 1093 hblank /= 2; 1094 h_de_hs /= 2; 1095 hsync_len /= 2; 1096 } 1097 1098 vdisplay = mode->vdisplay; 1099 vblank = mode->vtotal - mode->vdisplay; 1100 v_de_vs = mode->vsync_start - mode->vdisplay; 1101 vsync_len = mode->vsync_end - mode->vsync_start; 1102 1103 /* 1104 * When we're setting an interlaced mode, we need 1105 * to adjust the vertical timing to suit. 1106 */ 1107 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1108 vdisplay /= 2; 1109 vblank /= 2; 1110 v_de_vs /= 2; 1111 vsync_len /= 2; 1112 } else if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == 1113 DRM_MODE_FLAG_3D_FRAME_PACKING) { 1114 vdisplay += mode->vtotal; 1115 } 1116 1117 /* Scrambling Control */ 1118 if (hdmi_info->scdc.supported) { 1119 if (vmode->mtmdsclock > 340000000 || 1120 (hdmi_info->scdc.scrambling.low_rates && 1121 hdmi->scramble_low_rates)) { 1122 drm_scdc_readb(&hdmi->adap, SCDC_SINK_VERSION, &bytes); 1123 drm_scdc_writeb(&hdmi->adap, SCDC_SOURCE_VERSION, 1124 bytes); 1125 rockchip_dw_hdmi_scrambling_enable(hdmi, 1); 1126 } else { 1127 rockchip_dw_hdmi_scrambling_enable(hdmi, 0); 1128 } 1129 } 1130 1131 /* Set up horizontal active pixel width */ 1132 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1); 1133 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0); 1134 1135 /* Set up vertical active lines */ 1136 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 1137 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 1138 1139 /* Set up horizontal blanking pixel region width */ 1140 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 1141 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 1142 1143 /* Set up vertical blanking pixel region width */ 1144 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 1145 1146 /* Set up HSYNC active edge delay width (in pixel clks) */ 1147 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 1148 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 1149 1150 /* Set up VSYNC active edge delay (in lines) */ 1151 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 1152 1153 /* Set up HSYNC active pulse width (in pixel clks) */ 1154 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 1155 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 1156 1157 /* Set up VSYNC active edge delay (in lines) */ 1158 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 1159 } 1160 1161 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 1162 { 1163 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 1164 unsigned i; 1165 u32 csc_scale = 1; 1166 int enc_out_rgb, enc_in_rgb; 1167 1168 enc_out_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format); 1169 enc_in_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format); 1170 1171 if (is_color_space_conversion(hdmi)) { 1172 if (enc_out_rgb && enc_in_rgb) { 1173 csc_coeff = &csc_coeff_full_to_limited; 1174 csc_scale = 0; 1175 } else if (enc_out_rgb) { 1176 if (hdmi->hdmi_data.enc_out_encoding == 1177 V4L2_YCBCR_ENC_601) 1178 csc_coeff = &csc_coeff_rgb_out_eitu601; 1179 else 1180 csc_coeff = &csc_coeff_rgb_out_eitu709; 1181 } else if (enc_in_rgb) { 1182 if (hdmi->hdmi_data.enc_out_encoding == 1183 V4L2_YCBCR_ENC_601) 1184 csc_coeff = &csc_coeff_rgb_in_eitu601; 1185 else 1186 csc_coeff = &csc_coeff_rgb_in_eitu709; 1187 csc_scale = 0; 1188 } 1189 } 1190 1191 /* The CSC registers are sequential, alternating MSB then LSB */ 1192 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 1193 u16 coeff_a = (*csc_coeff)[0][i]; 1194 u16 coeff_b = (*csc_coeff)[1][i]; 1195 u16 coeff_c = (*csc_coeff)[2][i]; 1196 1197 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 1198 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 1199 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 1200 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 1201 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 1202 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 1203 } 1204 1205 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 1206 HDMI_CSC_SCALE); 1207 } 1208 1209 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 1210 { 1211 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 1212 return 0; 1213 1214 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1215 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1216 return 1; 1217 1218 return 0; 1219 } 1220 1221 static void hdmi_video_csc(struct dw_hdmi *hdmi) 1222 { 1223 int color_depth = 0; 1224 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 1225 int decimation = 0; 1226 1227 /* YCC422 interpolation to 444 mode */ 1228 if (is_color_space_interpolation(hdmi)) 1229 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 1230 else if (is_color_space_decimation(hdmi)) 1231 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 1232 1233 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 1234 case 8: 1235 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 1236 break; 1237 case 10: 1238 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 1239 break; 1240 case 12: 1241 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 1242 break; 1243 case 16: 1244 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 1245 break; 1246 1247 default: 1248 return; 1249 } 1250 1251 /* Configure the CSC registers */ 1252 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 1253 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 1254 HDMI_CSC_SCALE); 1255 1256 dw_hdmi_update_csc_coeffs(hdmi); 1257 } 1258 1259 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 1260 { 1261 u8 clkdis; 1262 1263 /* control period minimum duration */ 1264 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 1265 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 1266 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 1267 1268 /* Set to fill TMDS data channels */ 1269 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 1270 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 1271 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 1272 1273 /* Enable pixel clock and tmds data path */ 1274 clkdis = 0x7F; 1275 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 1276 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1277 1278 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1279 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1280 1281 /* Enable csc path */ 1282 if (is_color_space_conversion(hdmi)) { 1283 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 1284 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1285 } 1286 1287 /* Enable pixel repetition path */ 1288 if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) { 1289 clkdis &= ~HDMI_MC_CLKDIS_PREPCLK_DISABLE; 1290 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1291 } 1292 1293 /* Enable color space conversion if needed */ 1294 if (is_color_space_conversion(hdmi)) 1295 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 1296 HDMI_MC_FLOWCTRL); 1297 else 1298 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 1299 HDMI_MC_FLOWCTRL); 1300 } 1301 1302 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 1303 { 1304 unsigned int count; 1305 unsigned int i; 1306 u8 val; 1307 1308 /* 1309 * Under some circumstances the Frame Composer arithmetic unit can miss 1310 * an FC register write due to being busy processing the previous one. 1311 * The issue can be worked around by issuing a TMDS software reset and 1312 * then write one of the FC registers several times. 1313 * 1314 * The number of iterations matters and depends on the HDMI TX revision 1315 * (and possibly on the platform). So far only i.MX6Q (v1.30a) and 1316 * i.MX6DL (v1.31a) have been identified as needing the workaround, with 1317 * 4 and 1 iterations respectively. 1318 */ 1319 1320 switch (hdmi->version) { 1321 case 0x130a: 1322 count = 4; 1323 break; 1324 case 0x131a: 1325 case 0x200a: 1326 case 0x201a: 1327 case 0x211a: 1328 count = 1; 1329 break; 1330 default: 1331 return; 1332 } 1333 1334 /* TMDS software reset */ 1335 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 1336 1337 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 1338 for (i = 0; i < count; i++) 1339 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 1340 } 1341 1342 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 1343 { 1344 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 1345 HDMI_IH_MUTE_FC_STAT2); 1346 } 1347 1348 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 1349 { 1350 unsigned int color_depth = 0; 1351 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 1352 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 1353 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1354 u8 val, vp_conf; 1355 1356 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1357 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) || 1358 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1359 switch (hdmi_bus_fmt_color_depth( 1360 hdmi->hdmi_data.enc_out_bus_format)) { 1361 case 8: 1362 color_depth = 0; 1363 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1364 break; 1365 case 10: 1366 color_depth = 5; 1367 break; 1368 case 12: 1369 color_depth = 6; 1370 break; 1371 case 16: 1372 color_depth = 7; 1373 break; 1374 default: 1375 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1376 } 1377 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1378 switch (hdmi_bus_fmt_color_depth( 1379 hdmi->hdmi_data.enc_out_bus_format)) { 1380 case 0: 1381 case 8: 1382 remap_size = HDMI_VP_REMAP_YCC422_16bit; 1383 break; 1384 case 10: 1385 remap_size = HDMI_VP_REMAP_YCC422_20bit; 1386 break; 1387 case 12: 1388 remap_size = HDMI_VP_REMAP_YCC422_24bit; 1389 break; 1390 1391 default: 1392 return; 1393 } 1394 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 1395 } else { 1396 return; 1397 } 1398 1399 /* set the packetizer registers */ 1400 val = (color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 1401 HDMI_VP_PR_CD_COLOR_DEPTH_MASK; 1402 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 1403 1404 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 1405 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 1406 1407 /* Data from pixel repeater block */ 1408 if (hdmi_data->pix_repet_factor > 0) { 1409 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 1410 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 1411 } else { /* data from packetizer block */ 1412 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 1413 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 1414 } 1415 1416 hdmi_modb(hdmi, vp_conf, 1417 HDMI_VP_CONF_PR_EN_MASK | 1418 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 1419 1420 if ((color_depth == 5 && hdmi->previous_mode.htotal % 4) || 1421 (color_depth == 6 && hdmi->previous_mode.htotal % 2)) 1422 hdmi_modb(hdmi, 0, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, 1423 HDMI_VP_STUFF); 1424 else 1425 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 1426 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 1427 1428 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 1429 1430 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 1431 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1432 HDMI_VP_CONF_PP_EN_ENABLE | 1433 HDMI_VP_CONF_YCC422_EN_DISABLE; 1434 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 1435 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1436 HDMI_VP_CONF_PP_EN_DISABLE | 1437 HDMI_VP_CONF_YCC422_EN_ENABLE; 1438 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 1439 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 1440 HDMI_VP_CONF_PP_EN_DISABLE | 1441 HDMI_VP_CONF_YCC422_EN_DISABLE; 1442 } else { 1443 return; 1444 } 1445 1446 hdmi_modb(hdmi, vp_conf, 1447 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 1448 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 1449 1450 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 1451 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 1452 HDMI_VP_STUFF_PP_STUFFING_MASK | 1453 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 1454 1455 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 1456 HDMI_VP_CONF); 1457 } 1458 1459 static void hdmi_video_sample(struct dw_hdmi *hdmi) 1460 { 1461 int color_format = 0; 1462 u8 val; 1463 1464 switch (hdmi->hdmi_data.enc_in_bus_format) { 1465 case MEDIA_BUS_FMT_RGB888_1X24: 1466 color_format = 0x01; 1467 break; 1468 case MEDIA_BUS_FMT_RGB101010_1X30: 1469 color_format = 0x03; 1470 break; 1471 case MEDIA_BUS_FMT_RGB121212_1X36: 1472 color_format = 0x05; 1473 break; 1474 case MEDIA_BUS_FMT_RGB161616_1X48: 1475 color_format = 0x07; 1476 break; 1477 1478 case MEDIA_BUS_FMT_YUV8_1X24: 1479 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1480 color_format = 0x09; 1481 break; 1482 case MEDIA_BUS_FMT_YUV10_1X30: 1483 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1484 color_format = 0x0B; 1485 break; 1486 case MEDIA_BUS_FMT_YUV12_1X36: 1487 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 1488 color_format = 0x0D; 1489 break; 1490 case MEDIA_BUS_FMT_YUV16_1X48: 1491 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 1492 color_format = 0x0F; 1493 break; 1494 1495 case MEDIA_BUS_FMT_UYVY8_1X16: 1496 color_format = 0x16; 1497 break; 1498 case MEDIA_BUS_FMT_UYVY10_1X20: 1499 color_format = 0x14; 1500 break; 1501 case MEDIA_BUS_FMT_UYVY12_1X24: 1502 color_format = 0x12; 1503 break; 1504 1505 default: 1506 return; 1507 } 1508 1509 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 1510 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 1511 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 1512 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 1513 1514 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 1515 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 1516 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 1517 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 1518 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 1519 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 1520 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 1521 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 1522 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 1523 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 1524 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 1525 } 1526 1527 static void dw_hdmi_disable(struct dw_hdmi *hdmi, struct display_state *state) 1528 { 1529 if (hdmi->phy.enabled) { 1530 hdmi->phy.ops->disable(hdmi, state); 1531 hdmi->phy.enabled = false; 1532 } 1533 } 1534 1535 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1536 { 1537 struct hdmi_avi_infoframe frame; 1538 u8 val; 1539 bool is_hdmi2 = false; 1540 enum hdmi_quantization_range rgb_quant_range = 1541 hdmi->hdmi_data.quant_range; 1542 1543 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) || 1544 hdmi->edid_data.display_info.hdmi.scdc.supported) 1545 is_hdmi2 = true; 1546 /* Initialise info frame from DRM mode */ 1547 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2); 1548 1549 /* 1550 * Ignore monitor selectable quantization, use quantization set 1551 * by the user 1552 */ 1553 drm_hdmi_avi_infoframe_quant_range(&frame, mode, rgb_quant_range, 1554 true); 1555 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1556 frame.colorspace = HDMI_COLORSPACE_YUV444; 1557 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1558 frame.colorspace = HDMI_COLORSPACE_YUV422; 1559 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1560 frame.colorspace = HDMI_COLORSPACE_YUV420; 1561 else 1562 frame.colorspace = HDMI_COLORSPACE_RGB; 1563 1564 /* Set up colorimetry */ 1565 switch (hdmi->hdmi_data.enc_out_encoding) { 1566 case V4L2_YCBCR_ENC_601: 1567 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1568 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1569 else 1570 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1571 frame.extended_colorimetry = 1572 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1573 break; 1574 case V4L2_YCBCR_ENC_709: 1575 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1576 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1577 else 1578 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1579 frame.extended_colorimetry = 1580 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1581 break; 1582 default: /* Carries no data */ 1583 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1584 frame.extended_colorimetry = 1585 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1586 break; 1587 } 1588 1589 frame.scan_mode = HDMI_SCAN_MODE_NONE; 1590 1591 /* 1592 * The Designware IP uses a different byte format from standard 1593 * AVI info frames, though generally the bits are in the correct 1594 * bytes. 1595 */ 1596 1597 /* 1598 * AVI data byte 1 differences: Colorspace in bits 0,1,7 rather than 1599 * 5,6,7, active aspect present in bit 6 rather than 4. 1600 */ 1601 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 0x3); 1602 if (frame.active_aspect & 15) 1603 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1604 if (frame.top_bar || frame.bottom_bar) 1605 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1606 if (frame.left_bar || frame.right_bar) 1607 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1608 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1609 1610 /* AVI data byte 2 differences: none */ 1611 val = ((frame.colorimetry & 0x3) << 6) | 1612 ((frame.picture_aspect & 0x3) << 4) | 1613 (frame.active_aspect & 0xf); 1614 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1615 1616 /* AVI data byte 3 differences: none */ 1617 val = ((frame.extended_colorimetry & 0x7) << 4) | 1618 ((frame.quantization_range & 0x3) << 2) | 1619 (frame.nups & 0x3); 1620 if (frame.itc) 1621 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1622 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1623 1624 /* AVI data byte 4 differences: none */ 1625 val = frame.video_code & 0x7f; 1626 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1627 1628 /* AVI Data Byte 5- set up input and output pixel repetition */ 1629 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1630 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1631 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1632 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1633 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1634 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1635 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1636 1637 /* 1638 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1639 * ycc range in bits 2,3 rather than 6,7 1640 */ 1641 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1642 (frame.content_type & 0x3); 1643 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1644 1645 /* AVI Data Bytes 6-13 */ 1646 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1647 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1648 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1649 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1650 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1651 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1652 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1653 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1654 } 1655 1656 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1657 struct drm_display_mode *mode) 1658 { 1659 struct hdmi_vendor_infoframe frame; 1660 u8 buffer[10]; 1661 ssize_t err; 1662 1663 /* Disable HDMI vendor specific infoframe send */ 1664 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1665 HDMI_FC_DATAUTO0_VSD_MASK); 1666 1667 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode); 1668 if (err < 0) 1669 /* 1670 * Going into that statement does not means vendor infoframe 1671 * fails. It just informed us that vendor infoframe is not 1672 * needed for the selected mode. Only 4k or stereoscopic 3D 1673 * mode requires vendor infoframe. So just simply return. 1674 */ 1675 return; 1676 1677 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1678 if (err < 0) { 1679 printf("Failed to pack vendor infoframe: %zd\n", err); 1680 return; 1681 } 1682 1683 /* Set the length of HDMI vendor specific InfoFrame payload */ 1684 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1685 1686 /* Set 24bit IEEE Registration Identifier */ 1687 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1688 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1689 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1690 1691 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1692 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1693 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1694 1695 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1696 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1697 1698 /* Packet frame interpolation */ 1699 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1700 1701 /* Auto packets per frame and line spacing */ 1702 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1703 1704 /* Configures the Frame Composer On RDRB mode */ 1705 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1706 HDMI_FC_DATAUTO0_VSD_MASK); 1707 } 1708 1709 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 1710 unsigned int n) 1711 { 1712 /* Must be set/cleared first */ 1713 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 1714 1715 /* nshift factor = 0 */ 1716 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 1717 1718 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 1719 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 1720 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 1721 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 1722 1723 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 1724 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 1725 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 1726 } 1727 1728 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi, 1729 unsigned long pixel_clk, 1730 unsigned long freq) 1731 { 1732 const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data; 1733 const struct dw_hdmi_audio_tmds_n *tmds_n = NULL; 1734 int i; 1735 1736 if (plat_data->tmds_n_table) { 1737 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) { 1738 if (pixel_clk == plat_data->tmds_n_table[i].tmds) { 1739 tmds_n = &plat_data->tmds_n_table[i]; 1740 break; 1741 } 1742 } 1743 } 1744 1745 if (!tmds_n) { 1746 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) { 1747 if (pixel_clk == common_tmds_n_table[i].tmds) { 1748 tmds_n = &common_tmds_n_table[i]; 1749 break; 1750 } 1751 } 1752 } 1753 1754 if (!tmds_n) 1755 return -ENOENT; 1756 1757 switch (freq) { 1758 case 32000: 1759 return tmds_n->n_32k; 1760 case 44100: 1761 case 88200: 1762 case 176400: 1763 return (freq / 44100) * tmds_n->n_44k1; 1764 case 48000: 1765 case 96000: 1766 case 192000: 1767 return (freq / 48000) * tmds_n->n_48k; 1768 default: 1769 return -ENOENT; 1770 } 1771 } 1772 1773 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n, 1774 unsigned int pixel_clk) 1775 { 1776 u64 final, diff; 1777 u64 cts; 1778 1779 final = (u64)pixel_clk * n; 1780 1781 cts = final; 1782 do_div(cts, 128 * freq); 1783 1784 diff = final - (u64)cts * (128 * freq); 1785 1786 return diff; 1787 } 1788 1789 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi, 1790 unsigned long pixel_clk, 1791 unsigned long freq) 1792 { 1793 unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500); 1794 unsigned int max_n = (128 * freq) / 300; 1795 unsigned int ideal_n = (128 * freq) / 1000; 1796 unsigned int best_n_distance = ideal_n; 1797 unsigned int best_n = 0; 1798 u64 best_diff = U64_MAX; 1799 int n; 1800 1801 /* If the ideal N could satisfy the audio math, then just take it */ 1802 if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0) 1803 return ideal_n; 1804 1805 for (n = min_n; n <= max_n; n++) { 1806 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk); 1807 1808 if (diff < best_diff || (diff == best_diff && 1809 abs(n - ideal_n) < best_n_distance)) { 1810 best_n = n; 1811 best_diff = diff; 1812 best_n_distance = abs(best_n - ideal_n); 1813 } 1814 1815 /* 1816 * The best N already satisfy the audio math, and also be 1817 * the closest value to ideal N, so just cut the loop. 1818 */ 1819 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance)) 1820 break; 1821 } 1822 1823 return best_n; 1824 } 1825 1826 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk, 1827 unsigned long sample_rate) 1828 { 1829 int n; 1830 1831 n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate); 1832 if (n > 0) 1833 return n; 1834 1835 printf("Rate %lu missing; compute N dynamically\n", 1836 pixel_clk); 1837 1838 return hdmi_compute_n(hdmi, pixel_clk, sample_rate); 1839 } 1840 1841 static 1842 void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, unsigned long pixel_clk, 1843 unsigned int sample_rate) 1844 { 1845 unsigned long ftdms = pixel_clk; 1846 unsigned int n, cts; 1847 u64 tmp; 1848 1849 n = hdmi_find_n(hdmi, pixel_clk, sample_rate); 1850 1851 /* 1852 * Compute the CTS value from the N value. Note that CTS and N 1853 * can be up to 20 bits in total, so we need 64-bit math. Also 1854 * note that our TDMS clock is not fully accurate; it is accurate 1855 * to kHz. This can introduce an unnecessary remainder in the 1856 * calculation below, so we don't try to warn about that. 1857 */ 1858 tmp = (u64)ftdms * n; 1859 do_div(tmp, 128 * sample_rate); 1860 cts = tmp; 1861 1862 printf("%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", __func__, 1863 sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000, n, cts); 1864 1865 hdmi->audio_n = n; 1866 hdmi->audio_cts = cts; 1867 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 1868 } 1869 1870 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 1871 { 1872 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 1873 hdmi->sample_rate); 1874 } 1875 1876 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi) 1877 { 1878 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS); 1879 } 1880 1881 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 1882 { 1883 hdmi->sample_rate = rate; 1884 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 1885 hdmi->sample_rate); 1886 } 1887 1888 static int dw_hdmi_hdcp_load_key(struct dw_hdmi *hdmi) 1889 { 1890 int i, j, ret, val; 1891 struct hdcp_keys *hdcp_keys; 1892 1893 val = sizeof(*hdcp_keys); 1894 hdcp_keys = malloc(val); 1895 if (!hdcp_keys) 1896 return -ENOMEM; 1897 1898 memset(hdcp_keys, 0, val); 1899 1900 ret = vendor_storage_read(HDMI_HDCP1X_ID, hdcp_keys, val); 1901 if (ret < val) { 1902 printf("HDCP: read size %d\n", ret); 1903 free(hdcp_keys); 1904 return -EINVAL; 1905 } 1906 1907 if (hdcp_keys->KSV[0] == 0x00 && 1908 hdcp_keys->KSV[1] == 0x00 && 1909 hdcp_keys->KSV[2] == 0x00 && 1910 hdcp_keys->KSV[3] == 0x00 && 1911 hdcp_keys->KSV[4] == 0x00) { 1912 printf("HDCP: Invalid hdcp key\n"); 1913 free(hdcp_keys); 1914 return -EINVAL; 1915 } 1916 1917 /* Disable decryption logic */ 1918 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_RMCTL); 1919 /* Poll untile DPK write is allowed */ 1920 do { 1921 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1922 } while ((val & DPK_WR_OK_STS) == 0); 1923 1924 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_DPK6); 1925 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_DPK5); 1926 1927 /* The useful data in ksv should be 5 byte */ 1928 for (i = 4; i >= 0; i--) 1929 hdmi_writeb(hdmi, hdcp_keys->KSV[i], HDMI_HDCPREG_DPK0 + i); 1930 /* Poll untile DPK write is allowed */ 1931 do { 1932 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1933 } while ((val & DPK_WR_OK_STS) == 0); 1934 1935 /* Enable decryption logic */ 1936 hdmi_writeb(hdmi, 1, HDMI_HDCPREG_RMCTL); 1937 hdmi_writeb(hdmi, hdcp_keys->seeds[0], HDMI_HDCPREG_SEED1); 1938 hdmi_writeb(hdmi, hdcp_keys->seeds[1], HDMI_HDCPREG_SEED0); 1939 1940 /* Write encrypt device private key */ 1941 for (i = 0; i < DW_HDMI_HDCP_DPK_LEN - 6; i += 7) { 1942 for (j = 6; j >= 0; j--) 1943 hdmi_writeb(hdmi, hdcp_keys->devicekey[i + j], 1944 HDMI_HDCPREG_DPK0 + j); 1945 do { 1946 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1947 } while ((val & DPK_WR_OK_STS) == 0); 1948 } 1949 1950 free(hdcp_keys); 1951 return 0; 1952 } 1953 1954 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi, 1955 const struct drm_display_mode *mode) 1956 { 1957 u8 vsync_pol, hsync_pol, data_pol, hdmi_dvi; 1958 1959 if (!hdmi->hdcp1x_enable) 1960 return; 1961 1962 /* Configure the video polarity */ 1963 vsync_pol = mode->flags & DRM_MODE_FLAG_PVSYNC ? 1964 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH : 1965 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW; 1966 hsync_pol = mode->flags & DRM_MODE_FLAG_PHSYNC ? 1967 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH : 1968 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW; 1969 data_pol = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1970 hdmi_modb(hdmi, vsync_pol | hsync_pol | data_pol, 1971 HDMI_A_VIDPOLCFG_VSYNCPOL_MASK | 1972 HDMI_A_VIDPOLCFG_HSYNCPOL_MASK | 1973 HDMI_A_VIDPOLCFG_DATAENPOL_MASK, 1974 HDMI_A_VIDPOLCFG); 1975 1976 /* Config the display mode */ 1977 hdmi_dvi = hdmi->sink_is_hdmi ? HDMI_A_HDCPCFG0_HDMIDVI_HDMI : 1978 HDMI_A_HDCPCFG0_HDMIDVI_DVI; 1979 hdmi_modb(hdmi, hdmi_dvi, HDMI_A_HDCPCFG0_HDMIDVI_MASK, 1980 HDMI_A_HDCPCFG0); 1981 1982 if (!(hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS) & 0x3f)) 1983 dw_hdmi_hdcp_load_key(hdmi); 1984 1985 hdmi_modb(hdmi, HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE, 1986 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK, 1987 HDMI_FC_INVIDCONF); 1988 1989 if (hdmi_readb(hdmi, HDMI_CONFIG1_ID) & HDMI_A_HDCP22_MASK) { 1990 hdmi_modb(hdmi, HDMI_HDCP2_OVR_ENABLE | 1991 HDMI_HDCP2_FORCE_DISABLE, 1992 HDMI_HDCP2_OVR_EN_MASK | 1993 HDMI_HDCP2_FORCE_MASK, 1994 HDMI_HDCP2REG_CTRL); 1995 hdmi_writeb(hdmi, 0xff, HDMI_HDCP2REG_MASK); 1996 hdmi_writeb(hdmi, 0xff, HDMI_HDCP2REG_MUTE); 1997 } 1998 1999 hdmi_writeb(hdmi, 0x40, HDMI_A_OESSWCFG); 2000 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE | 2001 HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE | 2002 HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE, 2003 HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK | 2004 HDMI_A_HDCPCFG0_EN11FEATURE_MASK | 2005 HDMI_A_HDCPCFG0_SYNCRICHECK_MASK, HDMI_A_HDCPCFG0); 2006 2007 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE | 2008 HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE, 2009 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK | 2010 HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK, HDMI_A_HDCPCFG1); 2011 2012 /* Reset HDCP Engine */ 2013 if (hdmi_readb(hdmi, HDMI_MC_CLKDIS) & HDMI_MC_CLKDIS_HDCPCLK_MASK) { 2014 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_SWRESET_ASSERT, 2015 HDMI_A_HDCPCFG1_SWRESET_MASK, HDMI_A_HDCPCFG1); 2016 } 2017 2018 hdmi_writeb(hdmi, 0x00, HDMI_A_APIINTMSK); 2019 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_ENABLE, 2020 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 2021 2022 hdmi_modb(hdmi, HDMI_MC_CLKDIS_HDCPCLK_ENABLE, 2023 HDMI_MC_CLKDIS_HDCPCLK_MASK, HDMI_MC_CLKDIS); 2024 2025 printf("%s success\n", __func__); 2026 } 2027 2028 static int dw_hdmi_setup(struct dw_hdmi *hdmi, 2029 struct drm_display_mode *mode, 2030 struct display_state *state) 2031 { 2032 int ret; 2033 void *data = hdmi->plat_data->phy_data; 2034 2035 hdmi_disable_overflow_interrupts(hdmi); 2036 if (!hdmi->vic) 2037 printf("Non-CEA mode used in HDMI\n"); 2038 else 2039 printf("CEA mode used vic=%d\n", hdmi->vic); 2040 2041 if (hdmi->plat_data->get_enc_out_encoding) 2042 hdmi->hdmi_data.enc_out_encoding = 2043 hdmi->plat_data->get_enc_out_encoding(data); 2044 else if (hdmi->vic == 6 || hdmi->vic == 7 || 2045 hdmi->vic == 21 || hdmi->vic == 22 || 2046 hdmi->vic == 2 || hdmi->vic == 3 || 2047 hdmi->vic == 17 || hdmi->vic == 18) 2048 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 2049 else 2050 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 2051 2052 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2053 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1; 2054 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1; 2055 } else { 2056 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 2057 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 2058 } 2059 2060 /* TOFIX: Get input encoding from plat data or fallback to none */ 2061 if (hdmi->plat_data->get_enc_in_encoding) 2062 hdmi->hdmi_data.enc_in_encoding = 2063 hdmi->plat_data->get_enc_in_encoding(data); 2064 else if (hdmi->plat_data->input_bus_encoding) 2065 hdmi->hdmi_data.enc_in_encoding = 2066 hdmi->plat_data->input_bus_encoding; 2067 else 2068 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 2069 2070 if (hdmi->plat_data->get_quant_range) 2071 hdmi->hdmi_data.quant_range = 2072 hdmi->plat_data->get_quant_range(data); 2073 else 2074 hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 2075 2076 /* 2077 * According to the dw-hdmi specification 6.4.2 2078 * vp_pr_cd[3:0]: 2079 * 0000b: No pixel repetition (pixel sent only once) 2080 * 0001b: Pixel sent two times (pixel repeated once) 2081 */ 2082 hdmi->hdmi_data.pix_repet_factor = 2083 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0; 2084 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 2085 2086 /* HDMI Initialization Step B.1 */ 2087 hdmi_av_composer(hdmi, mode); 2088 2089 /* HDMI Initialization Step B.2 */ 2090 ret = hdmi->phy.ops->init(hdmi, state); 2091 if (ret) 2092 return ret; 2093 hdmi->phy.enabled = true; 2094 2095 /* HDMI Initializateion Step B.3 */ 2096 dw_hdmi_enable_video_path(hdmi); 2097 2098 /* HDMI Initialization Step E - Configure audio */ 2099 if (hdmi->sink_has_audio) { 2100 printf("sink has audio support\n"); 2101 hdmi_clk_regenerator_update_pixel_clock(hdmi); 2102 hdmi_enable_audio_clk(hdmi); 2103 } 2104 2105 /* not for DVI mode */ 2106 if (hdmi->sink_is_hdmi) { 2107 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 2108 hdmi_config_AVI(hdmi, mode); 2109 hdmi_config_vendor_specific_infoframe(hdmi, mode); 2110 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_HDMIDVI_HDMI, 2111 HDMI_A_HDCPCFG0_HDMIDVI_MASK, 2112 HDMI_A_HDCPCFG0); 2113 } else { 2114 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_HDMIDVI_DVI, 2115 HDMI_A_HDCPCFG0_HDMIDVI_MASK, 2116 HDMI_A_HDCPCFG0); 2117 printf("%s DVI mode\n", __func__); 2118 } 2119 2120 hdmi_video_packetize(hdmi); 2121 hdmi_video_csc(hdmi); 2122 hdmi_video_sample(hdmi); 2123 hdmi_tx_hdcp_config(hdmi, mode); 2124 dw_hdmi_clear_overflow(hdmi); 2125 2126 return 0; 2127 } 2128 2129 int dw_hdmi_detect_hotplug(struct dw_hdmi *hdmi, 2130 struct display_state *state) 2131 { 2132 return hdmi->phy.ops->read_hpd(hdmi, state); 2133 } 2134 2135 static int dw_hdmi_set_reg_wr(struct dw_hdmi *hdmi) 2136 { 2137 switch (hdmi->io_width) { 2138 case 4: 2139 hdmi->write = dw_hdmi_writel; 2140 hdmi->read = dw_hdmi_readl; 2141 break; 2142 case 1: 2143 hdmi->write = dw_hdmi_writeb; 2144 hdmi->read = dw_hdmi_readb; 2145 break; 2146 default: 2147 printf("reg-io-width must be 1 or 4\n"); 2148 return -EINVAL; 2149 } 2150 2151 return 0; 2152 } 2153 2154 static void initialize_hdmi_mutes(struct dw_hdmi *hdmi) 2155 { 2156 /*mute unnecessary interrupt, only enable hpd */ 2157 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 2158 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 2159 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 2160 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 2161 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 2162 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 2163 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 2164 hdmi_writeb(hdmi, 0xfe, HDMI_IH_MUTE_PHY_STAT0); 2165 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 2166 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 2167 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 2168 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 2169 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 2170 hdmi_writeb(hdmi, 0xf1, HDMI_PHY_MASK0); 2171 2172 /*Force output black*/ 2173 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS2); 2174 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS1); 2175 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS0); 2176 } 2177 2178 static void dw_hdmi_dev_init(struct dw_hdmi *hdmi) 2179 { 2180 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 2181 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 2182 2183 initialize_hdmi_mutes(hdmi); 2184 } 2185 2186 static void dw_hdmi_i2c_set_divs(struct dw_hdmi *hdmi) 2187 { 2188 unsigned long low_ns, high_ns; 2189 unsigned long div_low, div_high; 2190 2191 /* Standard-mode */ 2192 if (hdmi->i2c->scl_high_ns < 4000) 2193 high_ns = 4708; 2194 else 2195 high_ns = hdmi->i2c->scl_high_ns; 2196 2197 if (hdmi->i2c->scl_low_ns < 4700) 2198 low_ns = 4916; 2199 else 2200 low_ns = hdmi->i2c->scl_low_ns; 2201 2202 div_low = (24000 * low_ns) / 1000000; 2203 if ((24000 * low_ns) % 1000000) 2204 div_low++; 2205 2206 div_high = (24000 * high_ns) / 1000000; 2207 if ((24000 * high_ns) % 1000000) 2208 div_high++; 2209 2210 /* Maximum divider supported by hw is 0xffff */ 2211 if (div_low > 0xffff) 2212 div_low = 0xffff; 2213 2214 if (div_high > 0xffff) 2215 div_high = 0xffff; 2216 2217 hdmi_writeb(hdmi, div_high & 0xff, HDMI_I2CM_SS_SCL_HCNT_0_ADDR); 2218 hdmi_writeb(hdmi, (div_high >> 8) & 0xff, 2219 HDMI_I2CM_SS_SCL_HCNT_1_ADDR); 2220 hdmi_writeb(hdmi, div_low & 0xff, HDMI_I2CM_SS_SCL_LCNT_0_ADDR); 2221 hdmi_writeb(hdmi, (div_low >> 8) & 0xff, 2222 HDMI_I2CM_SS_SCL_LCNT_1_ADDR); 2223 } 2224 2225 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 2226 { 2227 /* Software reset */ 2228 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 2229 2230 /* Set Standard Mode speed */ 2231 hdmi_modb(hdmi, HDMI_I2CM_DIV_STD_MODE, 2232 HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV); 2233 2234 /* Set done, not acknowledged and arbitration interrupt polarities */ 2235 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 2236 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 2237 HDMI_I2CM_CTLINT); 2238 2239 /* Clear DONE and ERROR interrupts */ 2240 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 2241 HDMI_IH_I2CM_STAT0); 2242 2243 /* Mute DONE and ERROR interrupts */ 2244 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 2245 HDMI_IH_MUTE_I2CM_STAT0); 2246 2247 /* set SDA high level holding time */ 2248 hdmi_writeb(hdmi, 0x48, HDMI_I2CM_SDA_HOLD); 2249 2250 dw_hdmi_i2c_set_divs(hdmi); 2251 } 2252 2253 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 2254 { 2255 hdmi->audio_enable = true; 2256 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 2257 } 2258 2259 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 2260 { 2261 hdmi->audio_enable = false; 2262 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 2263 } 2264 2265 int rockchip_dw_hdmi_pre_init(struct display_state *state) 2266 { 2267 struct connector_state *conn_state = &state->conn_state; 2268 2269 conn_state->type = DRM_MODE_CONNECTOR_HDMIA; 2270 2271 return 0; 2272 } 2273 2274 int rockchip_dw_hdmi_init(struct display_state *state) 2275 { 2276 struct connector_state *conn_state = &state->conn_state; 2277 const struct rockchip_connector *connector = conn_state->connector; 2278 const struct dw_hdmi_plat_data *pdata = connector->data; 2279 struct crtc_state *crtc_state = &state->crtc_state; 2280 struct dw_hdmi *hdmi; 2281 struct drm_display_mode *mode_buf; 2282 ofnode hdmi_node = conn_state->node; 2283 u32 val; 2284 struct device_node *ddc_node; 2285 2286 hdmi = malloc(sizeof(struct dw_hdmi)); 2287 if (!hdmi) 2288 return -ENOMEM; 2289 2290 memset(hdmi, 0, sizeof(struct dw_hdmi)); 2291 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 2292 if (!mode_buf) 2293 return -ENOMEM; 2294 hdmi->id = of_alias_get_id(ofnode_to_np(hdmi_node), "hdmi"); 2295 if (hdmi->id < 0) 2296 hdmi->id = 0; 2297 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, hdmi->id); 2298 2299 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 2300 2301 hdmi->regs = dev_read_addr_ptr(conn_state->dev); 2302 hdmi->io_width = ofnode_read_s32_default(hdmi_node, "reg-io-width", -1); 2303 2304 if (ofnode_read_bool(hdmi_node, "scramble-low-rates")) 2305 hdmi->scramble_low_rates = true; 2306 2307 if (ofnode_read_bool(hdmi_node, "hdcp1x-enable")) 2308 hdmi->hdcp1x_enable = true; 2309 else 2310 hdmi->hdcp1x_enable = false; 2311 2312 ddc_node = of_parse_phandle(ofnode_to_np(hdmi_node), "ddc-i2c-bus", 0); 2313 if (ddc_node) { 2314 uclass_get_device_by_ofnode(UCLASS_I2C, np_to_ofnode(ddc_node), 2315 &hdmi->adap.i2c_bus); 2316 if (hdmi->adap.i2c_bus) 2317 hdmi->adap.ops = i2c_get_ops(hdmi->adap.i2c_bus); 2318 } 2319 2320 hdmi->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 2321 if (hdmi->grf <= 0) { 2322 printf("%s: Get syscon grf failed (ret=%p)\n", 2323 __func__, hdmi->grf); 2324 return -ENXIO; 2325 } 2326 2327 dw_hdmi_set_reg_wr(hdmi); 2328 2329 if (pdata->grf_vop_sel_reg) { 2330 if (crtc_state->crtc_id) 2331 val = ((1 << pdata->vop_sel_bit) | 2332 (1 << (16 + pdata->vop_sel_bit))); 2333 else 2334 val = ((0 << pdata->vop_sel_bit) | 2335 (1 << (16 + pdata->vop_sel_bit))); 2336 writel(val, hdmi->grf + pdata->grf_vop_sel_reg); 2337 } 2338 2339 hdmi->i2c = malloc(sizeof(struct dw_hdmi_i2c)); 2340 if (!hdmi->i2c) 2341 return -ENOMEM; 2342 hdmi->adap.ddc_xfer = dw_hdmi_i2c_xfer; 2343 2344 /* 2345 * Read high and low time from device tree. If not available use 2346 * the default timing scl clock rate is about 99.6KHz. 2347 */ 2348 hdmi->i2c->scl_high_ns = 2349 ofnode_read_s32_default(hdmi_node, 2350 "ddc-i2c-scl-high-time-ns", 4708); 2351 hdmi->i2c->scl_low_ns = 2352 ofnode_read_s32_default(hdmi_node, 2353 "ddc-i2c-scl-low-time-ns", 4916); 2354 2355 dw_hdmi_i2c_init(hdmi); 2356 conn_state->output_if |= VOP_OUTPUT_IF_HDMI0; 2357 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 2358 2359 hdmi->dev_type = pdata->dev_type; 2360 hdmi->plat_data = pdata; 2361 hdmi->edid_data.mode_buf = mode_buf; 2362 hdmi->sample_rate = 48000; 2363 2364 conn_state->private = hdmi; 2365 dw_hdmi_set_iomux(hdmi->grf, hdmi->dev_type); 2366 dw_hdmi_detect_phy(hdmi); 2367 dw_hdmi_dev_init(hdmi); 2368 2369 return 0; 2370 } 2371 2372 void rockchip_dw_hdmi_deinit(struct display_state *state) 2373 { 2374 struct connector_state *conn_state = &state->conn_state; 2375 struct dw_hdmi *hdmi = conn_state->private; 2376 2377 if (hdmi->i2c) 2378 free(hdmi->i2c); 2379 if (hdmi->edid_data.mode_buf) 2380 free(hdmi->edid_data.mode_buf); 2381 if (hdmi) 2382 free(hdmi); 2383 } 2384 2385 int rockchip_dw_hdmi_prepare(struct display_state *state) 2386 { 2387 return 0; 2388 } 2389 2390 int rockchip_dw_hdmi_enable(struct display_state *state) 2391 { 2392 struct connector_state *conn_state = &state->conn_state; 2393 struct drm_display_mode *mode = &conn_state->mode; 2394 struct dw_hdmi *hdmi = conn_state->private; 2395 2396 if (!hdmi) 2397 return -EFAULT; 2398 2399 /* Store the display mode for plugin/DKMS poweron events */ 2400 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 2401 2402 dw_hdmi_setup(hdmi, mode, state); 2403 2404 return 0; 2405 } 2406 2407 int rockchip_dw_hdmi_disable(struct display_state *state) 2408 { 2409 struct connector_state *conn_state = &state->conn_state; 2410 struct dw_hdmi *hdmi = conn_state->private; 2411 2412 dw_hdmi_disable(hdmi, state); 2413 return 0; 2414 } 2415 2416 int rockchip_dw_hdmi_get_timing(struct display_state *state) 2417 { 2418 int ret, i; 2419 struct connector_state *conn_state = &state->conn_state; 2420 struct drm_display_mode *mode = &conn_state->mode; 2421 struct dw_hdmi *hdmi = conn_state->private; 2422 struct edid *edid = (struct edid *)conn_state->edid; 2423 unsigned int bus_format; 2424 unsigned long enc_out_encoding; 2425 struct overscan *overscan = &conn_state->overscan; 2426 const u8 def_modes_vic[6] = {4, 16, 2, 17, 31, 19}; 2427 2428 if (!hdmi) 2429 return -EFAULT; 2430 2431 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 2432 2433 if (!ret) { 2434 hdmi->sink_is_hdmi = 2435 drm_detect_hdmi_monitor(edid); 2436 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 2437 ret = drm_add_edid_modes(&hdmi->edid_data, conn_state->edid); 2438 } 2439 if (ret < 0) { 2440 hdmi->sink_is_hdmi = true; 2441 hdmi->sink_has_audio = true; 2442 do_cea_modes(&hdmi->edid_data, def_modes_vic, 2443 sizeof(def_modes_vic)); 2444 hdmi->edid_data.preferred_mode = &hdmi->edid_data.mode_buf[0]; 2445 printf("failed to get edid\n"); 2446 } 2447 drm_rk_filter_whitelist(&hdmi->edid_data); 2448 if (hdmi->phy.ops->mode_valid) 2449 hdmi->phy.ops->mode_valid(hdmi, state); 2450 drm_mode_max_resolution_filter(&hdmi->edid_data, 2451 &state->crtc_state.max_output); 2452 if (!drm_mode_prune_invalid(&hdmi->edid_data)) { 2453 printf("can't find valid hdmi mode\n"); 2454 return -EINVAL; 2455 } 2456 2457 for (i = 0; i < hdmi->edid_data.modes; i++) 2458 hdmi->edid_data.mode_buf[i].vrefresh = 2459 drm_mode_vrefresh(&hdmi->edid_data.mode_buf[i]); 2460 2461 drm_mode_sort(&hdmi->edid_data); 2462 drm_rk_selete_output(&hdmi->edid_data, conn_state, &bus_format, 2463 overscan, hdmi->dev_type); 2464 2465 *mode = *hdmi->edid_data.preferred_mode; 2466 hdmi->vic = drm_match_cea_mode(mode); 2467 2468 printf("mode:%dx%d\n", mode->hdisplay, mode->vdisplay); 2469 conn_state->bus_format = bus_format; 2470 hdmi->hdmi_data.enc_in_bus_format = bus_format; 2471 hdmi->hdmi_data.enc_out_bus_format = bus_format; 2472 2473 switch (bus_format) { 2474 case MEDIA_BUS_FMT_UYVY10_1X20: 2475 conn_state->bus_format = MEDIA_BUS_FMT_YUV10_1X30; 2476 hdmi->hdmi_data.enc_in_bus_format = 2477 MEDIA_BUS_FMT_YUV10_1X30; 2478 break; 2479 case MEDIA_BUS_FMT_UYVY8_1X16: 2480 conn_state->bus_format = MEDIA_BUS_FMT_YUV8_1X24; 2481 hdmi->hdmi_data.enc_in_bus_format = 2482 MEDIA_BUS_FMT_YUV8_1X24; 2483 break; 2484 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 2485 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 2486 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420; 2487 break; 2488 } 2489 2490 if (hdmi->vic == 6 || hdmi->vic == 7 || hdmi->vic == 21 || 2491 hdmi->vic == 22 || hdmi->vic == 2 || hdmi->vic == 3 || 2492 hdmi->vic == 17 || hdmi->vic == 18) 2493 enc_out_encoding = V4L2_YCBCR_ENC_601; 2494 else 2495 enc_out_encoding = V4L2_YCBCR_ENC_709; 2496 2497 if (enc_out_encoding == V4L2_YCBCR_ENC_BT2020) 2498 conn_state->color_space = V4L2_COLORSPACE_BT2020; 2499 else if (bus_format == MEDIA_BUS_FMT_RGB888_1X24 || 2500 bus_format == MEDIA_BUS_FMT_RGB101010_1X30) 2501 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 2502 else if (enc_out_encoding == V4L2_YCBCR_ENC_709) 2503 conn_state->color_space = V4L2_COLORSPACE_REC709; 2504 else 2505 conn_state->color_space = V4L2_COLORSPACE_SMPTE170M; 2506 2507 return 0; 2508 } 2509 2510 int rockchip_dw_hdmi_detect(struct display_state *state) 2511 { 2512 int ret; 2513 struct connector_state *conn_state = &state->conn_state; 2514 struct dw_hdmi *hdmi = conn_state->private; 2515 2516 if (!hdmi) 2517 return -EFAULT; 2518 2519 ret = dw_hdmi_detect_hotplug(hdmi, state); 2520 2521 return ret; 2522 } 2523 2524 int rockchip_dw_hdmi_get_edid(struct display_state *state) 2525 { 2526 int ret; 2527 struct connector_state *conn_state = &state->conn_state; 2528 struct dw_hdmi *hdmi = conn_state->private; 2529 2530 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 2531 2532 return ret; 2533 } 2534 2535 int inno_dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data) 2536 { 2537 struct display_state *state = (struct display_state *)data; 2538 struct connector_state *conn_state = &state->conn_state; 2539 u32 color_depth, bus_width; 2540 2541 color_depth = 2542 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 2543 2544 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 2545 bus_width = color_depth / 2; 2546 else if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 2547 bus_width = color_depth; 2548 else 2549 bus_width = 8; 2550 rockchip_phy_set_bus_width(conn_state->phy, bus_width); 2551 rockchip_phy_set_pll(conn_state->phy, 2552 conn_state->mode.crtc_clock * 1000); 2553 if (hdmi->edid_data.display_info.hdmi.scdc.supported) 2554 rockchip_dw_hdmi_scdc_set_tmds_rate(hdmi); 2555 rockchip_phy_power_on(conn_state->phy); 2556 2557 return 0; 2558 } 2559 2560 void inno_dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 2561 { 2562 } 2563 2564 enum drm_connector_status 2565 inno_dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data) 2566 { 2567 enum drm_connector_status status; 2568 struct display_state *state = (struct display_state *)data; 2569 2570 status = dw_hdmi_phy_read_hpd(hdmi, state); 2571 2572 if (hdmi->dev_type == RK3328_HDMI) { 2573 if (status == connector_status_connected) 2574 inno_dw_hdmi_set_domain(hdmi->grf, 1); 2575 else 2576 inno_dw_hdmi_set_domain(hdmi->grf, 0); 2577 } 2578 2579 return status; 2580 } 2581 2582 void inno_dw_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data) 2583 { 2584 struct display_state *state = (struct display_state *)data; 2585 struct connector_state *conn_state = &state->conn_state; 2586 struct hdmi_edid_data *edid_data = &hdmi->edid_data; 2587 unsigned long rate; 2588 int i, ret; 2589 struct drm_display_mode *mode_buf = edid_data->mode_buf; 2590 2591 for (i = 0; i < edid_data->modes; i++) { 2592 if (edid_data->mode_buf[i].invalid) 2593 continue; 2594 if (edid_data->mode_buf[i].flags & DRM_MODE_FLAG_DBLCLK) 2595 rate = mode_buf[i].clock * 1000 * 2; 2596 else 2597 rate = mode_buf[i].clock * 1000; 2598 2599 /* Check whether mode is out of phy cfg range. */ 2600 ret = rockchip_phy_round_rate(conn_state->phy, rate); 2601 2602 if (ret < 0) 2603 edid_data->mode_buf[i].invalid = true; 2604 } 2605 } 2606