1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <syscon.h> 10 #include <asm/arch-rockchip/clock.h> 11 #include <asm/arch/vendor.h> 12 #include <edid.h> 13 #include <dm/device.h> 14 #include <dm/ofnode.h> 15 #include <dm/read.h> 16 #include <linux/hdmi.h> 17 #include <linux/media-bus-format.h> 18 #include <linux/dw_hdmi.h> 19 #include <asm/io.h> 20 #include "rockchip_display.h" 21 #include "rockchip_crtc.h" 22 #include "rockchip_connector.h" 23 #include "dw_hdmi.h" 24 #include "rockchip_phy.h" 25 26 #define HDCP_PRIVATE_KEY_SIZE 280 27 #define HDCP_KEY_SHA_SIZE 20 28 #define HDMI_HDCP1X_ID 5 29 /* 30 * Unless otherwise noted, entries in this table are 100% optimization. 31 * Values can be obtained from hdmi_compute_n() but that function is 32 * slow so we pre-compute values we expect to see. 33 * 34 * All 32k and 48k values are expected to be the same (due to the way 35 * the math works) for any rate that's an exact kHz. 36 */ 37 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = { 38 { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, }, 39 { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, }, 40 { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 41 { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, }, 42 { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, }, 43 { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, 44 { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, 45 { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 46 { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 47 { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, 48 { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 49 { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, 50 { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 51 { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 52 { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, }, 53 { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 54 { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, }, 55 { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 56 { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 57 { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, }, 58 { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, 59 { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, 60 { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, 61 { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 62 { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 63 { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 64 { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 65 { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 66 { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, 67 { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 68 { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, }, 69 { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, 70 { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 71 { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 72 { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 73 { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, 74 { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 75 76 /* For 297 MHz+ HDMI spec have some other rule for setting N */ 77 { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, }, 78 { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, }, 79 80 /* End of table */ 81 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, }, 82 }; 83 84 static const u16 csc_coeff_default[3][4] = { 85 { 0x2000, 0x0000, 0x0000, 0x0000 }, 86 { 0x0000, 0x2000, 0x0000, 0x0000 }, 87 { 0x0000, 0x0000, 0x2000, 0x0000 } 88 }; 89 90 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 91 { 0x2000, 0x6926, 0x74fd, 0x010e }, 92 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 93 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 94 }; 95 96 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 97 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 98 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 99 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 100 }; 101 102 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 103 { 0x2591, 0x1322, 0x074b, 0x0000 }, 104 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 105 { 0x6acd, 0x7534, 0x2000, 0x0200 } 106 }; 107 108 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 109 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 110 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 111 { 0x6756, 0x78ab, 0x2000, 0x0200 } 112 }; 113 114 struct hdmi_vmode { 115 bool mdataenablepolarity; 116 117 unsigned int mpixelclock; 118 unsigned int mpixelrepetitioninput; 119 unsigned int mpixelrepetitionoutput; 120 unsigned int mtmdsclock; 121 }; 122 123 struct hdmi_data_info { 124 unsigned int enc_in_bus_format; 125 unsigned int enc_out_bus_format; 126 unsigned int enc_in_encoding; 127 unsigned int enc_out_encoding; 128 unsigned int pix_repet_factor; 129 struct hdmi_vmode video_mode; 130 }; 131 132 struct dw_hdmi_phy_data { 133 enum dw_hdmi_phy_type type; 134 const char *name; 135 unsigned int gen; 136 bool has_svsret; 137 int (*configure)(struct dw_hdmi *hdmi, 138 const struct dw_hdmi_plat_data *pdata, 139 unsigned long mpixelclock); 140 }; 141 142 struct hdcp_keys { 143 u8 KSV[8]; 144 u8 devicekey[HDCP_PRIVATE_KEY_SIZE]; 145 u8 sha1[HDCP_KEY_SHA_SIZE]; 146 u8 seeds[2]; 147 }; 148 149 struct dw_hdmi_i2c { 150 u8 slave_reg; 151 bool is_regaddr; 152 bool is_segment; 153 154 unsigned int scl_high_ns; 155 unsigned int scl_low_ns; 156 }; 157 158 struct dw_hdmi { 159 enum dw_hdmi_devtype dev_type; 160 unsigned int version; 161 struct hdmi_data_info hdmi_data; 162 struct hdmi_edid_data edid_data; 163 const struct dw_hdmi_plat_data *plat_data; 164 struct ddc_adapter adap; 165 166 int vic; 167 int io_width; 168 169 unsigned long bus_format; 170 bool cable_plugin; 171 bool sink_is_hdmi; 172 bool sink_has_audio; 173 void *regs; 174 void *grf; 175 struct dw_hdmi_i2c *i2c; 176 177 struct { 178 const struct dw_hdmi_phy_ops *ops; 179 const char *name; 180 void *data; 181 bool enabled; 182 } phy; 183 184 struct drm_display_mode previous_mode; 185 186 unsigned int sample_rate; 187 unsigned int audio_cts; 188 unsigned int audio_n; 189 bool audio_enable; 190 bool scramble_low_rates; 191 192 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset); 193 u8 (*read)(struct dw_hdmi *hdmi, int offset); 194 195 bool hdcp1x_enable; 196 }; 197 198 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset) 199 { 200 writel(val, hdmi->regs + (offset << 2)); 201 } 202 203 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset) 204 { 205 return readl(hdmi->regs + (offset << 2)); 206 } 207 208 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 209 { 210 writeb(val, hdmi->regs + offset); 211 } 212 213 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset) 214 { 215 return readb(hdmi->regs + offset); 216 } 217 218 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 219 { 220 hdmi->write(hdmi, val, offset); 221 } 222 223 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 224 { 225 return hdmi->read(hdmi, offset); 226 } 227 228 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 229 { 230 u8 val = hdmi_readb(hdmi, reg) & ~mask; 231 232 val |= data & mask; 233 hdmi_writeb(hdmi, val, reg); 234 } 235 236 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 237 u8 shift, u8 mask) 238 { 239 hdmi_modb(hdmi, data << shift, mask, reg); 240 } 241 242 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 243 { 244 switch (bus_format) { 245 case MEDIA_BUS_FMT_RGB888_1X24: 246 case MEDIA_BUS_FMT_RGB101010_1X30: 247 case MEDIA_BUS_FMT_RGB121212_1X36: 248 case MEDIA_BUS_FMT_RGB161616_1X48: 249 return true; 250 251 default: 252 return false; 253 } 254 } 255 256 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 257 { 258 switch (bus_format) { 259 case MEDIA_BUS_FMT_YUV8_1X24: 260 case MEDIA_BUS_FMT_YUV10_1X30: 261 case MEDIA_BUS_FMT_YUV12_1X36: 262 case MEDIA_BUS_FMT_YUV16_1X48: 263 return true; 264 265 default: 266 return false; 267 } 268 } 269 270 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 271 { 272 switch (bus_format) { 273 case MEDIA_BUS_FMT_UYVY8_1X16: 274 case MEDIA_BUS_FMT_UYVY10_1X20: 275 case MEDIA_BUS_FMT_UYVY12_1X24: 276 return true; 277 278 default: 279 return false; 280 } 281 } 282 283 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 284 { 285 switch (bus_format) { 286 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 287 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 288 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 289 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 290 return true; 291 292 default: 293 return false; 294 } 295 } 296 297 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 298 { 299 switch (bus_format) { 300 case MEDIA_BUS_FMT_RGB888_1X24: 301 case MEDIA_BUS_FMT_YUV8_1X24: 302 case MEDIA_BUS_FMT_UYVY8_1X16: 303 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 304 return 8; 305 306 case MEDIA_BUS_FMT_RGB101010_1X30: 307 case MEDIA_BUS_FMT_YUV10_1X30: 308 case MEDIA_BUS_FMT_UYVY10_1X20: 309 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 310 return 10; 311 312 case MEDIA_BUS_FMT_RGB121212_1X36: 313 case MEDIA_BUS_FMT_YUV12_1X36: 314 case MEDIA_BUS_FMT_UYVY12_1X24: 315 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 316 return 12; 317 318 case MEDIA_BUS_FMT_RGB161616_1X48: 319 case MEDIA_BUS_FMT_YUV16_1X48: 320 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 321 return 16; 322 323 default: 324 return 0; 325 } 326 } 327 328 static int is_color_space_conversion(struct dw_hdmi *hdmi) 329 { 330 return hdmi->hdmi_data.enc_in_bus_format != 331 hdmi->hdmi_data.enc_out_bus_format; 332 } 333 334 static int is_color_space_decimation(struct dw_hdmi *hdmi) 335 { 336 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 337 return 0; 338 339 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 340 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 341 return 1; 342 343 return 0; 344 } 345 346 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 347 unsigned char bit) 348 { 349 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 350 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 351 } 352 353 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi, 354 unsigned char bit) 355 { 356 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET, 357 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0); 358 } 359 360 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi, 361 unsigned char bit) 362 { 363 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET, 364 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0); 365 } 366 367 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi, 368 unsigned char bit) 369 { 370 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1); 371 } 372 373 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi, 374 unsigned char bit) 375 { 376 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2); 377 } 378 379 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 380 unsigned char *buf, unsigned int length) 381 { 382 struct dw_hdmi_i2c *i2c = hdmi->i2c; 383 int interrupt = 0, i = 20; 384 385 if (!i2c->is_regaddr) { 386 printf("set read register address to 0\n"); 387 i2c->slave_reg = 0x00; 388 i2c->is_regaddr = true; 389 } 390 391 while (length--) { 392 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 393 if (i2c->is_segment) 394 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 395 HDMI_I2CM_OPERATION); 396 else 397 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 398 HDMI_I2CM_OPERATION); 399 400 while (i--) { 401 udelay(1000); 402 interrupt = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 403 if (interrupt) 404 hdmi_writeb(hdmi, interrupt, 405 HDMI_IH_I2CM_STAT0); 406 if (interrupt & (m_SCDC_READREQ | m_I2CM_DONE | 407 m_I2CM_ERROR)) 408 break; 409 } 410 411 if (!interrupt) { 412 printf("[%s] i2c read reg[0x%02x] no interrupt\n", 413 __func__, i2c->slave_reg); 414 return -EAGAIN; 415 } 416 417 /* Check for error condition on the bus */ 418 if (interrupt & HDMI_IH_I2CM_STAT0_ERROR) { 419 printf("[%s] read reg[0x%02x] data error:0x%02x\n", 420 __func__, i2c->slave_reg, interrupt); 421 return -EIO; 422 } 423 424 i = 20; 425 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 426 } 427 i2c->is_segment = false; 428 429 return 0; 430 } 431 432 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 433 unsigned char *buf, unsigned int length) 434 { 435 struct dw_hdmi_i2c *i2c = hdmi->i2c; 436 int i = 20; 437 u8 interrupt = 0; 438 439 if (!i2c->is_regaddr) { 440 /* Use the first write byte as register address */ 441 i2c->slave_reg = buf[0]; 442 length--; 443 buf++; 444 i2c->is_regaddr = true; 445 } 446 447 while (length--) { 448 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 449 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 450 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 451 HDMI_I2CM_OPERATION); 452 453 while (i--) { 454 udelay(1000); 455 interrupt = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 456 if (interrupt) 457 hdmi_writeb(hdmi, 458 interrupt, HDMI_IH_I2CM_STAT0); 459 460 if (interrupt & (m_SCDC_READREQ | 461 m_I2CM_DONE | m_I2CM_ERROR)) 462 break; 463 } 464 465 if ((interrupt & m_I2CM_ERROR) || (i == -1)) { 466 printf("[%s] write data error\n", __func__); 467 return -EIO; 468 } else if (interrupt & m_I2CM_DONE) { 469 printf("[%s] write offset %02x success\n", 470 __func__, i2c->slave_reg); 471 return -EAGAIN; 472 } 473 474 i = 20; 475 } 476 477 return 0; 478 } 479 480 static int dw_hdmi_i2c_xfer(struct ddc_adapter *adap, 481 struct i2c_msg *msgs, int num) 482 { 483 struct dw_hdmi *hdmi = container_of(adap, struct dw_hdmi, adap); 484 struct dw_hdmi_i2c *i2c = hdmi->i2c; 485 u8 addr = msgs[0].addr; 486 int i, ret = 0; 487 488 printf("xfer: num: %d, addr: %#x\n", num, addr); 489 for (i = 0; i < num; i++) { 490 if (msgs[i].len == 0) { 491 printf("unsupported transfer %d/%d, no data\n", 492 i + 1, num); 493 return -EOPNOTSUPP; 494 } 495 } 496 497 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 498 499 /* Set slave device address taken from the first I2C message */ 500 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1) 501 addr = DDC_ADDR; 502 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 503 504 /* Set slave device register address on transfer */ 505 i2c->is_regaddr = false; 506 507 /* Set segment pointer for I2C extended read mode operation */ 508 i2c->is_segment = false; 509 510 for (i = 0; i < num; i++) { 511 debug("xfer: num: %d/%d, len: %d, flags: %#x\n", 512 i + 1, num, msgs[i].len, msgs[i].flags); 513 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 514 i2c->is_segment = true; 515 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 516 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 517 } else { 518 if (msgs[i].flags & I2C_M_RD) 519 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 520 msgs[i].len); 521 else 522 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 523 msgs[i].len); 524 } 525 if (ret < 0) 526 break; 527 } 528 529 if (!ret) 530 ret = num; 531 532 /* Mute DONE and ERROR interrupts */ 533 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 534 HDMI_IH_MUTE_I2CM_STAT0); 535 536 return ret; 537 } 538 539 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 540 { 541 u32 val; 542 543 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 544 if (msec-- == 0) 545 return false; 546 udelay(1000); 547 } 548 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 549 550 return true; 551 } 552 553 static void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 554 unsigned char addr) 555 { 556 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 557 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 558 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 559 HDMI_PHY_I2CM_DATAO_1_ADDR); 560 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 561 HDMI_PHY_I2CM_DATAO_0_ADDR); 562 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 563 HDMI_PHY_I2CM_OPERATION_ADDR); 564 hdmi_phy_wait_i2c_done(hdmi, 1000); 565 } 566 567 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 568 { 569 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 570 HDMI_PHY_CONF0_PDZ_OFFSET, 571 HDMI_PHY_CONF0_PDZ_MASK); 572 } 573 574 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 575 { 576 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 577 HDMI_PHY_CONF0_ENTMDS_OFFSET, 578 HDMI_PHY_CONF0_ENTMDS_MASK); 579 } 580 581 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 582 { 583 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 584 HDMI_PHY_CONF0_SVSRET_OFFSET, 585 HDMI_PHY_CONF0_SVSRET_MASK); 586 } 587 588 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 589 { 590 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 591 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 592 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 593 } 594 595 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 596 { 597 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 598 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 599 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 600 } 601 602 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 603 { 604 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 605 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 606 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 607 } 608 609 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 610 { 611 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 612 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 613 HDMI_PHY_CONF0_SELDIPIF_MASK); 614 } 615 616 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 617 { 618 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 619 unsigned int i; 620 u16 val; 621 622 if (phy->gen == 1) { 623 dw_hdmi_phy_enable_tmds(hdmi, 0); 624 dw_hdmi_phy_enable_powerdown(hdmi, true); 625 return; 626 } 627 628 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 629 630 /* 631 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 632 * to low power mode. 633 */ 634 for (i = 0; i < 5; ++i) { 635 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 636 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 637 break; 638 639 udelay(2000); 640 } 641 642 if (val & HDMI_PHY_TX_PHY_LOCK) 643 printf("PHY failed to power down\n"); 644 else 645 printf("PHY powered down in %u iterations\n", i); 646 647 dw_hdmi_phy_gen2_pddq(hdmi, 1); 648 } 649 650 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 651 { 652 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 653 unsigned int i; 654 u8 val; 655 656 if (phy->gen == 1) { 657 dw_hdmi_phy_enable_powerdown(hdmi, false); 658 659 /* Toggle TMDS enable. */ 660 dw_hdmi_phy_enable_tmds(hdmi, 0); 661 dw_hdmi_phy_enable_tmds(hdmi, 1); 662 return 0; 663 } 664 665 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 666 dw_hdmi_phy_gen2_pddq(hdmi, 0); 667 668 /* Wait for PHY PLL lock */ 669 for (i = 0; i < 5; ++i) { 670 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 671 if (val) 672 break; 673 674 udelay(2000); 675 } 676 677 if (!val) { 678 printf("PHY PLL failed to lock\n"); 679 return -ETIMEDOUT; 680 } 681 printf("PHY PLL locked %u iterations\n", i); 682 683 return 0; 684 } 685 686 /* 687 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 688 * information the DWC MHL PHY has the same register layout and is thus also 689 * supported by this function. 690 */ 691 static 692 int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 693 const struct dw_hdmi_plat_data *pdata, 694 unsigned long mpixelclock) 695 { 696 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 697 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 698 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 699 unsigned int tmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 700 unsigned int depth = 701 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 702 703 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) && 704 pdata->mpll_cfg_420) 705 mpll_config = pdata->mpll_cfg_420; 706 707 /* PLL/MPLL Cfg - always match on final entry */ 708 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 709 if (mpixelclock <= mpll_config->mpixelclock) 710 break; 711 712 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 713 if (tmdsclock <= curr_ctrl->mpixelclock) 714 break; 715 716 for (; phy_config->mpixelclock != ~0UL; phy_config++) 717 if (tmdsclock <= phy_config->mpixelclock) 718 break; 719 720 if (mpll_config->mpixelclock == ~0UL || 721 curr_ctrl->mpixelclock == ~0UL || 722 phy_config->mpixelclock == ~0UL) 723 return -EINVAL; 724 725 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 726 depth = fls(depth - 8); 727 else 728 depth = 0; 729 if (depth) 730 depth--; 731 732 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].cpce, 733 HDMI_3D_TX_PHY_CPCE_CTRL); 734 735 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].gmp, 736 HDMI_3D_TX_PHY_GMPCTRL); 737 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[depth], 738 HDMI_3D_TX_PHY_CURRCTRL); 739 740 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 741 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 742 HDMI_3D_TX_PHY_MSM_CTRL); 743 744 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 745 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 746 HDMI_3D_TX_PHY_CKSYMTXCTRL); 747 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 748 HDMI_3D_TX_PHY_VLEVCTRL); 749 750 /* Override and disable clock termination. */ 751 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, 752 HDMI_3D_TX_PHY_CKCALCTRL); 753 return 0; 754 } 755 756 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 757 { 758 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 759 .name = "DWC HDMI TX PHY", 760 .gen = 1, 761 }, { 762 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 763 .name = "DWC MHL PHY + HEAC PHY", 764 .gen = 2, 765 .has_svsret = true, 766 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 767 }, { 768 .type = DW_HDMI_PHY_DWC_MHL_PHY, 769 .name = "DWC MHL PHY", 770 .gen = 2, 771 .has_svsret = true, 772 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 773 }, { 774 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 775 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 776 .gen = 2, 777 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 778 }, { 779 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 780 .name = "DWC HDMI 3D TX PHY", 781 .gen = 2, 782 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 783 }, { 784 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 785 .name = "DWC HDMI 2.0 TX PHY", 786 .gen = 2, 787 .has_svsret = true, 788 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 789 }, { 790 .type = DW_HDMI_PHY_VENDOR_PHY, 791 .name = "Vendor PHY", 792 } 793 }; 794 795 static int rockchip_dw_hdmi_scrambling_enable(struct dw_hdmi *hdmi, 796 int enable) 797 { 798 u8 stat; 799 800 drm_scdc_readb(&hdmi->adap, SCDC_TMDS_CONFIG, &stat); 801 802 if (stat < 0) { 803 debug("Failed to read tmds config\n"); 804 return false; 805 } 806 807 if (enable == 1) { 808 /* Write on Rx the bit Scrambling_Enable, register 0x20 */ 809 stat |= SCDC_SCRAMBLING_ENABLE; 810 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 811 /* TMDS software reset request */ 812 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 813 HDMI_MC_SWRSTZ); 814 /* Enable/Disable Scrambling */ 815 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); 816 } else { 817 /* Enable/Disable Scrambling */ 818 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); 819 /* TMDS software reset request */ 820 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 821 HDMI_MC_SWRSTZ); 822 /* Write on Rx the bit Scrambling_Enable, register 0x20 */ 823 stat &= ~SCDC_SCRAMBLING_ENABLE; 824 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 825 } 826 827 return 0; 828 } 829 830 static void rockchip_dw_hdmi_scdc_set_tmds_rate(struct dw_hdmi *hdmi) 831 { 832 u8 stat; 833 834 drm_scdc_readb(&hdmi->adap, SCDC_TMDS_CONFIG, &stat); 835 if (hdmi->hdmi_data.video_mode.mtmdsclock > 340000000) 836 stat |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 837 else 838 stat &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 839 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 840 } 841 842 static int hdmi_phy_configure(struct dw_hdmi *hdmi) 843 { 844 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 845 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 846 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 847 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 848 int ret; 849 850 dw_hdmi_phy_power_off(hdmi); 851 852 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ 853 if (hdmi->edid_data.display_info.hdmi.scdc.supported) 854 rockchip_dw_hdmi_scdc_set_tmds_rate(hdmi); 855 856 /* Leave low power consumption mode by asserting SVSRET. */ 857 if (phy->has_svsret) 858 dw_hdmi_phy_enable_svsret(hdmi, 1); 859 860 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 861 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 862 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 863 864 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 865 866 hdmi_phy_test_clear(hdmi, 1); 867 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, 868 HDMI_PHY_I2CM_SLAVE_ADDR); 869 hdmi_phy_test_clear(hdmi, 0); 870 871 /* Write to the PHY as configured by the platform */ 872 if (pdata->configure_phy) 873 ret = pdata->configure_phy(hdmi, pdata, mpixelclock); 874 else 875 ret = phy->configure(hdmi, pdata, mpixelclock); 876 if (ret) { 877 printf("PHY configuration failed (clock %lu)\n", 878 mpixelclock); 879 return ret; 880 } 881 882 /* Wait for resuming transmission of TMDS clock and data */ 883 if (mtmdsclock > 340000000) 884 mdelay(100); 885 886 return dw_hdmi_phy_power_on(hdmi); 887 } 888 889 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, 890 void *data) 891 { 892 int i, ret; 893 894 /* HDMI Phy spec says to do the phy initialization sequence twice */ 895 for (i = 0; i < 2; i++) { 896 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 897 dw_hdmi_phy_sel_interface_control(hdmi, 0); 898 ret = hdmi_phy_configure(hdmi); 899 if (ret) 900 return ret; 901 } 902 903 return 0; 904 } 905 906 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, 907 void *data) 908 { 909 dw_hdmi_phy_power_off(hdmi); 910 } 911 912 static enum drm_connector_status 913 dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data) 914 { 915 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 916 connector_status_connected : connector_status_disconnected; 917 } 918 919 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 920 .init = dw_hdmi_phy_init, 921 .disable = dw_hdmi_phy_disable, 922 .read_hpd = dw_hdmi_phy_read_hpd, 923 }; 924 925 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 926 { 927 unsigned int i; 928 u8 phy_type; 929 930 phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID); 931 932 /* 933 * RK3228 and RK3328 phy_type is DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 934 * but it has a vedor phy. 935 */ 936 if (phy_type == DW_HDMI_PHY_VENDOR_PHY || 937 hdmi->dev_type == RK3328_HDMI || 938 hdmi->dev_type == RK3228_HDMI) { 939 /* Vendor PHYs require support from the glue layer. */ 940 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 941 printf( 942 "Vendor HDMI PHY not supported by glue layer\n"); 943 return -ENODEV; 944 } 945 946 hdmi->phy.ops = hdmi->plat_data->phy_ops; 947 hdmi->phy.data = hdmi->plat_data->phy_data; 948 hdmi->phy.name = hdmi->plat_data->phy_name; 949 return 0; 950 } 951 952 /* Synopsys PHYs are handled internally. */ 953 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 954 if (dw_hdmi_phys[i].type == phy_type) { 955 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 956 hdmi->phy.name = dw_hdmi_phys[i].name; 957 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 958 959 if (!dw_hdmi_phys[i].configure && 960 !hdmi->plat_data->configure_phy) { 961 printf("%s requires platform support\n", 962 hdmi->phy.name); 963 return -ENODEV; 964 } 965 966 return 0; 967 } 968 } 969 970 printf("Unsupported HDMI PHY type (%02x)\n", phy_type); 971 return -ENODEV; 972 } 973 974 static unsigned int 975 hdmi_get_tmdsclock(struct dw_hdmi *hdmi, unsigned long mpixelclock) 976 { 977 unsigned int tmdsclock = mpixelclock; 978 unsigned int depth = 979 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 980 981 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 982 switch (depth) { 983 case 16: 984 tmdsclock = mpixelclock * 2; 985 break; 986 case 12: 987 tmdsclock = mpixelclock * 3 / 2; 988 break; 989 case 10: 990 tmdsclock = mpixelclock * 5 / 4; 991 break; 992 default: 993 break; 994 } 995 } 996 997 return tmdsclock; 998 } 999 1000 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1001 const struct drm_display_mode *mode) 1002 { 1003 u8 bytes = 0, inv_val = 0; 1004 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1005 struct drm_hdmi_info *hdmi_info = &hdmi->edid_data.display_info.hdmi; 1006 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1007 unsigned int hdisplay, vdisplay; 1008 1009 vmode->mpixelclock = mode->crtc_clock * 1000; 1010 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == 1011 DRM_MODE_FLAG_3D_FRAME_PACKING) 1012 vmode->mpixelclock *= 2; 1013 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock); 1014 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1015 vmode->mtmdsclock /= 2; 1016 printf("final pixclk = %d tmdsclk = %d\n", 1017 vmode->mpixelclock, vmode->mtmdsclock); 1018 1019 /* Set up HDMI_FC_INVIDCONF 1020 * fc_invidconf.HDCP_keepout must be set (1'b1) 1021 * when activate the scrambler feature. 1022 */ 1023 inv_val = (vmode->mtmdsclock > 340000000 || 1024 (hdmi_info->scdc.scrambling.low_rates && 1025 hdmi->scramble_low_rates) ? 1026 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 1027 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 1028 1029 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 1030 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 1031 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 1032 1033 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 1034 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 1035 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 1036 1037 inv_val |= (vmode->mdataenablepolarity ? 1038 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 1039 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 1040 1041 if (hdmi->vic == 39) 1042 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 1043 else 1044 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1045 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 1046 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 1047 1048 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1049 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 1050 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 1051 1052 inv_val |= hdmi->sink_is_hdmi ? 1053 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 1054 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 1055 1056 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 1057 1058 hdisplay = mode->hdisplay; 1059 hblank = mode->htotal - mode->hdisplay; 1060 h_de_hs = mode->hsync_start - mode->hdisplay; 1061 hsync_len = mode->hsync_end - mode->hsync_start; 1062 1063 /* 1064 * When we're setting a YCbCr420 mode, we need 1065 * to adjust the horizontal timing to suit. 1066 */ 1067 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1068 hdisplay /= 2; 1069 hblank /= 2; 1070 h_de_hs /= 2; 1071 hsync_len /= 2; 1072 } 1073 1074 vdisplay = mode->vdisplay; 1075 vblank = mode->vtotal - mode->vdisplay; 1076 v_de_vs = mode->vsync_start - mode->vdisplay; 1077 vsync_len = mode->vsync_end - mode->vsync_start; 1078 1079 /* 1080 * When we're setting an interlaced mode, we need 1081 * to adjust the vertical timing to suit. 1082 */ 1083 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1084 vdisplay /= 2; 1085 vblank /= 2; 1086 v_de_vs /= 2; 1087 vsync_len /= 2; 1088 } else if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == 1089 DRM_MODE_FLAG_3D_FRAME_PACKING) { 1090 vdisplay += mode->vtotal; 1091 } 1092 1093 /* Scrambling Control */ 1094 if (hdmi_info->scdc.supported) { 1095 if (vmode->mtmdsclock > 340000000 || 1096 (hdmi_info->scdc.scrambling.low_rates && 1097 hdmi->scramble_low_rates)) { 1098 drm_scdc_readb(&hdmi->adap, SCDC_SINK_VERSION, &bytes); 1099 drm_scdc_writeb(&hdmi->adap, SCDC_SOURCE_VERSION, 1100 bytes); 1101 rockchip_dw_hdmi_scrambling_enable(hdmi, 1); 1102 } else { 1103 rockchip_dw_hdmi_scrambling_enable(hdmi, 0); 1104 } 1105 } 1106 1107 /* Set up horizontal active pixel width */ 1108 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1); 1109 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0); 1110 1111 /* Set up vertical active lines */ 1112 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 1113 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 1114 1115 /* Set up horizontal blanking pixel region width */ 1116 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 1117 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 1118 1119 /* Set up vertical blanking pixel region width */ 1120 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 1121 1122 /* Set up HSYNC active edge delay width (in pixel clks) */ 1123 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 1124 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 1125 1126 /* Set up VSYNC active edge delay (in lines) */ 1127 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 1128 1129 /* Set up HSYNC active pulse width (in pixel clks) */ 1130 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 1131 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 1132 1133 /* Set up VSYNC active edge delay (in lines) */ 1134 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 1135 } 1136 1137 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 1138 { 1139 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 1140 unsigned i; 1141 u32 csc_scale = 1; 1142 1143 if (is_color_space_conversion(hdmi)) { 1144 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 1145 if (hdmi->hdmi_data.enc_out_encoding == 1146 V4L2_YCBCR_ENC_601) 1147 csc_coeff = &csc_coeff_rgb_out_eitu601; 1148 else 1149 csc_coeff = &csc_coeff_rgb_out_eitu709; 1150 } else if (hdmi_bus_fmt_is_rgb( 1151 hdmi->hdmi_data.enc_in_bus_format)) { 1152 if (hdmi->hdmi_data.enc_out_encoding == 1153 V4L2_YCBCR_ENC_601) 1154 csc_coeff = &csc_coeff_rgb_in_eitu601; 1155 else 1156 csc_coeff = &csc_coeff_rgb_in_eitu709; 1157 csc_scale = 0; 1158 } 1159 } 1160 1161 /* The CSC registers are sequential, alternating MSB then LSB */ 1162 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 1163 u16 coeff_a = (*csc_coeff)[0][i]; 1164 u16 coeff_b = (*csc_coeff)[1][i]; 1165 u16 coeff_c = (*csc_coeff)[2][i]; 1166 1167 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 1168 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 1169 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 1170 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 1171 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 1172 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 1173 } 1174 1175 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 1176 HDMI_CSC_SCALE); 1177 } 1178 1179 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 1180 { 1181 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 1182 return 0; 1183 1184 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1185 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1186 return 1; 1187 1188 return 0; 1189 } 1190 1191 static void hdmi_video_csc(struct dw_hdmi *hdmi) 1192 { 1193 int color_depth = 0; 1194 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 1195 int decimation = 0; 1196 1197 /* YCC422 interpolation to 444 mode */ 1198 if (is_color_space_interpolation(hdmi)) 1199 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 1200 else if (is_color_space_decimation(hdmi)) 1201 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 1202 1203 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 1204 case 8: 1205 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 1206 break; 1207 case 10: 1208 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 1209 break; 1210 case 12: 1211 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 1212 break; 1213 case 16: 1214 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 1215 break; 1216 1217 default: 1218 return; 1219 } 1220 1221 /* Configure the CSC registers */ 1222 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 1223 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 1224 HDMI_CSC_SCALE); 1225 1226 dw_hdmi_update_csc_coeffs(hdmi); 1227 } 1228 1229 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 1230 { 1231 u8 clkdis; 1232 1233 /* control period minimum duration */ 1234 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 1235 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 1236 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 1237 1238 /* Set to fill TMDS data channels */ 1239 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 1240 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 1241 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 1242 1243 /* Enable pixel clock and tmds data path */ 1244 clkdis = 0x7F; 1245 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 1246 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1247 1248 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1249 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1250 1251 /* Enable csc path */ 1252 if (is_color_space_conversion(hdmi)) { 1253 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 1254 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1255 } 1256 1257 /* Enable pixel repetition path */ 1258 if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) { 1259 clkdis &= ~HDMI_MC_CLKDIS_PREPCLK_DISABLE; 1260 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1261 } 1262 1263 /* Enable color space conversion if needed */ 1264 if (is_color_space_conversion(hdmi)) 1265 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 1266 HDMI_MC_FLOWCTRL); 1267 else 1268 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 1269 HDMI_MC_FLOWCTRL); 1270 } 1271 1272 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 1273 { 1274 unsigned int count; 1275 unsigned int i; 1276 u8 val; 1277 1278 /* 1279 * Under some circumstances the Frame Composer arithmetic unit can miss 1280 * an FC register write due to being busy processing the previous one. 1281 * The issue can be worked around by issuing a TMDS software reset and 1282 * then write one of the FC registers several times. 1283 * 1284 * The number of iterations matters and depends on the HDMI TX revision 1285 * (and possibly on the platform). So far only i.MX6Q (v1.30a) and 1286 * i.MX6DL (v1.31a) have been identified as needing the workaround, with 1287 * 4 and 1 iterations respectively. 1288 */ 1289 1290 switch (hdmi->version) { 1291 case 0x130a: 1292 count = 4; 1293 break; 1294 case 0x131a: 1295 case 0x200a: 1296 case 0x201a: 1297 case 0x211a: 1298 count = 1; 1299 break; 1300 default: 1301 return; 1302 } 1303 1304 /* TMDS software reset */ 1305 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 1306 1307 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 1308 for (i = 0; i < count; i++) 1309 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 1310 } 1311 1312 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 1313 { 1314 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 1315 HDMI_IH_MUTE_FC_STAT2); 1316 } 1317 1318 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 1319 { 1320 unsigned int color_depth = 0; 1321 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 1322 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 1323 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1324 u8 val, vp_conf; 1325 1326 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1327 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) || 1328 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1329 switch (hdmi_bus_fmt_color_depth( 1330 hdmi->hdmi_data.enc_out_bus_format)) { 1331 case 8: 1332 color_depth = 0; 1333 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1334 break; 1335 case 10: 1336 color_depth = 5; 1337 break; 1338 case 12: 1339 color_depth = 6; 1340 break; 1341 case 16: 1342 color_depth = 7; 1343 break; 1344 default: 1345 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1346 } 1347 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1348 switch (hdmi_bus_fmt_color_depth( 1349 hdmi->hdmi_data.enc_out_bus_format)) { 1350 case 0: 1351 case 8: 1352 remap_size = HDMI_VP_REMAP_YCC422_16bit; 1353 break; 1354 case 10: 1355 remap_size = HDMI_VP_REMAP_YCC422_20bit; 1356 break; 1357 case 12: 1358 remap_size = HDMI_VP_REMAP_YCC422_24bit; 1359 break; 1360 1361 default: 1362 return; 1363 } 1364 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 1365 } else { 1366 return; 1367 } 1368 1369 /* set the packetizer registers */ 1370 val = (color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 1371 HDMI_VP_PR_CD_COLOR_DEPTH_MASK; 1372 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 1373 1374 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 1375 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 1376 1377 /* Data from pixel repeater block */ 1378 if (hdmi_data->pix_repet_factor > 0) { 1379 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 1380 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 1381 } else { /* data from packetizer block */ 1382 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 1383 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 1384 } 1385 1386 hdmi_modb(hdmi, vp_conf, 1387 HDMI_VP_CONF_PR_EN_MASK | 1388 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 1389 1390 if ((color_depth == 5 && hdmi->previous_mode.htotal % 4) || 1391 (color_depth == 6 && hdmi->previous_mode.htotal % 2)) 1392 hdmi_modb(hdmi, 0, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, 1393 HDMI_VP_STUFF); 1394 else 1395 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 1396 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 1397 1398 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 1399 1400 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 1401 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1402 HDMI_VP_CONF_PP_EN_ENABLE | 1403 HDMI_VP_CONF_YCC422_EN_DISABLE; 1404 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 1405 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1406 HDMI_VP_CONF_PP_EN_DISABLE | 1407 HDMI_VP_CONF_YCC422_EN_ENABLE; 1408 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 1409 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 1410 HDMI_VP_CONF_PP_EN_DISABLE | 1411 HDMI_VP_CONF_YCC422_EN_DISABLE; 1412 } else { 1413 return; 1414 } 1415 1416 hdmi_modb(hdmi, vp_conf, 1417 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 1418 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 1419 1420 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 1421 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 1422 HDMI_VP_STUFF_PP_STUFFING_MASK | 1423 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 1424 1425 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 1426 HDMI_VP_CONF); 1427 } 1428 1429 static void hdmi_video_sample(struct dw_hdmi *hdmi) 1430 { 1431 int color_format = 0; 1432 u8 val; 1433 1434 switch (hdmi->hdmi_data.enc_in_bus_format) { 1435 case MEDIA_BUS_FMT_RGB888_1X24: 1436 color_format = 0x01; 1437 break; 1438 case MEDIA_BUS_FMT_RGB101010_1X30: 1439 color_format = 0x03; 1440 break; 1441 case MEDIA_BUS_FMT_RGB121212_1X36: 1442 color_format = 0x05; 1443 break; 1444 case MEDIA_BUS_FMT_RGB161616_1X48: 1445 color_format = 0x07; 1446 break; 1447 1448 case MEDIA_BUS_FMT_YUV8_1X24: 1449 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1450 color_format = 0x09; 1451 break; 1452 case MEDIA_BUS_FMT_YUV10_1X30: 1453 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1454 color_format = 0x0B; 1455 break; 1456 case MEDIA_BUS_FMT_YUV12_1X36: 1457 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 1458 color_format = 0x0D; 1459 break; 1460 case MEDIA_BUS_FMT_YUV16_1X48: 1461 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 1462 color_format = 0x0F; 1463 break; 1464 1465 case MEDIA_BUS_FMT_UYVY8_1X16: 1466 color_format = 0x16; 1467 break; 1468 case MEDIA_BUS_FMT_UYVY10_1X20: 1469 color_format = 0x14; 1470 break; 1471 case MEDIA_BUS_FMT_UYVY12_1X24: 1472 color_format = 0x12; 1473 break; 1474 1475 default: 1476 return; 1477 } 1478 1479 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 1480 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 1481 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 1482 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 1483 1484 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 1485 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 1486 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 1487 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 1488 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 1489 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 1490 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 1491 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 1492 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 1493 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 1494 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 1495 } 1496 1497 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi) 1498 { 1499 hdmi_writeb(hdmi, 0, HDMI_FC_MASK2); 1500 hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2); 1501 } 1502 1503 static void dw_hdmi_disable(struct dw_hdmi *hdmi, struct display_state *state) 1504 { 1505 if (hdmi->phy.enabled) { 1506 hdmi->phy.ops->disable(hdmi, state); 1507 hdmi->phy.enabled = false; 1508 } 1509 } 1510 1511 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1512 { 1513 struct hdmi_avi_infoframe frame; 1514 u8 val; 1515 bool is_hdmi2 = false; 1516 1517 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) || 1518 hdmi->edid_data.display_info.hdmi.scdc.supported) 1519 is_hdmi2 = true; 1520 /* Initialise info frame from DRM mode */ 1521 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2); 1522 1523 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1524 frame.colorspace = HDMI_COLORSPACE_YUV444; 1525 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1526 frame.colorspace = HDMI_COLORSPACE_YUV422; 1527 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1528 frame.colorspace = HDMI_COLORSPACE_YUV420; 1529 else 1530 frame.colorspace = HDMI_COLORSPACE_RGB; 1531 1532 /* Set up colorimetry */ 1533 switch (hdmi->hdmi_data.enc_out_encoding) { 1534 case V4L2_YCBCR_ENC_601: 1535 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1536 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1537 else 1538 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1539 frame.extended_colorimetry = 1540 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1541 break; 1542 case V4L2_YCBCR_ENC_709: 1543 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1544 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1545 else 1546 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1547 frame.extended_colorimetry = 1548 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1549 break; 1550 default: /* Carries no data */ 1551 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1552 frame.extended_colorimetry = 1553 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1554 break; 1555 } 1556 1557 frame.scan_mode = HDMI_SCAN_MODE_NONE; 1558 1559 /* 1560 * The Designware IP uses a different byte format from standard 1561 * AVI info frames, though generally the bits are in the correct 1562 * bytes. 1563 */ 1564 1565 /* 1566 * AVI data byte 1 differences: Colorspace in bits 0,1,7 rather than 1567 * 5,6,7, active aspect present in bit 6 rather than 4. 1568 */ 1569 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 0x3); 1570 if (frame.active_aspect & 15) 1571 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1572 if (frame.top_bar || frame.bottom_bar) 1573 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1574 if (frame.left_bar || frame.right_bar) 1575 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1576 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1577 1578 /* AVI data byte 2 differences: none */ 1579 val = ((frame.colorimetry & 0x3) << 6) | 1580 ((frame.picture_aspect & 0x3) << 4) | 1581 (frame.active_aspect & 0xf); 1582 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1583 1584 /* AVI data byte 3 differences: none */ 1585 val = ((frame.extended_colorimetry & 0x7) << 4) | 1586 ((frame.quantization_range & 0x3) << 2) | 1587 (frame.nups & 0x3); 1588 if (frame.itc) 1589 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1590 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1591 1592 /* AVI data byte 4 differences: none */ 1593 val = frame.video_code & 0x7f; 1594 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1595 1596 /* AVI Data Byte 5- set up input and output pixel repetition */ 1597 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1598 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1599 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1600 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1601 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1602 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1603 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1604 1605 /* 1606 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1607 * ycc range in bits 2,3 rather than 6,7 1608 */ 1609 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1610 (frame.content_type & 0x3); 1611 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1612 1613 /* AVI Data Bytes 6-13 */ 1614 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1615 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1616 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1617 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1618 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1619 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1620 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1621 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1622 } 1623 1624 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1625 struct drm_display_mode *mode) 1626 { 1627 struct hdmi_vendor_infoframe frame; 1628 u8 buffer[10]; 1629 ssize_t err; 1630 1631 /* Disable HDMI vendor specific infoframe send */ 1632 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1633 HDMI_FC_DATAUTO0_VSD_MASK); 1634 1635 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode); 1636 if (err < 0) 1637 /* 1638 * Going into that statement does not means vendor infoframe 1639 * fails. It just informed us that vendor infoframe is not 1640 * needed for the selected mode. Only 4k or stereoscopic 3D 1641 * mode requires vendor infoframe. So just simply return. 1642 */ 1643 return; 1644 1645 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1646 if (err < 0) { 1647 printf("Failed to pack vendor infoframe: %zd\n", err); 1648 return; 1649 } 1650 1651 /* Set the length of HDMI vendor specific InfoFrame payload */ 1652 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1653 1654 /* Set 24bit IEEE Registration Identifier */ 1655 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1656 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1657 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1658 1659 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1660 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1661 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1662 1663 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1664 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1665 1666 /* Packet frame interpolation */ 1667 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1668 1669 /* Auto packets per frame and line spacing */ 1670 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1671 1672 /* Configures the Frame Composer On RDRB mode */ 1673 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1674 HDMI_FC_DATAUTO0_VSD_MASK); 1675 } 1676 1677 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 1678 unsigned int n) 1679 { 1680 /* Must be set/cleared first */ 1681 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 1682 1683 /* nshift factor = 0 */ 1684 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 1685 1686 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 1687 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 1688 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 1689 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 1690 1691 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 1692 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 1693 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 1694 } 1695 1696 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi, 1697 unsigned long pixel_clk, 1698 unsigned long freq) 1699 { 1700 const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data; 1701 const struct dw_hdmi_audio_tmds_n *tmds_n = NULL; 1702 int i; 1703 1704 if (plat_data->tmds_n_table) { 1705 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) { 1706 if (pixel_clk == plat_data->tmds_n_table[i].tmds) { 1707 tmds_n = &plat_data->tmds_n_table[i]; 1708 break; 1709 } 1710 } 1711 } 1712 1713 if (!tmds_n) { 1714 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) { 1715 if (pixel_clk == common_tmds_n_table[i].tmds) { 1716 tmds_n = &common_tmds_n_table[i]; 1717 break; 1718 } 1719 } 1720 } 1721 1722 if (!tmds_n) 1723 return -ENOENT; 1724 1725 switch (freq) { 1726 case 32000: 1727 return tmds_n->n_32k; 1728 case 44100: 1729 case 88200: 1730 case 176400: 1731 return (freq / 44100) * tmds_n->n_44k1; 1732 case 48000: 1733 case 96000: 1734 case 192000: 1735 return (freq / 48000) * tmds_n->n_48k; 1736 default: 1737 return -ENOENT; 1738 } 1739 } 1740 1741 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n, 1742 unsigned int pixel_clk) 1743 { 1744 u64 final, diff; 1745 u64 cts; 1746 1747 final = (u64)pixel_clk * n; 1748 1749 cts = final; 1750 do_div(cts, 128 * freq); 1751 1752 diff = final - (u64)cts * (128 * freq); 1753 1754 return diff; 1755 } 1756 1757 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi, 1758 unsigned long pixel_clk, 1759 unsigned long freq) 1760 { 1761 unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500); 1762 unsigned int max_n = (128 * freq) / 300; 1763 unsigned int ideal_n = (128 * freq) / 1000; 1764 unsigned int best_n_distance = ideal_n; 1765 unsigned int best_n = 0; 1766 u64 best_diff = U64_MAX; 1767 int n; 1768 1769 /* If the ideal N could satisfy the audio math, then just take it */ 1770 if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0) 1771 return ideal_n; 1772 1773 for (n = min_n; n <= max_n; n++) { 1774 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk); 1775 1776 if (diff < best_diff || (diff == best_diff && 1777 abs(n - ideal_n) < best_n_distance)) { 1778 best_n = n; 1779 best_diff = diff; 1780 best_n_distance = abs(best_n - ideal_n); 1781 } 1782 1783 /* 1784 * The best N already satisfy the audio math, and also be 1785 * the closest value to ideal N, so just cut the loop. 1786 */ 1787 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance)) 1788 break; 1789 } 1790 1791 return best_n; 1792 } 1793 1794 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk, 1795 unsigned long sample_rate) 1796 { 1797 int n; 1798 1799 n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate); 1800 if (n > 0) 1801 return n; 1802 1803 printf("Rate %lu missing; compute N dynamically\n", 1804 pixel_clk); 1805 1806 return hdmi_compute_n(hdmi, pixel_clk, sample_rate); 1807 } 1808 1809 static 1810 void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, unsigned long pixel_clk, 1811 unsigned int sample_rate) 1812 { 1813 unsigned long ftdms = pixel_clk; 1814 unsigned int n, cts; 1815 u64 tmp; 1816 1817 n = hdmi_find_n(hdmi, pixel_clk, sample_rate); 1818 1819 /* 1820 * Compute the CTS value from the N value. Note that CTS and N 1821 * can be up to 20 bits in total, so we need 64-bit math. Also 1822 * note that our TDMS clock is not fully accurate; it is accurate 1823 * to kHz. This can introduce an unnecessary remainder in the 1824 * calculation below, so we don't try to warn about that. 1825 */ 1826 tmp = (u64)ftdms * n; 1827 do_div(tmp, 128 * sample_rate); 1828 cts = tmp; 1829 1830 printf("%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", __func__, 1831 sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000, n, cts); 1832 1833 hdmi->audio_n = n; 1834 hdmi->audio_cts = cts; 1835 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 1836 } 1837 1838 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 1839 { 1840 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 1841 hdmi->sample_rate); 1842 } 1843 1844 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi) 1845 { 1846 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS); 1847 } 1848 1849 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 1850 { 1851 hdmi->sample_rate = rate; 1852 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 1853 hdmi->sample_rate); 1854 } 1855 1856 static int dw_hdmi_hdcp_load_key(struct dw_hdmi *hdmi) 1857 { 1858 int i, j, ret, val; 1859 struct hdcp_keys *hdcp_keys; 1860 1861 val = sizeof(*hdcp_keys); 1862 hdcp_keys = malloc(val); 1863 if (!hdcp_keys) 1864 return -ENOMEM; 1865 1866 memset(hdcp_keys, 0, val); 1867 1868 ret = vendor_storage_read(HDMI_HDCP1X_ID, hdcp_keys, val); 1869 if (ret < val) { 1870 printf("HDCP: read size %d\n", ret); 1871 free(hdcp_keys); 1872 return -EINVAL; 1873 } 1874 1875 if (hdcp_keys->KSV[0] == 0x00 && 1876 hdcp_keys->KSV[1] == 0x00 && 1877 hdcp_keys->KSV[2] == 0x00 && 1878 hdcp_keys->KSV[3] == 0x00 && 1879 hdcp_keys->KSV[4] == 0x00) { 1880 printf("HDCP: Invalid hdcp key\n"); 1881 free(hdcp_keys); 1882 return -EINVAL; 1883 } 1884 1885 /* Disable decryption logic */ 1886 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_RMCTL); 1887 /* Poll untile DPK write is allowed */ 1888 do { 1889 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1890 } while ((val & DPK_WR_OK_STS) == 0); 1891 1892 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_DPK6); 1893 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_DPK5); 1894 1895 /* The useful data in ksv should be 5 byte */ 1896 for (i = 4; i >= 0; i--) 1897 hdmi_writeb(hdmi, hdcp_keys->KSV[i], HDMI_HDCPREG_DPK0 + i); 1898 /* Poll untile DPK write is allowed */ 1899 do { 1900 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1901 } while ((val & DPK_WR_OK_STS) == 0); 1902 1903 /* Enable decryption logic */ 1904 hdmi_writeb(hdmi, 1, HDMI_HDCPREG_RMCTL); 1905 hdmi_writeb(hdmi, hdcp_keys->seeds[0], HDMI_HDCPREG_SEED1); 1906 hdmi_writeb(hdmi, hdcp_keys->seeds[1], HDMI_HDCPREG_SEED0); 1907 1908 /* Write encrypt device private key */ 1909 for (i = 0; i < DW_HDMI_HDCP_DPK_LEN - 6; i += 7) { 1910 for (j = 6; j >= 0; j--) 1911 hdmi_writeb(hdmi, hdcp_keys->devicekey[i + j], 1912 HDMI_HDCPREG_DPK0 + j); 1913 do { 1914 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1915 } while ((val & DPK_WR_OK_STS) == 0); 1916 } 1917 1918 free(hdcp_keys); 1919 return 0; 1920 } 1921 1922 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi, 1923 const struct drm_display_mode *mode) 1924 { 1925 u8 vsync_pol, hsync_pol, data_pol, hdmi_dvi; 1926 1927 if (!hdmi->hdcp1x_enable) 1928 return; 1929 1930 /* Configure the video polarity */ 1931 vsync_pol = mode->flags & DRM_MODE_FLAG_PVSYNC ? 1932 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH : 1933 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW; 1934 hsync_pol = mode->flags & DRM_MODE_FLAG_PHSYNC ? 1935 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH : 1936 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW; 1937 data_pol = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1938 hdmi_modb(hdmi, vsync_pol | hsync_pol | data_pol, 1939 HDMI_A_VIDPOLCFG_VSYNCPOL_MASK | 1940 HDMI_A_VIDPOLCFG_HSYNCPOL_MASK | 1941 HDMI_A_VIDPOLCFG_DATAENPOL_MASK, 1942 HDMI_A_VIDPOLCFG); 1943 1944 /* Config the display mode */ 1945 hdmi_dvi = hdmi->sink_is_hdmi ? HDMI_A_HDCPCFG0_HDMIDVI_HDMI : 1946 HDMI_A_HDCPCFG0_HDMIDVI_DVI; 1947 hdmi_modb(hdmi, hdmi_dvi, HDMI_A_HDCPCFG0_HDMIDVI_MASK, 1948 HDMI_A_HDCPCFG0); 1949 1950 if (!(hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS) & 0x3f)) 1951 dw_hdmi_hdcp_load_key(hdmi); 1952 1953 hdmi_modb(hdmi, HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE, 1954 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK, 1955 HDMI_FC_INVIDCONF); 1956 1957 if (hdmi_readb(hdmi, HDMI_CONFIG1_ID) & HDMI_A_HDCP22_MASK) { 1958 hdmi_modb(hdmi, HDMI_HDCP2_OVR_ENABLE | 1959 HDMI_HDCP2_FORCE_DISABLE, 1960 HDMI_HDCP2_OVR_EN_MASK | 1961 HDMI_HDCP2_FORCE_MASK, 1962 HDMI_HDCP2REG_CTRL); 1963 hdmi_writeb(hdmi, 0xff, HDMI_HDCP2REG_MASK); 1964 hdmi_writeb(hdmi, 0xff, HDMI_HDCP2REG_MUTE); 1965 } 1966 1967 hdmi_writeb(hdmi, 0x40, HDMI_A_OESSWCFG); 1968 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE | 1969 HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE | 1970 HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE, 1971 HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK | 1972 HDMI_A_HDCPCFG0_EN11FEATURE_MASK | 1973 HDMI_A_HDCPCFG0_SYNCRICHECK_MASK, HDMI_A_HDCPCFG0); 1974 1975 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE | 1976 HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE, 1977 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK | 1978 HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK, HDMI_A_HDCPCFG1); 1979 1980 /* Reset HDCP Engine */ 1981 if (hdmi_readb(hdmi, HDMI_MC_CLKDIS) & HDMI_MC_CLKDIS_HDCPCLK_MASK) { 1982 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_SWRESET_ASSERT, 1983 HDMI_A_HDCPCFG1_SWRESET_MASK, HDMI_A_HDCPCFG1); 1984 } 1985 1986 hdmi_writeb(hdmi, 0x00, HDMI_A_APIINTMSK); 1987 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_ENABLE, 1988 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 1989 1990 hdmi_modb(hdmi, HDMI_MC_CLKDIS_HDCPCLK_ENABLE, 1991 HDMI_MC_CLKDIS_HDCPCLK_MASK, HDMI_MC_CLKDIS); 1992 1993 printf("%s success\n", __func__); 1994 } 1995 1996 static int dw_hdmi_setup(struct dw_hdmi *hdmi, 1997 struct drm_display_mode *mode, 1998 struct display_state *state) 1999 { 2000 int ret; 2001 void *data = hdmi->plat_data->phy_data; 2002 2003 hdmi_disable_overflow_interrupts(hdmi); 2004 if (!hdmi->vic) 2005 printf("Non-CEA mode used in HDMI\n"); 2006 else 2007 printf("CEA mode used vic=%d\n", hdmi->vic); 2008 2009 if (hdmi->plat_data->get_enc_out_encoding) 2010 hdmi->hdmi_data.enc_out_encoding = 2011 hdmi->plat_data->get_enc_out_encoding(data); 2012 else if ((hdmi->vic == 6) || (hdmi->vic == 7) || 2013 (hdmi->vic == 21) || (hdmi->vic == 22) || 2014 (hdmi->vic == 2) || (hdmi->vic == 3) || 2015 (hdmi->vic == 17) || (hdmi->vic == 18)) 2016 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 2017 else 2018 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 2019 2020 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2021 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1; 2022 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1; 2023 } else { 2024 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 2025 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 2026 } 2027 2028 /* TOFIX: Get input encoding from plat data or fallback to none */ 2029 if (hdmi->plat_data->get_enc_in_encoding) 2030 hdmi->hdmi_data.enc_in_encoding = 2031 hdmi->plat_data->get_enc_in_encoding(data); 2032 else if (hdmi->plat_data->input_bus_encoding) 2033 hdmi->hdmi_data.enc_in_encoding = 2034 hdmi->plat_data->input_bus_encoding; 2035 else 2036 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 2037 /* 2038 * According to the dw-hdmi specification 6.4.2 2039 * vp_pr_cd[3:0]: 2040 * 0000b: No pixel repetition (pixel sent only once) 2041 * 0001b: Pixel sent two times (pixel repeated once) 2042 */ 2043 hdmi->hdmi_data.pix_repet_factor = 2044 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0; 2045 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 2046 2047 /* HDMI Initialization Step B.1 */ 2048 hdmi_av_composer(hdmi, mode); 2049 2050 /* HDMI Initialization Step B.2 */ 2051 ret = hdmi->phy.ops->init(hdmi, state); 2052 if (ret) 2053 return ret; 2054 hdmi->phy.enabled = true; 2055 2056 /* HDMI Initializateion Step B.3 */ 2057 dw_hdmi_enable_video_path(hdmi); 2058 2059 /* HDMI Initialization Step E - Configure audio */ 2060 if (hdmi->sink_has_audio) { 2061 printf("sink has audio support\n"); 2062 hdmi_clk_regenerator_update_pixel_clock(hdmi); 2063 hdmi_enable_audio_clk(hdmi); 2064 } 2065 2066 /* not for DVI mode */ 2067 if (hdmi->sink_is_hdmi) { 2068 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 2069 hdmi_config_AVI(hdmi, mode); 2070 hdmi_config_vendor_specific_infoframe(hdmi, mode); 2071 } else { 2072 printf("%s DVI mode\n", __func__); 2073 } 2074 2075 hdmi_video_packetize(hdmi); 2076 hdmi_video_csc(hdmi); 2077 hdmi_video_sample(hdmi); 2078 hdmi_tx_hdcp_config(hdmi, mode); 2079 dw_hdmi_clear_overflow(hdmi); 2080 if (hdmi->cable_plugin && hdmi->sink_is_hdmi) 2081 hdmi_enable_overflow_interrupts(hdmi); 2082 2083 return 0; 2084 } 2085 2086 int dw_hdmi_detect_hotplug(struct dw_hdmi *hdmi, 2087 struct display_state *state) 2088 { 2089 return hdmi->phy.ops->read_hpd(hdmi, state); 2090 } 2091 2092 static int dw_hdmi_set_reg_wr(struct dw_hdmi *hdmi) 2093 { 2094 switch (hdmi->io_width) { 2095 case 4: 2096 hdmi->write = dw_hdmi_writel; 2097 hdmi->read = dw_hdmi_readl; 2098 break; 2099 case 1: 2100 hdmi->write = dw_hdmi_writeb; 2101 hdmi->read = dw_hdmi_readb; 2102 break; 2103 default: 2104 printf("reg-io-width must be 1 or 4\n"); 2105 return -EINVAL; 2106 } 2107 2108 return 0; 2109 } 2110 2111 static void initialize_hdmi_mutes(struct dw_hdmi *hdmi) 2112 { 2113 /*mute unnecessary interrupt, only enable hpd */ 2114 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 2115 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 2116 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 2117 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 2118 hdmi_writeb(hdmi, 0xfe, HDMI_IH_MUTE_PHY_STAT0); 2119 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 2120 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 2121 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 2122 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 2123 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 2124 hdmi_writeb(hdmi, 0xf1, HDMI_PHY_MASK0); 2125 2126 /*Force output black*/ 2127 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS2); 2128 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS1); 2129 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS0); 2130 } 2131 2132 static void dw_hdmi_dev_init(struct dw_hdmi *hdmi) 2133 { 2134 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 2135 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 2136 2137 initialize_hdmi_mutes(hdmi); 2138 } 2139 2140 static void dw_hdmi_i2c_set_divs(struct dw_hdmi *hdmi) 2141 { 2142 unsigned long low_ns, high_ns; 2143 unsigned long div_low, div_high; 2144 2145 /* Standard-mode */ 2146 if (hdmi->i2c->scl_high_ns < 4000) 2147 high_ns = 4708; 2148 else 2149 high_ns = hdmi->i2c->scl_high_ns; 2150 2151 if (hdmi->i2c->scl_low_ns < 4700) 2152 low_ns = 4916; 2153 else 2154 low_ns = hdmi->i2c->scl_low_ns; 2155 2156 div_low = (24000 * low_ns) / 1000000; 2157 if ((24000 * low_ns) % 1000000) 2158 div_low++; 2159 2160 div_high = (24000 * high_ns) / 1000000; 2161 if ((24000 * high_ns) % 1000000) 2162 div_high++; 2163 2164 /* Maximum divider supported by hw is 0xffff */ 2165 if (div_low > 0xffff) 2166 div_low = 0xffff; 2167 2168 if (div_high > 0xffff) 2169 div_high = 0xffff; 2170 2171 hdmi_writeb(hdmi, div_high & 0xff, HDMI_I2CM_SS_SCL_HCNT_0_ADDR); 2172 hdmi_writeb(hdmi, (div_high >> 8) & 0xff, 2173 HDMI_I2CM_SS_SCL_HCNT_1_ADDR); 2174 hdmi_writeb(hdmi, div_low & 0xff, HDMI_I2CM_SS_SCL_LCNT_0_ADDR); 2175 hdmi_writeb(hdmi, (div_low >> 8) & 0xff, 2176 HDMI_I2CM_SS_SCL_LCNT_1_ADDR); 2177 } 2178 2179 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 2180 { 2181 /* Software reset */ 2182 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 2183 2184 /* Set Standard Mode speed */ 2185 hdmi_modb(hdmi, HDMI_I2CM_DIV_STD_MODE, 2186 HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV); 2187 2188 /* Set done, not acknowledged and arbitration interrupt polarities */ 2189 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 2190 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 2191 HDMI_I2CM_CTLINT); 2192 2193 /* Clear DONE and ERROR interrupts */ 2194 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 2195 HDMI_IH_I2CM_STAT0); 2196 2197 /* Mute DONE and ERROR interrupts */ 2198 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 2199 HDMI_IH_MUTE_I2CM_STAT0); 2200 2201 /* set SDA high level holding time */ 2202 hdmi_writeb(hdmi, 0x48, HDMI_I2CM_SDA_HOLD); 2203 2204 dw_hdmi_i2c_set_divs(hdmi); 2205 } 2206 2207 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 2208 { 2209 hdmi->audio_enable = true; 2210 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 2211 } 2212 2213 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 2214 { 2215 hdmi->audio_enable = false; 2216 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 2217 } 2218 2219 int rockchip_dw_hdmi_init(struct display_state *state) 2220 { 2221 struct connector_state *conn_state = &state->conn_state; 2222 const struct rockchip_connector *connector = conn_state->connector; 2223 const struct dw_hdmi_plat_data *pdata = connector->data; 2224 struct crtc_state *crtc_state = &state->crtc_state; 2225 struct dw_hdmi *hdmi; 2226 struct drm_display_mode *mode_buf; 2227 ofnode hdmi_node = conn_state->node; 2228 u32 val; 2229 2230 hdmi = malloc(sizeof(struct dw_hdmi)); 2231 if (!hdmi) 2232 return -ENOMEM; 2233 2234 memset(hdmi, 0, sizeof(struct dw_hdmi)); 2235 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 2236 if (!mode_buf) 2237 return -ENOMEM; 2238 2239 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 2240 2241 hdmi->regs = dev_read_addr_ptr(conn_state->dev); 2242 hdmi->io_width = ofnode_read_s32_default(hdmi_node, "reg-io-width", -1); 2243 2244 if (ofnode_read_bool(hdmi_node, "scramble-low-rates")) 2245 hdmi->scramble_low_rates = true; 2246 2247 if (ofnode_read_bool(hdmi_node, "hdcp1x-enable")) 2248 hdmi->hdcp1x_enable = true; 2249 else 2250 hdmi->hdcp1x_enable = false; 2251 2252 hdmi->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 2253 if (hdmi->grf <= 0) { 2254 printf("%s: Get syscon grf failed (ret=%p)\n", 2255 __func__, hdmi->grf); 2256 return -ENXIO; 2257 } 2258 2259 dw_hdmi_set_reg_wr(hdmi); 2260 2261 if (pdata->grf_vop_sel_reg) { 2262 if (crtc_state->crtc_id) 2263 val = ((1 << pdata->vop_sel_bit) | 2264 (1 << (16 + pdata->vop_sel_bit))); 2265 else 2266 val = ((0 << pdata->vop_sel_bit) | 2267 (1 << (16 + pdata->vop_sel_bit))); 2268 writel(val, hdmi->grf + pdata->grf_vop_sel_reg); 2269 } 2270 2271 hdmi->i2c = malloc(sizeof(struct dw_hdmi_i2c)); 2272 if (!hdmi->i2c) 2273 return -ENOMEM; 2274 hdmi->adap.ddc_xfer = dw_hdmi_i2c_xfer; 2275 2276 /* 2277 * Read high and low time from device tree. If not available use 2278 * the default timing scl clock rate is about 99.6KHz. 2279 */ 2280 hdmi->i2c->scl_high_ns = 2281 ofnode_read_s32_default(hdmi_node, 2282 "ddc-i2c-scl-high-time-ns", -1); 2283 if (hdmi->i2c->scl_high_ns < 0) 2284 hdmi->i2c->scl_high_ns = 4708; 2285 2286 hdmi->i2c->scl_low_ns = 2287 ofnode_read_s32_default(hdmi_node, 2288 "ddc-i2c-scl-low-time-ns", -1); 2289 if (hdmi->i2c->scl_low_ns < 0) 2290 hdmi->i2c->scl_low_ns = 4916; 2291 2292 dw_hdmi_i2c_init(hdmi); 2293 conn_state->type = DRM_MODE_CONNECTOR_HDMIA; 2294 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 2295 2296 hdmi->dev_type = pdata->dev_type; 2297 hdmi->plat_data = pdata; 2298 hdmi->edid_data.mode_buf = mode_buf; 2299 hdmi->sample_rate = 48000; 2300 2301 conn_state->private = hdmi; 2302 dw_hdmi_set_iomux(hdmi->grf, hdmi->dev_type); 2303 dw_hdmi_detect_phy(hdmi); 2304 dw_hdmi_dev_init(hdmi); 2305 2306 return 0; 2307 } 2308 2309 void rockchip_dw_hdmi_deinit(struct display_state *state) 2310 { 2311 struct connector_state *conn_state = &state->conn_state; 2312 struct dw_hdmi *hdmi = conn_state->private; 2313 2314 if (hdmi->i2c) 2315 free(hdmi->i2c); 2316 if (hdmi->edid_data.mode_buf) 2317 free(hdmi->edid_data.mode_buf); 2318 if (hdmi) 2319 free(hdmi); 2320 } 2321 2322 int rockchip_dw_hdmi_prepare(struct display_state *state) 2323 { 2324 return 0; 2325 } 2326 2327 int rockchip_dw_hdmi_enable(struct display_state *state) 2328 { 2329 struct connector_state *conn_state = &state->conn_state; 2330 struct drm_display_mode *mode = &conn_state->mode; 2331 struct dw_hdmi *hdmi = conn_state->private; 2332 2333 if (!hdmi) 2334 return -EFAULT; 2335 2336 /* Store the display mode for plugin/DKMS poweron events */ 2337 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 2338 2339 dw_hdmi_setup(hdmi, mode, state); 2340 2341 return 0; 2342 } 2343 2344 int rockchip_dw_hdmi_disable(struct display_state *state) 2345 { 2346 struct connector_state *conn_state = &state->conn_state; 2347 struct dw_hdmi *hdmi = conn_state->private; 2348 2349 dw_hdmi_disable(hdmi, state); 2350 return 0; 2351 } 2352 2353 int rockchip_dw_hdmi_get_timing(struct display_state *state) 2354 { 2355 int ret, i; 2356 struct connector_state *conn_state = &state->conn_state; 2357 struct drm_display_mode *mode = &conn_state->mode; 2358 struct dw_hdmi *hdmi = conn_state->private; 2359 struct edid *edid = (struct edid *)conn_state->edid; 2360 unsigned int bus_format; 2361 struct overscan *overscan = &conn_state->overscan; 2362 const u8 def_modes_vic[6] = {4, 16, 2, 17, 31, 19}; 2363 2364 if (!hdmi) 2365 return -EFAULT; 2366 2367 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 2368 if (!ret) { 2369 hdmi->sink_is_hdmi = 2370 drm_detect_hdmi_monitor(edid); 2371 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 2372 ret = drm_add_edid_modes(&hdmi->edid_data, conn_state->edid); 2373 } 2374 if (ret <= 0) { 2375 hdmi->sink_is_hdmi = true; 2376 hdmi->sink_has_audio = true; 2377 do_cea_modes(&hdmi->edid_data, def_modes_vic, 2378 sizeof(def_modes_vic)); 2379 hdmi->edid_data.preferred_mode = &hdmi->edid_data.mode_buf[0]; 2380 printf("failed to get edid\n"); 2381 } 2382 drm_rk_filter_whitelist(&hdmi->edid_data); 2383 if (hdmi->phy.ops->mode_valid) 2384 hdmi->phy.ops->mode_valid(hdmi, state); 2385 if (!drm_mode_prune_invalid(&hdmi->edid_data)) { 2386 printf("can't find valid hdmi mode\n"); 2387 return -EINVAL; 2388 } 2389 2390 for (i = 0; i < hdmi->edid_data.modes; i++) 2391 hdmi->edid_data.mode_buf[i].vrefresh = 2392 drm_mode_vrefresh(&hdmi->edid_data.mode_buf[i]); 2393 2394 drm_mode_sort(&hdmi->edid_data); 2395 drm_rk_selete_output(&hdmi->edid_data, &bus_format, 2396 overscan, hdmi->dev_type); 2397 2398 *mode = *hdmi->edid_data.preferred_mode; 2399 hdmi->vic = drm_match_cea_mode(mode); 2400 2401 printf("mode:%dx%d\n", mode->hdisplay, mode->vdisplay); 2402 conn_state->bus_format = bus_format; 2403 hdmi->hdmi_data.enc_in_bus_format = bus_format; 2404 hdmi->hdmi_data.enc_out_bus_format = bus_format; 2405 2406 switch (bus_format) { 2407 case MEDIA_BUS_FMT_UYVY10_1X20: 2408 conn_state->bus_format = MEDIA_BUS_FMT_YUV10_1X30; 2409 hdmi->hdmi_data.enc_in_bus_format = 2410 MEDIA_BUS_FMT_YUV10_1X30; 2411 break; 2412 case MEDIA_BUS_FMT_UYVY8_1X16: 2413 conn_state->bus_format = MEDIA_BUS_FMT_YUV8_1X24; 2414 hdmi->hdmi_data.enc_in_bus_format = 2415 MEDIA_BUS_FMT_YUV8_1X24; 2416 break; 2417 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 2418 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 2419 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420; 2420 break; 2421 } 2422 2423 return 0; 2424 } 2425 2426 int rockchip_dw_hdmi_detect(struct display_state *state) 2427 { 2428 int ret; 2429 struct connector_state *conn_state = &state->conn_state; 2430 struct dw_hdmi *hdmi = conn_state->private; 2431 2432 if (!hdmi) 2433 return -EFAULT; 2434 2435 ret = dw_hdmi_detect_hotplug(hdmi, state); 2436 2437 return ret; 2438 } 2439 2440 int rockchip_dw_hdmi_get_edid(struct display_state *state) 2441 { 2442 int ret; 2443 struct connector_state *conn_state = &state->conn_state; 2444 struct dw_hdmi *hdmi = conn_state->private; 2445 2446 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 2447 2448 return ret; 2449 } 2450 2451 int inno_dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data) 2452 { 2453 struct display_state *state = (struct display_state *)data; 2454 struct connector_state *conn_state = &state->conn_state; 2455 u32 color_depth, bus_width; 2456 2457 color_depth = 2458 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 2459 2460 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 2461 bus_width = color_depth / 2; 2462 else if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 2463 bus_width = color_depth; 2464 else 2465 bus_width = 8; 2466 rockchip_phy_set_bus_width(conn_state->phy, bus_width); 2467 rockchip_phy_set_pll(conn_state->phy, 2468 conn_state->mode.crtc_clock * 1000); 2469 if (hdmi->edid_data.display_info.hdmi.scdc.supported) 2470 rockchip_dw_hdmi_scdc_set_tmds_rate(hdmi); 2471 rockchip_phy_power_on(conn_state->phy); 2472 2473 return 0; 2474 } 2475 2476 void inno_dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 2477 { 2478 } 2479 2480 enum drm_connector_status 2481 inno_dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data) 2482 { 2483 enum drm_connector_status status; 2484 struct display_state *state = (struct display_state *)data; 2485 2486 status = dw_hdmi_phy_read_hpd(hdmi, state); 2487 2488 if (hdmi->dev_type == RK3328_HDMI) { 2489 if (status == connector_status_connected) 2490 inno_dw_hdmi_set_domain(hdmi->grf, 1); 2491 else 2492 inno_dw_hdmi_set_domain(hdmi->grf, 0); 2493 } 2494 2495 return status; 2496 } 2497 2498 void inno_dw_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data) 2499 { 2500 struct display_state *state = (struct display_state *)data; 2501 struct connector_state *conn_state = &state->conn_state; 2502 struct hdmi_edid_data *edid_data = &hdmi->edid_data; 2503 unsigned long rate; 2504 int i, ret; 2505 struct drm_display_mode *mode_buf = edid_data->mode_buf; 2506 2507 for (i = 0; i < edid_data->modes; i++) { 2508 if (edid_data->mode_buf[i].invalid) 2509 continue; 2510 if (edid_data->mode_buf[i].flags & DRM_MODE_FLAG_DBLCLK) 2511 rate = mode_buf[i].clock * 1000 * 2; 2512 else 2513 rate = mode_buf[i].clock * 1000; 2514 2515 /* Check whether mode is out of phy cfg range. */ 2516 ret = rockchip_phy_round_rate(conn_state->phy, rate); 2517 2518 if (ret < 0) 2519 edid_data->mode_buf[i].invalid = true; 2520 } 2521 } 2522