1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <syscon.h> 10 #include <asm/arch-rockchip/clock.h> 11 #include <asm/arch/vendor.h> 12 #include <edid.h> 13 #include <dm/device.h> 14 #include <dm/of_access.h> 15 #include <dm/ofnode.h> 16 #include <dm/read.h> 17 #include <linux/hdmi.h> 18 #include <linux/media-bus-format.h> 19 #include <linux/dw_hdmi.h> 20 #include <asm/io.h> 21 #include "rockchip_display.h" 22 #include "rockchip_crtc.h" 23 #include "rockchip_connector.h" 24 #include "dw_hdmi.h" 25 #include "rockchip_phy.h" 26 27 #define HDCP_PRIVATE_KEY_SIZE 280 28 #define HDCP_KEY_SHA_SIZE 20 29 #define HDMI_HDCP1X_ID 5 30 /* 31 * Unless otherwise noted, entries in this table are 100% optimization. 32 * Values can be obtained from hdmi_compute_n() but that function is 33 * slow so we pre-compute values we expect to see. 34 * 35 * All 32k and 48k values are expected to be the same (due to the way 36 * the math works) for any rate that's an exact kHz. 37 */ 38 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = { 39 { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, }, 40 { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, }, 41 { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 42 { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, }, 43 { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, }, 44 { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, 45 { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, 46 { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 47 { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 48 { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, 49 { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 50 { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, 51 { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 52 { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 53 { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, }, 54 { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 55 { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, }, 56 { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 57 { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 58 { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, }, 59 { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, 60 { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, 61 { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, 62 { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 63 { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 64 { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 65 { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 66 { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 67 { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, 68 { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 69 { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, }, 70 { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, 71 { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 72 { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 73 { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 74 { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, 75 { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 76 77 /* For 297 MHz+ HDMI spec have some other rule for setting N */ 78 { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, }, 79 { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, }, 80 81 /* End of table */ 82 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, }, 83 }; 84 85 static const u16 csc_coeff_default[3][4] = { 86 { 0x2000, 0x0000, 0x0000, 0x0000 }, 87 { 0x0000, 0x2000, 0x0000, 0x0000 }, 88 { 0x0000, 0x0000, 0x2000, 0x0000 } 89 }; 90 91 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 92 { 0x2000, 0x6926, 0x74fd, 0x010e }, 93 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 94 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 95 }; 96 97 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 98 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 99 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 100 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 101 }; 102 103 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 104 { 0x2591, 0x1322, 0x074b, 0x0000 }, 105 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 106 { 0x6acd, 0x7534, 0x2000, 0x0200 } 107 }; 108 109 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 110 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 111 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 112 { 0x6756, 0x78ab, 0x2000, 0x0200 } 113 }; 114 115 static const u16 csc_coeff_full_to_limited[3][4] = { 116 { 0x36f7, 0x0000, 0x0000, 0x0040 }, 117 { 0x0000, 0x36f7, 0x0000, 0x0040 }, 118 { 0x0000, 0x0000, 0x36f7, 0x0040 } 119 }; 120 121 struct hdmi_vmode { 122 bool mdataenablepolarity; 123 124 unsigned int mpixelclock; 125 unsigned int mpixelrepetitioninput; 126 unsigned int mpixelrepetitionoutput; 127 unsigned int mtmdsclock; 128 }; 129 130 struct hdmi_data_info { 131 unsigned int enc_in_bus_format; 132 unsigned int enc_out_bus_format; 133 unsigned int enc_in_encoding; 134 unsigned int enc_out_encoding; 135 unsigned int quant_range; 136 unsigned int pix_repet_factor; 137 struct hdmi_vmode video_mode; 138 }; 139 140 struct dw_hdmi_phy_data { 141 enum dw_hdmi_phy_type type; 142 const char *name; 143 unsigned int gen; 144 bool has_svsret; 145 int (*configure)(struct dw_hdmi *hdmi, 146 const struct dw_hdmi_plat_data *pdata, 147 unsigned long mpixelclock); 148 }; 149 150 struct hdcp_keys { 151 u8 KSV[8]; 152 u8 devicekey[HDCP_PRIVATE_KEY_SIZE]; 153 u8 sha1[HDCP_KEY_SHA_SIZE]; 154 u8 seeds[2]; 155 }; 156 157 struct dw_hdmi_i2c { 158 u8 slave_reg; 159 bool is_regaddr; 160 bool is_segment; 161 162 unsigned int scl_high_ns; 163 unsigned int scl_low_ns; 164 }; 165 166 struct dw_hdmi { 167 int id; 168 enum dw_hdmi_devtype dev_type; 169 unsigned int version; 170 struct hdmi_data_info hdmi_data; 171 struct hdmi_edid_data edid_data; 172 const struct dw_hdmi_plat_data *plat_data; 173 struct ddc_adapter adap; 174 175 int vic; 176 int io_width; 177 178 unsigned long bus_format; 179 bool cable_plugin; 180 bool sink_is_hdmi; 181 bool sink_has_audio; 182 void *regs; 183 void *grf; 184 struct dw_hdmi_i2c *i2c; 185 186 struct { 187 const struct dw_hdmi_phy_ops *ops; 188 const char *name; 189 void *data; 190 bool enabled; 191 } phy; 192 193 struct drm_display_mode previous_mode; 194 195 unsigned int sample_rate; 196 unsigned int audio_cts; 197 unsigned int audio_n; 198 bool audio_enable; 199 bool scramble_low_rates; 200 201 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset); 202 u8 (*read)(struct dw_hdmi *hdmi, int offset); 203 204 bool hdcp1x_enable; 205 bool output_bus_format_rgb; 206 }; 207 208 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset) 209 { 210 writel(val, hdmi->regs + (offset << 2)); 211 } 212 213 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset) 214 { 215 return readl(hdmi->regs + (offset << 2)); 216 } 217 218 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 219 { 220 writeb(val, hdmi->regs + offset); 221 } 222 223 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset) 224 { 225 return readb(hdmi->regs + offset); 226 } 227 228 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 229 { 230 hdmi->write(hdmi, val, offset); 231 } 232 233 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 234 { 235 return hdmi->read(hdmi, offset); 236 } 237 238 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 239 { 240 u8 val = hdmi_readb(hdmi, reg) & ~mask; 241 242 val |= data & mask; 243 hdmi_writeb(hdmi, val, reg); 244 } 245 246 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 247 u8 shift, u8 mask) 248 { 249 hdmi_modb(hdmi, data << shift, mask, reg); 250 } 251 252 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 253 { 254 switch (bus_format) { 255 case MEDIA_BUS_FMT_RGB888_1X24: 256 case MEDIA_BUS_FMT_RGB101010_1X30: 257 case MEDIA_BUS_FMT_RGB121212_1X36: 258 case MEDIA_BUS_FMT_RGB161616_1X48: 259 return true; 260 261 default: 262 return false; 263 } 264 } 265 266 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 267 { 268 switch (bus_format) { 269 case MEDIA_BUS_FMT_YUV8_1X24: 270 case MEDIA_BUS_FMT_YUV10_1X30: 271 case MEDIA_BUS_FMT_YUV12_1X36: 272 case MEDIA_BUS_FMT_YUV16_1X48: 273 return true; 274 275 default: 276 return false; 277 } 278 } 279 280 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 281 { 282 switch (bus_format) { 283 case MEDIA_BUS_FMT_UYVY8_1X16: 284 case MEDIA_BUS_FMT_UYVY10_1X20: 285 case MEDIA_BUS_FMT_UYVY12_1X24: 286 return true; 287 288 default: 289 return false; 290 } 291 } 292 293 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 294 { 295 switch (bus_format) { 296 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 297 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 298 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 299 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 300 return true; 301 302 default: 303 return false; 304 } 305 } 306 307 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 308 { 309 switch (bus_format) { 310 case MEDIA_BUS_FMT_RGB888_1X24: 311 case MEDIA_BUS_FMT_YUV8_1X24: 312 case MEDIA_BUS_FMT_UYVY8_1X16: 313 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 314 return 8; 315 316 case MEDIA_BUS_FMT_RGB101010_1X30: 317 case MEDIA_BUS_FMT_YUV10_1X30: 318 case MEDIA_BUS_FMT_UYVY10_1X20: 319 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 320 return 10; 321 322 case MEDIA_BUS_FMT_RGB121212_1X36: 323 case MEDIA_BUS_FMT_YUV12_1X36: 324 case MEDIA_BUS_FMT_UYVY12_1X24: 325 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 326 return 12; 327 328 case MEDIA_BUS_FMT_RGB161616_1X48: 329 case MEDIA_BUS_FMT_YUV16_1X48: 330 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 331 return 16; 332 333 default: 334 return 0; 335 } 336 } 337 338 static int is_color_space_conversion(struct dw_hdmi *hdmi) 339 { 340 struct drm_display_mode *mode = 341 hdmi->edid_data.preferred_mode; 342 bool is_cea_default; 343 344 is_cea_default = (drm_match_cea_mode(mode) > 1) && 345 (hdmi->hdmi_data.quant_range == 346 HDMI_QUANTIZATION_RANGE_DEFAULT); 347 348 /* 349 * When output is rgb limited range or default range with 350 * cea mode, csc should be enabled. 351 */ 352 if (hdmi->hdmi_data.enc_in_bus_format != 353 hdmi->hdmi_data.enc_out_bus_format || 354 ((hdmi->hdmi_data.quant_range == HDMI_QUANTIZATION_RANGE_LIMITED || 355 is_cea_default) && 356 hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format))) 357 return 1; 358 359 return 0; 360 } 361 362 static int is_color_space_decimation(struct dw_hdmi *hdmi) 363 { 364 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 365 return 0; 366 367 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 368 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 369 return 1; 370 371 return 0; 372 } 373 374 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 375 unsigned char bit) 376 { 377 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 378 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 379 } 380 381 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi, 382 unsigned char bit) 383 { 384 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET, 385 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0); 386 } 387 388 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi, 389 unsigned char bit) 390 { 391 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET, 392 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0); 393 } 394 395 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi, 396 unsigned char bit) 397 { 398 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1); 399 } 400 401 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi, 402 unsigned char bit) 403 { 404 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2); 405 } 406 407 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 408 unsigned char *buf, unsigned int length) 409 { 410 struct dw_hdmi_i2c *i2c = hdmi->i2c; 411 int interrupt = 0, i = 20; 412 413 if (!i2c->is_regaddr) { 414 printf("set read register address to 0\n"); 415 i2c->slave_reg = 0x00; 416 i2c->is_regaddr = true; 417 } 418 419 while (length--) { 420 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 421 if (i2c->is_segment) 422 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 423 HDMI_I2CM_OPERATION); 424 else 425 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 426 HDMI_I2CM_OPERATION); 427 428 while (i--) { 429 udelay(1000); 430 interrupt = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 431 if (interrupt) 432 hdmi_writeb(hdmi, interrupt, 433 HDMI_IH_I2CM_STAT0); 434 if (interrupt & (m_SCDC_READREQ | m_I2CM_DONE | 435 m_I2CM_ERROR)) 436 break; 437 } 438 439 if (!interrupt) { 440 printf("[%s] i2c read reg[0x%02x] no interrupt\n", 441 __func__, i2c->slave_reg); 442 return -EAGAIN; 443 } 444 445 /* Check for error condition on the bus */ 446 if (interrupt & HDMI_IH_I2CM_STAT0_ERROR) { 447 printf("[%s] read reg[0x%02x] data error:0x%02x\n", 448 __func__, i2c->slave_reg, interrupt); 449 return -EIO; 450 } 451 452 i = 20; 453 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 454 } 455 i2c->is_segment = false; 456 457 return 0; 458 } 459 460 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 461 unsigned char *buf, unsigned int length) 462 { 463 struct dw_hdmi_i2c *i2c = hdmi->i2c; 464 int i = 20; 465 u8 interrupt = 0; 466 467 if (!i2c->is_regaddr) { 468 /* Use the first write byte as register address */ 469 i2c->slave_reg = buf[0]; 470 length--; 471 buf++; 472 i2c->is_regaddr = true; 473 } 474 475 while (length--) { 476 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 477 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 478 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 479 HDMI_I2CM_OPERATION); 480 481 while (i--) { 482 udelay(1000); 483 interrupt = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 484 if (interrupt) 485 hdmi_writeb(hdmi, 486 interrupt, HDMI_IH_I2CM_STAT0); 487 488 if (interrupt & (m_SCDC_READREQ | 489 m_I2CM_DONE | m_I2CM_ERROR)) 490 break; 491 } 492 493 if ((interrupt & m_I2CM_ERROR) || (i == -1)) { 494 printf("[%s] write data error\n", __func__); 495 return -EIO; 496 } else if (interrupt & m_I2CM_DONE) { 497 printf("[%s] write offset %02x success\n", 498 __func__, i2c->slave_reg); 499 return -EAGAIN; 500 } 501 502 i = 20; 503 } 504 505 return 0; 506 } 507 508 static int dw_hdmi_i2c_xfer(struct ddc_adapter *adap, 509 struct i2c_msg *msgs, int num) 510 { 511 struct dw_hdmi *hdmi = container_of(adap, struct dw_hdmi, adap); 512 struct dw_hdmi_i2c *i2c = hdmi->i2c; 513 u8 addr = msgs[0].addr; 514 int i, ret = 0; 515 516 printf("xfer: num: %d, addr: %#x\n", num, addr); 517 for (i = 0; i < num; i++) { 518 if (msgs[i].len == 0) { 519 printf("unsupported transfer %d/%d, no data\n", 520 i + 1, num); 521 return -EOPNOTSUPP; 522 } 523 } 524 525 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 526 527 /* Set slave device address taken from the first I2C message */ 528 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1) 529 addr = DDC_ADDR; 530 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 531 532 /* Set slave device register address on transfer */ 533 i2c->is_regaddr = false; 534 535 /* Set segment pointer for I2C extended read mode operation */ 536 i2c->is_segment = false; 537 538 for (i = 0; i < num; i++) { 539 debug("xfer: num: %d/%d, len: %d, flags: %#x\n", 540 i + 1, num, msgs[i].len, msgs[i].flags); 541 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 542 i2c->is_segment = true; 543 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 544 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 545 } else { 546 if (msgs[i].flags & I2C_M_RD) 547 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 548 msgs[i].len); 549 else 550 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 551 msgs[i].len); 552 } 553 if (ret < 0) 554 break; 555 } 556 557 if (!ret) 558 ret = num; 559 560 /* Mute DONE and ERROR interrupts */ 561 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 562 HDMI_IH_MUTE_I2CM_STAT0); 563 564 return ret; 565 } 566 567 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 568 { 569 u32 val; 570 571 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 572 if (msec-- == 0) 573 return false; 574 udelay(1000); 575 } 576 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 577 578 return true; 579 } 580 581 static void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 582 unsigned char addr) 583 { 584 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 585 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 586 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 587 HDMI_PHY_I2CM_DATAO_1_ADDR); 588 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 589 HDMI_PHY_I2CM_DATAO_0_ADDR); 590 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 591 HDMI_PHY_I2CM_OPERATION_ADDR); 592 hdmi_phy_wait_i2c_done(hdmi, 1000); 593 } 594 595 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 596 { 597 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 598 HDMI_PHY_CONF0_PDZ_OFFSET, 599 HDMI_PHY_CONF0_PDZ_MASK); 600 } 601 602 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 603 { 604 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 605 HDMI_PHY_CONF0_ENTMDS_OFFSET, 606 HDMI_PHY_CONF0_ENTMDS_MASK); 607 } 608 609 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 610 { 611 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 612 HDMI_PHY_CONF0_SVSRET_OFFSET, 613 HDMI_PHY_CONF0_SVSRET_MASK); 614 } 615 616 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 617 { 618 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 619 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 620 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 621 } 622 623 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 624 { 625 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 626 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 627 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 628 } 629 630 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 631 { 632 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 633 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 634 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 635 } 636 637 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 638 { 639 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 640 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 641 HDMI_PHY_CONF0_SELDIPIF_MASK); 642 } 643 644 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 645 { 646 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 647 unsigned int i; 648 u16 val; 649 650 if (phy->gen == 1) { 651 dw_hdmi_phy_enable_tmds(hdmi, 0); 652 dw_hdmi_phy_enable_powerdown(hdmi, true); 653 return; 654 } 655 656 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 657 658 /* 659 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 660 * to low power mode. 661 */ 662 for (i = 0; i < 5; ++i) { 663 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 664 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 665 break; 666 667 udelay(2000); 668 } 669 670 if (val & HDMI_PHY_TX_PHY_LOCK) 671 printf("PHY failed to power down\n"); 672 else 673 printf("PHY powered down in %u iterations\n", i); 674 675 dw_hdmi_phy_gen2_pddq(hdmi, 1); 676 } 677 678 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 679 { 680 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 681 unsigned int i; 682 u8 val; 683 684 if (phy->gen == 1) { 685 dw_hdmi_phy_enable_powerdown(hdmi, false); 686 687 /* Toggle TMDS enable. */ 688 dw_hdmi_phy_enable_tmds(hdmi, 0); 689 dw_hdmi_phy_enable_tmds(hdmi, 1); 690 return 0; 691 } 692 693 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 694 dw_hdmi_phy_gen2_pddq(hdmi, 0); 695 696 /* Wait for PHY PLL lock */ 697 for (i = 0; i < 5; ++i) { 698 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 699 if (val) 700 break; 701 702 udelay(2000); 703 } 704 705 if (!val) { 706 printf("PHY PLL failed to lock\n"); 707 return -ETIMEDOUT; 708 } 709 printf("PHY PLL locked %u iterations\n", i); 710 711 return 0; 712 } 713 714 /* 715 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 716 * information the DWC MHL PHY has the same register layout and is thus also 717 * supported by this function. 718 */ 719 static 720 int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 721 const struct dw_hdmi_plat_data *pdata, 722 unsigned long mpixelclock) 723 { 724 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 725 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 726 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 727 unsigned int tmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 728 unsigned int depth = 729 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 730 731 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) && 732 pdata->mpll_cfg_420) 733 mpll_config = pdata->mpll_cfg_420; 734 735 /* PLL/MPLL Cfg - always match on final entry */ 736 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 737 if (mpixelclock <= mpll_config->mpixelclock) 738 break; 739 740 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 741 if (tmdsclock <= curr_ctrl->mpixelclock) 742 break; 743 744 for (; phy_config->mpixelclock != ~0UL; phy_config++) 745 if (tmdsclock <= phy_config->mpixelclock) 746 break; 747 748 if (mpll_config->mpixelclock == ~0UL || 749 curr_ctrl->mpixelclock == ~0UL || 750 phy_config->mpixelclock == ~0UL) 751 return -EINVAL; 752 753 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 754 depth = fls(depth - 8); 755 else 756 depth = 0; 757 if (depth) 758 depth--; 759 760 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].cpce, 761 HDMI_3D_TX_PHY_CPCE_CTRL); 762 763 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].gmp, 764 HDMI_3D_TX_PHY_GMPCTRL); 765 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[depth], 766 HDMI_3D_TX_PHY_CURRCTRL); 767 768 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 769 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 770 HDMI_3D_TX_PHY_MSM_CTRL); 771 772 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 773 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 774 HDMI_3D_TX_PHY_CKSYMTXCTRL); 775 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 776 HDMI_3D_TX_PHY_VLEVCTRL); 777 778 return 0; 779 } 780 781 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 782 { 783 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 784 .name = "DWC HDMI TX PHY", 785 .gen = 1, 786 }, { 787 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 788 .name = "DWC MHL PHY + HEAC PHY", 789 .gen = 2, 790 .has_svsret = true, 791 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 792 }, { 793 .type = DW_HDMI_PHY_DWC_MHL_PHY, 794 .name = "DWC MHL PHY", 795 .gen = 2, 796 .has_svsret = true, 797 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 798 }, { 799 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 800 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 801 .gen = 2, 802 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 803 }, { 804 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 805 .name = "DWC HDMI 3D TX PHY", 806 .gen = 2, 807 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 808 }, { 809 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 810 .name = "DWC HDMI 2.0 TX PHY", 811 .gen = 2, 812 .has_svsret = true, 813 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 814 }, { 815 .type = DW_HDMI_PHY_VENDOR_PHY, 816 .name = "Vendor PHY", 817 } 818 }; 819 820 static int rockchip_dw_hdmi_scrambling_enable(struct dw_hdmi *hdmi, 821 int enable) 822 { 823 u8 stat; 824 825 drm_scdc_readb(&hdmi->adap, SCDC_TMDS_CONFIG, &stat); 826 827 if (stat < 0) { 828 debug("Failed to read tmds config\n"); 829 return false; 830 } 831 832 if (enable == 1) { 833 /* Write on Rx the bit Scrambling_Enable, register 0x20 */ 834 stat |= SCDC_SCRAMBLING_ENABLE; 835 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 836 /* TMDS software reset request */ 837 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 838 HDMI_MC_SWRSTZ); 839 /* Enable/Disable Scrambling */ 840 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); 841 } else { 842 /* Enable/Disable Scrambling */ 843 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); 844 /* TMDS software reset request */ 845 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 846 HDMI_MC_SWRSTZ); 847 /* Write on Rx the bit Scrambling_Enable, register 0x20 */ 848 stat &= ~SCDC_SCRAMBLING_ENABLE; 849 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 850 } 851 852 return 0; 853 } 854 855 static void rockchip_dw_hdmi_scdc_set_tmds_rate(struct dw_hdmi *hdmi) 856 { 857 u8 stat; 858 859 drm_scdc_readb(&hdmi->adap, SCDC_TMDS_CONFIG, &stat); 860 if (hdmi->hdmi_data.video_mode.mtmdsclock > 340000000) 861 stat |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 862 else 863 stat &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 864 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 865 } 866 867 static int hdmi_phy_configure(struct dw_hdmi *hdmi) 868 { 869 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 870 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 871 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 872 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 873 int ret; 874 875 dw_hdmi_phy_power_off(hdmi); 876 877 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ 878 if (hdmi->edid_data.display_info.hdmi.scdc.supported) 879 rockchip_dw_hdmi_scdc_set_tmds_rate(hdmi); 880 881 /* Leave low power consumption mode by asserting SVSRET. */ 882 if (phy->has_svsret) 883 dw_hdmi_phy_enable_svsret(hdmi, 1); 884 885 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 886 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 887 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 888 889 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 890 891 hdmi_phy_test_clear(hdmi, 1); 892 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, 893 HDMI_PHY_I2CM_SLAVE_ADDR); 894 hdmi_phy_test_clear(hdmi, 0); 895 896 /* Write to the PHY as configured by the platform */ 897 if (pdata->configure_phy) 898 ret = pdata->configure_phy(hdmi, pdata, mpixelclock); 899 else 900 ret = phy->configure(hdmi, pdata, mpixelclock); 901 if (ret) { 902 printf("PHY configuration failed (clock %lu)\n", 903 mpixelclock); 904 return ret; 905 } 906 907 /* Wait for resuming transmission of TMDS clock and data */ 908 if (mtmdsclock > 340000000) 909 mdelay(100); 910 911 return dw_hdmi_phy_power_on(hdmi); 912 } 913 914 static int dw_hdmi_phy_init(struct rockchip_connector *conn, struct dw_hdmi *hdmi, 915 void *data) 916 { 917 int i, ret; 918 919 /* HDMI Phy spec says to do the phy initialization sequence twice */ 920 for (i = 0; i < 2; i++) { 921 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 922 dw_hdmi_phy_sel_interface_control(hdmi, 0); 923 ret = hdmi_phy_configure(hdmi); 924 if (ret) 925 return ret; 926 } 927 928 return 0; 929 } 930 931 static void dw_hdmi_phy_disable(struct rockchip_connector *conn, struct dw_hdmi *hdmi, 932 void *data) 933 { 934 dw_hdmi_phy_power_off(hdmi); 935 } 936 937 static enum drm_connector_status 938 dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data) 939 { 940 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 941 connector_status_connected : connector_status_disconnected; 942 } 943 944 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 945 .init = dw_hdmi_phy_init, 946 .disable = dw_hdmi_phy_disable, 947 .read_hpd = dw_hdmi_phy_read_hpd, 948 }; 949 950 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 951 { 952 unsigned int i; 953 u8 phy_type; 954 955 phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID); 956 957 /* 958 * RK3228 and RK3328 phy_type is DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 959 * but it has a vedor phy. 960 */ 961 if (phy_type == DW_HDMI_PHY_VENDOR_PHY || 962 hdmi->dev_type == RK3328_HDMI || 963 hdmi->dev_type == RK3228_HDMI) { 964 /* Vendor PHYs require support from the glue layer. */ 965 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 966 printf( 967 "Vendor HDMI PHY not supported by glue layer\n"); 968 return -ENODEV; 969 } 970 971 hdmi->phy.ops = hdmi->plat_data->phy_ops; 972 hdmi->phy.data = hdmi->plat_data->phy_data; 973 hdmi->phy.name = hdmi->plat_data->phy_name; 974 return 0; 975 } 976 977 /* Synopsys PHYs are handled internally. */ 978 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 979 if (dw_hdmi_phys[i].type == phy_type) { 980 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 981 hdmi->phy.name = dw_hdmi_phys[i].name; 982 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 983 984 if (!dw_hdmi_phys[i].configure && 985 !hdmi->plat_data->configure_phy) { 986 printf("%s requires platform support\n", 987 hdmi->phy.name); 988 return -ENODEV; 989 } 990 991 return 0; 992 } 993 } 994 995 printf("Unsupported HDMI PHY type (%02x)\n", phy_type); 996 return -ENODEV; 997 } 998 999 static unsigned int 1000 hdmi_get_tmdsclock(struct dw_hdmi *hdmi, unsigned long mpixelclock) 1001 { 1002 unsigned int tmdsclock = mpixelclock; 1003 unsigned int depth = 1004 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 1005 1006 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1007 switch (depth) { 1008 case 16: 1009 tmdsclock = mpixelclock * 2; 1010 break; 1011 case 12: 1012 tmdsclock = mpixelclock * 3 / 2; 1013 break; 1014 case 10: 1015 tmdsclock = mpixelclock * 5 / 4; 1016 break; 1017 default: 1018 break; 1019 } 1020 } 1021 1022 return tmdsclock; 1023 } 1024 1025 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1026 const struct drm_display_mode *mode) 1027 { 1028 u8 bytes = 0, inv_val = 0; 1029 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1030 struct drm_hdmi_info *hdmi_info = &hdmi->edid_data.display_info.hdmi; 1031 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1032 unsigned int hdisplay, vdisplay; 1033 1034 vmode->mpixelclock = mode->crtc_clock * 1000; 1035 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == 1036 DRM_MODE_FLAG_3D_FRAME_PACKING) 1037 vmode->mpixelclock *= 2; 1038 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock); 1039 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1040 vmode->mtmdsclock /= 2; 1041 printf("final pixclk = %d tmdsclk = %d\n", 1042 vmode->mpixelclock, vmode->mtmdsclock); 1043 1044 /* Set up HDMI_FC_INVIDCONF 1045 * fc_invidconf.HDCP_keepout must be set (1'b1) 1046 * when activate the scrambler feature. 1047 */ 1048 inv_val = (vmode->mtmdsclock > 340000000 || 1049 (hdmi_info->scdc.scrambling.low_rates && 1050 hdmi->scramble_low_rates) ? 1051 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 1052 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 1053 1054 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 1055 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 1056 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 1057 1058 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 1059 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 1060 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 1061 1062 inv_val |= (vmode->mdataenablepolarity ? 1063 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 1064 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 1065 1066 if (hdmi->vic == 39) 1067 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 1068 else 1069 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1070 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 1071 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 1072 1073 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1074 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 1075 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 1076 1077 inv_val |= hdmi->sink_is_hdmi ? 1078 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 1079 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 1080 1081 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 1082 1083 hdisplay = mode->hdisplay; 1084 hblank = mode->htotal - mode->hdisplay; 1085 h_de_hs = mode->hsync_start - mode->hdisplay; 1086 hsync_len = mode->hsync_end - mode->hsync_start; 1087 1088 /* 1089 * When we're setting a YCbCr420 mode, we need 1090 * to adjust the horizontal timing to suit. 1091 */ 1092 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1093 hdisplay /= 2; 1094 hblank /= 2; 1095 h_de_hs /= 2; 1096 hsync_len /= 2; 1097 } 1098 1099 vdisplay = mode->vdisplay; 1100 vblank = mode->vtotal - mode->vdisplay; 1101 v_de_vs = mode->vsync_start - mode->vdisplay; 1102 vsync_len = mode->vsync_end - mode->vsync_start; 1103 1104 /* 1105 * When we're setting an interlaced mode, we need 1106 * to adjust the vertical timing to suit. 1107 */ 1108 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1109 vdisplay /= 2; 1110 vblank /= 2; 1111 v_de_vs /= 2; 1112 vsync_len /= 2; 1113 } else if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == 1114 DRM_MODE_FLAG_3D_FRAME_PACKING) { 1115 vdisplay += mode->vtotal; 1116 } 1117 1118 /* Scrambling Control */ 1119 if (hdmi_info->scdc.supported) { 1120 if (vmode->mtmdsclock > 340000000 || 1121 (hdmi_info->scdc.scrambling.low_rates && 1122 hdmi->scramble_low_rates)) { 1123 drm_scdc_readb(&hdmi->adap, SCDC_SINK_VERSION, &bytes); 1124 drm_scdc_writeb(&hdmi->adap, SCDC_SOURCE_VERSION, 1125 bytes); 1126 rockchip_dw_hdmi_scrambling_enable(hdmi, 1); 1127 } else { 1128 rockchip_dw_hdmi_scrambling_enable(hdmi, 0); 1129 } 1130 } 1131 1132 /* Set up horizontal active pixel width */ 1133 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1); 1134 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0); 1135 1136 /* Set up vertical active lines */ 1137 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 1138 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 1139 1140 /* Set up horizontal blanking pixel region width */ 1141 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 1142 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 1143 1144 /* Set up vertical blanking pixel region width */ 1145 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 1146 1147 /* Set up HSYNC active edge delay width (in pixel clks) */ 1148 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 1149 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 1150 1151 /* Set up VSYNC active edge delay (in lines) */ 1152 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 1153 1154 /* Set up HSYNC active pulse width (in pixel clks) */ 1155 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 1156 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 1157 1158 /* Set up VSYNC active edge delay (in lines) */ 1159 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 1160 } 1161 1162 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 1163 { 1164 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 1165 unsigned i; 1166 u32 csc_scale = 1; 1167 int enc_out_rgb, enc_in_rgb; 1168 1169 enc_out_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format); 1170 enc_in_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format); 1171 1172 if (is_color_space_conversion(hdmi)) { 1173 if (enc_out_rgb && enc_in_rgb) { 1174 csc_coeff = &csc_coeff_full_to_limited; 1175 csc_scale = 0; 1176 } else if (enc_out_rgb) { 1177 if (hdmi->hdmi_data.enc_out_encoding == 1178 V4L2_YCBCR_ENC_601) 1179 csc_coeff = &csc_coeff_rgb_out_eitu601; 1180 else 1181 csc_coeff = &csc_coeff_rgb_out_eitu709; 1182 } else if (enc_in_rgb) { 1183 if (hdmi->hdmi_data.enc_out_encoding == 1184 V4L2_YCBCR_ENC_601) 1185 csc_coeff = &csc_coeff_rgb_in_eitu601; 1186 else 1187 csc_coeff = &csc_coeff_rgb_in_eitu709; 1188 csc_scale = 0; 1189 } 1190 } 1191 1192 /* The CSC registers are sequential, alternating MSB then LSB */ 1193 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 1194 u16 coeff_a = (*csc_coeff)[0][i]; 1195 u16 coeff_b = (*csc_coeff)[1][i]; 1196 u16 coeff_c = (*csc_coeff)[2][i]; 1197 1198 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 1199 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 1200 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 1201 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 1202 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 1203 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 1204 } 1205 1206 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 1207 HDMI_CSC_SCALE); 1208 } 1209 1210 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 1211 { 1212 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 1213 return 0; 1214 1215 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1216 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1217 return 1; 1218 1219 return 0; 1220 } 1221 1222 static void hdmi_video_csc(struct dw_hdmi *hdmi) 1223 { 1224 int color_depth = 0; 1225 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 1226 int decimation = 0; 1227 1228 /* YCC422 interpolation to 444 mode */ 1229 if (is_color_space_interpolation(hdmi)) 1230 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 1231 else if (is_color_space_decimation(hdmi)) 1232 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 1233 1234 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 1235 case 8: 1236 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 1237 break; 1238 case 10: 1239 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 1240 break; 1241 case 12: 1242 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 1243 break; 1244 case 16: 1245 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 1246 break; 1247 1248 default: 1249 return; 1250 } 1251 1252 /* Configure the CSC registers */ 1253 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 1254 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 1255 HDMI_CSC_SCALE); 1256 1257 dw_hdmi_update_csc_coeffs(hdmi); 1258 } 1259 1260 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 1261 { 1262 u8 clkdis; 1263 1264 /* control period minimum duration */ 1265 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 1266 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 1267 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 1268 1269 /* Set to fill TMDS data channels */ 1270 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 1271 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 1272 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 1273 1274 /* Enable pixel clock and tmds data path */ 1275 clkdis = 0x7F; 1276 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 1277 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1278 1279 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1280 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1281 1282 /* Enable csc path */ 1283 if (is_color_space_conversion(hdmi)) { 1284 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 1285 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1286 } 1287 1288 /* Enable pixel repetition path */ 1289 if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) { 1290 clkdis &= ~HDMI_MC_CLKDIS_PREPCLK_DISABLE; 1291 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1292 } 1293 1294 /* Enable color space conversion if needed */ 1295 if (is_color_space_conversion(hdmi)) 1296 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 1297 HDMI_MC_FLOWCTRL); 1298 else 1299 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 1300 HDMI_MC_FLOWCTRL); 1301 } 1302 1303 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 1304 { 1305 unsigned int count; 1306 unsigned int i; 1307 u8 val; 1308 1309 /* 1310 * Under some circumstances the Frame Composer arithmetic unit can miss 1311 * an FC register write due to being busy processing the previous one. 1312 * The issue can be worked around by issuing a TMDS software reset and 1313 * then write one of the FC registers several times. 1314 * 1315 * The number of iterations matters and depends on the HDMI TX revision 1316 * (and possibly on the platform). So far only i.MX6Q (v1.30a) and 1317 * i.MX6DL (v1.31a) have been identified as needing the workaround, with 1318 * 4 and 1 iterations respectively. 1319 */ 1320 1321 switch (hdmi->version) { 1322 case 0x130a: 1323 count = 4; 1324 break; 1325 case 0x131a: 1326 case 0x200a: 1327 case 0x201a: 1328 case 0x211a: 1329 count = 1; 1330 break; 1331 default: 1332 return; 1333 } 1334 1335 /* TMDS software reset */ 1336 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 1337 1338 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 1339 for (i = 0; i < count; i++) 1340 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 1341 } 1342 1343 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 1344 { 1345 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 1346 HDMI_IH_MUTE_FC_STAT2); 1347 } 1348 1349 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 1350 { 1351 unsigned int color_depth = 0; 1352 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 1353 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 1354 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1355 u8 val, vp_conf; 1356 1357 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1358 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) || 1359 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1360 switch (hdmi_bus_fmt_color_depth( 1361 hdmi->hdmi_data.enc_out_bus_format)) { 1362 case 8: 1363 color_depth = 0; 1364 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1365 break; 1366 case 10: 1367 color_depth = 5; 1368 break; 1369 case 12: 1370 color_depth = 6; 1371 break; 1372 case 16: 1373 color_depth = 7; 1374 break; 1375 default: 1376 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1377 } 1378 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1379 switch (hdmi_bus_fmt_color_depth( 1380 hdmi->hdmi_data.enc_out_bus_format)) { 1381 case 0: 1382 case 8: 1383 remap_size = HDMI_VP_REMAP_YCC422_16bit; 1384 break; 1385 case 10: 1386 remap_size = HDMI_VP_REMAP_YCC422_20bit; 1387 break; 1388 case 12: 1389 remap_size = HDMI_VP_REMAP_YCC422_24bit; 1390 break; 1391 1392 default: 1393 return; 1394 } 1395 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 1396 } else { 1397 return; 1398 } 1399 1400 /* set the packetizer registers */ 1401 val = (color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 1402 HDMI_VP_PR_CD_COLOR_DEPTH_MASK; 1403 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 1404 1405 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 1406 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 1407 1408 /* Data from pixel repeater block */ 1409 if (hdmi_data->pix_repet_factor > 0) { 1410 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 1411 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 1412 } else { /* data from packetizer block */ 1413 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 1414 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 1415 } 1416 1417 hdmi_modb(hdmi, vp_conf, 1418 HDMI_VP_CONF_PR_EN_MASK | 1419 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 1420 1421 if ((color_depth == 5 && hdmi->previous_mode.htotal % 4) || 1422 (color_depth == 6 && hdmi->previous_mode.htotal % 2)) 1423 hdmi_modb(hdmi, 0, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, 1424 HDMI_VP_STUFF); 1425 else 1426 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 1427 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 1428 1429 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 1430 1431 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 1432 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1433 HDMI_VP_CONF_PP_EN_ENABLE | 1434 HDMI_VP_CONF_YCC422_EN_DISABLE; 1435 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 1436 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1437 HDMI_VP_CONF_PP_EN_DISABLE | 1438 HDMI_VP_CONF_YCC422_EN_ENABLE; 1439 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 1440 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 1441 HDMI_VP_CONF_PP_EN_DISABLE | 1442 HDMI_VP_CONF_YCC422_EN_DISABLE; 1443 } else { 1444 return; 1445 } 1446 1447 hdmi_modb(hdmi, vp_conf, 1448 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 1449 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 1450 1451 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 1452 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 1453 HDMI_VP_STUFF_PP_STUFFING_MASK | 1454 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 1455 1456 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 1457 HDMI_VP_CONF); 1458 } 1459 1460 static void hdmi_video_sample(struct dw_hdmi *hdmi) 1461 { 1462 int color_format = 0; 1463 u8 val; 1464 1465 switch (hdmi->hdmi_data.enc_in_bus_format) { 1466 case MEDIA_BUS_FMT_RGB888_1X24: 1467 color_format = 0x01; 1468 break; 1469 case MEDIA_BUS_FMT_RGB101010_1X30: 1470 color_format = 0x03; 1471 break; 1472 case MEDIA_BUS_FMT_RGB121212_1X36: 1473 color_format = 0x05; 1474 break; 1475 case MEDIA_BUS_FMT_RGB161616_1X48: 1476 color_format = 0x07; 1477 break; 1478 1479 case MEDIA_BUS_FMT_YUV8_1X24: 1480 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1481 color_format = 0x09; 1482 break; 1483 case MEDIA_BUS_FMT_YUV10_1X30: 1484 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1485 color_format = 0x0B; 1486 break; 1487 case MEDIA_BUS_FMT_YUV12_1X36: 1488 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 1489 color_format = 0x0D; 1490 break; 1491 case MEDIA_BUS_FMT_YUV16_1X48: 1492 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 1493 color_format = 0x0F; 1494 break; 1495 1496 case MEDIA_BUS_FMT_UYVY8_1X16: 1497 color_format = 0x16; 1498 break; 1499 case MEDIA_BUS_FMT_UYVY10_1X20: 1500 color_format = 0x14; 1501 break; 1502 case MEDIA_BUS_FMT_UYVY12_1X24: 1503 color_format = 0x12; 1504 break; 1505 1506 default: 1507 return; 1508 } 1509 1510 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 1511 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 1512 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 1513 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 1514 1515 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 1516 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 1517 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 1518 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 1519 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 1520 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 1521 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 1522 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 1523 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 1524 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 1525 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 1526 } 1527 1528 static void dw_hdmi_disable(struct rockchip_connector *conn, struct dw_hdmi *hdmi, 1529 struct display_state *state) 1530 { 1531 if (hdmi->phy.enabled) { 1532 hdmi->phy.ops->disable(conn, hdmi, state); 1533 hdmi->phy.enabled = false; 1534 } 1535 } 1536 1537 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1538 { 1539 struct hdmi_avi_infoframe frame; 1540 u8 val; 1541 bool is_hdmi2 = false; 1542 enum hdmi_quantization_range rgb_quant_range = 1543 hdmi->hdmi_data.quant_range; 1544 1545 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) || 1546 hdmi->edid_data.display_info.hdmi.scdc.supported) 1547 is_hdmi2 = true; 1548 /* Initialise info frame from DRM mode */ 1549 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2); 1550 1551 /* 1552 * Ignore monitor selectable quantization, use quantization set 1553 * by the user 1554 */ 1555 drm_hdmi_avi_infoframe_quant_range(&frame, mode, rgb_quant_range, 1556 true); 1557 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1558 frame.colorspace = HDMI_COLORSPACE_YUV444; 1559 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1560 frame.colorspace = HDMI_COLORSPACE_YUV422; 1561 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1562 frame.colorspace = HDMI_COLORSPACE_YUV420; 1563 else 1564 frame.colorspace = HDMI_COLORSPACE_RGB; 1565 1566 /* Set up colorimetry */ 1567 switch (hdmi->hdmi_data.enc_out_encoding) { 1568 case V4L2_YCBCR_ENC_601: 1569 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1570 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1571 else 1572 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1573 frame.extended_colorimetry = 1574 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1575 break; 1576 case V4L2_YCBCR_ENC_709: 1577 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1578 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1579 else 1580 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1581 frame.extended_colorimetry = 1582 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1583 break; 1584 default: /* Carries no data */ 1585 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1586 frame.extended_colorimetry = 1587 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1588 break; 1589 } 1590 1591 frame.scan_mode = HDMI_SCAN_MODE_NONE; 1592 1593 /* 1594 * The Designware IP uses a different byte format from standard 1595 * AVI info frames, though generally the bits are in the correct 1596 * bytes. 1597 */ 1598 1599 /* 1600 * AVI data byte 1 differences: Colorspace in bits 0,1,7 rather than 1601 * 5,6,7, active aspect present in bit 6 rather than 4. 1602 */ 1603 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 0x3); 1604 if (frame.active_aspect & 15) 1605 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1606 if (frame.top_bar || frame.bottom_bar) 1607 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1608 if (frame.left_bar || frame.right_bar) 1609 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1610 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1611 1612 /* AVI data byte 2 differences: none */ 1613 val = ((frame.colorimetry & 0x3) << 6) | 1614 ((frame.picture_aspect & 0x3) << 4) | 1615 (frame.active_aspect & 0xf); 1616 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1617 1618 /* AVI data byte 3 differences: none */ 1619 val = ((frame.extended_colorimetry & 0x7) << 4) | 1620 ((frame.quantization_range & 0x3) << 2) | 1621 (frame.nups & 0x3); 1622 if (frame.itc) 1623 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1624 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1625 1626 /* AVI data byte 4 differences: none */ 1627 val = frame.video_code & 0x7f; 1628 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1629 1630 /* AVI Data Byte 5- set up input and output pixel repetition */ 1631 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1632 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1633 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1634 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1635 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1636 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1637 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1638 1639 /* 1640 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1641 * ycc range in bits 2,3 rather than 6,7 1642 */ 1643 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1644 (frame.content_type & 0x3); 1645 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1646 1647 /* AVI Data Bytes 6-13 */ 1648 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1649 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1650 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1651 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1652 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1653 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1654 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1655 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1656 } 1657 1658 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1659 struct drm_display_mode *mode) 1660 { 1661 struct hdmi_vendor_infoframe frame; 1662 u8 buffer[10]; 1663 ssize_t err; 1664 1665 /* Disable HDMI vendor specific infoframe send */ 1666 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1667 HDMI_FC_DATAUTO0_VSD_MASK); 1668 1669 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode); 1670 if (err < 0) 1671 /* 1672 * Going into that statement does not means vendor infoframe 1673 * fails. It just informed us that vendor infoframe is not 1674 * needed for the selected mode. Only 4k or stereoscopic 3D 1675 * mode requires vendor infoframe. So just simply return. 1676 */ 1677 return; 1678 1679 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1680 if (err < 0) { 1681 printf("Failed to pack vendor infoframe: %zd\n", err); 1682 return; 1683 } 1684 1685 /* Set the length of HDMI vendor specific InfoFrame payload */ 1686 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1687 1688 /* Set 24bit IEEE Registration Identifier */ 1689 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1690 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1691 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1692 1693 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1694 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1695 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1696 1697 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1698 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1699 1700 /* Packet frame interpolation */ 1701 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1702 1703 /* Auto packets per frame and line spacing */ 1704 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1705 1706 /* Configures the Frame Composer On RDRB mode */ 1707 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1708 HDMI_FC_DATAUTO0_VSD_MASK); 1709 } 1710 1711 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 1712 unsigned int n) 1713 { 1714 /* Must be set/cleared first */ 1715 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 1716 1717 /* nshift factor = 0 */ 1718 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 1719 1720 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 1721 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 1722 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 1723 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 1724 1725 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 1726 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 1727 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 1728 } 1729 1730 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi, 1731 unsigned long pixel_clk, 1732 unsigned long freq) 1733 { 1734 const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data; 1735 const struct dw_hdmi_audio_tmds_n *tmds_n = NULL; 1736 int i; 1737 1738 if (plat_data->tmds_n_table) { 1739 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) { 1740 if (pixel_clk == plat_data->tmds_n_table[i].tmds) { 1741 tmds_n = &plat_data->tmds_n_table[i]; 1742 break; 1743 } 1744 } 1745 } 1746 1747 if (!tmds_n) { 1748 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) { 1749 if (pixel_clk == common_tmds_n_table[i].tmds) { 1750 tmds_n = &common_tmds_n_table[i]; 1751 break; 1752 } 1753 } 1754 } 1755 1756 if (!tmds_n) 1757 return -ENOENT; 1758 1759 switch (freq) { 1760 case 32000: 1761 return tmds_n->n_32k; 1762 case 44100: 1763 case 88200: 1764 case 176400: 1765 return (freq / 44100) * tmds_n->n_44k1; 1766 case 48000: 1767 case 96000: 1768 case 192000: 1769 return (freq / 48000) * tmds_n->n_48k; 1770 default: 1771 return -ENOENT; 1772 } 1773 } 1774 1775 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n, 1776 unsigned int pixel_clk) 1777 { 1778 u64 final, diff; 1779 u64 cts; 1780 1781 final = (u64)pixel_clk * n; 1782 1783 cts = final; 1784 do_div(cts, 128 * freq); 1785 1786 diff = final - (u64)cts * (128 * freq); 1787 1788 return diff; 1789 } 1790 1791 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi, 1792 unsigned long pixel_clk, 1793 unsigned long freq) 1794 { 1795 unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500); 1796 unsigned int max_n = (128 * freq) / 300; 1797 unsigned int ideal_n = (128 * freq) / 1000; 1798 unsigned int best_n_distance = ideal_n; 1799 unsigned int best_n = 0; 1800 u64 best_diff = U64_MAX; 1801 int n; 1802 1803 /* If the ideal N could satisfy the audio math, then just take it */ 1804 if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0) 1805 return ideal_n; 1806 1807 for (n = min_n; n <= max_n; n++) { 1808 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk); 1809 1810 if (diff < best_diff || (diff == best_diff && 1811 abs(n - ideal_n) < best_n_distance)) { 1812 best_n = n; 1813 best_diff = diff; 1814 best_n_distance = abs(best_n - ideal_n); 1815 } 1816 1817 /* 1818 * The best N already satisfy the audio math, and also be 1819 * the closest value to ideal N, so just cut the loop. 1820 */ 1821 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance)) 1822 break; 1823 } 1824 1825 return best_n; 1826 } 1827 1828 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk, 1829 unsigned long sample_rate) 1830 { 1831 int n; 1832 1833 n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate); 1834 if (n > 0) 1835 return n; 1836 1837 printf("Rate %lu missing; compute N dynamically\n", 1838 pixel_clk); 1839 1840 return hdmi_compute_n(hdmi, pixel_clk, sample_rate); 1841 } 1842 1843 static 1844 void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, unsigned long pixel_clk, 1845 unsigned int sample_rate) 1846 { 1847 unsigned long ftdms = pixel_clk; 1848 unsigned int n, cts; 1849 u64 tmp; 1850 1851 n = hdmi_find_n(hdmi, pixel_clk, sample_rate); 1852 1853 /* 1854 * Compute the CTS value from the N value. Note that CTS and N 1855 * can be up to 20 bits in total, so we need 64-bit math. Also 1856 * note that our TDMS clock is not fully accurate; it is accurate 1857 * to kHz. This can introduce an unnecessary remainder in the 1858 * calculation below, so we don't try to warn about that. 1859 */ 1860 tmp = (u64)ftdms * n; 1861 do_div(tmp, 128 * sample_rate); 1862 cts = tmp; 1863 1864 printf("%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", __func__, 1865 sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000, n, cts); 1866 1867 hdmi->audio_n = n; 1868 hdmi->audio_cts = cts; 1869 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 1870 } 1871 1872 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 1873 { 1874 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 1875 hdmi->sample_rate); 1876 } 1877 1878 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi) 1879 { 1880 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS); 1881 } 1882 1883 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 1884 { 1885 hdmi->sample_rate = rate; 1886 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 1887 hdmi->sample_rate); 1888 } 1889 1890 static int dw_hdmi_hdcp_load_key(struct dw_hdmi *hdmi) 1891 { 1892 int i, j, ret, val; 1893 struct hdcp_keys *hdcp_keys; 1894 1895 val = sizeof(*hdcp_keys); 1896 hdcp_keys = malloc(val); 1897 if (!hdcp_keys) 1898 return -ENOMEM; 1899 1900 memset(hdcp_keys, 0, val); 1901 1902 ret = vendor_storage_read(HDMI_HDCP1X_ID, hdcp_keys, val); 1903 if (ret < val) { 1904 printf("HDCP: read size %d\n", ret); 1905 free(hdcp_keys); 1906 return -EINVAL; 1907 } 1908 1909 if (hdcp_keys->KSV[0] == 0x00 && 1910 hdcp_keys->KSV[1] == 0x00 && 1911 hdcp_keys->KSV[2] == 0x00 && 1912 hdcp_keys->KSV[3] == 0x00 && 1913 hdcp_keys->KSV[4] == 0x00) { 1914 printf("HDCP: Invalid hdcp key\n"); 1915 free(hdcp_keys); 1916 return -EINVAL; 1917 } 1918 1919 /* Disable decryption logic */ 1920 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_RMCTL); 1921 /* Poll untile DPK write is allowed */ 1922 do { 1923 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1924 } while ((val & DPK_WR_OK_STS) == 0); 1925 1926 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_DPK6); 1927 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_DPK5); 1928 1929 /* The useful data in ksv should be 5 byte */ 1930 for (i = 4; i >= 0; i--) 1931 hdmi_writeb(hdmi, hdcp_keys->KSV[i], HDMI_HDCPREG_DPK0 + i); 1932 /* Poll untile DPK write is allowed */ 1933 do { 1934 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1935 } while ((val & DPK_WR_OK_STS) == 0); 1936 1937 /* Enable decryption logic */ 1938 hdmi_writeb(hdmi, 1, HDMI_HDCPREG_RMCTL); 1939 hdmi_writeb(hdmi, hdcp_keys->seeds[0], HDMI_HDCPREG_SEED1); 1940 hdmi_writeb(hdmi, hdcp_keys->seeds[1], HDMI_HDCPREG_SEED0); 1941 1942 /* Write encrypt device private key */ 1943 for (i = 0; i < DW_HDMI_HDCP_DPK_LEN - 6; i += 7) { 1944 for (j = 6; j >= 0; j--) 1945 hdmi_writeb(hdmi, hdcp_keys->devicekey[i + j], 1946 HDMI_HDCPREG_DPK0 + j); 1947 do { 1948 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1949 } while ((val & DPK_WR_OK_STS) == 0); 1950 } 1951 1952 free(hdcp_keys); 1953 return 0; 1954 } 1955 1956 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi, 1957 const struct drm_display_mode *mode) 1958 { 1959 u8 vsync_pol, hsync_pol, data_pol, hdmi_dvi; 1960 1961 if (!hdmi->hdcp1x_enable) 1962 return; 1963 1964 /* Configure the video polarity */ 1965 vsync_pol = mode->flags & DRM_MODE_FLAG_PVSYNC ? 1966 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH : 1967 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW; 1968 hsync_pol = mode->flags & DRM_MODE_FLAG_PHSYNC ? 1969 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH : 1970 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW; 1971 data_pol = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1972 hdmi_modb(hdmi, vsync_pol | hsync_pol | data_pol, 1973 HDMI_A_VIDPOLCFG_VSYNCPOL_MASK | 1974 HDMI_A_VIDPOLCFG_HSYNCPOL_MASK | 1975 HDMI_A_VIDPOLCFG_DATAENPOL_MASK, 1976 HDMI_A_VIDPOLCFG); 1977 1978 /* Config the display mode */ 1979 hdmi_dvi = hdmi->sink_is_hdmi ? HDMI_A_HDCPCFG0_HDMIDVI_HDMI : 1980 HDMI_A_HDCPCFG0_HDMIDVI_DVI; 1981 hdmi_modb(hdmi, hdmi_dvi, HDMI_A_HDCPCFG0_HDMIDVI_MASK, 1982 HDMI_A_HDCPCFG0); 1983 1984 if (!(hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS) & 0x3f)) 1985 dw_hdmi_hdcp_load_key(hdmi); 1986 1987 hdmi_modb(hdmi, HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE, 1988 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK, 1989 HDMI_FC_INVIDCONF); 1990 1991 if (hdmi_readb(hdmi, HDMI_CONFIG1_ID) & HDMI_A_HDCP22_MASK) { 1992 hdmi_modb(hdmi, HDMI_HDCP2_OVR_ENABLE | 1993 HDMI_HDCP2_FORCE_DISABLE, 1994 HDMI_HDCP2_OVR_EN_MASK | 1995 HDMI_HDCP2_FORCE_MASK, 1996 HDMI_HDCP2REG_CTRL); 1997 hdmi_writeb(hdmi, 0xff, HDMI_HDCP2REG_MASK); 1998 hdmi_writeb(hdmi, 0xff, HDMI_HDCP2REG_MUTE); 1999 } 2000 2001 hdmi_writeb(hdmi, 0x40, HDMI_A_OESSWCFG); 2002 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE | 2003 HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE | 2004 HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE, 2005 HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK | 2006 HDMI_A_HDCPCFG0_EN11FEATURE_MASK | 2007 HDMI_A_HDCPCFG0_SYNCRICHECK_MASK, HDMI_A_HDCPCFG0); 2008 2009 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE | 2010 HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE, 2011 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK | 2012 HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK, HDMI_A_HDCPCFG1); 2013 2014 /* Reset HDCP Engine */ 2015 if (hdmi_readb(hdmi, HDMI_MC_CLKDIS) & HDMI_MC_CLKDIS_HDCPCLK_MASK) { 2016 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_SWRESET_ASSERT, 2017 HDMI_A_HDCPCFG1_SWRESET_MASK, HDMI_A_HDCPCFG1); 2018 } 2019 2020 hdmi_writeb(hdmi, 0x00, HDMI_A_APIINTMSK); 2021 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_ENABLE, 2022 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 2023 2024 hdmi_modb(hdmi, HDMI_MC_CLKDIS_HDCPCLK_ENABLE, 2025 HDMI_MC_CLKDIS_HDCPCLK_MASK, HDMI_MC_CLKDIS); 2026 2027 printf("%s success\n", __func__); 2028 } 2029 2030 static int dw_hdmi_setup(struct dw_hdmi *hdmi, 2031 struct rockchip_connector *conn, 2032 struct drm_display_mode *mode, 2033 struct display_state *state) 2034 { 2035 int ret; 2036 void *data = hdmi->plat_data->phy_data; 2037 2038 hdmi_disable_overflow_interrupts(hdmi); 2039 if (!hdmi->vic) 2040 printf("Non-CEA mode used in HDMI\n"); 2041 else 2042 printf("CEA mode used vic=%d\n", hdmi->vic); 2043 2044 if (hdmi->plat_data->get_enc_out_encoding) 2045 hdmi->hdmi_data.enc_out_encoding = 2046 hdmi->plat_data->get_enc_out_encoding(data); 2047 else if (hdmi->vic == 6 || hdmi->vic == 7 || 2048 hdmi->vic == 21 || hdmi->vic == 22 || 2049 hdmi->vic == 2 || hdmi->vic == 3 || 2050 hdmi->vic == 17 || hdmi->vic == 18) 2051 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 2052 else 2053 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 2054 2055 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2056 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1; 2057 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1; 2058 } else { 2059 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 2060 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 2061 } 2062 2063 /* TOFIX: Get input encoding from plat data or fallback to none */ 2064 if (hdmi->plat_data->get_enc_in_encoding) 2065 hdmi->hdmi_data.enc_in_encoding = 2066 hdmi->plat_data->get_enc_in_encoding(data); 2067 else if (hdmi->plat_data->input_bus_encoding) 2068 hdmi->hdmi_data.enc_in_encoding = 2069 hdmi->plat_data->input_bus_encoding; 2070 else 2071 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 2072 2073 if (hdmi->plat_data->get_quant_range) 2074 hdmi->hdmi_data.quant_range = 2075 hdmi->plat_data->get_quant_range(data); 2076 else 2077 hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 2078 2079 /* 2080 * According to the dw-hdmi specification 6.4.2 2081 * vp_pr_cd[3:0]: 2082 * 0000b: No pixel repetition (pixel sent only once) 2083 * 0001b: Pixel sent two times (pixel repeated once) 2084 */ 2085 hdmi->hdmi_data.pix_repet_factor = 2086 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0; 2087 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 2088 2089 /* HDMI Initialization Step B.1 */ 2090 hdmi_av_composer(hdmi, mode); 2091 2092 /* HDMI Initialization Step B.2 */ 2093 ret = hdmi->phy.ops->init(conn, hdmi, state); 2094 if (ret) 2095 return ret; 2096 hdmi->phy.enabled = true; 2097 2098 /* HDMI Initializateion Step B.3 */ 2099 dw_hdmi_enable_video_path(hdmi); 2100 2101 /* HDMI Initialization Step E - Configure audio */ 2102 if (hdmi->sink_has_audio) { 2103 printf("sink has audio support\n"); 2104 hdmi_clk_regenerator_update_pixel_clock(hdmi); 2105 hdmi_enable_audio_clk(hdmi); 2106 } 2107 2108 /* not for DVI mode */ 2109 if (hdmi->sink_is_hdmi) { 2110 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 2111 hdmi_config_AVI(hdmi, mode); 2112 hdmi_config_vendor_specific_infoframe(hdmi, mode); 2113 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_HDMIDVI_HDMI, 2114 HDMI_A_HDCPCFG0_HDMIDVI_MASK, 2115 HDMI_A_HDCPCFG0); 2116 } else { 2117 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_HDMIDVI_DVI, 2118 HDMI_A_HDCPCFG0_HDMIDVI_MASK, 2119 HDMI_A_HDCPCFG0); 2120 printf("%s DVI mode\n", __func__); 2121 } 2122 2123 hdmi_video_packetize(hdmi); 2124 hdmi_video_csc(hdmi); 2125 hdmi_video_sample(hdmi); 2126 hdmi_tx_hdcp_config(hdmi, mode); 2127 dw_hdmi_clear_overflow(hdmi); 2128 2129 return 0; 2130 } 2131 2132 int dw_hdmi_detect_hotplug(struct dw_hdmi *hdmi, 2133 struct display_state *state) 2134 { 2135 return hdmi->phy.ops->read_hpd(hdmi, state); 2136 } 2137 2138 static int dw_hdmi_set_reg_wr(struct dw_hdmi *hdmi) 2139 { 2140 switch (hdmi->io_width) { 2141 case 4: 2142 hdmi->write = dw_hdmi_writel; 2143 hdmi->read = dw_hdmi_readl; 2144 break; 2145 case 1: 2146 hdmi->write = dw_hdmi_writeb; 2147 hdmi->read = dw_hdmi_readb; 2148 break; 2149 default: 2150 printf("reg-io-width must be 1 or 4\n"); 2151 return -EINVAL; 2152 } 2153 2154 return 0; 2155 } 2156 2157 static void initialize_hdmi_mutes(struct dw_hdmi *hdmi) 2158 { 2159 /*mute unnecessary interrupt, only enable hpd */ 2160 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 2161 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 2162 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 2163 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 2164 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 2165 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 2166 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 2167 hdmi_writeb(hdmi, 0xfe, HDMI_IH_MUTE_PHY_STAT0); 2168 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 2169 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 2170 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 2171 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 2172 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 2173 hdmi_writeb(hdmi, 0xf1, HDMI_PHY_MASK0); 2174 2175 /*Force output black*/ 2176 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS2); 2177 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS1); 2178 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS0); 2179 } 2180 2181 static void dw_hdmi_dev_init(struct dw_hdmi *hdmi) 2182 { 2183 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 2184 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 2185 2186 initialize_hdmi_mutes(hdmi); 2187 } 2188 2189 static void dw_hdmi_i2c_set_divs(struct dw_hdmi *hdmi) 2190 { 2191 unsigned long low_ns, high_ns; 2192 unsigned long div_low, div_high; 2193 2194 /* Standard-mode */ 2195 if (hdmi->i2c->scl_high_ns < 4000) 2196 high_ns = 4708; 2197 else 2198 high_ns = hdmi->i2c->scl_high_ns; 2199 2200 if (hdmi->i2c->scl_low_ns < 4700) 2201 low_ns = 4916; 2202 else 2203 low_ns = hdmi->i2c->scl_low_ns; 2204 2205 div_low = (24000 * low_ns) / 1000000; 2206 if ((24000 * low_ns) % 1000000) 2207 div_low++; 2208 2209 div_high = (24000 * high_ns) / 1000000; 2210 if ((24000 * high_ns) % 1000000) 2211 div_high++; 2212 2213 /* Maximum divider supported by hw is 0xffff */ 2214 if (div_low > 0xffff) 2215 div_low = 0xffff; 2216 2217 if (div_high > 0xffff) 2218 div_high = 0xffff; 2219 2220 hdmi_writeb(hdmi, div_high & 0xff, HDMI_I2CM_SS_SCL_HCNT_0_ADDR); 2221 hdmi_writeb(hdmi, (div_high >> 8) & 0xff, 2222 HDMI_I2CM_SS_SCL_HCNT_1_ADDR); 2223 hdmi_writeb(hdmi, div_low & 0xff, HDMI_I2CM_SS_SCL_LCNT_0_ADDR); 2224 hdmi_writeb(hdmi, (div_low >> 8) & 0xff, 2225 HDMI_I2CM_SS_SCL_LCNT_1_ADDR); 2226 } 2227 2228 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 2229 { 2230 /* Software reset */ 2231 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 2232 2233 /* Set Standard Mode speed */ 2234 hdmi_modb(hdmi, HDMI_I2CM_DIV_STD_MODE, 2235 HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV); 2236 2237 /* Set done, not acknowledged and arbitration interrupt polarities */ 2238 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 2239 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 2240 HDMI_I2CM_CTLINT); 2241 2242 /* Clear DONE and ERROR interrupts */ 2243 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 2244 HDMI_IH_I2CM_STAT0); 2245 2246 /* Mute DONE and ERROR interrupts */ 2247 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 2248 HDMI_IH_MUTE_I2CM_STAT0); 2249 2250 /* set SDA high level holding time */ 2251 hdmi_writeb(hdmi, 0x48, HDMI_I2CM_SDA_HOLD); 2252 2253 dw_hdmi_i2c_set_divs(hdmi); 2254 } 2255 2256 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 2257 { 2258 hdmi->audio_enable = true; 2259 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 2260 } 2261 2262 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 2263 { 2264 hdmi->audio_enable = false; 2265 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 2266 } 2267 2268 int rockchip_dw_hdmi_init(struct rockchip_connector *conn, struct display_state *state) 2269 { 2270 struct connector_state *conn_state = &state->conn_state; 2271 const struct dw_hdmi_plat_data *pdata = 2272 (const struct dw_hdmi_plat_data *)dev_get_driver_data(conn->dev); 2273 struct crtc_state *crtc_state = &state->crtc_state; 2274 struct dw_hdmi *hdmi; 2275 struct drm_display_mode *mode_buf; 2276 ofnode hdmi_node = conn->dev->node; 2277 u32 val; 2278 struct device_node *ddc_node; 2279 2280 hdmi = malloc(sizeof(struct dw_hdmi)); 2281 if (!hdmi) 2282 return -ENOMEM; 2283 2284 memset(hdmi, 0, sizeof(struct dw_hdmi)); 2285 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 2286 if (!mode_buf) 2287 return -ENOMEM; 2288 hdmi->id = of_alias_get_id(ofnode_to_np(hdmi_node), "hdmi"); 2289 if (hdmi->id < 0) 2290 hdmi->id = 0; 2291 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, hdmi->id); 2292 2293 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 2294 2295 hdmi->regs = dev_read_addr_ptr(conn->dev); 2296 hdmi->io_width = ofnode_read_s32_default(hdmi_node, "reg-io-width", -1); 2297 2298 if (ofnode_read_bool(hdmi_node, "scramble-low-rates")) 2299 hdmi->scramble_low_rates = true; 2300 2301 if (ofnode_read_bool(hdmi_node, "hdcp1x-enable")) 2302 hdmi->hdcp1x_enable = true; 2303 else 2304 hdmi->hdcp1x_enable = false; 2305 2306 if (ofnode_read_bool(hdmi_node, "force_output_bus_format_RGB") || 2307 ofnode_read_bool(hdmi_node, "unsupported-yuv-input")) 2308 hdmi->output_bus_format_rgb = true; 2309 else 2310 hdmi->output_bus_format_rgb = false; 2311 2312 ddc_node = of_parse_phandle(ofnode_to_np(hdmi_node), "ddc-i2c-bus", 0); 2313 if (ddc_node) { 2314 uclass_get_device_by_ofnode(UCLASS_I2C, np_to_ofnode(ddc_node), 2315 &hdmi->adap.i2c_bus); 2316 if (hdmi->adap.i2c_bus) 2317 hdmi->adap.ops = i2c_get_ops(hdmi->adap.i2c_bus); 2318 } 2319 2320 hdmi->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 2321 if (hdmi->grf <= 0) { 2322 printf("%s: Get syscon grf failed (ret=%p)\n", 2323 __func__, hdmi->grf); 2324 return -ENXIO; 2325 } 2326 2327 dw_hdmi_set_reg_wr(hdmi); 2328 2329 if (pdata->grf_vop_sel_reg) { 2330 if (crtc_state->crtc_id) 2331 val = ((1 << pdata->vop_sel_bit) | 2332 (1 << (16 + pdata->vop_sel_bit))); 2333 else 2334 val = ((0 << pdata->vop_sel_bit) | 2335 (1 << (16 + pdata->vop_sel_bit))); 2336 writel(val, hdmi->grf + pdata->grf_vop_sel_reg); 2337 } 2338 2339 hdmi->i2c = malloc(sizeof(struct dw_hdmi_i2c)); 2340 if (!hdmi->i2c) 2341 return -ENOMEM; 2342 hdmi->adap.ddc_xfer = dw_hdmi_i2c_xfer; 2343 2344 /* 2345 * Read high and low time from device tree. If not available use 2346 * the default timing scl clock rate is about 99.6KHz. 2347 */ 2348 hdmi->i2c->scl_high_ns = 2349 ofnode_read_s32_default(hdmi_node, 2350 "ddc-i2c-scl-high-time-ns", 4708); 2351 hdmi->i2c->scl_low_ns = 2352 ofnode_read_s32_default(hdmi_node, 2353 "ddc-i2c-scl-low-time-ns", 4916); 2354 2355 dw_hdmi_i2c_init(hdmi); 2356 conn_state->output_if |= VOP_OUTPUT_IF_HDMI0; 2357 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 2358 2359 hdmi->dev_type = pdata->dev_type; 2360 hdmi->plat_data = pdata; 2361 hdmi->edid_data.mode_buf = mode_buf; 2362 hdmi->sample_rate = 48000; 2363 2364 conn->data = hdmi; 2365 dw_hdmi_set_iomux(hdmi->grf, hdmi->dev_type); 2366 dw_hdmi_detect_phy(hdmi); 2367 dw_hdmi_dev_init(hdmi); 2368 2369 return 0; 2370 } 2371 2372 void rockchip_dw_hdmi_deinit(struct rockchip_connector *conn, struct display_state *state) 2373 { 2374 struct dw_hdmi *hdmi = conn->data; 2375 2376 if (hdmi->i2c) 2377 free(hdmi->i2c); 2378 if (hdmi->edid_data.mode_buf) 2379 free(hdmi->edid_data.mode_buf); 2380 if (hdmi) 2381 free(hdmi); 2382 } 2383 2384 int rockchip_dw_hdmi_prepare(struct rockchip_connector *conn, struct display_state *state) 2385 { 2386 return 0; 2387 } 2388 2389 int rockchip_dw_hdmi_enable(struct rockchip_connector *conn, struct display_state *state) 2390 { 2391 struct connector_state *conn_state = &state->conn_state; 2392 struct drm_display_mode *mode = &conn_state->mode; 2393 struct dw_hdmi *hdmi = conn->data; 2394 2395 if (!hdmi) 2396 return -EFAULT; 2397 2398 /* Store the display mode for plugin/DKMS poweron events */ 2399 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 2400 2401 dw_hdmi_setup(hdmi, conn, mode, state); 2402 2403 return 0; 2404 } 2405 2406 int rockchip_dw_hdmi_disable(struct rockchip_connector *conn, struct display_state *state) 2407 { 2408 struct dw_hdmi *hdmi = conn->data; 2409 2410 dw_hdmi_disable(conn, hdmi, state); 2411 return 0; 2412 } 2413 2414 int rockchip_dw_hdmi_get_timing(struct rockchip_connector *conn, struct display_state *state) 2415 { 2416 int ret, i; 2417 struct connector_state *conn_state = &state->conn_state; 2418 struct drm_display_mode *mode = &conn_state->mode; 2419 struct dw_hdmi *hdmi = conn->data; 2420 struct edid *edid = (struct edid *)conn_state->edid; 2421 unsigned int bus_format; 2422 unsigned long enc_out_encoding; 2423 struct overscan *overscan = &conn_state->overscan; 2424 const u8 def_modes_vic[6] = {4, 16, 2, 17, 31, 19}; 2425 2426 if (!hdmi) 2427 return -EFAULT; 2428 2429 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 2430 2431 if (!ret) { 2432 hdmi->sink_is_hdmi = 2433 drm_detect_hdmi_monitor(edid); 2434 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 2435 ret = drm_add_edid_modes(&hdmi->edid_data, conn_state->edid); 2436 } 2437 if (ret < 0) { 2438 hdmi->sink_is_hdmi = true; 2439 hdmi->sink_has_audio = true; 2440 do_cea_modes(&hdmi->edid_data, def_modes_vic, 2441 sizeof(def_modes_vic)); 2442 hdmi->edid_data.preferred_mode = &hdmi->edid_data.mode_buf[0]; 2443 printf("failed to get edid\n"); 2444 } 2445 drm_rk_filter_whitelist(&hdmi->edid_data); 2446 if (hdmi->phy.ops->mode_valid) 2447 hdmi->phy.ops->mode_valid(conn, hdmi, state); 2448 drm_mode_max_resolution_filter(&hdmi->edid_data, 2449 &state->crtc_state.max_output); 2450 if (!drm_mode_prune_invalid(&hdmi->edid_data)) { 2451 printf("can't find valid hdmi mode\n"); 2452 return -EINVAL; 2453 } 2454 2455 for (i = 0; i < hdmi->edid_data.modes; i++) 2456 hdmi->edid_data.mode_buf[i].vrefresh = 2457 drm_mode_vrefresh(&hdmi->edid_data.mode_buf[i]); 2458 2459 drm_mode_sort(&hdmi->edid_data); 2460 drm_rk_selete_output(&hdmi->edid_data, conn_state, &bus_format, 2461 overscan, hdmi->dev_type, hdmi->output_bus_format_rgb); 2462 2463 *mode = *hdmi->edid_data.preferred_mode; 2464 hdmi->vic = drm_match_cea_mode(mode); 2465 2466 printf("mode:%dx%d\n", mode->hdisplay, mode->vdisplay); 2467 if (state->force_output) 2468 bus_format = state->force_bus_format; 2469 conn_state->bus_format = bus_format; 2470 hdmi->hdmi_data.enc_in_bus_format = bus_format; 2471 hdmi->hdmi_data.enc_out_bus_format = bus_format; 2472 2473 switch (bus_format) { 2474 case MEDIA_BUS_FMT_UYVY10_1X20: 2475 conn_state->bus_format = MEDIA_BUS_FMT_YUV10_1X30; 2476 hdmi->hdmi_data.enc_in_bus_format = 2477 MEDIA_BUS_FMT_YUV10_1X30; 2478 break; 2479 case MEDIA_BUS_FMT_UYVY8_1X16: 2480 conn_state->bus_format = MEDIA_BUS_FMT_YUV8_1X24; 2481 hdmi->hdmi_data.enc_in_bus_format = 2482 MEDIA_BUS_FMT_YUV8_1X24; 2483 break; 2484 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 2485 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 2486 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420; 2487 break; 2488 } 2489 2490 if (hdmi->vic == 6 || hdmi->vic == 7 || hdmi->vic == 21 || 2491 hdmi->vic == 22 || hdmi->vic == 2 || hdmi->vic == 3 || 2492 hdmi->vic == 17 || hdmi->vic == 18) 2493 enc_out_encoding = V4L2_YCBCR_ENC_601; 2494 else 2495 enc_out_encoding = V4L2_YCBCR_ENC_709; 2496 2497 if (enc_out_encoding == V4L2_YCBCR_ENC_BT2020) 2498 conn_state->color_space = V4L2_COLORSPACE_BT2020; 2499 else if (bus_format == MEDIA_BUS_FMT_RGB888_1X24 || 2500 bus_format == MEDIA_BUS_FMT_RGB101010_1X30) 2501 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 2502 else if (enc_out_encoding == V4L2_YCBCR_ENC_709) 2503 conn_state->color_space = V4L2_COLORSPACE_REC709; 2504 else 2505 conn_state->color_space = V4L2_COLORSPACE_SMPTE170M; 2506 2507 return 0; 2508 } 2509 2510 int rockchip_dw_hdmi_detect(struct rockchip_connector *conn, struct display_state *state) 2511 { 2512 int ret; 2513 struct dw_hdmi *hdmi = conn->data; 2514 2515 if (!hdmi) 2516 return -EFAULT; 2517 2518 ret = dw_hdmi_detect_hotplug(hdmi, state); 2519 2520 return ret; 2521 } 2522 2523 int rockchip_dw_hdmi_get_edid(struct rockchip_connector *conn, struct display_state *state) 2524 { 2525 int ret; 2526 struct connector_state *conn_state = &state->conn_state; 2527 struct dw_hdmi *hdmi = conn->data; 2528 2529 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 2530 2531 return ret; 2532 } 2533 2534 int inno_dw_hdmi_phy_init(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data) 2535 { 2536 struct display_state *state = (struct display_state *)data; 2537 struct connector_state *conn_state = &state->conn_state; 2538 u32 color_depth, bus_width; 2539 2540 color_depth = 2541 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 2542 2543 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 2544 bus_width = color_depth / 2; 2545 else if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 2546 bus_width = color_depth; 2547 else 2548 bus_width = 8; 2549 rockchip_phy_set_bus_width(conn->phy, bus_width); 2550 rockchip_phy_set_pll(conn->phy, 2551 conn_state->mode.crtc_clock * 1000); 2552 if (hdmi->edid_data.display_info.hdmi.scdc.supported) 2553 rockchip_dw_hdmi_scdc_set_tmds_rate(hdmi); 2554 rockchip_phy_power_on(conn->phy); 2555 2556 return 0; 2557 } 2558 2559 void inno_dw_hdmi_phy_disable(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data) 2560 { 2561 } 2562 2563 enum drm_connector_status 2564 inno_dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data) 2565 { 2566 enum drm_connector_status status; 2567 struct display_state *state = (struct display_state *)data; 2568 2569 status = dw_hdmi_phy_read_hpd(hdmi, state); 2570 2571 if (hdmi->dev_type == RK3328_HDMI) { 2572 if (status == connector_status_connected) 2573 inno_dw_hdmi_set_domain(hdmi->grf, 1); 2574 else 2575 inno_dw_hdmi_set_domain(hdmi->grf, 0); 2576 } 2577 2578 return status; 2579 } 2580 2581 void inno_dw_hdmi_mode_valid(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data) 2582 { 2583 struct hdmi_edid_data *edid_data = &hdmi->edid_data; 2584 unsigned long rate; 2585 int i, ret; 2586 struct drm_display_mode *mode_buf = edid_data->mode_buf; 2587 2588 for (i = 0; i < edid_data->modes; i++) { 2589 if (edid_data->mode_buf[i].invalid) 2590 continue; 2591 if (edid_data->mode_buf[i].flags & DRM_MODE_FLAG_DBLCLK) 2592 rate = mode_buf[i].clock * 1000 * 2; 2593 else 2594 rate = mode_buf[i].clock * 1000; 2595 2596 /* Check whether mode is out of phy cfg range. */ 2597 ret = rockchip_phy_round_rate(conn->phy, rate); 2598 2599 if (ret < 0) 2600 edid_data->mode_buf[i].invalid = true; 2601 } 2602 } 2603