1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <syscon.h> 10 #include <asm/arch-rockchip/clock.h> 11 #include <asm/arch/vendor.h> 12 #include <edid.h> 13 #include <dm/device.h> 14 #include <dm/ofnode.h> 15 #include <dm/read.h> 16 #include <linux/hdmi.h> 17 #include <linux/media-bus-format.h> 18 #include <linux/dw_hdmi.h> 19 #include <asm/io.h> 20 #include "rockchip_display.h" 21 #include "rockchip_crtc.h" 22 #include "rockchip_connector.h" 23 #include "dw_hdmi.h" 24 #include "rockchip_phy.h" 25 26 #define HDCP_PRIVATE_KEY_SIZE 280 27 #define HDCP_KEY_SHA_SIZE 20 28 #define HDMI_HDCP1X_ID 5 29 /* 30 * Unless otherwise noted, entries in this table are 100% optimization. 31 * Values can be obtained from hdmi_compute_n() but that function is 32 * slow so we pre-compute values we expect to see. 33 * 34 * All 32k and 48k values are expected to be the same (due to the way 35 * the math works) for any rate that's an exact kHz. 36 */ 37 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = { 38 { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, }, 39 { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, }, 40 { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 41 { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, }, 42 { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, }, 43 { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, 44 { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, 45 { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 46 { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 47 { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, 48 { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 49 { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, 50 { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 51 { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 52 { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, }, 53 { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 54 { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, }, 55 { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 56 { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 57 { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, }, 58 { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, 59 { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, 60 { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, 61 { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 62 { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 63 { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 64 { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 65 { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 66 { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, 67 { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 68 { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, }, 69 { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, 70 { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 71 { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 72 { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 73 { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, 74 { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 75 76 /* For 297 MHz+ HDMI spec have some other rule for setting N */ 77 { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, }, 78 { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, }, 79 80 /* End of table */ 81 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, }, 82 }; 83 84 static const u16 csc_coeff_default[3][4] = { 85 { 0x2000, 0x0000, 0x0000, 0x0000 }, 86 { 0x0000, 0x2000, 0x0000, 0x0000 }, 87 { 0x0000, 0x0000, 0x2000, 0x0000 } 88 }; 89 90 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 91 { 0x2000, 0x6926, 0x74fd, 0x010e }, 92 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 93 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 94 }; 95 96 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 97 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 98 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 99 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 100 }; 101 102 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 103 { 0x2591, 0x1322, 0x074b, 0x0000 }, 104 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 105 { 0x6acd, 0x7534, 0x2000, 0x0200 } 106 }; 107 108 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 109 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 110 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 111 { 0x6756, 0x78ab, 0x2000, 0x0200 } 112 }; 113 114 static const u16 csc_coeff_full_to_limited[3][4] = { 115 { 0x36f7, 0x0000, 0x0000, 0x0040 }, 116 { 0x0000, 0x36f7, 0x0000, 0x0040 }, 117 { 0x0000, 0x0000, 0x36f7, 0x0040 } 118 }; 119 120 struct hdmi_vmode { 121 bool mdataenablepolarity; 122 123 unsigned int mpixelclock; 124 unsigned int mpixelrepetitioninput; 125 unsigned int mpixelrepetitionoutput; 126 unsigned int mtmdsclock; 127 }; 128 129 struct hdmi_data_info { 130 unsigned int enc_in_bus_format; 131 unsigned int enc_out_bus_format; 132 unsigned int enc_in_encoding; 133 unsigned int enc_out_encoding; 134 unsigned int quant_range; 135 unsigned int pix_repet_factor; 136 struct hdmi_vmode video_mode; 137 }; 138 139 struct dw_hdmi_phy_data { 140 enum dw_hdmi_phy_type type; 141 const char *name; 142 unsigned int gen; 143 bool has_svsret; 144 int (*configure)(struct dw_hdmi *hdmi, 145 const struct dw_hdmi_plat_data *pdata, 146 unsigned long mpixelclock); 147 }; 148 149 struct hdcp_keys { 150 u8 KSV[8]; 151 u8 devicekey[HDCP_PRIVATE_KEY_SIZE]; 152 u8 sha1[HDCP_KEY_SHA_SIZE]; 153 u8 seeds[2]; 154 }; 155 156 struct dw_hdmi_i2c { 157 u8 slave_reg; 158 bool is_regaddr; 159 bool is_segment; 160 161 unsigned int scl_high_ns; 162 unsigned int scl_low_ns; 163 }; 164 165 struct dw_hdmi { 166 enum dw_hdmi_devtype dev_type; 167 unsigned int version; 168 struct hdmi_data_info hdmi_data; 169 struct hdmi_edid_data edid_data; 170 const struct dw_hdmi_plat_data *plat_data; 171 struct ddc_adapter adap; 172 173 int vic; 174 int io_width; 175 176 unsigned long bus_format; 177 bool cable_plugin; 178 bool sink_is_hdmi; 179 bool sink_has_audio; 180 void *regs; 181 void *grf; 182 struct dw_hdmi_i2c *i2c; 183 184 struct { 185 const struct dw_hdmi_phy_ops *ops; 186 const char *name; 187 void *data; 188 bool enabled; 189 } phy; 190 191 struct drm_display_mode previous_mode; 192 193 unsigned int sample_rate; 194 unsigned int audio_cts; 195 unsigned int audio_n; 196 bool audio_enable; 197 bool scramble_low_rates; 198 199 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset); 200 u8 (*read)(struct dw_hdmi *hdmi, int offset); 201 202 bool hdcp1x_enable; 203 }; 204 205 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset) 206 { 207 writel(val, hdmi->regs + (offset << 2)); 208 } 209 210 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset) 211 { 212 return readl(hdmi->regs + (offset << 2)); 213 } 214 215 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 216 { 217 writeb(val, hdmi->regs + offset); 218 } 219 220 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset) 221 { 222 return readb(hdmi->regs + offset); 223 } 224 225 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 226 { 227 hdmi->write(hdmi, val, offset); 228 } 229 230 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 231 { 232 return hdmi->read(hdmi, offset); 233 } 234 235 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 236 { 237 u8 val = hdmi_readb(hdmi, reg) & ~mask; 238 239 val |= data & mask; 240 hdmi_writeb(hdmi, val, reg); 241 } 242 243 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 244 u8 shift, u8 mask) 245 { 246 hdmi_modb(hdmi, data << shift, mask, reg); 247 } 248 249 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 250 { 251 switch (bus_format) { 252 case MEDIA_BUS_FMT_RGB888_1X24: 253 case MEDIA_BUS_FMT_RGB101010_1X30: 254 case MEDIA_BUS_FMT_RGB121212_1X36: 255 case MEDIA_BUS_FMT_RGB161616_1X48: 256 return true; 257 258 default: 259 return false; 260 } 261 } 262 263 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 264 { 265 switch (bus_format) { 266 case MEDIA_BUS_FMT_YUV8_1X24: 267 case MEDIA_BUS_FMT_YUV10_1X30: 268 case MEDIA_BUS_FMT_YUV12_1X36: 269 case MEDIA_BUS_FMT_YUV16_1X48: 270 return true; 271 272 default: 273 return false; 274 } 275 } 276 277 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 278 { 279 switch (bus_format) { 280 case MEDIA_BUS_FMT_UYVY8_1X16: 281 case MEDIA_BUS_FMT_UYVY10_1X20: 282 case MEDIA_BUS_FMT_UYVY12_1X24: 283 return true; 284 285 default: 286 return false; 287 } 288 } 289 290 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 291 { 292 switch (bus_format) { 293 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 294 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 295 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 296 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 297 return true; 298 299 default: 300 return false; 301 } 302 } 303 304 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 305 { 306 switch (bus_format) { 307 case MEDIA_BUS_FMT_RGB888_1X24: 308 case MEDIA_BUS_FMT_YUV8_1X24: 309 case MEDIA_BUS_FMT_UYVY8_1X16: 310 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 311 return 8; 312 313 case MEDIA_BUS_FMT_RGB101010_1X30: 314 case MEDIA_BUS_FMT_YUV10_1X30: 315 case MEDIA_BUS_FMT_UYVY10_1X20: 316 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 317 return 10; 318 319 case MEDIA_BUS_FMT_RGB121212_1X36: 320 case MEDIA_BUS_FMT_YUV12_1X36: 321 case MEDIA_BUS_FMT_UYVY12_1X24: 322 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 323 return 12; 324 325 case MEDIA_BUS_FMT_RGB161616_1X48: 326 case MEDIA_BUS_FMT_YUV16_1X48: 327 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 328 return 16; 329 330 default: 331 return 0; 332 } 333 } 334 335 static int is_color_space_conversion(struct dw_hdmi *hdmi) 336 { 337 struct drm_display_mode *mode = 338 hdmi->edid_data.preferred_mode; 339 bool is_cea_default; 340 341 is_cea_default = (drm_match_cea_mode(mode) > 1) && 342 (hdmi->hdmi_data.quant_range == 343 HDMI_QUANTIZATION_RANGE_DEFAULT); 344 345 /* 346 * When output is rgb limited range or default range with 347 * cea mode, csc should be enabled. 348 */ 349 if (hdmi->hdmi_data.enc_in_bus_format != 350 hdmi->hdmi_data.enc_out_bus_format || 351 ((hdmi->hdmi_data.quant_range == HDMI_QUANTIZATION_RANGE_LIMITED || 352 is_cea_default) && 353 hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format))) 354 return 1; 355 356 return 0; 357 } 358 359 static int is_color_space_decimation(struct dw_hdmi *hdmi) 360 { 361 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 362 return 0; 363 364 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 365 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 366 return 1; 367 368 return 0; 369 } 370 371 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 372 unsigned char bit) 373 { 374 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 375 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 376 } 377 378 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi, 379 unsigned char bit) 380 { 381 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET, 382 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0); 383 } 384 385 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi, 386 unsigned char bit) 387 { 388 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET, 389 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0); 390 } 391 392 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi, 393 unsigned char bit) 394 { 395 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1); 396 } 397 398 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi, 399 unsigned char bit) 400 { 401 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2); 402 } 403 404 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 405 unsigned char *buf, unsigned int length) 406 { 407 struct dw_hdmi_i2c *i2c = hdmi->i2c; 408 int interrupt = 0, i = 20; 409 410 if (!i2c->is_regaddr) { 411 printf("set read register address to 0\n"); 412 i2c->slave_reg = 0x00; 413 i2c->is_regaddr = true; 414 } 415 416 while (length--) { 417 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 418 if (i2c->is_segment) 419 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 420 HDMI_I2CM_OPERATION); 421 else 422 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 423 HDMI_I2CM_OPERATION); 424 425 while (i--) { 426 udelay(1000); 427 interrupt = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 428 if (interrupt) 429 hdmi_writeb(hdmi, interrupt, 430 HDMI_IH_I2CM_STAT0); 431 if (interrupt & (m_SCDC_READREQ | m_I2CM_DONE | 432 m_I2CM_ERROR)) 433 break; 434 } 435 436 if (!interrupt) { 437 printf("[%s] i2c read reg[0x%02x] no interrupt\n", 438 __func__, i2c->slave_reg); 439 return -EAGAIN; 440 } 441 442 /* Check for error condition on the bus */ 443 if (interrupt & HDMI_IH_I2CM_STAT0_ERROR) { 444 printf("[%s] read reg[0x%02x] data error:0x%02x\n", 445 __func__, i2c->slave_reg, interrupt); 446 return -EIO; 447 } 448 449 i = 20; 450 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 451 } 452 i2c->is_segment = false; 453 454 return 0; 455 } 456 457 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 458 unsigned char *buf, unsigned int length) 459 { 460 struct dw_hdmi_i2c *i2c = hdmi->i2c; 461 int i = 20; 462 u8 interrupt = 0; 463 464 if (!i2c->is_regaddr) { 465 /* Use the first write byte as register address */ 466 i2c->slave_reg = buf[0]; 467 length--; 468 buf++; 469 i2c->is_regaddr = true; 470 } 471 472 while (length--) { 473 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 474 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 475 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 476 HDMI_I2CM_OPERATION); 477 478 while (i--) { 479 udelay(1000); 480 interrupt = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 481 if (interrupt) 482 hdmi_writeb(hdmi, 483 interrupt, HDMI_IH_I2CM_STAT0); 484 485 if (interrupt & (m_SCDC_READREQ | 486 m_I2CM_DONE | m_I2CM_ERROR)) 487 break; 488 } 489 490 if ((interrupt & m_I2CM_ERROR) || (i == -1)) { 491 printf("[%s] write data error\n", __func__); 492 return -EIO; 493 } else if (interrupt & m_I2CM_DONE) { 494 printf("[%s] write offset %02x success\n", 495 __func__, i2c->slave_reg); 496 return -EAGAIN; 497 } 498 499 i = 20; 500 } 501 502 return 0; 503 } 504 505 static int dw_hdmi_i2c_xfer(struct ddc_adapter *adap, 506 struct i2c_msg *msgs, int num) 507 { 508 struct dw_hdmi *hdmi = container_of(adap, struct dw_hdmi, adap); 509 struct dw_hdmi_i2c *i2c = hdmi->i2c; 510 u8 addr = msgs[0].addr; 511 int i, ret = 0; 512 513 printf("xfer: num: %d, addr: %#x\n", num, addr); 514 for (i = 0; i < num; i++) { 515 if (msgs[i].len == 0) { 516 printf("unsupported transfer %d/%d, no data\n", 517 i + 1, num); 518 return -EOPNOTSUPP; 519 } 520 } 521 522 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 523 524 /* Set slave device address taken from the first I2C message */ 525 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1) 526 addr = DDC_ADDR; 527 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 528 529 /* Set slave device register address on transfer */ 530 i2c->is_regaddr = false; 531 532 /* Set segment pointer for I2C extended read mode operation */ 533 i2c->is_segment = false; 534 535 for (i = 0; i < num; i++) { 536 debug("xfer: num: %d/%d, len: %d, flags: %#x\n", 537 i + 1, num, msgs[i].len, msgs[i].flags); 538 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 539 i2c->is_segment = true; 540 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 541 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 542 } else { 543 if (msgs[i].flags & I2C_M_RD) 544 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 545 msgs[i].len); 546 else 547 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 548 msgs[i].len); 549 } 550 if (ret < 0) 551 break; 552 } 553 554 if (!ret) 555 ret = num; 556 557 /* Mute DONE and ERROR interrupts */ 558 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 559 HDMI_IH_MUTE_I2CM_STAT0); 560 561 return ret; 562 } 563 564 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 565 { 566 u32 val; 567 568 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 569 if (msec-- == 0) 570 return false; 571 udelay(1000); 572 } 573 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 574 575 return true; 576 } 577 578 static void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 579 unsigned char addr) 580 { 581 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 582 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 583 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 584 HDMI_PHY_I2CM_DATAO_1_ADDR); 585 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 586 HDMI_PHY_I2CM_DATAO_0_ADDR); 587 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 588 HDMI_PHY_I2CM_OPERATION_ADDR); 589 hdmi_phy_wait_i2c_done(hdmi, 1000); 590 } 591 592 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 593 { 594 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 595 HDMI_PHY_CONF0_PDZ_OFFSET, 596 HDMI_PHY_CONF0_PDZ_MASK); 597 } 598 599 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 600 { 601 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 602 HDMI_PHY_CONF0_ENTMDS_OFFSET, 603 HDMI_PHY_CONF0_ENTMDS_MASK); 604 } 605 606 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 607 { 608 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 609 HDMI_PHY_CONF0_SVSRET_OFFSET, 610 HDMI_PHY_CONF0_SVSRET_MASK); 611 } 612 613 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 614 { 615 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 616 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 617 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 618 } 619 620 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 621 { 622 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 623 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 624 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 625 } 626 627 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 628 { 629 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 630 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 631 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 632 } 633 634 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 635 { 636 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 637 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 638 HDMI_PHY_CONF0_SELDIPIF_MASK); 639 } 640 641 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 642 { 643 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 644 unsigned int i; 645 u16 val; 646 647 if (phy->gen == 1) { 648 dw_hdmi_phy_enable_tmds(hdmi, 0); 649 dw_hdmi_phy_enable_powerdown(hdmi, true); 650 return; 651 } 652 653 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 654 655 /* 656 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 657 * to low power mode. 658 */ 659 for (i = 0; i < 5; ++i) { 660 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 661 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 662 break; 663 664 udelay(2000); 665 } 666 667 if (val & HDMI_PHY_TX_PHY_LOCK) 668 printf("PHY failed to power down\n"); 669 else 670 printf("PHY powered down in %u iterations\n", i); 671 672 dw_hdmi_phy_gen2_pddq(hdmi, 1); 673 } 674 675 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 676 { 677 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 678 unsigned int i; 679 u8 val; 680 681 if (phy->gen == 1) { 682 dw_hdmi_phy_enable_powerdown(hdmi, false); 683 684 /* Toggle TMDS enable. */ 685 dw_hdmi_phy_enable_tmds(hdmi, 0); 686 dw_hdmi_phy_enable_tmds(hdmi, 1); 687 return 0; 688 } 689 690 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 691 dw_hdmi_phy_gen2_pddq(hdmi, 0); 692 693 /* Wait for PHY PLL lock */ 694 for (i = 0; i < 5; ++i) { 695 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 696 if (val) 697 break; 698 699 udelay(2000); 700 } 701 702 if (!val) { 703 printf("PHY PLL failed to lock\n"); 704 return -ETIMEDOUT; 705 } 706 printf("PHY PLL locked %u iterations\n", i); 707 708 return 0; 709 } 710 711 /* 712 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 713 * information the DWC MHL PHY has the same register layout and is thus also 714 * supported by this function. 715 */ 716 static 717 int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 718 const struct dw_hdmi_plat_data *pdata, 719 unsigned long mpixelclock) 720 { 721 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 722 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 723 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 724 unsigned int tmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 725 unsigned int depth = 726 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 727 728 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) && 729 pdata->mpll_cfg_420) 730 mpll_config = pdata->mpll_cfg_420; 731 732 /* PLL/MPLL Cfg - always match on final entry */ 733 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 734 if (mpixelclock <= mpll_config->mpixelclock) 735 break; 736 737 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 738 if (tmdsclock <= curr_ctrl->mpixelclock) 739 break; 740 741 for (; phy_config->mpixelclock != ~0UL; phy_config++) 742 if (tmdsclock <= phy_config->mpixelclock) 743 break; 744 745 if (mpll_config->mpixelclock == ~0UL || 746 curr_ctrl->mpixelclock == ~0UL || 747 phy_config->mpixelclock == ~0UL) 748 return -EINVAL; 749 750 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 751 depth = fls(depth - 8); 752 else 753 depth = 0; 754 if (depth) 755 depth--; 756 757 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].cpce, 758 HDMI_3D_TX_PHY_CPCE_CTRL); 759 760 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].gmp, 761 HDMI_3D_TX_PHY_GMPCTRL); 762 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[depth], 763 HDMI_3D_TX_PHY_CURRCTRL); 764 765 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 766 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 767 HDMI_3D_TX_PHY_MSM_CTRL); 768 769 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 770 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 771 HDMI_3D_TX_PHY_CKSYMTXCTRL); 772 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 773 HDMI_3D_TX_PHY_VLEVCTRL); 774 775 return 0; 776 } 777 778 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 779 { 780 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 781 .name = "DWC HDMI TX PHY", 782 .gen = 1, 783 }, { 784 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 785 .name = "DWC MHL PHY + HEAC PHY", 786 .gen = 2, 787 .has_svsret = true, 788 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 789 }, { 790 .type = DW_HDMI_PHY_DWC_MHL_PHY, 791 .name = "DWC MHL PHY", 792 .gen = 2, 793 .has_svsret = true, 794 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 795 }, { 796 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 797 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 798 .gen = 2, 799 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 800 }, { 801 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 802 .name = "DWC HDMI 3D TX PHY", 803 .gen = 2, 804 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 805 }, { 806 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 807 .name = "DWC HDMI 2.0 TX PHY", 808 .gen = 2, 809 .has_svsret = true, 810 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 811 }, { 812 .type = DW_HDMI_PHY_VENDOR_PHY, 813 .name = "Vendor PHY", 814 } 815 }; 816 817 static int rockchip_dw_hdmi_scrambling_enable(struct dw_hdmi *hdmi, 818 int enable) 819 { 820 u8 stat; 821 822 drm_scdc_readb(&hdmi->adap, SCDC_TMDS_CONFIG, &stat); 823 824 if (stat < 0) { 825 debug("Failed to read tmds config\n"); 826 return false; 827 } 828 829 if (enable == 1) { 830 /* Write on Rx the bit Scrambling_Enable, register 0x20 */ 831 stat |= SCDC_SCRAMBLING_ENABLE; 832 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 833 /* TMDS software reset request */ 834 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 835 HDMI_MC_SWRSTZ); 836 /* Enable/Disable Scrambling */ 837 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); 838 } else { 839 /* Enable/Disable Scrambling */ 840 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); 841 /* TMDS software reset request */ 842 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 843 HDMI_MC_SWRSTZ); 844 /* Write on Rx the bit Scrambling_Enable, register 0x20 */ 845 stat &= ~SCDC_SCRAMBLING_ENABLE; 846 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 847 } 848 849 return 0; 850 } 851 852 static void rockchip_dw_hdmi_scdc_set_tmds_rate(struct dw_hdmi *hdmi) 853 { 854 u8 stat; 855 856 drm_scdc_readb(&hdmi->adap, SCDC_TMDS_CONFIG, &stat); 857 if (hdmi->hdmi_data.video_mode.mtmdsclock > 340000000) 858 stat |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 859 else 860 stat &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 861 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 862 } 863 864 static int hdmi_phy_configure(struct dw_hdmi *hdmi) 865 { 866 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 867 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 868 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 869 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 870 int ret; 871 872 dw_hdmi_phy_power_off(hdmi); 873 874 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ 875 if (hdmi->edid_data.display_info.hdmi.scdc.supported) 876 rockchip_dw_hdmi_scdc_set_tmds_rate(hdmi); 877 878 /* Leave low power consumption mode by asserting SVSRET. */ 879 if (phy->has_svsret) 880 dw_hdmi_phy_enable_svsret(hdmi, 1); 881 882 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 883 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 884 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 885 886 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 887 888 hdmi_phy_test_clear(hdmi, 1); 889 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, 890 HDMI_PHY_I2CM_SLAVE_ADDR); 891 hdmi_phy_test_clear(hdmi, 0); 892 893 /* Write to the PHY as configured by the platform */ 894 if (pdata->configure_phy) 895 ret = pdata->configure_phy(hdmi, pdata, mpixelclock); 896 else 897 ret = phy->configure(hdmi, pdata, mpixelclock); 898 if (ret) { 899 printf("PHY configuration failed (clock %lu)\n", 900 mpixelclock); 901 return ret; 902 } 903 904 /* Wait for resuming transmission of TMDS clock and data */ 905 if (mtmdsclock > 340000000) 906 mdelay(100); 907 908 return dw_hdmi_phy_power_on(hdmi); 909 } 910 911 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, 912 void *data) 913 { 914 int i, ret; 915 916 /* HDMI Phy spec says to do the phy initialization sequence twice */ 917 for (i = 0; i < 2; i++) { 918 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 919 dw_hdmi_phy_sel_interface_control(hdmi, 0); 920 ret = hdmi_phy_configure(hdmi); 921 if (ret) 922 return ret; 923 } 924 925 return 0; 926 } 927 928 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, 929 void *data) 930 { 931 dw_hdmi_phy_power_off(hdmi); 932 } 933 934 static enum drm_connector_status 935 dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data) 936 { 937 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 938 connector_status_connected : connector_status_disconnected; 939 } 940 941 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 942 .init = dw_hdmi_phy_init, 943 .disable = dw_hdmi_phy_disable, 944 .read_hpd = dw_hdmi_phy_read_hpd, 945 }; 946 947 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 948 { 949 unsigned int i; 950 u8 phy_type; 951 952 phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID); 953 954 /* 955 * RK3228 and RK3328 phy_type is DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 956 * but it has a vedor phy. 957 */ 958 if (phy_type == DW_HDMI_PHY_VENDOR_PHY || 959 hdmi->dev_type == RK3328_HDMI || 960 hdmi->dev_type == RK3228_HDMI) { 961 /* Vendor PHYs require support from the glue layer. */ 962 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 963 printf( 964 "Vendor HDMI PHY not supported by glue layer\n"); 965 return -ENODEV; 966 } 967 968 hdmi->phy.ops = hdmi->plat_data->phy_ops; 969 hdmi->phy.data = hdmi->plat_data->phy_data; 970 hdmi->phy.name = hdmi->plat_data->phy_name; 971 return 0; 972 } 973 974 /* Synopsys PHYs are handled internally. */ 975 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 976 if (dw_hdmi_phys[i].type == phy_type) { 977 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 978 hdmi->phy.name = dw_hdmi_phys[i].name; 979 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 980 981 if (!dw_hdmi_phys[i].configure && 982 !hdmi->plat_data->configure_phy) { 983 printf("%s requires platform support\n", 984 hdmi->phy.name); 985 return -ENODEV; 986 } 987 988 return 0; 989 } 990 } 991 992 printf("Unsupported HDMI PHY type (%02x)\n", phy_type); 993 return -ENODEV; 994 } 995 996 static unsigned int 997 hdmi_get_tmdsclock(struct dw_hdmi *hdmi, unsigned long mpixelclock) 998 { 999 unsigned int tmdsclock = mpixelclock; 1000 unsigned int depth = 1001 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 1002 1003 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1004 switch (depth) { 1005 case 16: 1006 tmdsclock = mpixelclock * 2; 1007 break; 1008 case 12: 1009 tmdsclock = mpixelclock * 3 / 2; 1010 break; 1011 case 10: 1012 tmdsclock = mpixelclock * 5 / 4; 1013 break; 1014 default: 1015 break; 1016 } 1017 } 1018 1019 return tmdsclock; 1020 } 1021 1022 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1023 const struct drm_display_mode *mode) 1024 { 1025 u8 bytes = 0, inv_val = 0; 1026 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1027 struct drm_hdmi_info *hdmi_info = &hdmi->edid_data.display_info.hdmi; 1028 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1029 unsigned int hdisplay, vdisplay; 1030 1031 vmode->mpixelclock = mode->crtc_clock * 1000; 1032 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == 1033 DRM_MODE_FLAG_3D_FRAME_PACKING) 1034 vmode->mpixelclock *= 2; 1035 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock); 1036 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1037 vmode->mtmdsclock /= 2; 1038 printf("final pixclk = %d tmdsclk = %d\n", 1039 vmode->mpixelclock, vmode->mtmdsclock); 1040 1041 /* Set up HDMI_FC_INVIDCONF 1042 * fc_invidconf.HDCP_keepout must be set (1'b1) 1043 * when activate the scrambler feature. 1044 */ 1045 inv_val = (vmode->mtmdsclock > 340000000 || 1046 (hdmi_info->scdc.scrambling.low_rates && 1047 hdmi->scramble_low_rates) ? 1048 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 1049 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 1050 1051 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 1052 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 1053 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 1054 1055 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 1056 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 1057 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 1058 1059 inv_val |= (vmode->mdataenablepolarity ? 1060 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 1061 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 1062 1063 if (hdmi->vic == 39) 1064 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 1065 else 1066 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1067 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 1068 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 1069 1070 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1071 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 1072 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 1073 1074 inv_val |= hdmi->sink_is_hdmi ? 1075 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 1076 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 1077 1078 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 1079 1080 hdisplay = mode->hdisplay; 1081 hblank = mode->htotal - mode->hdisplay; 1082 h_de_hs = mode->hsync_start - mode->hdisplay; 1083 hsync_len = mode->hsync_end - mode->hsync_start; 1084 1085 /* 1086 * When we're setting a YCbCr420 mode, we need 1087 * to adjust the horizontal timing to suit. 1088 */ 1089 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1090 hdisplay /= 2; 1091 hblank /= 2; 1092 h_de_hs /= 2; 1093 hsync_len /= 2; 1094 } 1095 1096 vdisplay = mode->vdisplay; 1097 vblank = mode->vtotal - mode->vdisplay; 1098 v_de_vs = mode->vsync_start - mode->vdisplay; 1099 vsync_len = mode->vsync_end - mode->vsync_start; 1100 1101 /* 1102 * When we're setting an interlaced mode, we need 1103 * to adjust the vertical timing to suit. 1104 */ 1105 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1106 vdisplay /= 2; 1107 vblank /= 2; 1108 v_de_vs /= 2; 1109 vsync_len /= 2; 1110 } else if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == 1111 DRM_MODE_FLAG_3D_FRAME_PACKING) { 1112 vdisplay += mode->vtotal; 1113 } 1114 1115 /* Scrambling Control */ 1116 if (hdmi_info->scdc.supported) { 1117 if (vmode->mtmdsclock > 340000000 || 1118 (hdmi_info->scdc.scrambling.low_rates && 1119 hdmi->scramble_low_rates)) { 1120 drm_scdc_readb(&hdmi->adap, SCDC_SINK_VERSION, &bytes); 1121 drm_scdc_writeb(&hdmi->adap, SCDC_SOURCE_VERSION, 1122 bytes); 1123 rockchip_dw_hdmi_scrambling_enable(hdmi, 1); 1124 } else { 1125 rockchip_dw_hdmi_scrambling_enable(hdmi, 0); 1126 } 1127 } 1128 1129 /* Set up horizontal active pixel width */ 1130 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1); 1131 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0); 1132 1133 /* Set up vertical active lines */ 1134 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 1135 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 1136 1137 /* Set up horizontal blanking pixel region width */ 1138 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 1139 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 1140 1141 /* Set up vertical blanking pixel region width */ 1142 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 1143 1144 /* Set up HSYNC active edge delay width (in pixel clks) */ 1145 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 1146 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 1147 1148 /* Set up VSYNC active edge delay (in lines) */ 1149 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 1150 1151 /* Set up HSYNC active pulse width (in pixel clks) */ 1152 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 1153 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 1154 1155 /* Set up VSYNC active edge delay (in lines) */ 1156 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 1157 } 1158 1159 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 1160 { 1161 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 1162 unsigned i; 1163 u32 csc_scale = 1; 1164 int enc_out_rgb, enc_in_rgb; 1165 1166 enc_out_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format); 1167 enc_in_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format); 1168 1169 if (is_color_space_conversion(hdmi)) { 1170 if (enc_out_rgb && enc_in_rgb) { 1171 csc_coeff = &csc_coeff_full_to_limited; 1172 csc_scale = 0; 1173 } else if (enc_out_rgb) { 1174 if (hdmi->hdmi_data.enc_out_encoding == 1175 V4L2_YCBCR_ENC_601) 1176 csc_coeff = &csc_coeff_rgb_out_eitu601; 1177 else 1178 csc_coeff = &csc_coeff_rgb_out_eitu709; 1179 } else if (enc_in_rgb) { 1180 if (hdmi->hdmi_data.enc_out_encoding == 1181 V4L2_YCBCR_ENC_601) 1182 csc_coeff = &csc_coeff_rgb_in_eitu601; 1183 else 1184 csc_coeff = &csc_coeff_rgb_in_eitu709; 1185 csc_scale = 0; 1186 } 1187 } 1188 1189 /* The CSC registers are sequential, alternating MSB then LSB */ 1190 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 1191 u16 coeff_a = (*csc_coeff)[0][i]; 1192 u16 coeff_b = (*csc_coeff)[1][i]; 1193 u16 coeff_c = (*csc_coeff)[2][i]; 1194 1195 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 1196 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 1197 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 1198 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 1199 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 1200 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 1201 } 1202 1203 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 1204 HDMI_CSC_SCALE); 1205 } 1206 1207 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 1208 { 1209 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 1210 return 0; 1211 1212 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1213 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1214 return 1; 1215 1216 return 0; 1217 } 1218 1219 static void hdmi_video_csc(struct dw_hdmi *hdmi) 1220 { 1221 int color_depth = 0; 1222 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 1223 int decimation = 0; 1224 1225 /* YCC422 interpolation to 444 mode */ 1226 if (is_color_space_interpolation(hdmi)) 1227 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 1228 else if (is_color_space_decimation(hdmi)) 1229 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 1230 1231 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 1232 case 8: 1233 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 1234 break; 1235 case 10: 1236 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 1237 break; 1238 case 12: 1239 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 1240 break; 1241 case 16: 1242 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 1243 break; 1244 1245 default: 1246 return; 1247 } 1248 1249 /* Configure the CSC registers */ 1250 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 1251 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 1252 HDMI_CSC_SCALE); 1253 1254 dw_hdmi_update_csc_coeffs(hdmi); 1255 } 1256 1257 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 1258 { 1259 u8 clkdis; 1260 1261 /* control period minimum duration */ 1262 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 1263 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 1264 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 1265 1266 /* Set to fill TMDS data channels */ 1267 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 1268 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 1269 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 1270 1271 /* Enable pixel clock and tmds data path */ 1272 clkdis = 0x7F; 1273 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 1274 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1275 1276 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1277 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1278 1279 /* Enable csc path */ 1280 if (is_color_space_conversion(hdmi)) { 1281 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 1282 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1283 } 1284 1285 /* Enable pixel repetition path */ 1286 if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) { 1287 clkdis &= ~HDMI_MC_CLKDIS_PREPCLK_DISABLE; 1288 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1289 } 1290 1291 /* Enable color space conversion if needed */ 1292 if (is_color_space_conversion(hdmi)) 1293 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 1294 HDMI_MC_FLOWCTRL); 1295 else 1296 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 1297 HDMI_MC_FLOWCTRL); 1298 } 1299 1300 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 1301 { 1302 unsigned int count; 1303 unsigned int i; 1304 u8 val; 1305 1306 /* 1307 * Under some circumstances the Frame Composer arithmetic unit can miss 1308 * an FC register write due to being busy processing the previous one. 1309 * The issue can be worked around by issuing a TMDS software reset and 1310 * then write one of the FC registers several times. 1311 * 1312 * The number of iterations matters and depends on the HDMI TX revision 1313 * (and possibly on the platform). So far only i.MX6Q (v1.30a) and 1314 * i.MX6DL (v1.31a) have been identified as needing the workaround, with 1315 * 4 and 1 iterations respectively. 1316 */ 1317 1318 switch (hdmi->version) { 1319 case 0x130a: 1320 count = 4; 1321 break; 1322 case 0x131a: 1323 case 0x200a: 1324 case 0x201a: 1325 case 0x211a: 1326 count = 1; 1327 break; 1328 default: 1329 return; 1330 } 1331 1332 /* TMDS software reset */ 1333 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 1334 1335 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 1336 for (i = 0; i < count; i++) 1337 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 1338 } 1339 1340 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 1341 { 1342 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 1343 HDMI_IH_MUTE_FC_STAT2); 1344 } 1345 1346 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 1347 { 1348 unsigned int color_depth = 0; 1349 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 1350 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 1351 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1352 u8 val, vp_conf; 1353 1354 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1355 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) || 1356 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1357 switch (hdmi_bus_fmt_color_depth( 1358 hdmi->hdmi_data.enc_out_bus_format)) { 1359 case 8: 1360 color_depth = 0; 1361 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1362 break; 1363 case 10: 1364 color_depth = 5; 1365 break; 1366 case 12: 1367 color_depth = 6; 1368 break; 1369 case 16: 1370 color_depth = 7; 1371 break; 1372 default: 1373 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1374 } 1375 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1376 switch (hdmi_bus_fmt_color_depth( 1377 hdmi->hdmi_data.enc_out_bus_format)) { 1378 case 0: 1379 case 8: 1380 remap_size = HDMI_VP_REMAP_YCC422_16bit; 1381 break; 1382 case 10: 1383 remap_size = HDMI_VP_REMAP_YCC422_20bit; 1384 break; 1385 case 12: 1386 remap_size = HDMI_VP_REMAP_YCC422_24bit; 1387 break; 1388 1389 default: 1390 return; 1391 } 1392 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 1393 } else { 1394 return; 1395 } 1396 1397 /* set the packetizer registers */ 1398 val = (color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 1399 HDMI_VP_PR_CD_COLOR_DEPTH_MASK; 1400 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 1401 1402 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 1403 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 1404 1405 /* Data from pixel repeater block */ 1406 if (hdmi_data->pix_repet_factor > 0) { 1407 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 1408 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 1409 } else { /* data from packetizer block */ 1410 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 1411 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 1412 } 1413 1414 hdmi_modb(hdmi, vp_conf, 1415 HDMI_VP_CONF_PR_EN_MASK | 1416 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 1417 1418 if ((color_depth == 5 && hdmi->previous_mode.htotal % 4) || 1419 (color_depth == 6 && hdmi->previous_mode.htotal % 2)) 1420 hdmi_modb(hdmi, 0, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, 1421 HDMI_VP_STUFF); 1422 else 1423 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 1424 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 1425 1426 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 1427 1428 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 1429 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1430 HDMI_VP_CONF_PP_EN_ENABLE | 1431 HDMI_VP_CONF_YCC422_EN_DISABLE; 1432 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 1433 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1434 HDMI_VP_CONF_PP_EN_DISABLE | 1435 HDMI_VP_CONF_YCC422_EN_ENABLE; 1436 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 1437 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 1438 HDMI_VP_CONF_PP_EN_DISABLE | 1439 HDMI_VP_CONF_YCC422_EN_DISABLE; 1440 } else { 1441 return; 1442 } 1443 1444 hdmi_modb(hdmi, vp_conf, 1445 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 1446 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 1447 1448 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 1449 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 1450 HDMI_VP_STUFF_PP_STUFFING_MASK | 1451 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 1452 1453 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 1454 HDMI_VP_CONF); 1455 } 1456 1457 static void hdmi_video_sample(struct dw_hdmi *hdmi) 1458 { 1459 int color_format = 0; 1460 u8 val; 1461 1462 switch (hdmi->hdmi_data.enc_in_bus_format) { 1463 case MEDIA_BUS_FMT_RGB888_1X24: 1464 color_format = 0x01; 1465 break; 1466 case MEDIA_BUS_FMT_RGB101010_1X30: 1467 color_format = 0x03; 1468 break; 1469 case MEDIA_BUS_FMT_RGB121212_1X36: 1470 color_format = 0x05; 1471 break; 1472 case MEDIA_BUS_FMT_RGB161616_1X48: 1473 color_format = 0x07; 1474 break; 1475 1476 case MEDIA_BUS_FMT_YUV8_1X24: 1477 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1478 color_format = 0x09; 1479 break; 1480 case MEDIA_BUS_FMT_YUV10_1X30: 1481 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1482 color_format = 0x0B; 1483 break; 1484 case MEDIA_BUS_FMT_YUV12_1X36: 1485 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 1486 color_format = 0x0D; 1487 break; 1488 case MEDIA_BUS_FMT_YUV16_1X48: 1489 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 1490 color_format = 0x0F; 1491 break; 1492 1493 case MEDIA_BUS_FMT_UYVY8_1X16: 1494 color_format = 0x16; 1495 break; 1496 case MEDIA_BUS_FMT_UYVY10_1X20: 1497 color_format = 0x14; 1498 break; 1499 case MEDIA_BUS_FMT_UYVY12_1X24: 1500 color_format = 0x12; 1501 break; 1502 1503 default: 1504 return; 1505 } 1506 1507 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 1508 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 1509 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 1510 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 1511 1512 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 1513 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 1514 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 1515 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 1516 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 1517 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 1518 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 1519 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 1520 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 1521 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 1522 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 1523 } 1524 1525 static void dw_hdmi_disable(struct dw_hdmi *hdmi, struct display_state *state) 1526 { 1527 if (hdmi->phy.enabled) { 1528 hdmi->phy.ops->disable(hdmi, state); 1529 hdmi->phy.enabled = false; 1530 } 1531 } 1532 1533 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1534 { 1535 struct hdmi_avi_infoframe frame; 1536 u8 val; 1537 bool is_hdmi2 = false; 1538 enum hdmi_quantization_range rgb_quant_range = 1539 hdmi->hdmi_data.quant_range; 1540 1541 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) || 1542 hdmi->edid_data.display_info.hdmi.scdc.supported) 1543 is_hdmi2 = true; 1544 /* Initialise info frame from DRM mode */ 1545 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2); 1546 1547 /* 1548 * Ignore monitor selectable quantization, use quantization set 1549 * by the user 1550 */ 1551 drm_hdmi_avi_infoframe_quant_range(&frame, mode, rgb_quant_range, 1552 true); 1553 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1554 frame.colorspace = HDMI_COLORSPACE_YUV444; 1555 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1556 frame.colorspace = HDMI_COLORSPACE_YUV422; 1557 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1558 frame.colorspace = HDMI_COLORSPACE_YUV420; 1559 else 1560 frame.colorspace = HDMI_COLORSPACE_RGB; 1561 1562 /* Set up colorimetry */ 1563 switch (hdmi->hdmi_data.enc_out_encoding) { 1564 case V4L2_YCBCR_ENC_601: 1565 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1566 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1567 else 1568 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1569 frame.extended_colorimetry = 1570 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1571 break; 1572 case V4L2_YCBCR_ENC_709: 1573 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1574 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1575 else 1576 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1577 frame.extended_colorimetry = 1578 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1579 break; 1580 default: /* Carries no data */ 1581 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1582 frame.extended_colorimetry = 1583 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1584 break; 1585 } 1586 1587 frame.scan_mode = HDMI_SCAN_MODE_NONE; 1588 1589 /* 1590 * The Designware IP uses a different byte format from standard 1591 * AVI info frames, though generally the bits are in the correct 1592 * bytes. 1593 */ 1594 1595 /* 1596 * AVI data byte 1 differences: Colorspace in bits 0,1,7 rather than 1597 * 5,6,7, active aspect present in bit 6 rather than 4. 1598 */ 1599 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 0x3); 1600 if (frame.active_aspect & 15) 1601 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1602 if (frame.top_bar || frame.bottom_bar) 1603 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1604 if (frame.left_bar || frame.right_bar) 1605 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1606 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1607 1608 /* AVI data byte 2 differences: none */ 1609 val = ((frame.colorimetry & 0x3) << 6) | 1610 ((frame.picture_aspect & 0x3) << 4) | 1611 (frame.active_aspect & 0xf); 1612 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1613 1614 /* AVI data byte 3 differences: none */ 1615 val = ((frame.extended_colorimetry & 0x7) << 4) | 1616 ((frame.quantization_range & 0x3) << 2) | 1617 (frame.nups & 0x3); 1618 if (frame.itc) 1619 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1620 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1621 1622 /* AVI data byte 4 differences: none */ 1623 val = frame.video_code & 0x7f; 1624 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1625 1626 /* AVI Data Byte 5- set up input and output pixel repetition */ 1627 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1628 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1629 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1630 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1631 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1632 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1633 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1634 1635 /* 1636 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1637 * ycc range in bits 2,3 rather than 6,7 1638 */ 1639 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1640 (frame.content_type & 0x3); 1641 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1642 1643 /* AVI Data Bytes 6-13 */ 1644 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1645 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1646 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1647 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1648 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1649 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1650 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1651 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1652 } 1653 1654 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1655 struct drm_display_mode *mode) 1656 { 1657 struct hdmi_vendor_infoframe frame; 1658 u8 buffer[10]; 1659 ssize_t err; 1660 1661 /* Disable HDMI vendor specific infoframe send */ 1662 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1663 HDMI_FC_DATAUTO0_VSD_MASK); 1664 1665 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode); 1666 if (err < 0) 1667 /* 1668 * Going into that statement does not means vendor infoframe 1669 * fails. It just informed us that vendor infoframe is not 1670 * needed for the selected mode. Only 4k or stereoscopic 3D 1671 * mode requires vendor infoframe. So just simply return. 1672 */ 1673 return; 1674 1675 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1676 if (err < 0) { 1677 printf("Failed to pack vendor infoframe: %zd\n", err); 1678 return; 1679 } 1680 1681 /* Set the length of HDMI vendor specific InfoFrame payload */ 1682 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1683 1684 /* Set 24bit IEEE Registration Identifier */ 1685 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1686 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1687 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1688 1689 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1690 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1691 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1692 1693 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1694 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1695 1696 /* Packet frame interpolation */ 1697 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1698 1699 /* Auto packets per frame and line spacing */ 1700 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1701 1702 /* Configures the Frame Composer On RDRB mode */ 1703 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1704 HDMI_FC_DATAUTO0_VSD_MASK); 1705 } 1706 1707 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 1708 unsigned int n) 1709 { 1710 /* Must be set/cleared first */ 1711 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 1712 1713 /* nshift factor = 0 */ 1714 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 1715 1716 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 1717 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 1718 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 1719 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 1720 1721 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 1722 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 1723 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 1724 } 1725 1726 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi, 1727 unsigned long pixel_clk, 1728 unsigned long freq) 1729 { 1730 const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data; 1731 const struct dw_hdmi_audio_tmds_n *tmds_n = NULL; 1732 int i; 1733 1734 if (plat_data->tmds_n_table) { 1735 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) { 1736 if (pixel_clk == plat_data->tmds_n_table[i].tmds) { 1737 tmds_n = &plat_data->tmds_n_table[i]; 1738 break; 1739 } 1740 } 1741 } 1742 1743 if (!tmds_n) { 1744 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) { 1745 if (pixel_clk == common_tmds_n_table[i].tmds) { 1746 tmds_n = &common_tmds_n_table[i]; 1747 break; 1748 } 1749 } 1750 } 1751 1752 if (!tmds_n) 1753 return -ENOENT; 1754 1755 switch (freq) { 1756 case 32000: 1757 return tmds_n->n_32k; 1758 case 44100: 1759 case 88200: 1760 case 176400: 1761 return (freq / 44100) * tmds_n->n_44k1; 1762 case 48000: 1763 case 96000: 1764 case 192000: 1765 return (freq / 48000) * tmds_n->n_48k; 1766 default: 1767 return -ENOENT; 1768 } 1769 } 1770 1771 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n, 1772 unsigned int pixel_clk) 1773 { 1774 u64 final, diff; 1775 u64 cts; 1776 1777 final = (u64)pixel_clk * n; 1778 1779 cts = final; 1780 do_div(cts, 128 * freq); 1781 1782 diff = final - (u64)cts * (128 * freq); 1783 1784 return diff; 1785 } 1786 1787 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi, 1788 unsigned long pixel_clk, 1789 unsigned long freq) 1790 { 1791 unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500); 1792 unsigned int max_n = (128 * freq) / 300; 1793 unsigned int ideal_n = (128 * freq) / 1000; 1794 unsigned int best_n_distance = ideal_n; 1795 unsigned int best_n = 0; 1796 u64 best_diff = U64_MAX; 1797 int n; 1798 1799 /* If the ideal N could satisfy the audio math, then just take it */ 1800 if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0) 1801 return ideal_n; 1802 1803 for (n = min_n; n <= max_n; n++) { 1804 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk); 1805 1806 if (diff < best_diff || (diff == best_diff && 1807 abs(n - ideal_n) < best_n_distance)) { 1808 best_n = n; 1809 best_diff = diff; 1810 best_n_distance = abs(best_n - ideal_n); 1811 } 1812 1813 /* 1814 * The best N already satisfy the audio math, and also be 1815 * the closest value to ideal N, so just cut the loop. 1816 */ 1817 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance)) 1818 break; 1819 } 1820 1821 return best_n; 1822 } 1823 1824 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk, 1825 unsigned long sample_rate) 1826 { 1827 int n; 1828 1829 n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate); 1830 if (n > 0) 1831 return n; 1832 1833 printf("Rate %lu missing; compute N dynamically\n", 1834 pixel_clk); 1835 1836 return hdmi_compute_n(hdmi, pixel_clk, sample_rate); 1837 } 1838 1839 static 1840 void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, unsigned long pixel_clk, 1841 unsigned int sample_rate) 1842 { 1843 unsigned long ftdms = pixel_clk; 1844 unsigned int n, cts; 1845 u64 tmp; 1846 1847 n = hdmi_find_n(hdmi, pixel_clk, sample_rate); 1848 1849 /* 1850 * Compute the CTS value from the N value. Note that CTS and N 1851 * can be up to 20 bits in total, so we need 64-bit math. Also 1852 * note that our TDMS clock is not fully accurate; it is accurate 1853 * to kHz. This can introduce an unnecessary remainder in the 1854 * calculation below, so we don't try to warn about that. 1855 */ 1856 tmp = (u64)ftdms * n; 1857 do_div(tmp, 128 * sample_rate); 1858 cts = tmp; 1859 1860 printf("%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", __func__, 1861 sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000, n, cts); 1862 1863 hdmi->audio_n = n; 1864 hdmi->audio_cts = cts; 1865 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 1866 } 1867 1868 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 1869 { 1870 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 1871 hdmi->sample_rate); 1872 } 1873 1874 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi) 1875 { 1876 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS); 1877 } 1878 1879 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 1880 { 1881 hdmi->sample_rate = rate; 1882 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 1883 hdmi->sample_rate); 1884 } 1885 1886 static int dw_hdmi_hdcp_load_key(struct dw_hdmi *hdmi) 1887 { 1888 int i, j, ret, val; 1889 struct hdcp_keys *hdcp_keys; 1890 1891 val = sizeof(*hdcp_keys); 1892 hdcp_keys = malloc(val); 1893 if (!hdcp_keys) 1894 return -ENOMEM; 1895 1896 memset(hdcp_keys, 0, val); 1897 1898 ret = vendor_storage_read(HDMI_HDCP1X_ID, hdcp_keys, val); 1899 if (ret < val) { 1900 printf("HDCP: read size %d\n", ret); 1901 free(hdcp_keys); 1902 return -EINVAL; 1903 } 1904 1905 if (hdcp_keys->KSV[0] == 0x00 && 1906 hdcp_keys->KSV[1] == 0x00 && 1907 hdcp_keys->KSV[2] == 0x00 && 1908 hdcp_keys->KSV[3] == 0x00 && 1909 hdcp_keys->KSV[4] == 0x00) { 1910 printf("HDCP: Invalid hdcp key\n"); 1911 free(hdcp_keys); 1912 return -EINVAL; 1913 } 1914 1915 /* Disable decryption logic */ 1916 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_RMCTL); 1917 /* Poll untile DPK write is allowed */ 1918 do { 1919 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1920 } while ((val & DPK_WR_OK_STS) == 0); 1921 1922 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_DPK6); 1923 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_DPK5); 1924 1925 /* The useful data in ksv should be 5 byte */ 1926 for (i = 4; i >= 0; i--) 1927 hdmi_writeb(hdmi, hdcp_keys->KSV[i], HDMI_HDCPREG_DPK0 + i); 1928 /* Poll untile DPK write is allowed */ 1929 do { 1930 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1931 } while ((val & DPK_WR_OK_STS) == 0); 1932 1933 /* Enable decryption logic */ 1934 hdmi_writeb(hdmi, 1, HDMI_HDCPREG_RMCTL); 1935 hdmi_writeb(hdmi, hdcp_keys->seeds[0], HDMI_HDCPREG_SEED1); 1936 hdmi_writeb(hdmi, hdcp_keys->seeds[1], HDMI_HDCPREG_SEED0); 1937 1938 /* Write encrypt device private key */ 1939 for (i = 0; i < DW_HDMI_HDCP_DPK_LEN - 6; i += 7) { 1940 for (j = 6; j >= 0; j--) 1941 hdmi_writeb(hdmi, hdcp_keys->devicekey[i + j], 1942 HDMI_HDCPREG_DPK0 + j); 1943 do { 1944 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1945 } while ((val & DPK_WR_OK_STS) == 0); 1946 } 1947 1948 free(hdcp_keys); 1949 return 0; 1950 } 1951 1952 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi, 1953 const struct drm_display_mode *mode) 1954 { 1955 u8 vsync_pol, hsync_pol, data_pol, hdmi_dvi; 1956 1957 if (!hdmi->hdcp1x_enable) 1958 return; 1959 1960 /* Configure the video polarity */ 1961 vsync_pol = mode->flags & DRM_MODE_FLAG_PVSYNC ? 1962 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH : 1963 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW; 1964 hsync_pol = mode->flags & DRM_MODE_FLAG_PHSYNC ? 1965 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH : 1966 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW; 1967 data_pol = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1968 hdmi_modb(hdmi, vsync_pol | hsync_pol | data_pol, 1969 HDMI_A_VIDPOLCFG_VSYNCPOL_MASK | 1970 HDMI_A_VIDPOLCFG_HSYNCPOL_MASK | 1971 HDMI_A_VIDPOLCFG_DATAENPOL_MASK, 1972 HDMI_A_VIDPOLCFG); 1973 1974 /* Config the display mode */ 1975 hdmi_dvi = hdmi->sink_is_hdmi ? HDMI_A_HDCPCFG0_HDMIDVI_HDMI : 1976 HDMI_A_HDCPCFG0_HDMIDVI_DVI; 1977 hdmi_modb(hdmi, hdmi_dvi, HDMI_A_HDCPCFG0_HDMIDVI_MASK, 1978 HDMI_A_HDCPCFG0); 1979 1980 if (!(hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS) & 0x3f)) 1981 dw_hdmi_hdcp_load_key(hdmi); 1982 1983 hdmi_modb(hdmi, HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE, 1984 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK, 1985 HDMI_FC_INVIDCONF); 1986 1987 if (hdmi_readb(hdmi, HDMI_CONFIG1_ID) & HDMI_A_HDCP22_MASK) { 1988 hdmi_modb(hdmi, HDMI_HDCP2_OVR_ENABLE | 1989 HDMI_HDCP2_FORCE_DISABLE, 1990 HDMI_HDCP2_OVR_EN_MASK | 1991 HDMI_HDCP2_FORCE_MASK, 1992 HDMI_HDCP2REG_CTRL); 1993 hdmi_writeb(hdmi, 0xff, HDMI_HDCP2REG_MASK); 1994 hdmi_writeb(hdmi, 0xff, HDMI_HDCP2REG_MUTE); 1995 } 1996 1997 hdmi_writeb(hdmi, 0x40, HDMI_A_OESSWCFG); 1998 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE | 1999 HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE | 2000 HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE, 2001 HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK | 2002 HDMI_A_HDCPCFG0_EN11FEATURE_MASK | 2003 HDMI_A_HDCPCFG0_SYNCRICHECK_MASK, HDMI_A_HDCPCFG0); 2004 2005 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE | 2006 HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE, 2007 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK | 2008 HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK, HDMI_A_HDCPCFG1); 2009 2010 /* Reset HDCP Engine */ 2011 if (hdmi_readb(hdmi, HDMI_MC_CLKDIS) & HDMI_MC_CLKDIS_HDCPCLK_MASK) { 2012 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_SWRESET_ASSERT, 2013 HDMI_A_HDCPCFG1_SWRESET_MASK, HDMI_A_HDCPCFG1); 2014 } 2015 2016 hdmi_writeb(hdmi, 0x00, HDMI_A_APIINTMSK); 2017 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_ENABLE, 2018 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 2019 2020 hdmi_modb(hdmi, HDMI_MC_CLKDIS_HDCPCLK_ENABLE, 2021 HDMI_MC_CLKDIS_HDCPCLK_MASK, HDMI_MC_CLKDIS); 2022 2023 printf("%s success\n", __func__); 2024 } 2025 2026 static int dw_hdmi_setup(struct dw_hdmi *hdmi, 2027 struct drm_display_mode *mode, 2028 struct display_state *state) 2029 { 2030 int ret; 2031 void *data = hdmi->plat_data->phy_data; 2032 2033 hdmi_disable_overflow_interrupts(hdmi); 2034 if (!hdmi->vic) 2035 printf("Non-CEA mode used in HDMI\n"); 2036 else 2037 printf("CEA mode used vic=%d\n", hdmi->vic); 2038 2039 if (hdmi->plat_data->get_enc_out_encoding) 2040 hdmi->hdmi_data.enc_out_encoding = 2041 hdmi->plat_data->get_enc_out_encoding(data); 2042 else if (hdmi->vic == 6 || hdmi->vic == 7 || 2043 hdmi->vic == 21 || hdmi->vic == 22 || 2044 hdmi->vic == 2 || hdmi->vic == 3 || 2045 hdmi->vic == 17 || hdmi->vic == 18) 2046 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 2047 else 2048 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 2049 2050 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2051 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1; 2052 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1; 2053 } else { 2054 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 2055 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 2056 } 2057 2058 /* TOFIX: Get input encoding from plat data or fallback to none */ 2059 if (hdmi->plat_data->get_enc_in_encoding) 2060 hdmi->hdmi_data.enc_in_encoding = 2061 hdmi->plat_data->get_enc_in_encoding(data); 2062 else if (hdmi->plat_data->input_bus_encoding) 2063 hdmi->hdmi_data.enc_in_encoding = 2064 hdmi->plat_data->input_bus_encoding; 2065 else 2066 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 2067 2068 if (hdmi->plat_data->get_quant_range) 2069 hdmi->hdmi_data.quant_range = 2070 hdmi->plat_data->get_quant_range(data); 2071 else 2072 hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 2073 2074 /* 2075 * According to the dw-hdmi specification 6.4.2 2076 * vp_pr_cd[3:0]: 2077 * 0000b: No pixel repetition (pixel sent only once) 2078 * 0001b: Pixel sent two times (pixel repeated once) 2079 */ 2080 hdmi->hdmi_data.pix_repet_factor = 2081 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0; 2082 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 2083 2084 /* HDMI Initialization Step B.1 */ 2085 hdmi_av_composer(hdmi, mode); 2086 2087 /* HDMI Initialization Step B.2 */ 2088 ret = hdmi->phy.ops->init(hdmi, state); 2089 if (ret) 2090 return ret; 2091 hdmi->phy.enabled = true; 2092 2093 /* HDMI Initializateion Step B.3 */ 2094 dw_hdmi_enable_video_path(hdmi); 2095 2096 /* HDMI Initialization Step E - Configure audio */ 2097 if (hdmi->sink_has_audio) { 2098 printf("sink has audio support\n"); 2099 hdmi_clk_regenerator_update_pixel_clock(hdmi); 2100 hdmi_enable_audio_clk(hdmi); 2101 } 2102 2103 /* not for DVI mode */ 2104 if (hdmi->sink_is_hdmi) { 2105 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 2106 hdmi_config_AVI(hdmi, mode); 2107 hdmi_config_vendor_specific_infoframe(hdmi, mode); 2108 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_HDMIDVI_HDMI, 2109 HDMI_A_HDCPCFG0_HDMIDVI_MASK, 2110 HDMI_A_HDCPCFG0); 2111 } else { 2112 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_HDMIDVI_DVI, 2113 HDMI_A_HDCPCFG0_HDMIDVI_MASK, 2114 HDMI_A_HDCPCFG0); 2115 printf("%s DVI mode\n", __func__); 2116 } 2117 2118 hdmi_video_packetize(hdmi); 2119 hdmi_video_csc(hdmi); 2120 hdmi_video_sample(hdmi); 2121 hdmi_tx_hdcp_config(hdmi, mode); 2122 dw_hdmi_clear_overflow(hdmi); 2123 2124 return 0; 2125 } 2126 2127 int dw_hdmi_detect_hotplug(struct dw_hdmi *hdmi, 2128 struct display_state *state) 2129 { 2130 return hdmi->phy.ops->read_hpd(hdmi, state); 2131 } 2132 2133 static int dw_hdmi_set_reg_wr(struct dw_hdmi *hdmi) 2134 { 2135 switch (hdmi->io_width) { 2136 case 4: 2137 hdmi->write = dw_hdmi_writel; 2138 hdmi->read = dw_hdmi_readl; 2139 break; 2140 case 1: 2141 hdmi->write = dw_hdmi_writeb; 2142 hdmi->read = dw_hdmi_readb; 2143 break; 2144 default: 2145 printf("reg-io-width must be 1 or 4\n"); 2146 return -EINVAL; 2147 } 2148 2149 return 0; 2150 } 2151 2152 static void initialize_hdmi_mutes(struct dw_hdmi *hdmi) 2153 { 2154 /*mute unnecessary interrupt, only enable hpd */ 2155 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 2156 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 2157 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 2158 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 2159 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 2160 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 2161 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 2162 hdmi_writeb(hdmi, 0xfe, HDMI_IH_MUTE_PHY_STAT0); 2163 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 2164 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 2165 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 2166 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 2167 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 2168 hdmi_writeb(hdmi, 0xf1, HDMI_PHY_MASK0); 2169 2170 /*Force output black*/ 2171 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS2); 2172 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS1); 2173 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS0); 2174 } 2175 2176 static void dw_hdmi_dev_init(struct dw_hdmi *hdmi) 2177 { 2178 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 2179 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 2180 2181 initialize_hdmi_mutes(hdmi); 2182 } 2183 2184 static void dw_hdmi_i2c_set_divs(struct dw_hdmi *hdmi) 2185 { 2186 unsigned long low_ns, high_ns; 2187 unsigned long div_low, div_high; 2188 2189 /* Standard-mode */ 2190 if (hdmi->i2c->scl_high_ns < 4000) 2191 high_ns = 4708; 2192 else 2193 high_ns = hdmi->i2c->scl_high_ns; 2194 2195 if (hdmi->i2c->scl_low_ns < 4700) 2196 low_ns = 4916; 2197 else 2198 low_ns = hdmi->i2c->scl_low_ns; 2199 2200 div_low = (24000 * low_ns) / 1000000; 2201 if ((24000 * low_ns) % 1000000) 2202 div_low++; 2203 2204 div_high = (24000 * high_ns) / 1000000; 2205 if ((24000 * high_ns) % 1000000) 2206 div_high++; 2207 2208 /* Maximum divider supported by hw is 0xffff */ 2209 if (div_low > 0xffff) 2210 div_low = 0xffff; 2211 2212 if (div_high > 0xffff) 2213 div_high = 0xffff; 2214 2215 hdmi_writeb(hdmi, div_high & 0xff, HDMI_I2CM_SS_SCL_HCNT_0_ADDR); 2216 hdmi_writeb(hdmi, (div_high >> 8) & 0xff, 2217 HDMI_I2CM_SS_SCL_HCNT_1_ADDR); 2218 hdmi_writeb(hdmi, div_low & 0xff, HDMI_I2CM_SS_SCL_LCNT_0_ADDR); 2219 hdmi_writeb(hdmi, (div_low >> 8) & 0xff, 2220 HDMI_I2CM_SS_SCL_LCNT_1_ADDR); 2221 } 2222 2223 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 2224 { 2225 /* Software reset */ 2226 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 2227 2228 /* Set Standard Mode speed */ 2229 hdmi_modb(hdmi, HDMI_I2CM_DIV_STD_MODE, 2230 HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV); 2231 2232 /* Set done, not acknowledged and arbitration interrupt polarities */ 2233 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 2234 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 2235 HDMI_I2CM_CTLINT); 2236 2237 /* Clear DONE and ERROR interrupts */ 2238 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 2239 HDMI_IH_I2CM_STAT0); 2240 2241 /* Mute DONE and ERROR interrupts */ 2242 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 2243 HDMI_IH_MUTE_I2CM_STAT0); 2244 2245 /* set SDA high level holding time */ 2246 hdmi_writeb(hdmi, 0x48, HDMI_I2CM_SDA_HOLD); 2247 2248 dw_hdmi_i2c_set_divs(hdmi); 2249 } 2250 2251 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 2252 { 2253 hdmi->audio_enable = true; 2254 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 2255 } 2256 2257 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 2258 { 2259 hdmi->audio_enable = false; 2260 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 2261 } 2262 2263 int rockchip_dw_hdmi_init(struct display_state *state) 2264 { 2265 struct connector_state *conn_state = &state->conn_state; 2266 const struct rockchip_connector *connector = conn_state->connector; 2267 const struct dw_hdmi_plat_data *pdata = connector->data; 2268 struct crtc_state *crtc_state = &state->crtc_state; 2269 struct dw_hdmi *hdmi; 2270 struct drm_display_mode *mode_buf; 2271 ofnode hdmi_node = conn_state->node; 2272 u32 val; 2273 2274 hdmi = malloc(sizeof(struct dw_hdmi)); 2275 if (!hdmi) 2276 return -ENOMEM; 2277 2278 memset(hdmi, 0, sizeof(struct dw_hdmi)); 2279 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 2280 if (!mode_buf) 2281 return -ENOMEM; 2282 2283 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 2284 2285 hdmi->regs = dev_read_addr_ptr(conn_state->dev); 2286 hdmi->io_width = ofnode_read_s32_default(hdmi_node, "reg-io-width", -1); 2287 2288 if (ofnode_read_bool(hdmi_node, "scramble-low-rates")) 2289 hdmi->scramble_low_rates = true; 2290 2291 if (ofnode_read_bool(hdmi_node, "hdcp1x-enable")) 2292 hdmi->hdcp1x_enable = true; 2293 else 2294 hdmi->hdcp1x_enable = false; 2295 2296 hdmi->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 2297 if (hdmi->grf <= 0) { 2298 printf("%s: Get syscon grf failed (ret=%p)\n", 2299 __func__, hdmi->grf); 2300 return -ENXIO; 2301 } 2302 2303 dw_hdmi_set_reg_wr(hdmi); 2304 2305 if (pdata->grf_vop_sel_reg) { 2306 if (crtc_state->crtc_id) 2307 val = ((1 << pdata->vop_sel_bit) | 2308 (1 << (16 + pdata->vop_sel_bit))); 2309 else 2310 val = ((0 << pdata->vop_sel_bit) | 2311 (1 << (16 + pdata->vop_sel_bit))); 2312 writel(val, hdmi->grf + pdata->grf_vop_sel_reg); 2313 } 2314 2315 hdmi->i2c = malloc(sizeof(struct dw_hdmi_i2c)); 2316 if (!hdmi->i2c) 2317 return -ENOMEM; 2318 hdmi->adap.ddc_xfer = dw_hdmi_i2c_xfer; 2319 2320 /* 2321 * Read high and low time from device tree. If not available use 2322 * the default timing scl clock rate is about 99.6KHz. 2323 */ 2324 hdmi->i2c->scl_high_ns = 2325 ofnode_read_s32_default(hdmi_node, 2326 "ddc-i2c-scl-high-time-ns", 4708); 2327 hdmi->i2c->scl_low_ns = 2328 ofnode_read_s32_default(hdmi_node, 2329 "ddc-i2c-scl-low-time-ns", 4916); 2330 2331 dw_hdmi_i2c_init(hdmi); 2332 conn_state->type = DRM_MODE_CONNECTOR_HDMIA; 2333 conn_state->output_if |= VOP_OUTPUT_IF_HDMI0; 2334 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 2335 2336 hdmi->dev_type = pdata->dev_type; 2337 hdmi->plat_data = pdata; 2338 hdmi->edid_data.mode_buf = mode_buf; 2339 hdmi->sample_rate = 48000; 2340 2341 conn_state->private = hdmi; 2342 dw_hdmi_set_iomux(hdmi->grf, hdmi->dev_type); 2343 dw_hdmi_detect_phy(hdmi); 2344 dw_hdmi_dev_init(hdmi); 2345 2346 return 0; 2347 } 2348 2349 void rockchip_dw_hdmi_deinit(struct display_state *state) 2350 { 2351 struct connector_state *conn_state = &state->conn_state; 2352 struct dw_hdmi *hdmi = conn_state->private; 2353 2354 if (hdmi->i2c) 2355 free(hdmi->i2c); 2356 if (hdmi->edid_data.mode_buf) 2357 free(hdmi->edid_data.mode_buf); 2358 if (hdmi) 2359 free(hdmi); 2360 } 2361 2362 int rockchip_dw_hdmi_prepare(struct display_state *state) 2363 { 2364 return 0; 2365 } 2366 2367 int rockchip_dw_hdmi_enable(struct display_state *state) 2368 { 2369 struct connector_state *conn_state = &state->conn_state; 2370 struct drm_display_mode *mode = &conn_state->mode; 2371 struct dw_hdmi *hdmi = conn_state->private; 2372 2373 if (!hdmi) 2374 return -EFAULT; 2375 2376 /* Store the display mode for plugin/DKMS poweron events */ 2377 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 2378 2379 dw_hdmi_setup(hdmi, mode, state); 2380 2381 return 0; 2382 } 2383 2384 int rockchip_dw_hdmi_disable(struct display_state *state) 2385 { 2386 struct connector_state *conn_state = &state->conn_state; 2387 struct dw_hdmi *hdmi = conn_state->private; 2388 2389 dw_hdmi_disable(hdmi, state); 2390 return 0; 2391 } 2392 2393 int rockchip_dw_hdmi_get_timing(struct display_state *state) 2394 { 2395 int ret, i; 2396 struct connector_state *conn_state = &state->conn_state; 2397 struct drm_display_mode *mode = &conn_state->mode; 2398 struct dw_hdmi *hdmi = conn_state->private; 2399 struct edid *edid = (struct edid *)conn_state->edid; 2400 unsigned int bus_format; 2401 unsigned long enc_out_encoding; 2402 struct overscan *overscan = &conn_state->overscan; 2403 const u8 def_modes_vic[6] = {4, 16, 2, 17, 31, 19}; 2404 2405 if (!hdmi) 2406 return -EFAULT; 2407 2408 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 2409 2410 if (!ret) { 2411 hdmi->sink_is_hdmi = 2412 drm_detect_hdmi_monitor(edid); 2413 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 2414 ret = drm_add_edid_modes(&hdmi->edid_data, conn_state->edid); 2415 } 2416 if (ret <= 0) { 2417 hdmi->sink_is_hdmi = true; 2418 hdmi->sink_has_audio = true; 2419 do_cea_modes(&hdmi->edid_data, def_modes_vic, 2420 sizeof(def_modes_vic)); 2421 hdmi->edid_data.preferred_mode = &hdmi->edid_data.mode_buf[0]; 2422 printf("failed to get edid\n"); 2423 } 2424 drm_rk_filter_whitelist(&hdmi->edid_data); 2425 if (hdmi->phy.ops->mode_valid) 2426 hdmi->phy.ops->mode_valid(hdmi, state); 2427 drm_mode_max_resolution_filter(&hdmi->edid_data, 2428 &state->crtc_state.max_output); 2429 if (!drm_mode_prune_invalid(&hdmi->edid_data)) { 2430 printf("can't find valid hdmi mode\n"); 2431 return -EINVAL; 2432 } 2433 2434 for (i = 0; i < hdmi->edid_data.modes; i++) 2435 hdmi->edid_data.mode_buf[i].vrefresh = 2436 drm_mode_vrefresh(&hdmi->edid_data.mode_buf[i]); 2437 2438 drm_mode_sort(&hdmi->edid_data); 2439 drm_rk_selete_output(&hdmi->edid_data, &bus_format, 2440 overscan, hdmi->dev_type); 2441 2442 *mode = *hdmi->edid_data.preferred_mode; 2443 hdmi->vic = drm_match_cea_mode(mode); 2444 2445 printf("mode:%dx%d\n", mode->hdisplay, mode->vdisplay); 2446 conn_state->bus_format = bus_format; 2447 hdmi->hdmi_data.enc_in_bus_format = bus_format; 2448 hdmi->hdmi_data.enc_out_bus_format = bus_format; 2449 2450 switch (bus_format) { 2451 case MEDIA_BUS_FMT_UYVY10_1X20: 2452 conn_state->bus_format = MEDIA_BUS_FMT_YUV10_1X30; 2453 hdmi->hdmi_data.enc_in_bus_format = 2454 MEDIA_BUS_FMT_YUV10_1X30; 2455 break; 2456 case MEDIA_BUS_FMT_UYVY8_1X16: 2457 conn_state->bus_format = MEDIA_BUS_FMT_YUV8_1X24; 2458 hdmi->hdmi_data.enc_in_bus_format = 2459 MEDIA_BUS_FMT_YUV8_1X24; 2460 break; 2461 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 2462 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 2463 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420; 2464 break; 2465 } 2466 2467 if (hdmi->vic == 6 || hdmi->vic == 7 || hdmi->vic == 21 || 2468 hdmi->vic == 22 || hdmi->vic == 2 || hdmi->vic == 3 || 2469 hdmi->vic == 17 || hdmi->vic == 18) 2470 enc_out_encoding = V4L2_YCBCR_ENC_601; 2471 else 2472 enc_out_encoding = V4L2_YCBCR_ENC_709; 2473 2474 if (enc_out_encoding == V4L2_YCBCR_ENC_BT2020) 2475 conn_state->color_space = V4L2_COLORSPACE_BT2020; 2476 else if (bus_format == MEDIA_BUS_FMT_RGB888_1X24 || 2477 bus_format == MEDIA_BUS_FMT_RGB101010_1X30) 2478 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 2479 else if (enc_out_encoding == V4L2_YCBCR_ENC_709) 2480 conn_state->color_space = V4L2_COLORSPACE_REC709; 2481 else 2482 conn_state->color_space = V4L2_COLORSPACE_SMPTE170M; 2483 2484 return 0; 2485 } 2486 2487 int rockchip_dw_hdmi_detect(struct display_state *state) 2488 { 2489 int ret; 2490 struct connector_state *conn_state = &state->conn_state; 2491 struct dw_hdmi *hdmi = conn_state->private; 2492 2493 if (!hdmi) 2494 return -EFAULT; 2495 2496 ret = dw_hdmi_detect_hotplug(hdmi, state); 2497 2498 return ret; 2499 } 2500 2501 int rockchip_dw_hdmi_get_edid(struct display_state *state) 2502 { 2503 int ret; 2504 struct connector_state *conn_state = &state->conn_state; 2505 struct dw_hdmi *hdmi = conn_state->private; 2506 2507 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 2508 2509 return ret; 2510 } 2511 2512 int inno_dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data) 2513 { 2514 struct display_state *state = (struct display_state *)data; 2515 struct connector_state *conn_state = &state->conn_state; 2516 u32 color_depth, bus_width; 2517 2518 color_depth = 2519 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 2520 2521 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 2522 bus_width = color_depth / 2; 2523 else if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 2524 bus_width = color_depth; 2525 else 2526 bus_width = 8; 2527 rockchip_phy_set_bus_width(conn_state->phy, bus_width); 2528 rockchip_phy_set_pll(conn_state->phy, 2529 conn_state->mode.crtc_clock * 1000); 2530 if (hdmi->edid_data.display_info.hdmi.scdc.supported) 2531 rockchip_dw_hdmi_scdc_set_tmds_rate(hdmi); 2532 rockchip_phy_power_on(conn_state->phy); 2533 2534 return 0; 2535 } 2536 2537 void inno_dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 2538 { 2539 } 2540 2541 enum drm_connector_status 2542 inno_dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data) 2543 { 2544 enum drm_connector_status status; 2545 struct display_state *state = (struct display_state *)data; 2546 2547 status = dw_hdmi_phy_read_hpd(hdmi, state); 2548 2549 if (hdmi->dev_type == RK3328_HDMI) { 2550 if (status == connector_status_connected) 2551 inno_dw_hdmi_set_domain(hdmi->grf, 1); 2552 else 2553 inno_dw_hdmi_set_domain(hdmi->grf, 0); 2554 } 2555 2556 return status; 2557 } 2558 2559 void inno_dw_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data) 2560 { 2561 struct display_state *state = (struct display_state *)data; 2562 struct connector_state *conn_state = &state->conn_state; 2563 struct hdmi_edid_data *edid_data = &hdmi->edid_data; 2564 unsigned long rate; 2565 int i, ret; 2566 struct drm_display_mode *mode_buf = edid_data->mode_buf; 2567 2568 for (i = 0; i < edid_data->modes; i++) { 2569 if (edid_data->mode_buf[i].invalid) 2570 continue; 2571 if (edid_data->mode_buf[i].flags & DRM_MODE_FLAG_DBLCLK) 2572 rate = mode_buf[i].clock * 1000 * 2; 2573 else 2574 rate = mode_buf[i].clock * 1000; 2575 2576 /* Check whether mode is out of phy cfg range. */ 2577 ret = rockchip_phy_round_rate(conn_state->phy, rate); 2578 2579 if (ret < 0) 2580 edid_data->mode_buf[i].invalid = true; 2581 } 2582 } 2583