1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <syscon.h> 10 #include <asm/arch-rockchip/clock.h> 11 #include <asm/arch/vendor.h> 12 #include <edid.h> 13 #include <dm/device.h> 14 #include <dm/ofnode.h> 15 #include <dm/read.h> 16 #include <linux/hdmi.h> 17 #include <linux/media-bus-format.h> 18 #include <linux/dw_hdmi.h> 19 #include <asm/io.h> 20 #include "rockchip_display.h" 21 #include "rockchip_crtc.h" 22 #include "rockchip_connector.h" 23 #include "dw_hdmi.h" 24 #include "rockchip_phy.h" 25 26 #define HDCP_PRIVATE_KEY_SIZE 280 27 #define HDCP_KEY_SHA_SIZE 20 28 #define HDMI_HDCP1X_ID 5 29 /* 30 * Unless otherwise noted, entries in this table are 100% optimization. 31 * Values can be obtained from hdmi_compute_n() but that function is 32 * slow so we pre-compute values we expect to see. 33 * 34 * All 32k and 48k values are expected to be the same (due to the way 35 * the math works) for any rate that's an exact kHz. 36 */ 37 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = { 38 { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, }, 39 { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, }, 40 { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 41 { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, }, 42 { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, }, 43 { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, 44 { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, 45 { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 46 { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 47 { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, 48 { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 49 { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, 50 { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 51 { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 52 { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, }, 53 { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 54 { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, }, 55 { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 56 { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 57 { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, }, 58 { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, 59 { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, 60 { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, 61 { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 62 { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 63 { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 64 { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 65 { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 66 { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, 67 { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 68 { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, }, 69 { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, 70 { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 71 { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 72 { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 73 { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, 74 { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 75 76 /* For 297 MHz+ HDMI spec have some other rule for setting N */ 77 { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, }, 78 { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, }, 79 80 /* End of table */ 81 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, }, 82 }; 83 84 static const u16 csc_coeff_default[3][4] = { 85 { 0x2000, 0x0000, 0x0000, 0x0000 }, 86 { 0x0000, 0x2000, 0x0000, 0x0000 }, 87 { 0x0000, 0x0000, 0x2000, 0x0000 } 88 }; 89 90 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 91 { 0x2000, 0x6926, 0x74fd, 0x010e }, 92 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 93 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 94 }; 95 96 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 97 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 98 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 99 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 100 }; 101 102 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 103 { 0x2591, 0x1322, 0x074b, 0x0000 }, 104 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 105 { 0x6acd, 0x7534, 0x2000, 0x0200 } 106 }; 107 108 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 109 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 110 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 111 { 0x6756, 0x78ab, 0x2000, 0x0200 } 112 }; 113 114 static const u16 csc_coeff_full_to_limited[3][4] = { 115 { 0x36f7, 0x0000, 0x0000, 0x0040 }, 116 { 0x0000, 0x36f7, 0x0000, 0x0040 }, 117 { 0x0000, 0x0000, 0x36f7, 0x0040 } 118 }; 119 120 struct hdmi_vmode { 121 bool mdataenablepolarity; 122 123 unsigned int mpixelclock; 124 unsigned int mpixelrepetitioninput; 125 unsigned int mpixelrepetitionoutput; 126 unsigned int mtmdsclock; 127 }; 128 129 struct hdmi_data_info { 130 unsigned int enc_in_bus_format; 131 unsigned int enc_out_bus_format; 132 unsigned int enc_in_encoding; 133 unsigned int enc_out_encoding; 134 unsigned int quant_range; 135 unsigned int pix_repet_factor; 136 struct hdmi_vmode video_mode; 137 }; 138 139 struct dw_hdmi_phy_data { 140 enum dw_hdmi_phy_type type; 141 const char *name; 142 unsigned int gen; 143 bool has_svsret; 144 int (*configure)(struct dw_hdmi *hdmi, 145 const struct dw_hdmi_plat_data *pdata, 146 unsigned long mpixelclock); 147 }; 148 149 struct hdcp_keys { 150 u8 KSV[8]; 151 u8 devicekey[HDCP_PRIVATE_KEY_SIZE]; 152 u8 sha1[HDCP_KEY_SHA_SIZE]; 153 u8 seeds[2]; 154 }; 155 156 struct dw_hdmi_i2c { 157 u8 slave_reg; 158 bool is_regaddr; 159 bool is_segment; 160 161 unsigned int scl_high_ns; 162 unsigned int scl_low_ns; 163 }; 164 165 struct dw_hdmi { 166 enum dw_hdmi_devtype dev_type; 167 unsigned int version; 168 struct hdmi_data_info hdmi_data; 169 struct hdmi_edid_data edid_data; 170 const struct dw_hdmi_plat_data *plat_data; 171 struct ddc_adapter adap; 172 173 int vic; 174 int io_width; 175 176 unsigned long bus_format; 177 bool cable_plugin; 178 bool sink_is_hdmi; 179 bool sink_has_audio; 180 void *regs; 181 void *grf; 182 struct dw_hdmi_i2c *i2c; 183 184 struct { 185 const struct dw_hdmi_phy_ops *ops; 186 const char *name; 187 void *data; 188 bool enabled; 189 } phy; 190 191 struct drm_display_mode previous_mode; 192 193 unsigned int sample_rate; 194 unsigned int audio_cts; 195 unsigned int audio_n; 196 bool audio_enable; 197 bool scramble_low_rates; 198 199 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset); 200 u8 (*read)(struct dw_hdmi *hdmi, int offset); 201 202 bool hdcp1x_enable; 203 }; 204 205 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset) 206 { 207 writel(val, hdmi->regs + (offset << 2)); 208 } 209 210 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset) 211 { 212 return readl(hdmi->regs + (offset << 2)); 213 } 214 215 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 216 { 217 writeb(val, hdmi->regs + offset); 218 } 219 220 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset) 221 { 222 return readb(hdmi->regs + offset); 223 } 224 225 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 226 { 227 hdmi->write(hdmi, val, offset); 228 } 229 230 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 231 { 232 return hdmi->read(hdmi, offset); 233 } 234 235 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 236 { 237 u8 val = hdmi_readb(hdmi, reg) & ~mask; 238 239 val |= data & mask; 240 hdmi_writeb(hdmi, val, reg); 241 } 242 243 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 244 u8 shift, u8 mask) 245 { 246 hdmi_modb(hdmi, data << shift, mask, reg); 247 } 248 249 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 250 { 251 switch (bus_format) { 252 case MEDIA_BUS_FMT_RGB888_1X24: 253 case MEDIA_BUS_FMT_RGB101010_1X30: 254 case MEDIA_BUS_FMT_RGB121212_1X36: 255 case MEDIA_BUS_FMT_RGB161616_1X48: 256 return true; 257 258 default: 259 return false; 260 } 261 } 262 263 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 264 { 265 switch (bus_format) { 266 case MEDIA_BUS_FMT_YUV8_1X24: 267 case MEDIA_BUS_FMT_YUV10_1X30: 268 case MEDIA_BUS_FMT_YUV12_1X36: 269 case MEDIA_BUS_FMT_YUV16_1X48: 270 return true; 271 272 default: 273 return false; 274 } 275 } 276 277 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 278 { 279 switch (bus_format) { 280 case MEDIA_BUS_FMT_UYVY8_1X16: 281 case MEDIA_BUS_FMT_UYVY10_1X20: 282 case MEDIA_BUS_FMT_UYVY12_1X24: 283 return true; 284 285 default: 286 return false; 287 } 288 } 289 290 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 291 { 292 switch (bus_format) { 293 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 294 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 295 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 296 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 297 return true; 298 299 default: 300 return false; 301 } 302 } 303 304 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 305 { 306 switch (bus_format) { 307 case MEDIA_BUS_FMT_RGB888_1X24: 308 case MEDIA_BUS_FMT_YUV8_1X24: 309 case MEDIA_BUS_FMT_UYVY8_1X16: 310 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 311 return 8; 312 313 case MEDIA_BUS_FMT_RGB101010_1X30: 314 case MEDIA_BUS_FMT_YUV10_1X30: 315 case MEDIA_BUS_FMT_UYVY10_1X20: 316 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 317 return 10; 318 319 case MEDIA_BUS_FMT_RGB121212_1X36: 320 case MEDIA_BUS_FMT_YUV12_1X36: 321 case MEDIA_BUS_FMT_UYVY12_1X24: 322 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 323 return 12; 324 325 case MEDIA_BUS_FMT_RGB161616_1X48: 326 case MEDIA_BUS_FMT_YUV16_1X48: 327 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 328 return 16; 329 330 default: 331 return 0; 332 } 333 } 334 335 static int is_color_space_conversion(struct dw_hdmi *hdmi) 336 { 337 struct drm_display_mode *mode = 338 hdmi->edid_data.preferred_mode; 339 bool is_cea_default; 340 341 is_cea_default = (drm_match_cea_mode(mode) > 1) && 342 (hdmi->hdmi_data.quant_range == 343 HDMI_QUANTIZATION_RANGE_DEFAULT); 344 345 /* 346 * When output is rgb limited range or default range with 347 * cea mode, csc should be enabled. 348 */ 349 if (hdmi->hdmi_data.enc_in_bus_format != 350 hdmi->hdmi_data.enc_out_bus_format || 351 ((hdmi->hdmi_data.quant_range == HDMI_QUANTIZATION_RANGE_LIMITED || 352 is_cea_default) && 353 hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format))) 354 return 1; 355 356 return 0; 357 } 358 359 static int is_color_space_decimation(struct dw_hdmi *hdmi) 360 { 361 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 362 return 0; 363 364 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 365 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 366 return 1; 367 368 return 0; 369 } 370 371 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 372 unsigned char bit) 373 { 374 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 375 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 376 } 377 378 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi, 379 unsigned char bit) 380 { 381 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET, 382 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0); 383 } 384 385 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi, 386 unsigned char bit) 387 { 388 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET, 389 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0); 390 } 391 392 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi, 393 unsigned char bit) 394 { 395 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1); 396 } 397 398 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi, 399 unsigned char bit) 400 { 401 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2); 402 } 403 404 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 405 unsigned char *buf, unsigned int length) 406 { 407 struct dw_hdmi_i2c *i2c = hdmi->i2c; 408 int interrupt = 0, i = 20; 409 410 if (!i2c->is_regaddr) { 411 printf("set read register address to 0\n"); 412 i2c->slave_reg = 0x00; 413 i2c->is_regaddr = true; 414 } 415 416 while (length--) { 417 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 418 if (i2c->is_segment) 419 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 420 HDMI_I2CM_OPERATION); 421 else 422 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 423 HDMI_I2CM_OPERATION); 424 425 while (i--) { 426 udelay(1000); 427 interrupt = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 428 if (interrupt) 429 hdmi_writeb(hdmi, interrupt, 430 HDMI_IH_I2CM_STAT0); 431 if (interrupt & (m_SCDC_READREQ | m_I2CM_DONE | 432 m_I2CM_ERROR)) 433 break; 434 } 435 436 if (!interrupt) { 437 printf("[%s] i2c read reg[0x%02x] no interrupt\n", 438 __func__, i2c->slave_reg); 439 return -EAGAIN; 440 } 441 442 /* Check for error condition on the bus */ 443 if (interrupt & HDMI_IH_I2CM_STAT0_ERROR) { 444 printf("[%s] read reg[0x%02x] data error:0x%02x\n", 445 __func__, i2c->slave_reg, interrupt); 446 return -EIO; 447 } 448 449 i = 20; 450 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 451 } 452 i2c->is_segment = false; 453 454 return 0; 455 } 456 457 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 458 unsigned char *buf, unsigned int length) 459 { 460 struct dw_hdmi_i2c *i2c = hdmi->i2c; 461 int i = 20; 462 u8 interrupt = 0; 463 464 if (!i2c->is_regaddr) { 465 /* Use the first write byte as register address */ 466 i2c->slave_reg = buf[0]; 467 length--; 468 buf++; 469 i2c->is_regaddr = true; 470 } 471 472 while (length--) { 473 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 474 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 475 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 476 HDMI_I2CM_OPERATION); 477 478 while (i--) { 479 udelay(1000); 480 interrupt = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 481 if (interrupt) 482 hdmi_writeb(hdmi, 483 interrupt, HDMI_IH_I2CM_STAT0); 484 485 if (interrupt & (m_SCDC_READREQ | 486 m_I2CM_DONE | m_I2CM_ERROR)) 487 break; 488 } 489 490 if ((interrupt & m_I2CM_ERROR) || (i == -1)) { 491 printf("[%s] write data error\n", __func__); 492 return -EIO; 493 } else if (interrupt & m_I2CM_DONE) { 494 printf("[%s] write offset %02x success\n", 495 __func__, i2c->slave_reg); 496 return -EAGAIN; 497 } 498 499 i = 20; 500 } 501 502 return 0; 503 } 504 505 static int dw_hdmi_i2c_xfer(struct ddc_adapter *adap, 506 struct i2c_msg *msgs, int num) 507 { 508 struct dw_hdmi *hdmi = container_of(adap, struct dw_hdmi, adap); 509 struct dw_hdmi_i2c *i2c = hdmi->i2c; 510 u8 addr = msgs[0].addr; 511 int i, ret = 0; 512 513 printf("xfer: num: %d, addr: %#x\n", num, addr); 514 for (i = 0; i < num; i++) { 515 if (msgs[i].len == 0) { 516 printf("unsupported transfer %d/%d, no data\n", 517 i + 1, num); 518 return -EOPNOTSUPP; 519 } 520 } 521 522 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 523 524 /* Set slave device address taken from the first I2C message */ 525 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1) 526 addr = DDC_ADDR; 527 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 528 529 /* Set slave device register address on transfer */ 530 i2c->is_regaddr = false; 531 532 /* Set segment pointer for I2C extended read mode operation */ 533 i2c->is_segment = false; 534 535 for (i = 0; i < num; i++) { 536 debug("xfer: num: %d/%d, len: %d, flags: %#x\n", 537 i + 1, num, msgs[i].len, msgs[i].flags); 538 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 539 i2c->is_segment = true; 540 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 541 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 542 } else { 543 if (msgs[i].flags & I2C_M_RD) 544 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 545 msgs[i].len); 546 else 547 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 548 msgs[i].len); 549 } 550 if (ret < 0) 551 break; 552 } 553 554 if (!ret) 555 ret = num; 556 557 /* Mute DONE and ERROR interrupts */ 558 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 559 HDMI_IH_MUTE_I2CM_STAT0); 560 561 return ret; 562 } 563 564 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 565 { 566 u32 val; 567 568 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 569 if (msec-- == 0) 570 return false; 571 udelay(1000); 572 } 573 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 574 575 return true; 576 } 577 578 static void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 579 unsigned char addr) 580 { 581 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 582 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 583 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 584 HDMI_PHY_I2CM_DATAO_1_ADDR); 585 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 586 HDMI_PHY_I2CM_DATAO_0_ADDR); 587 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 588 HDMI_PHY_I2CM_OPERATION_ADDR); 589 hdmi_phy_wait_i2c_done(hdmi, 1000); 590 } 591 592 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 593 { 594 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 595 HDMI_PHY_CONF0_PDZ_OFFSET, 596 HDMI_PHY_CONF0_PDZ_MASK); 597 } 598 599 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 600 { 601 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 602 HDMI_PHY_CONF0_ENTMDS_OFFSET, 603 HDMI_PHY_CONF0_ENTMDS_MASK); 604 } 605 606 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 607 { 608 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 609 HDMI_PHY_CONF0_SVSRET_OFFSET, 610 HDMI_PHY_CONF0_SVSRET_MASK); 611 } 612 613 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 614 { 615 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 616 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 617 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 618 } 619 620 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 621 { 622 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 623 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 624 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 625 } 626 627 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 628 { 629 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 630 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 631 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 632 } 633 634 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 635 { 636 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 637 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 638 HDMI_PHY_CONF0_SELDIPIF_MASK); 639 } 640 641 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 642 { 643 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 644 unsigned int i; 645 u16 val; 646 647 if (phy->gen == 1) { 648 dw_hdmi_phy_enable_tmds(hdmi, 0); 649 dw_hdmi_phy_enable_powerdown(hdmi, true); 650 return; 651 } 652 653 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 654 655 /* 656 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 657 * to low power mode. 658 */ 659 for (i = 0; i < 5; ++i) { 660 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 661 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 662 break; 663 664 udelay(2000); 665 } 666 667 if (val & HDMI_PHY_TX_PHY_LOCK) 668 printf("PHY failed to power down\n"); 669 else 670 printf("PHY powered down in %u iterations\n", i); 671 672 dw_hdmi_phy_gen2_pddq(hdmi, 1); 673 } 674 675 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 676 { 677 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 678 unsigned int i; 679 u8 val; 680 681 if (phy->gen == 1) { 682 dw_hdmi_phy_enable_powerdown(hdmi, false); 683 684 /* Toggle TMDS enable. */ 685 dw_hdmi_phy_enable_tmds(hdmi, 0); 686 dw_hdmi_phy_enable_tmds(hdmi, 1); 687 return 0; 688 } 689 690 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 691 dw_hdmi_phy_gen2_pddq(hdmi, 0); 692 693 /* Wait for PHY PLL lock */ 694 for (i = 0; i < 5; ++i) { 695 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 696 if (val) 697 break; 698 699 udelay(2000); 700 } 701 702 if (!val) { 703 printf("PHY PLL failed to lock\n"); 704 return -ETIMEDOUT; 705 } 706 printf("PHY PLL locked %u iterations\n", i); 707 708 return 0; 709 } 710 711 /* 712 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 713 * information the DWC MHL PHY has the same register layout and is thus also 714 * supported by this function. 715 */ 716 static 717 int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 718 const struct dw_hdmi_plat_data *pdata, 719 unsigned long mpixelclock) 720 { 721 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 722 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 723 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 724 unsigned int tmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 725 unsigned int depth = 726 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 727 728 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) && 729 pdata->mpll_cfg_420) 730 mpll_config = pdata->mpll_cfg_420; 731 732 /* PLL/MPLL Cfg - always match on final entry */ 733 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 734 if (mpixelclock <= mpll_config->mpixelclock) 735 break; 736 737 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 738 if (tmdsclock <= curr_ctrl->mpixelclock) 739 break; 740 741 for (; phy_config->mpixelclock != ~0UL; phy_config++) 742 if (tmdsclock <= phy_config->mpixelclock) 743 break; 744 745 if (mpll_config->mpixelclock == ~0UL || 746 curr_ctrl->mpixelclock == ~0UL || 747 phy_config->mpixelclock == ~0UL) 748 return -EINVAL; 749 750 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 751 depth = fls(depth - 8); 752 else 753 depth = 0; 754 if (depth) 755 depth--; 756 757 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].cpce, 758 HDMI_3D_TX_PHY_CPCE_CTRL); 759 760 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].gmp, 761 HDMI_3D_TX_PHY_GMPCTRL); 762 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[depth], 763 HDMI_3D_TX_PHY_CURRCTRL); 764 765 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 766 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 767 HDMI_3D_TX_PHY_MSM_CTRL); 768 769 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 770 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 771 HDMI_3D_TX_PHY_CKSYMTXCTRL); 772 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 773 HDMI_3D_TX_PHY_VLEVCTRL); 774 775 /* Override and disable clock termination. */ 776 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, 777 HDMI_3D_TX_PHY_CKCALCTRL); 778 return 0; 779 } 780 781 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 782 { 783 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 784 .name = "DWC HDMI TX PHY", 785 .gen = 1, 786 }, { 787 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 788 .name = "DWC MHL PHY + HEAC PHY", 789 .gen = 2, 790 .has_svsret = true, 791 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 792 }, { 793 .type = DW_HDMI_PHY_DWC_MHL_PHY, 794 .name = "DWC MHL PHY", 795 .gen = 2, 796 .has_svsret = true, 797 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 798 }, { 799 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 800 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 801 .gen = 2, 802 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 803 }, { 804 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 805 .name = "DWC HDMI 3D TX PHY", 806 .gen = 2, 807 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 808 }, { 809 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 810 .name = "DWC HDMI 2.0 TX PHY", 811 .gen = 2, 812 .has_svsret = true, 813 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 814 }, { 815 .type = DW_HDMI_PHY_VENDOR_PHY, 816 .name = "Vendor PHY", 817 } 818 }; 819 820 static int rockchip_dw_hdmi_scrambling_enable(struct dw_hdmi *hdmi, 821 int enable) 822 { 823 u8 stat; 824 825 drm_scdc_readb(&hdmi->adap, SCDC_TMDS_CONFIG, &stat); 826 827 if (stat < 0) { 828 debug("Failed to read tmds config\n"); 829 return false; 830 } 831 832 if (enable == 1) { 833 /* Write on Rx the bit Scrambling_Enable, register 0x20 */ 834 stat |= SCDC_SCRAMBLING_ENABLE; 835 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 836 /* TMDS software reset request */ 837 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 838 HDMI_MC_SWRSTZ); 839 /* Enable/Disable Scrambling */ 840 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); 841 } else { 842 /* Enable/Disable Scrambling */ 843 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); 844 /* TMDS software reset request */ 845 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 846 HDMI_MC_SWRSTZ); 847 /* Write on Rx the bit Scrambling_Enable, register 0x20 */ 848 stat &= ~SCDC_SCRAMBLING_ENABLE; 849 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 850 } 851 852 return 0; 853 } 854 855 static void rockchip_dw_hdmi_scdc_set_tmds_rate(struct dw_hdmi *hdmi) 856 { 857 u8 stat; 858 859 drm_scdc_readb(&hdmi->adap, SCDC_TMDS_CONFIG, &stat); 860 if (hdmi->hdmi_data.video_mode.mtmdsclock > 340000000) 861 stat |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 862 else 863 stat &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 864 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat); 865 } 866 867 static int hdmi_phy_configure(struct dw_hdmi *hdmi) 868 { 869 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 870 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 871 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 872 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 873 int ret; 874 875 dw_hdmi_phy_power_off(hdmi); 876 877 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ 878 if (hdmi->edid_data.display_info.hdmi.scdc.supported) 879 rockchip_dw_hdmi_scdc_set_tmds_rate(hdmi); 880 881 /* Leave low power consumption mode by asserting SVSRET. */ 882 if (phy->has_svsret) 883 dw_hdmi_phy_enable_svsret(hdmi, 1); 884 885 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 886 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 887 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 888 889 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 890 891 hdmi_phy_test_clear(hdmi, 1); 892 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, 893 HDMI_PHY_I2CM_SLAVE_ADDR); 894 hdmi_phy_test_clear(hdmi, 0); 895 896 /* Write to the PHY as configured by the platform */ 897 if (pdata->configure_phy) 898 ret = pdata->configure_phy(hdmi, pdata, mpixelclock); 899 else 900 ret = phy->configure(hdmi, pdata, mpixelclock); 901 if (ret) { 902 printf("PHY configuration failed (clock %lu)\n", 903 mpixelclock); 904 return ret; 905 } 906 907 /* Wait for resuming transmission of TMDS clock and data */ 908 if (mtmdsclock > 340000000) 909 mdelay(100); 910 911 return dw_hdmi_phy_power_on(hdmi); 912 } 913 914 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, 915 void *data) 916 { 917 int i, ret; 918 919 /* HDMI Phy spec says to do the phy initialization sequence twice */ 920 for (i = 0; i < 2; i++) { 921 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 922 dw_hdmi_phy_sel_interface_control(hdmi, 0); 923 ret = hdmi_phy_configure(hdmi); 924 if (ret) 925 return ret; 926 } 927 928 return 0; 929 } 930 931 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, 932 void *data) 933 { 934 dw_hdmi_phy_power_off(hdmi); 935 } 936 937 static enum drm_connector_status 938 dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data) 939 { 940 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 941 connector_status_connected : connector_status_disconnected; 942 } 943 944 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 945 .init = dw_hdmi_phy_init, 946 .disable = dw_hdmi_phy_disable, 947 .read_hpd = dw_hdmi_phy_read_hpd, 948 }; 949 950 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 951 { 952 unsigned int i; 953 u8 phy_type; 954 955 phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID); 956 957 /* 958 * RK3228 and RK3328 phy_type is DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 959 * but it has a vedor phy. 960 */ 961 if (phy_type == DW_HDMI_PHY_VENDOR_PHY || 962 hdmi->dev_type == RK3328_HDMI || 963 hdmi->dev_type == RK3228_HDMI) { 964 /* Vendor PHYs require support from the glue layer. */ 965 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 966 printf( 967 "Vendor HDMI PHY not supported by glue layer\n"); 968 return -ENODEV; 969 } 970 971 hdmi->phy.ops = hdmi->plat_data->phy_ops; 972 hdmi->phy.data = hdmi->plat_data->phy_data; 973 hdmi->phy.name = hdmi->plat_data->phy_name; 974 return 0; 975 } 976 977 /* Synopsys PHYs are handled internally. */ 978 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 979 if (dw_hdmi_phys[i].type == phy_type) { 980 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 981 hdmi->phy.name = dw_hdmi_phys[i].name; 982 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 983 984 if (!dw_hdmi_phys[i].configure && 985 !hdmi->plat_data->configure_phy) { 986 printf("%s requires platform support\n", 987 hdmi->phy.name); 988 return -ENODEV; 989 } 990 991 return 0; 992 } 993 } 994 995 printf("Unsupported HDMI PHY type (%02x)\n", phy_type); 996 return -ENODEV; 997 } 998 999 static unsigned int 1000 hdmi_get_tmdsclock(struct dw_hdmi *hdmi, unsigned long mpixelclock) 1001 { 1002 unsigned int tmdsclock = mpixelclock; 1003 unsigned int depth = 1004 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 1005 1006 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1007 switch (depth) { 1008 case 16: 1009 tmdsclock = mpixelclock * 2; 1010 break; 1011 case 12: 1012 tmdsclock = mpixelclock * 3 / 2; 1013 break; 1014 case 10: 1015 tmdsclock = mpixelclock * 5 / 4; 1016 break; 1017 default: 1018 break; 1019 } 1020 } 1021 1022 return tmdsclock; 1023 } 1024 1025 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1026 const struct drm_display_mode *mode) 1027 { 1028 u8 bytes = 0, inv_val = 0; 1029 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1030 struct drm_hdmi_info *hdmi_info = &hdmi->edid_data.display_info.hdmi; 1031 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1032 unsigned int hdisplay, vdisplay; 1033 1034 vmode->mpixelclock = mode->crtc_clock * 1000; 1035 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == 1036 DRM_MODE_FLAG_3D_FRAME_PACKING) 1037 vmode->mpixelclock *= 2; 1038 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock); 1039 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1040 vmode->mtmdsclock /= 2; 1041 printf("final pixclk = %d tmdsclk = %d\n", 1042 vmode->mpixelclock, vmode->mtmdsclock); 1043 1044 /* Set up HDMI_FC_INVIDCONF 1045 * fc_invidconf.HDCP_keepout must be set (1'b1) 1046 * when activate the scrambler feature. 1047 */ 1048 inv_val = (vmode->mtmdsclock > 340000000 || 1049 (hdmi_info->scdc.scrambling.low_rates && 1050 hdmi->scramble_low_rates) ? 1051 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 1052 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 1053 1054 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 1055 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 1056 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 1057 1058 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 1059 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 1060 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 1061 1062 inv_val |= (vmode->mdataenablepolarity ? 1063 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 1064 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 1065 1066 if (hdmi->vic == 39) 1067 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 1068 else 1069 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1070 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 1071 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 1072 1073 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1074 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 1075 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 1076 1077 inv_val |= hdmi->sink_is_hdmi ? 1078 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 1079 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 1080 1081 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 1082 1083 hdisplay = mode->hdisplay; 1084 hblank = mode->htotal - mode->hdisplay; 1085 h_de_hs = mode->hsync_start - mode->hdisplay; 1086 hsync_len = mode->hsync_end - mode->hsync_start; 1087 1088 /* 1089 * When we're setting a YCbCr420 mode, we need 1090 * to adjust the horizontal timing to suit. 1091 */ 1092 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1093 hdisplay /= 2; 1094 hblank /= 2; 1095 h_de_hs /= 2; 1096 hsync_len /= 2; 1097 } 1098 1099 vdisplay = mode->vdisplay; 1100 vblank = mode->vtotal - mode->vdisplay; 1101 v_de_vs = mode->vsync_start - mode->vdisplay; 1102 vsync_len = mode->vsync_end - mode->vsync_start; 1103 1104 /* 1105 * When we're setting an interlaced mode, we need 1106 * to adjust the vertical timing to suit. 1107 */ 1108 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1109 vdisplay /= 2; 1110 vblank /= 2; 1111 v_de_vs /= 2; 1112 vsync_len /= 2; 1113 } else if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == 1114 DRM_MODE_FLAG_3D_FRAME_PACKING) { 1115 vdisplay += mode->vtotal; 1116 } 1117 1118 /* Scrambling Control */ 1119 if (hdmi_info->scdc.supported) { 1120 if (vmode->mtmdsclock > 340000000 || 1121 (hdmi_info->scdc.scrambling.low_rates && 1122 hdmi->scramble_low_rates)) { 1123 drm_scdc_readb(&hdmi->adap, SCDC_SINK_VERSION, &bytes); 1124 drm_scdc_writeb(&hdmi->adap, SCDC_SOURCE_VERSION, 1125 bytes); 1126 rockchip_dw_hdmi_scrambling_enable(hdmi, 1); 1127 } else { 1128 rockchip_dw_hdmi_scrambling_enable(hdmi, 0); 1129 } 1130 } 1131 1132 /* Set up horizontal active pixel width */ 1133 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1); 1134 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0); 1135 1136 /* Set up vertical active lines */ 1137 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 1138 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 1139 1140 /* Set up horizontal blanking pixel region width */ 1141 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 1142 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 1143 1144 /* Set up vertical blanking pixel region width */ 1145 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 1146 1147 /* Set up HSYNC active edge delay width (in pixel clks) */ 1148 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 1149 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 1150 1151 /* Set up VSYNC active edge delay (in lines) */ 1152 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 1153 1154 /* Set up HSYNC active pulse width (in pixel clks) */ 1155 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 1156 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 1157 1158 /* Set up VSYNC active edge delay (in lines) */ 1159 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 1160 } 1161 1162 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 1163 { 1164 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 1165 unsigned i; 1166 u32 csc_scale = 1; 1167 int enc_out_rgb, enc_in_rgb; 1168 1169 enc_out_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format); 1170 enc_in_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format); 1171 1172 if (is_color_space_conversion(hdmi)) { 1173 if (enc_out_rgb && enc_in_rgb) { 1174 csc_coeff = &csc_coeff_full_to_limited; 1175 csc_scale = 0; 1176 } else if (enc_out_rgb) { 1177 if (hdmi->hdmi_data.enc_out_encoding == 1178 V4L2_YCBCR_ENC_601) 1179 csc_coeff = &csc_coeff_rgb_out_eitu601; 1180 else 1181 csc_coeff = &csc_coeff_rgb_out_eitu709; 1182 } else if (enc_in_rgb) { 1183 if (hdmi->hdmi_data.enc_out_encoding == 1184 V4L2_YCBCR_ENC_601) 1185 csc_coeff = &csc_coeff_rgb_in_eitu601; 1186 else 1187 csc_coeff = &csc_coeff_rgb_in_eitu709; 1188 csc_scale = 0; 1189 } 1190 } 1191 1192 /* The CSC registers are sequential, alternating MSB then LSB */ 1193 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 1194 u16 coeff_a = (*csc_coeff)[0][i]; 1195 u16 coeff_b = (*csc_coeff)[1][i]; 1196 u16 coeff_c = (*csc_coeff)[2][i]; 1197 1198 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 1199 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 1200 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 1201 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 1202 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 1203 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 1204 } 1205 1206 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 1207 HDMI_CSC_SCALE); 1208 } 1209 1210 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 1211 { 1212 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 1213 return 0; 1214 1215 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1216 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1217 return 1; 1218 1219 return 0; 1220 } 1221 1222 static void hdmi_video_csc(struct dw_hdmi *hdmi) 1223 { 1224 int color_depth = 0; 1225 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 1226 int decimation = 0; 1227 1228 /* YCC422 interpolation to 444 mode */ 1229 if (is_color_space_interpolation(hdmi)) 1230 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 1231 else if (is_color_space_decimation(hdmi)) 1232 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 1233 1234 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 1235 case 8: 1236 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 1237 break; 1238 case 10: 1239 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 1240 break; 1241 case 12: 1242 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 1243 break; 1244 case 16: 1245 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 1246 break; 1247 1248 default: 1249 return; 1250 } 1251 1252 /* Configure the CSC registers */ 1253 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 1254 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 1255 HDMI_CSC_SCALE); 1256 1257 dw_hdmi_update_csc_coeffs(hdmi); 1258 } 1259 1260 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 1261 { 1262 u8 clkdis; 1263 1264 /* control period minimum duration */ 1265 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 1266 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 1267 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 1268 1269 /* Set to fill TMDS data channels */ 1270 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 1271 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 1272 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 1273 1274 /* Enable pixel clock and tmds data path */ 1275 clkdis = 0x7F; 1276 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 1277 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1278 1279 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1280 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1281 1282 /* Enable csc path */ 1283 if (is_color_space_conversion(hdmi)) { 1284 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 1285 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1286 } 1287 1288 /* Enable pixel repetition path */ 1289 if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) { 1290 clkdis &= ~HDMI_MC_CLKDIS_PREPCLK_DISABLE; 1291 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1292 } 1293 1294 /* Enable color space conversion if needed */ 1295 if (is_color_space_conversion(hdmi)) 1296 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 1297 HDMI_MC_FLOWCTRL); 1298 else 1299 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 1300 HDMI_MC_FLOWCTRL); 1301 } 1302 1303 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 1304 { 1305 unsigned int count; 1306 unsigned int i; 1307 u8 val; 1308 1309 /* 1310 * Under some circumstances the Frame Composer arithmetic unit can miss 1311 * an FC register write due to being busy processing the previous one. 1312 * The issue can be worked around by issuing a TMDS software reset and 1313 * then write one of the FC registers several times. 1314 * 1315 * The number of iterations matters and depends on the HDMI TX revision 1316 * (and possibly on the platform). So far only i.MX6Q (v1.30a) and 1317 * i.MX6DL (v1.31a) have been identified as needing the workaround, with 1318 * 4 and 1 iterations respectively. 1319 */ 1320 1321 switch (hdmi->version) { 1322 case 0x130a: 1323 count = 4; 1324 break; 1325 case 0x131a: 1326 case 0x200a: 1327 case 0x201a: 1328 case 0x211a: 1329 count = 1; 1330 break; 1331 default: 1332 return; 1333 } 1334 1335 /* TMDS software reset */ 1336 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 1337 1338 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 1339 for (i = 0; i < count; i++) 1340 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 1341 } 1342 1343 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 1344 { 1345 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 1346 HDMI_IH_MUTE_FC_STAT2); 1347 } 1348 1349 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 1350 { 1351 unsigned int color_depth = 0; 1352 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 1353 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 1354 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1355 u8 val, vp_conf; 1356 1357 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1358 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) || 1359 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1360 switch (hdmi_bus_fmt_color_depth( 1361 hdmi->hdmi_data.enc_out_bus_format)) { 1362 case 8: 1363 color_depth = 0; 1364 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1365 break; 1366 case 10: 1367 color_depth = 5; 1368 break; 1369 case 12: 1370 color_depth = 6; 1371 break; 1372 case 16: 1373 color_depth = 7; 1374 break; 1375 default: 1376 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1377 } 1378 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1379 switch (hdmi_bus_fmt_color_depth( 1380 hdmi->hdmi_data.enc_out_bus_format)) { 1381 case 0: 1382 case 8: 1383 remap_size = HDMI_VP_REMAP_YCC422_16bit; 1384 break; 1385 case 10: 1386 remap_size = HDMI_VP_REMAP_YCC422_20bit; 1387 break; 1388 case 12: 1389 remap_size = HDMI_VP_REMAP_YCC422_24bit; 1390 break; 1391 1392 default: 1393 return; 1394 } 1395 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 1396 } else { 1397 return; 1398 } 1399 1400 /* set the packetizer registers */ 1401 val = (color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 1402 HDMI_VP_PR_CD_COLOR_DEPTH_MASK; 1403 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 1404 1405 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 1406 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 1407 1408 /* Data from pixel repeater block */ 1409 if (hdmi_data->pix_repet_factor > 0) { 1410 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 1411 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 1412 } else { /* data from packetizer block */ 1413 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 1414 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 1415 } 1416 1417 hdmi_modb(hdmi, vp_conf, 1418 HDMI_VP_CONF_PR_EN_MASK | 1419 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 1420 1421 if ((color_depth == 5 && hdmi->previous_mode.htotal % 4) || 1422 (color_depth == 6 && hdmi->previous_mode.htotal % 2)) 1423 hdmi_modb(hdmi, 0, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, 1424 HDMI_VP_STUFF); 1425 else 1426 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 1427 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 1428 1429 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 1430 1431 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 1432 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1433 HDMI_VP_CONF_PP_EN_ENABLE | 1434 HDMI_VP_CONF_YCC422_EN_DISABLE; 1435 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 1436 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1437 HDMI_VP_CONF_PP_EN_DISABLE | 1438 HDMI_VP_CONF_YCC422_EN_ENABLE; 1439 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 1440 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 1441 HDMI_VP_CONF_PP_EN_DISABLE | 1442 HDMI_VP_CONF_YCC422_EN_DISABLE; 1443 } else { 1444 return; 1445 } 1446 1447 hdmi_modb(hdmi, vp_conf, 1448 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 1449 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 1450 1451 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 1452 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 1453 HDMI_VP_STUFF_PP_STUFFING_MASK | 1454 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 1455 1456 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 1457 HDMI_VP_CONF); 1458 } 1459 1460 static void hdmi_video_sample(struct dw_hdmi *hdmi) 1461 { 1462 int color_format = 0; 1463 u8 val; 1464 1465 switch (hdmi->hdmi_data.enc_in_bus_format) { 1466 case MEDIA_BUS_FMT_RGB888_1X24: 1467 color_format = 0x01; 1468 break; 1469 case MEDIA_BUS_FMT_RGB101010_1X30: 1470 color_format = 0x03; 1471 break; 1472 case MEDIA_BUS_FMT_RGB121212_1X36: 1473 color_format = 0x05; 1474 break; 1475 case MEDIA_BUS_FMT_RGB161616_1X48: 1476 color_format = 0x07; 1477 break; 1478 1479 case MEDIA_BUS_FMT_YUV8_1X24: 1480 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1481 color_format = 0x09; 1482 break; 1483 case MEDIA_BUS_FMT_YUV10_1X30: 1484 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1485 color_format = 0x0B; 1486 break; 1487 case MEDIA_BUS_FMT_YUV12_1X36: 1488 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 1489 color_format = 0x0D; 1490 break; 1491 case MEDIA_BUS_FMT_YUV16_1X48: 1492 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 1493 color_format = 0x0F; 1494 break; 1495 1496 case MEDIA_BUS_FMT_UYVY8_1X16: 1497 color_format = 0x16; 1498 break; 1499 case MEDIA_BUS_FMT_UYVY10_1X20: 1500 color_format = 0x14; 1501 break; 1502 case MEDIA_BUS_FMT_UYVY12_1X24: 1503 color_format = 0x12; 1504 break; 1505 1506 default: 1507 return; 1508 } 1509 1510 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 1511 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 1512 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 1513 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 1514 1515 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 1516 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 1517 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 1518 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 1519 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 1520 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 1521 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 1522 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 1523 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 1524 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 1525 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 1526 } 1527 1528 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi) 1529 { 1530 hdmi_writeb(hdmi, 0, HDMI_FC_MASK2); 1531 hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2); 1532 } 1533 1534 static void dw_hdmi_disable(struct dw_hdmi *hdmi, struct display_state *state) 1535 { 1536 if (hdmi->phy.enabled) { 1537 hdmi->phy.ops->disable(hdmi, state); 1538 hdmi->phy.enabled = false; 1539 } 1540 } 1541 1542 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1543 { 1544 struct hdmi_avi_infoframe frame; 1545 u8 val; 1546 bool is_hdmi2 = false; 1547 enum hdmi_quantization_range rgb_quant_range = 1548 hdmi->hdmi_data.quant_range; 1549 1550 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) || 1551 hdmi->edid_data.display_info.hdmi.scdc.supported) 1552 is_hdmi2 = true; 1553 /* Initialise info frame from DRM mode */ 1554 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2); 1555 1556 /* 1557 * Ignore monitor selectable quantization, use quantization set 1558 * by the user 1559 */ 1560 drm_hdmi_avi_infoframe_quant_range(&frame, mode, rgb_quant_range, 1561 true); 1562 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1563 frame.colorspace = HDMI_COLORSPACE_YUV444; 1564 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1565 frame.colorspace = HDMI_COLORSPACE_YUV422; 1566 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1567 frame.colorspace = HDMI_COLORSPACE_YUV420; 1568 else 1569 frame.colorspace = HDMI_COLORSPACE_RGB; 1570 1571 /* Set up colorimetry */ 1572 switch (hdmi->hdmi_data.enc_out_encoding) { 1573 case V4L2_YCBCR_ENC_601: 1574 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1575 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1576 else 1577 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1578 frame.extended_colorimetry = 1579 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1580 break; 1581 case V4L2_YCBCR_ENC_709: 1582 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1583 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1584 else 1585 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1586 frame.extended_colorimetry = 1587 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1588 break; 1589 default: /* Carries no data */ 1590 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1591 frame.extended_colorimetry = 1592 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1593 break; 1594 } 1595 1596 frame.scan_mode = HDMI_SCAN_MODE_NONE; 1597 1598 /* 1599 * The Designware IP uses a different byte format from standard 1600 * AVI info frames, though generally the bits are in the correct 1601 * bytes. 1602 */ 1603 1604 /* 1605 * AVI data byte 1 differences: Colorspace in bits 0,1,7 rather than 1606 * 5,6,7, active aspect present in bit 6 rather than 4. 1607 */ 1608 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 0x3); 1609 if (frame.active_aspect & 15) 1610 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1611 if (frame.top_bar || frame.bottom_bar) 1612 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1613 if (frame.left_bar || frame.right_bar) 1614 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1615 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1616 1617 /* AVI data byte 2 differences: none */ 1618 val = ((frame.colorimetry & 0x3) << 6) | 1619 ((frame.picture_aspect & 0x3) << 4) | 1620 (frame.active_aspect & 0xf); 1621 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1622 1623 /* AVI data byte 3 differences: none */ 1624 val = ((frame.extended_colorimetry & 0x7) << 4) | 1625 ((frame.quantization_range & 0x3) << 2) | 1626 (frame.nups & 0x3); 1627 if (frame.itc) 1628 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1629 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1630 1631 /* AVI data byte 4 differences: none */ 1632 val = frame.video_code & 0x7f; 1633 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1634 1635 /* AVI Data Byte 5- set up input and output pixel repetition */ 1636 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1637 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1638 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1639 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1640 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1641 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1642 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1643 1644 /* 1645 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1646 * ycc range in bits 2,3 rather than 6,7 1647 */ 1648 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1649 (frame.content_type & 0x3); 1650 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1651 1652 /* AVI Data Bytes 6-13 */ 1653 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1654 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1655 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1656 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1657 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1658 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1659 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1660 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1661 } 1662 1663 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1664 struct drm_display_mode *mode) 1665 { 1666 struct hdmi_vendor_infoframe frame; 1667 u8 buffer[10]; 1668 ssize_t err; 1669 1670 /* Disable HDMI vendor specific infoframe send */ 1671 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1672 HDMI_FC_DATAUTO0_VSD_MASK); 1673 1674 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode); 1675 if (err < 0) 1676 /* 1677 * Going into that statement does not means vendor infoframe 1678 * fails. It just informed us that vendor infoframe is not 1679 * needed for the selected mode. Only 4k or stereoscopic 3D 1680 * mode requires vendor infoframe. So just simply return. 1681 */ 1682 return; 1683 1684 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1685 if (err < 0) { 1686 printf("Failed to pack vendor infoframe: %zd\n", err); 1687 return; 1688 } 1689 1690 /* Set the length of HDMI vendor specific InfoFrame payload */ 1691 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1692 1693 /* Set 24bit IEEE Registration Identifier */ 1694 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1695 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1696 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1697 1698 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1699 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1700 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1701 1702 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1703 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1704 1705 /* Packet frame interpolation */ 1706 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1707 1708 /* Auto packets per frame and line spacing */ 1709 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1710 1711 /* Configures the Frame Composer On RDRB mode */ 1712 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1713 HDMI_FC_DATAUTO0_VSD_MASK); 1714 } 1715 1716 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 1717 unsigned int n) 1718 { 1719 /* Must be set/cleared first */ 1720 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 1721 1722 /* nshift factor = 0 */ 1723 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 1724 1725 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 1726 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 1727 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 1728 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 1729 1730 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 1731 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 1732 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 1733 } 1734 1735 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi, 1736 unsigned long pixel_clk, 1737 unsigned long freq) 1738 { 1739 const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data; 1740 const struct dw_hdmi_audio_tmds_n *tmds_n = NULL; 1741 int i; 1742 1743 if (plat_data->tmds_n_table) { 1744 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) { 1745 if (pixel_clk == plat_data->tmds_n_table[i].tmds) { 1746 tmds_n = &plat_data->tmds_n_table[i]; 1747 break; 1748 } 1749 } 1750 } 1751 1752 if (!tmds_n) { 1753 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) { 1754 if (pixel_clk == common_tmds_n_table[i].tmds) { 1755 tmds_n = &common_tmds_n_table[i]; 1756 break; 1757 } 1758 } 1759 } 1760 1761 if (!tmds_n) 1762 return -ENOENT; 1763 1764 switch (freq) { 1765 case 32000: 1766 return tmds_n->n_32k; 1767 case 44100: 1768 case 88200: 1769 case 176400: 1770 return (freq / 44100) * tmds_n->n_44k1; 1771 case 48000: 1772 case 96000: 1773 case 192000: 1774 return (freq / 48000) * tmds_n->n_48k; 1775 default: 1776 return -ENOENT; 1777 } 1778 } 1779 1780 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n, 1781 unsigned int pixel_clk) 1782 { 1783 u64 final, diff; 1784 u64 cts; 1785 1786 final = (u64)pixel_clk * n; 1787 1788 cts = final; 1789 do_div(cts, 128 * freq); 1790 1791 diff = final - (u64)cts * (128 * freq); 1792 1793 return diff; 1794 } 1795 1796 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi, 1797 unsigned long pixel_clk, 1798 unsigned long freq) 1799 { 1800 unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500); 1801 unsigned int max_n = (128 * freq) / 300; 1802 unsigned int ideal_n = (128 * freq) / 1000; 1803 unsigned int best_n_distance = ideal_n; 1804 unsigned int best_n = 0; 1805 u64 best_diff = U64_MAX; 1806 int n; 1807 1808 /* If the ideal N could satisfy the audio math, then just take it */ 1809 if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0) 1810 return ideal_n; 1811 1812 for (n = min_n; n <= max_n; n++) { 1813 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk); 1814 1815 if (diff < best_diff || (diff == best_diff && 1816 abs(n - ideal_n) < best_n_distance)) { 1817 best_n = n; 1818 best_diff = diff; 1819 best_n_distance = abs(best_n - ideal_n); 1820 } 1821 1822 /* 1823 * The best N already satisfy the audio math, and also be 1824 * the closest value to ideal N, so just cut the loop. 1825 */ 1826 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance)) 1827 break; 1828 } 1829 1830 return best_n; 1831 } 1832 1833 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk, 1834 unsigned long sample_rate) 1835 { 1836 int n; 1837 1838 n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate); 1839 if (n > 0) 1840 return n; 1841 1842 printf("Rate %lu missing; compute N dynamically\n", 1843 pixel_clk); 1844 1845 return hdmi_compute_n(hdmi, pixel_clk, sample_rate); 1846 } 1847 1848 static 1849 void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, unsigned long pixel_clk, 1850 unsigned int sample_rate) 1851 { 1852 unsigned long ftdms = pixel_clk; 1853 unsigned int n, cts; 1854 u64 tmp; 1855 1856 n = hdmi_find_n(hdmi, pixel_clk, sample_rate); 1857 1858 /* 1859 * Compute the CTS value from the N value. Note that CTS and N 1860 * can be up to 20 bits in total, so we need 64-bit math. Also 1861 * note that our TDMS clock is not fully accurate; it is accurate 1862 * to kHz. This can introduce an unnecessary remainder in the 1863 * calculation below, so we don't try to warn about that. 1864 */ 1865 tmp = (u64)ftdms * n; 1866 do_div(tmp, 128 * sample_rate); 1867 cts = tmp; 1868 1869 printf("%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", __func__, 1870 sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000, n, cts); 1871 1872 hdmi->audio_n = n; 1873 hdmi->audio_cts = cts; 1874 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 1875 } 1876 1877 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 1878 { 1879 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 1880 hdmi->sample_rate); 1881 } 1882 1883 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi) 1884 { 1885 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS); 1886 } 1887 1888 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 1889 { 1890 hdmi->sample_rate = rate; 1891 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 1892 hdmi->sample_rate); 1893 } 1894 1895 static int dw_hdmi_hdcp_load_key(struct dw_hdmi *hdmi) 1896 { 1897 int i, j, ret, val; 1898 struct hdcp_keys *hdcp_keys; 1899 1900 val = sizeof(*hdcp_keys); 1901 hdcp_keys = malloc(val); 1902 if (!hdcp_keys) 1903 return -ENOMEM; 1904 1905 memset(hdcp_keys, 0, val); 1906 1907 ret = vendor_storage_read(HDMI_HDCP1X_ID, hdcp_keys, val); 1908 if (ret < val) { 1909 printf("HDCP: read size %d\n", ret); 1910 free(hdcp_keys); 1911 return -EINVAL; 1912 } 1913 1914 if (hdcp_keys->KSV[0] == 0x00 && 1915 hdcp_keys->KSV[1] == 0x00 && 1916 hdcp_keys->KSV[2] == 0x00 && 1917 hdcp_keys->KSV[3] == 0x00 && 1918 hdcp_keys->KSV[4] == 0x00) { 1919 printf("HDCP: Invalid hdcp key\n"); 1920 free(hdcp_keys); 1921 return -EINVAL; 1922 } 1923 1924 /* Disable decryption logic */ 1925 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_RMCTL); 1926 /* Poll untile DPK write is allowed */ 1927 do { 1928 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1929 } while ((val & DPK_WR_OK_STS) == 0); 1930 1931 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_DPK6); 1932 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_DPK5); 1933 1934 /* The useful data in ksv should be 5 byte */ 1935 for (i = 4; i >= 0; i--) 1936 hdmi_writeb(hdmi, hdcp_keys->KSV[i], HDMI_HDCPREG_DPK0 + i); 1937 /* Poll untile DPK write is allowed */ 1938 do { 1939 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1940 } while ((val & DPK_WR_OK_STS) == 0); 1941 1942 /* Enable decryption logic */ 1943 hdmi_writeb(hdmi, 1, HDMI_HDCPREG_RMCTL); 1944 hdmi_writeb(hdmi, hdcp_keys->seeds[0], HDMI_HDCPREG_SEED1); 1945 hdmi_writeb(hdmi, hdcp_keys->seeds[1], HDMI_HDCPREG_SEED0); 1946 1947 /* Write encrypt device private key */ 1948 for (i = 0; i < DW_HDMI_HDCP_DPK_LEN - 6; i += 7) { 1949 for (j = 6; j >= 0; j--) 1950 hdmi_writeb(hdmi, hdcp_keys->devicekey[i + j], 1951 HDMI_HDCPREG_DPK0 + j); 1952 do { 1953 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS); 1954 } while ((val & DPK_WR_OK_STS) == 0); 1955 } 1956 1957 free(hdcp_keys); 1958 return 0; 1959 } 1960 1961 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi, 1962 const struct drm_display_mode *mode) 1963 { 1964 u8 vsync_pol, hsync_pol, data_pol, hdmi_dvi; 1965 1966 if (!hdmi->hdcp1x_enable) 1967 return; 1968 1969 /* Configure the video polarity */ 1970 vsync_pol = mode->flags & DRM_MODE_FLAG_PVSYNC ? 1971 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH : 1972 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW; 1973 hsync_pol = mode->flags & DRM_MODE_FLAG_PHSYNC ? 1974 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH : 1975 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW; 1976 data_pol = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1977 hdmi_modb(hdmi, vsync_pol | hsync_pol | data_pol, 1978 HDMI_A_VIDPOLCFG_VSYNCPOL_MASK | 1979 HDMI_A_VIDPOLCFG_HSYNCPOL_MASK | 1980 HDMI_A_VIDPOLCFG_DATAENPOL_MASK, 1981 HDMI_A_VIDPOLCFG); 1982 1983 /* Config the display mode */ 1984 hdmi_dvi = hdmi->sink_is_hdmi ? HDMI_A_HDCPCFG0_HDMIDVI_HDMI : 1985 HDMI_A_HDCPCFG0_HDMIDVI_DVI; 1986 hdmi_modb(hdmi, hdmi_dvi, HDMI_A_HDCPCFG0_HDMIDVI_MASK, 1987 HDMI_A_HDCPCFG0); 1988 1989 if (!(hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS) & 0x3f)) 1990 dw_hdmi_hdcp_load_key(hdmi); 1991 1992 hdmi_modb(hdmi, HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE, 1993 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK, 1994 HDMI_FC_INVIDCONF); 1995 1996 if (hdmi_readb(hdmi, HDMI_CONFIG1_ID) & HDMI_A_HDCP22_MASK) { 1997 hdmi_modb(hdmi, HDMI_HDCP2_OVR_ENABLE | 1998 HDMI_HDCP2_FORCE_DISABLE, 1999 HDMI_HDCP2_OVR_EN_MASK | 2000 HDMI_HDCP2_FORCE_MASK, 2001 HDMI_HDCP2REG_CTRL); 2002 hdmi_writeb(hdmi, 0xff, HDMI_HDCP2REG_MASK); 2003 hdmi_writeb(hdmi, 0xff, HDMI_HDCP2REG_MUTE); 2004 } 2005 2006 hdmi_writeb(hdmi, 0x40, HDMI_A_OESSWCFG); 2007 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE | 2008 HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE | 2009 HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE, 2010 HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK | 2011 HDMI_A_HDCPCFG0_EN11FEATURE_MASK | 2012 HDMI_A_HDCPCFG0_SYNCRICHECK_MASK, HDMI_A_HDCPCFG0); 2013 2014 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE | 2015 HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE, 2016 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK | 2017 HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK, HDMI_A_HDCPCFG1); 2018 2019 /* Reset HDCP Engine */ 2020 if (hdmi_readb(hdmi, HDMI_MC_CLKDIS) & HDMI_MC_CLKDIS_HDCPCLK_MASK) { 2021 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_SWRESET_ASSERT, 2022 HDMI_A_HDCPCFG1_SWRESET_MASK, HDMI_A_HDCPCFG1); 2023 } 2024 2025 hdmi_writeb(hdmi, 0x00, HDMI_A_APIINTMSK); 2026 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_ENABLE, 2027 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 2028 2029 hdmi_modb(hdmi, HDMI_MC_CLKDIS_HDCPCLK_ENABLE, 2030 HDMI_MC_CLKDIS_HDCPCLK_MASK, HDMI_MC_CLKDIS); 2031 2032 printf("%s success\n", __func__); 2033 } 2034 2035 static int dw_hdmi_setup(struct dw_hdmi *hdmi, 2036 struct drm_display_mode *mode, 2037 struct display_state *state) 2038 { 2039 int ret; 2040 void *data = hdmi->plat_data->phy_data; 2041 2042 hdmi_disable_overflow_interrupts(hdmi); 2043 if (!hdmi->vic) 2044 printf("Non-CEA mode used in HDMI\n"); 2045 else 2046 printf("CEA mode used vic=%d\n", hdmi->vic); 2047 2048 if (hdmi->plat_data->get_enc_out_encoding) 2049 hdmi->hdmi_data.enc_out_encoding = 2050 hdmi->plat_data->get_enc_out_encoding(data); 2051 else if ((hdmi->vic == 6) || (hdmi->vic == 7) || 2052 (hdmi->vic == 21) || (hdmi->vic == 22) || 2053 (hdmi->vic == 2) || (hdmi->vic == 3) || 2054 (hdmi->vic == 17) || (hdmi->vic == 18)) 2055 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 2056 else 2057 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 2058 2059 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2060 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1; 2061 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1; 2062 } else { 2063 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 2064 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 2065 } 2066 2067 /* TOFIX: Get input encoding from plat data or fallback to none */ 2068 if (hdmi->plat_data->get_enc_in_encoding) 2069 hdmi->hdmi_data.enc_in_encoding = 2070 hdmi->plat_data->get_enc_in_encoding(data); 2071 else if (hdmi->plat_data->input_bus_encoding) 2072 hdmi->hdmi_data.enc_in_encoding = 2073 hdmi->plat_data->input_bus_encoding; 2074 else 2075 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 2076 2077 if (hdmi->plat_data->get_quant_range) 2078 hdmi->hdmi_data.quant_range = 2079 hdmi->plat_data->get_quant_range(data); 2080 else 2081 hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 2082 2083 /* 2084 * According to the dw-hdmi specification 6.4.2 2085 * vp_pr_cd[3:0]: 2086 * 0000b: No pixel repetition (pixel sent only once) 2087 * 0001b: Pixel sent two times (pixel repeated once) 2088 */ 2089 hdmi->hdmi_data.pix_repet_factor = 2090 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0; 2091 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 2092 2093 /* HDMI Initialization Step B.1 */ 2094 hdmi_av_composer(hdmi, mode); 2095 2096 /* HDMI Initialization Step B.2 */ 2097 ret = hdmi->phy.ops->init(hdmi, state); 2098 if (ret) 2099 return ret; 2100 hdmi->phy.enabled = true; 2101 2102 /* HDMI Initializateion Step B.3 */ 2103 dw_hdmi_enable_video_path(hdmi); 2104 2105 /* HDMI Initialization Step E - Configure audio */ 2106 if (hdmi->sink_has_audio) { 2107 printf("sink has audio support\n"); 2108 hdmi_clk_regenerator_update_pixel_clock(hdmi); 2109 hdmi_enable_audio_clk(hdmi); 2110 } 2111 2112 /* not for DVI mode */ 2113 if (hdmi->sink_is_hdmi) { 2114 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 2115 hdmi_config_AVI(hdmi, mode); 2116 hdmi_config_vendor_specific_infoframe(hdmi, mode); 2117 } else { 2118 printf("%s DVI mode\n", __func__); 2119 } 2120 2121 hdmi_video_packetize(hdmi); 2122 hdmi_video_csc(hdmi); 2123 hdmi_video_sample(hdmi); 2124 hdmi_tx_hdcp_config(hdmi, mode); 2125 dw_hdmi_clear_overflow(hdmi); 2126 if (hdmi->cable_plugin && hdmi->sink_is_hdmi) 2127 hdmi_enable_overflow_interrupts(hdmi); 2128 2129 return 0; 2130 } 2131 2132 int dw_hdmi_detect_hotplug(struct dw_hdmi *hdmi, 2133 struct display_state *state) 2134 { 2135 return hdmi->phy.ops->read_hpd(hdmi, state); 2136 } 2137 2138 static int dw_hdmi_set_reg_wr(struct dw_hdmi *hdmi) 2139 { 2140 switch (hdmi->io_width) { 2141 case 4: 2142 hdmi->write = dw_hdmi_writel; 2143 hdmi->read = dw_hdmi_readl; 2144 break; 2145 case 1: 2146 hdmi->write = dw_hdmi_writeb; 2147 hdmi->read = dw_hdmi_readb; 2148 break; 2149 default: 2150 printf("reg-io-width must be 1 or 4\n"); 2151 return -EINVAL; 2152 } 2153 2154 return 0; 2155 } 2156 2157 static void initialize_hdmi_mutes(struct dw_hdmi *hdmi) 2158 { 2159 /*mute unnecessary interrupt, only enable hpd */ 2160 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 2161 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 2162 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 2163 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 2164 hdmi_writeb(hdmi, 0xfe, HDMI_IH_MUTE_PHY_STAT0); 2165 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 2166 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 2167 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 2168 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 2169 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 2170 hdmi_writeb(hdmi, 0xf1, HDMI_PHY_MASK0); 2171 2172 /*Force output black*/ 2173 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS2); 2174 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS1); 2175 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS0); 2176 } 2177 2178 static void dw_hdmi_dev_init(struct dw_hdmi *hdmi) 2179 { 2180 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 2181 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 2182 2183 initialize_hdmi_mutes(hdmi); 2184 } 2185 2186 static void dw_hdmi_i2c_set_divs(struct dw_hdmi *hdmi) 2187 { 2188 unsigned long low_ns, high_ns; 2189 unsigned long div_low, div_high; 2190 2191 /* Standard-mode */ 2192 if (hdmi->i2c->scl_high_ns < 4000) 2193 high_ns = 4708; 2194 else 2195 high_ns = hdmi->i2c->scl_high_ns; 2196 2197 if (hdmi->i2c->scl_low_ns < 4700) 2198 low_ns = 4916; 2199 else 2200 low_ns = hdmi->i2c->scl_low_ns; 2201 2202 div_low = (24000 * low_ns) / 1000000; 2203 if ((24000 * low_ns) % 1000000) 2204 div_low++; 2205 2206 div_high = (24000 * high_ns) / 1000000; 2207 if ((24000 * high_ns) % 1000000) 2208 div_high++; 2209 2210 /* Maximum divider supported by hw is 0xffff */ 2211 if (div_low > 0xffff) 2212 div_low = 0xffff; 2213 2214 if (div_high > 0xffff) 2215 div_high = 0xffff; 2216 2217 hdmi_writeb(hdmi, div_high & 0xff, HDMI_I2CM_SS_SCL_HCNT_0_ADDR); 2218 hdmi_writeb(hdmi, (div_high >> 8) & 0xff, 2219 HDMI_I2CM_SS_SCL_HCNT_1_ADDR); 2220 hdmi_writeb(hdmi, div_low & 0xff, HDMI_I2CM_SS_SCL_LCNT_0_ADDR); 2221 hdmi_writeb(hdmi, (div_low >> 8) & 0xff, 2222 HDMI_I2CM_SS_SCL_LCNT_1_ADDR); 2223 } 2224 2225 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 2226 { 2227 /* Software reset */ 2228 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 2229 2230 /* Set Standard Mode speed */ 2231 hdmi_modb(hdmi, HDMI_I2CM_DIV_STD_MODE, 2232 HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV); 2233 2234 /* Set done, not acknowledged and arbitration interrupt polarities */ 2235 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 2236 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 2237 HDMI_I2CM_CTLINT); 2238 2239 /* Clear DONE and ERROR interrupts */ 2240 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 2241 HDMI_IH_I2CM_STAT0); 2242 2243 /* Mute DONE and ERROR interrupts */ 2244 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 2245 HDMI_IH_MUTE_I2CM_STAT0); 2246 2247 /* set SDA high level holding time */ 2248 hdmi_writeb(hdmi, 0x48, HDMI_I2CM_SDA_HOLD); 2249 2250 dw_hdmi_i2c_set_divs(hdmi); 2251 } 2252 2253 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 2254 { 2255 hdmi->audio_enable = true; 2256 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 2257 } 2258 2259 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 2260 { 2261 hdmi->audio_enable = false; 2262 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 2263 } 2264 2265 int rockchip_dw_hdmi_init(struct display_state *state) 2266 { 2267 struct connector_state *conn_state = &state->conn_state; 2268 const struct rockchip_connector *connector = conn_state->connector; 2269 const struct dw_hdmi_plat_data *pdata = connector->data; 2270 struct crtc_state *crtc_state = &state->crtc_state; 2271 struct dw_hdmi *hdmi; 2272 struct drm_display_mode *mode_buf; 2273 ofnode hdmi_node = conn_state->node; 2274 u32 val; 2275 2276 hdmi = malloc(sizeof(struct dw_hdmi)); 2277 if (!hdmi) 2278 return -ENOMEM; 2279 2280 memset(hdmi, 0, sizeof(struct dw_hdmi)); 2281 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 2282 if (!mode_buf) 2283 return -ENOMEM; 2284 2285 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 2286 2287 hdmi->regs = dev_read_addr_ptr(conn_state->dev); 2288 hdmi->io_width = ofnode_read_s32_default(hdmi_node, "reg-io-width", -1); 2289 2290 if (ofnode_read_bool(hdmi_node, "scramble-low-rates")) 2291 hdmi->scramble_low_rates = true; 2292 2293 if (ofnode_read_bool(hdmi_node, "hdcp1x-enable")) 2294 hdmi->hdcp1x_enable = true; 2295 else 2296 hdmi->hdcp1x_enable = false; 2297 2298 hdmi->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 2299 if (hdmi->grf <= 0) { 2300 printf("%s: Get syscon grf failed (ret=%p)\n", 2301 __func__, hdmi->grf); 2302 return -ENXIO; 2303 } 2304 2305 dw_hdmi_set_reg_wr(hdmi); 2306 2307 if (pdata->grf_vop_sel_reg) { 2308 if (crtc_state->crtc_id) 2309 val = ((1 << pdata->vop_sel_bit) | 2310 (1 << (16 + pdata->vop_sel_bit))); 2311 else 2312 val = ((0 << pdata->vop_sel_bit) | 2313 (1 << (16 + pdata->vop_sel_bit))); 2314 writel(val, hdmi->grf + pdata->grf_vop_sel_reg); 2315 } 2316 2317 hdmi->i2c = malloc(sizeof(struct dw_hdmi_i2c)); 2318 if (!hdmi->i2c) 2319 return -ENOMEM; 2320 hdmi->adap.ddc_xfer = dw_hdmi_i2c_xfer; 2321 2322 /* 2323 * Read high and low time from device tree. If not available use 2324 * the default timing scl clock rate is about 99.6KHz. 2325 */ 2326 hdmi->i2c->scl_high_ns = 2327 ofnode_read_s32_default(hdmi_node, 2328 "ddc-i2c-scl-high-time-ns", 4708); 2329 hdmi->i2c->scl_low_ns = 2330 ofnode_read_s32_default(hdmi_node, 2331 "ddc-i2c-scl-low-time-ns", 4916); 2332 2333 dw_hdmi_i2c_init(hdmi); 2334 conn_state->type = DRM_MODE_CONNECTOR_HDMIA; 2335 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 2336 2337 hdmi->dev_type = pdata->dev_type; 2338 hdmi->plat_data = pdata; 2339 hdmi->edid_data.mode_buf = mode_buf; 2340 hdmi->sample_rate = 48000; 2341 2342 conn_state->private = hdmi; 2343 dw_hdmi_set_iomux(hdmi->grf, hdmi->dev_type); 2344 dw_hdmi_detect_phy(hdmi); 2345 dw_hdmi_dev_init(hdmi); 2346 2347 return 0; 2348 } 2349 2350 void rockchip_dw_hdmi_deinit(struct display_state *state) 2351 { 2352 struct connector_state *conn_state = &state->conn_state; 2353 struct dw_hdmi *hdmi = conn_state->private; 2354 2355 if (hdmi->i2c) 2356 free(hdmi->i2c); 2357 if (hdmi->edid_data.mode_buf) 2358 free(hdmi->edid_data.mode_buf); 2359 if (hdmi) 2360 free(hdmi); 2361 } 2362 2363 int rockchip_dw_hdmi_prepare(struct display_state *state) 2364 { 2365 return 0; 2366 } 2367 2368 int rockchip_dw_hdmi_enable(struct display_state *state) 2369 { 2370 struct connector_state *conn_state = &state->conn_state; 2371 struct drm_display_mode *mode = &conn_state->mode; 2372 struct dw_hdmi *hdmi = conn_state->private; 2373 2374 if (!hdmi) 2375 return -EFAULT; 2376 2377 /* Store the display mode for plugin/DKMS poweron events */ 2378 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 2379 2380 dw_hdmi_setup(hdmi, mode, state); 2381 2382 return 0; 2383 } 2384 2385 int rockchip_dw_hdmi_disable(struct display_state *state) 2386 { 2387 struct connector_state *conn_state = &state->conn_state; 2388 struct dw_hdmi *hdmi = conn_state->private; 2389 2390 dw_hdmi_disable(hdmi, state); 2391 return 0; 2392 } 2393 2394 int rockchip_dw_hdmi_get_timing(struct display_state *state) 2395 { 2396 int ret, i; 2397 struct connector_state *conn_state = &state->conn_state; 2398 struct drm_display_mode *mode = &conn_state->mode; 2399 struct dw_hdmi *hdmi = conn_state->private; 2400 struct edid *edid = (struct edid *)conn_state->edid; 2401 unsigned int bus_format; 2402 struct overscan *overscan = &conn_state->overscan; 2403 const u8 def_modes_vic[6] = {4, 16, 2, 17, 31, 19}; 2404 2405 if (!hdmi) 2406 return -EFAULT; 2407 2408 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 2409 if (!ret) { 2410 hdmi->sink_is_hdmi = 2411 drm_detect_hdmi_monitor(edid); 2412 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 2413 ret = drm_add_edid_modes(&hdmi->edid_data, conn_state->edid); 2414 } 2415 if (ret <= 0) { 2416 hdmi->sink_is_hdmi = true; 2417 hdmi->sink_has_audio = true; 2418 do_cea_modes(&hdmi->edid_data, def_modes_vic, 2419 sizeof(def_modes_vic)); 2420 hdmi->edid_data.preferred_mode = &hdmi->edid_data.mode_buf[0]; 2421 printf("failed to get edid\n"); 2422 } 2423 drm_rk_filter_whitelist(&hdmi->edid_data); 2424 if (hdmi->phy.ops->mode_valid) 2425 hdmi->phy.ops->mode_valid(hdmi, state); 2426 drm_mode_max_resolution_filter(&hdmi->edid_data, 2427 &state->crtc_state.max_output); 2428 if (!drm_mode_prune_invalid(&hdmi->edid_data)) { 2429 printf("can't find valid hdmi mode\n"); 2430 return -EINVAL; 2431 } 2432 2433 for (i = 0; i < hdmi->edid_data.modes; i++) 2434 hdmi->edid_data.mode_buf[i].vrefresh = 2435 drm_mode_vrefresh(&hdmi->edid_data.mode_buf[i]); 2436 2437 drm_mode_sort(&hdmi->edid_data); 2438 drm_rk_selete_output(&hdmi->edid_data, &bus_format, 2439 overscan, hdmi->dev_type); 2440 2441 *mode = *hdmi->edid_data.preferred_mode; 2442 hdmi->vic = drm_match_cea_mode(mode); 2443 2444 printf("mode:%dx%d\n", mode->hdisplay, mode->vdisplay); 2445 conn_state->bus_format = bus_format; 2446 hdmi->hdmi_data.enc_in_bus_format = bus_format; 2447 hdmi->hdmi_data.enc_out_bus_format = bus_format; 2448 2449 switch (bus_format) { 2450 case MEDIA_BUS_FMT_UYVY10_1X20: 2451 conn_state->bus_format = MEDIA_BUS_FMT_YUV10_1X30; 2452 hdmi->hdmi_data.enc_in_bus_format = 2453 MEDIA_BUS_FMT_YUV10_1X30; 2454 break; 2455 case MEDIA_BUS_FMT_UYVY8_1X16: 2456 conn_state->bus_format = MEDIA_BUS_FMT_YUV8_1X24; 2457 hdmi->hdmi_data.enc_in_bus_format = 2458 MEDIA_BUS_FMT_YUV8_1X24; 2459 break; 2460 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 2461 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 2462 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420; 2463 break; 2464 } 2465 2466 return 0; 2467 } 2468 2469 int rockchip_dw_hdmi_detect(struct display_state *state) 2470 { 2471 int ret; 2472 struct connector_state *conn_state = &state->conn_state; 2473 struct dw_hdmi *hdmi = conn_state->private; 2474 2475 if (!hdmi) 2476 return -EFAULT; 2477 2478 ret = dw_hdmi_detect_hotplug(hdmi, state); 2479 2480 return ret; 2481 } 2482 2483 int rockchip_dw_hdmi_get_edid(struct display_state *state) 2484 { 2485 int ret; 2486 struct connector_state *conn_state = &state->conn_state; 2487 struct dw_hdmi *hdmi = conn_state->private; 2488 2489 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 2490 2491 return ret; 2492 } 2493 2494 int inno_dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data) 2495 { 2496 struct display_state *state = (struct display_state *)data; 2497 struct connector_state *conn_state = &state->conn_state; 2498 u32 color_depth, bus_width; 2499 2500 color_depth = 2501 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 2502 2503 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 2504 bus_width = color_depth / 2; 2505 else if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 2506 bus_width = color_depth; 2507 else 2508 bus_width = 8; 2509 rockchip_phy_set_bus_width(conn_state->phy, bus_width); 2510 rockchip_phy_set_pll(conn_state->phy, 2511 conn_state->mode.crtc_clock * 1000); 2512 if (hdmi->edid_data.display_info.hdmi.scdc.supported) 2513 rockchip_dw_hdmi_scdc_set_tmds_rate(hdmi); 2514 rockchip_phy_power_on(conn_state->phy); 2515 2516 return 0; 2517 } 2518 2519 void inno_dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 2520 { 2521 } 2522 2523 enum drm_connector_status 2524 inno_dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data) 2525 { 2526 enum drm_connector_status status; 2527 struct display_state *state = (struct display_state *)data; 2528 2529 status = dw_hdmi_phy_read_hpd(hdmi, state); 2530 2531 if (hdmi->dev_type == RK3328_HDMI) { 2532 if (status == connector_status_connected) 2533 inno_dw_hdmi_set_domain(hdmi->grf, 1); 2534 else 2535 inno_dw_hdmi_set_domain(hdmi->grf, 0); 2536 } 2537 2538 return status; 2539 } 2540 2541 void inno_dw_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data) 2542 { 2543 struct display_state *state = (struct display_state *)data; 2544 struct connector_state *conn_state = &state->conn_state; 2545 struct hdmi_edid_data *edid_data = &hdmi->edid_data; 2546 unsigned long rate; 2547 int i, ret; 2548 struct drm_display_mode *mode_buf = edid_data->mode_buf; 2549 2550 for (i = 0; i < edid_data->modes; i++) { 2551 if (edid_data->mode_buf[i].invalid) 2552 continue; 2553 if (edid_data->mode_buf[i].flags & DRM_MODE_FLAG_DBLCLK) 2554 rate = mode_buf[i].clock * 1000 * 2; 2555 else 2556 rate = mode_buf[i].clock * 1000; 2557 2558 /* Check whether mode is out of phy cfg range. */ 2559 ret = rockchip_phy_round_rate(conn_state->phy, rate); 2560 2561 if (ret < 0) 2562 edid_data->mode_buf[i].invalid = true; 2563 } 2564 } 2565