1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Rockchip USBDP Combo PHY with Samsung IP block driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd 6 */ 7 8 #include <config.h> 9 #include <common.h> 10 #include <errno.h> 11 #include <malloc.h> 12 #include <asm/unaligned.h> 13 #include <asm/io.h> 14 #include <clk.h> 15 #include <dm/device.h> 16 #include <dm/of_access.h> 17 #include <dm/lists.h> 18 #include <dm/read.h> 19 #include <generic-phy.h> 20 #include <linux/bitfield.h> 21 #include <linux/hdmi.h> 22 #include <linux/media-bus-format.h> 23 #include <linux/list.h> 24 #include <asm/gpio.h> 25 #include <generic-phy.h> 26 #include <regmap.h> 27 #include <reset.h> 28 #include <drm/drm_dp_helper.h> 29 30 #include "rockchip_display.h" 31 #include "rockchip_crtc.h" 32 #include "rockchip_connector.h" 33 34 #define DPTX_VERSION_NUMBER 0x0000 35 #define DPTX_VERSION_TYPE 0x0004 36 #define DPTX_ID 0x0008 37 38 #define DPTX_CONFIG_REG1 0x0100 39 #define DPTX_CONFIG_REG2 0x0104 40 #define DPTX_CONFIG_REG3 0x0108 41 42 #define DPTX_CCTL 0x0200 43 #define FORCE_HPD BIT(4) 44 #define DEFAULT_FAST_LINK_TRAIN_EN BIT(2) 45 #define ENHANCE_FRAMING_EN BIT(1) 46 #define SCRAMBLE_DIS BIT(0) 47 #define DPTX_SOFT_RESET_CTRL 0x0204 48 #define VIDEO_RESET BIT(5) 49 #define AUX_RESET BIT(4) 50 #define AUDIO_SAMPLER_RESET BIT(3) 51 #define PHY_SOFT_RESET BIT(1) 52 #define CONTROLLER_RESET BIT(0) 53 54 #define DPTX_VSAMPLE_CTRL 0x0300 55 #define PIXEL_MODE_SELECT GENMASK(22, 21) 56 #define VIDEO_MAPPING GENMASK(20, 16) 57 #define VIDEO_STREAM_ENABLE BIT(5) 58 #define DPTX_VSAMPLE_STUFF_CTRL1 0x0304 59 #define DPTX_VSAMPLE_STUFF_CTRL2 0x0308 60 #define DPTX_VINPUT_POLARITY_CTRL 0x030c 61 #define DE_IN_POLARITY BIT(2) 62 #define HSYNC_IN_POLARITY BIT(1) 63 #define VSYNC_IN_POLARITY BIT(0) 64 #define DPTX_VIDEO_CONFIG1 0x0310 65 #define HACTIVE GENMASK(31, 16) 66 #define HBLANK GENMASK(15, 2) 67 #define I_P BIT(1) 68 #define R_V_BLANK_IN_OSC BIT(0) 69 #define DPTX_VIDEO_CONFIG2 0x0314 70 #define VBLANK GENMASK(31, 16) 71 #define VACTIVE GENMASK(15, 0) 72 #define DPTX_VIDEO_CONFIG3 0x0318 73 #define H_SYNC_WIDTH GENMASK(31, 16) 74 #define H_FRONT_PORCH GENMASK(15, 0) 75 #define DPTX_VIDEO_CONFIG4 0x031c 76 #define V_SYNC_WIDTH GENMASK(31, 16) 77 #define V_FRONT_PORCH GENMASK(15, 0) 78 #define DPTX_VIDEO_CONFIG5 0x0320 79 #define INIT_THRESHOLD_HI GENMASK(22, 21) 80 #define AVERAGE_BYTES_PER_TU_FRAC GENMASK(19, 16) 81 #define INIT_THRESHOLD GENMASK(13, 7) 82 #define AVERAGE_BYTES_PER_TU GENMASK(6, 0) 83 #define DPTX_VIDEO_MSA1 0x0324 84 #define VSTART GENMASK(31, 16) 85 #define HSTART GENMASK(15, 0) 86 #define DPTX_VIDEO_MSA2 0x0328 87 #define MISC0 GENMASK(31, 24) 88 #define DPTX_VIDEO_MSA3 0x032c 89 #define MISC1 GENMASK(31, 24) 90 #define DPTX_VIDEO_HBLANK_INTERVAL 0x0330 91 #define HBLANK_INTERVAL_EN BIT(16) 92 #define HBLANK_INTERVAL GENMASK(15, 0) 93 94 #define DPTX_AUD_CONFIG1 0x0400 95 #define AUDIO_TIMESTAMP_VERSION_NUM GENMASK(29, 24) 96 #define AUDIO_PACKET_ID GENMASK(23, 16) 97 #define AUDIO_MUTE BIT(15) 98 #define NUM_CHANNELS GENMASK(14, 12) 99 #define HBR_MODE_ENABLE BIT(10) 100 #define AUDIO_DATA_WIDTH GENMASK(9, 5) 101 #define AUDIO_DATA_IN_EN GENMASK(4, 1) 102 #define AUDIO_INF_SELECT BIT(0) 103 104 #define DPTX_SDP_VERTICAL_CTRL 0x0500 105 #define EN_VERTICAL_SDP BIT(2) 106 #define EN_AUDIO_STREAM_SDP BIT(1) 107 #define EN_AUDIO_TIMESTAMP_SDP BIT(0) 108 #define DPTX_SDP_HORIZONTAL_CTRL 0x0504 109 #define EN_HORIZONTAL_SDP BIT(2) 110 #define DPTX_SDP_STATUS_REGISTER 0x0508 111 #define DPTX_SDP_MANUAL_CTRL 0x050c 112 #define DPTX_SDP_STATUS_EN 0x0510 113 114 #define DPTX_SDP_REGISTER_BANK 0x0600 115 #define SDP_REGS GENMASK(31, 0) 116 117 #define DPTX_PHYIF_CTRL 0x0a00 118 #define PHY_WIDTH BIT(25) 119 #define PHY_POWERDOWN GENMASK(20, 17) 120 #define PHY_BUSY GENMASK(15, 12) 121 #define SSC_DIS BIT(16) 122 #define XMIT_ENABLE GENMASK(11, 8) 123 #define PHY_LANES GENMASK(7, 6) 124 #define PHY_RATE GENMASK(5, 4) 125 #define TPS_SEL GENMASK(3, 0) 126 #define DPTX_PHY_TX_EQ 0x0a04 127 #define DPTX_CUSTOMPAT0 0x0a08 128 #define DPTX_CUSTOMPAT1 0x0a0c 129 #define DPTX_CUSTOMPAT2 0x0a10 130 #define DPTX_HBR2_COMPLIANCE_SCRAMBLER_RESET 0x0a14 131 #define DPTX_PHYIF_PWRDOWN_CTRL 0x0a18 132 133 #define DPTX_AUX_CMD 0x0b00 134 #define AUX_CMD_TYPE GENMASK(31, 28) 135 #define AUX_ADDR GENMASK(27, 8) 136 #define I2C_ADDR_ONLY BIT(4) 137 #define AUX_LEN_REQ GENMASK(3, 0) 138 #define DPTX_AUX_STATUS 0x0b04 139 #define AUX_TIMEOUT BIT(17) 140 #define AUX_BYTES_READ GENMASK(23, 19) 141 #define AUX_STATUS GENMASK(7, 4) 142 #define DPTX_AUX_DATA0 0x0b08 143 #define DPTX_AUX_DATA1 0x0b0c 144 #define DPTX_AUX_DATA2 0x0b10 145 #define DPTX_AUX_DATA3 0x0b14 146 147 #define DPTX_GENERAL_INTERRUPT 0x0d00 148 #define VIDEO_FIFO_OVERFLOW_STREAM0 BIT(6) 149 #define AUDIO_FIFO_OVERFLOW_STREAM0 BIT(5) 150 #define SDP_EVENT_STREAM0 BIT(4) 151 #define AUX_CMD_INVALID BIT(3) 152 #define AUX_REPLY_EVENT BIT(1) 153 #define HPD_EVENT BIT(0) 154 #define DPTX_GENERAL_INTERRUPT_ENABLE 0x0d04 155 #define AUX_REPLY_EVENT_EN BIT(1) 156 #define HPD_EVENT_EN BIT(0) 157 #define DPTX_HPD_STATUS 0x0d08 158 #define HPD_STATE GENMASK(11, 9) 159 #define HPD_STATUS BIT(8) 160 #define HPD_HOT_UNPLUG BIT(2) 161 #define HPD_HOT_PLUG BIT(1) 162 #define HPD_IRQ BIT(0) 163 #define DPTX_HPD_INTERRUPT_ENABLE 0x0d0c 164 #define HPD_UNPLUG_ERR_EN BIT(3) 165 #define HPD_UNPLUG_EN BIT(2) 166 #define HPD_PLUG_EN BIT(1) 167 #define HPD_IRQ_EN BIT(0) 168 169 #define DPTX_MAX_REGISTER DPTX_HPD_INTERRUPT_ENABLE 170 171 #define SDP_REG_BANK_SIZE 16 172 173 struct drm_dp_link_caps { 174 bool enhanced_framing; 175 bool tps3_supported; 176 bool tps4_supported; 177 bool channel_coding; 178 bool ssc; 179 }; 180 181 struct drm_dp_link_train_set { 182 unsigned int voltage_swing[4]; 183 unsigned int pre_emphasis[4]; 184 }; 185 186 struct drm_dp_link_train { 187 struct drm_dp_link_train_set request; 188 struct drm_dp_link_train_set adjust; 189 bool clock_recovered; 190 bool channel_equalized; 191 }; 192 193 struct dw_dp_link { 194 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 195 unsigned char revision; 196 unsigned int rate; 197 unsigned int lanes; 198 struct drm_dp_link_caps caps; 199 struct drm_dp_link_train train; 200 u8 sink_count; 201 u8 vsc_sdp_extension_for_colorimetry_supported; 202 }; 203 204 struct dw_dp_video { 205 struct drm_display_mode mode; 206 u32 bus_format; 207 u8 video_mapping; 208 u8 pixel_mode; 209 u8 color_format; 210 u8 bpc; 211 u8 bpp; 212 }; 213 214 struct dw_dp_sdp { 215 struct dp_sdp_header header; 216 u8 db[32]; 217 unsigned long flags; 218 }; 219 220 struct dw_dp_chip_data { 221 int pixel_mode; 222 }; 223 224 struct dw_dp { 225 struct rockchip_connector connector; 226 struct udevice *dev; 227 struct regmap *regmap; 228 struct phy phy; 229 struct reset_ctl reset; 230 int id; 231 232 struct gpio_desc hpd_gpio; 233 struct drm_dp_aux aux; 234 struct dw_dp_link link; 235 struct dw_dp_video video; 236 237 bool force_hpd; 238 bool force_output; 239 u32 max_link_rate; 240 }; 241 242 enum { 243 SOURCE_STATE_IDLE, 244 SOURCE_STATE_UNPLUG, 245 SOURCE_STATE_HPD_TIMEOUT = 4, 246 SOURCE_STATE_PLUG = 7 247 }; 248 249 enum { 250 DPTX_VM_RGB_6BIT, 251 DPTX_VM_RGB_8BIT, 252 DPTX_VM_RGB_10BIT, 253 DPTX_VM_RGB_12BIT, 254 DPTX_VM_RGB_16BIT, 255 DPTX_VM_YCBCR444_8BIT, 256 DPTX_VM_YCBCR444_10BIT, 257 DPTX_VM_YCBCR444_12BIT, 258 DPTX_VM_YCBCR444_16BIT, 259 DPTX_VM_YCBCR422_8BIT, 260 DPTX_VM_YCBCR422_10BIT, 261 DPTX_VM_YCBCR422_12BIT, 262 DPTX_VM_YCBCR422_16BIT, 263 DPTX_VM_YCBCR420_8BIT, 264 DPTX_VM_YCBCR420_10BIT, 265 DPTX_VM_YCBCR420_12BIT, 266 DPTX_VM_YCBCR420_16BIT, 267 }; 268 269 enum { 270 DPTX_MP_SINGLE_PIXEL, 271 DPTX_MP_DUAL_PIXEL, 272 DPTX_MP_QUAD_PIXEL, 273 }; 274 275 enum { 276 DPTX_SDP_VERTICAL_INTERVAL = BIT(0), 277 DPTX_SDP_HORIZONTAL_INTERVAL = BIT(1), 278 }; 279 280 enum { 281 DPTX_PHY_PATTERN_NONE, 282 DPTX_PHY_PATTERN_TPS_1, 283 DPTX_PHY_PATTERN_TPS_2, 284 DPTX_PHY_PATTERN_TPS_3, 285 DPTX_PHY_PATTERN_TPS_4, 286 DPTX_PHY_PATTERN_SERM, 287 DPTX_PHY_PATTERN_PBRS7, 288 DPTX_PHY_PATTERN_CUSTOM_80BIT, 289 DPTX_PHY_PATTERN_CP2520_1, 290 DPTX_PHY_PATTERN_CP2520_2, 291 }; 292 293 enum { 294 DPTX_PHYRATE_RBR, 295 DPTX_PHYRATE_HBR, 296 DPTX_PHYRATE_HBR2, 297 DPTX_PHYRATE_HBR3, 298 }; 299 300 struct dw_dp_output_format { 301 u32 bus_format; 302 u32 color_format; 303 u8 video_mapping; 304 u8 bpc; 305 u8 bpp; 306 }; 307 308 static const struct dw_dp_output_format possible_output_fmts[] = { 309 { MEDIA_BUS_FMT_RGB101010_1X30, DRM_COLOR_FORMAT_RGB444, 310 DPTX_VM_RGB_10BIT, 10, 30 }, 311 { MEDIA_BUS_FMT_RGB888_1X24, DRM_COLOR_FORMAT_RGB444, 312 DPTX_VM_RGB_8BIT, 8, 24 }, 313 { MEDIA_BUS_FMT_YUV10_1X30, DRM_COLOR_FORMAT_YCRCB444, 314 DPTX_VM_YCBCR444_10BIT, 10, 30 }, 315 { MEDIA_BUS_FMT_YUV8_1X24, DRM_COLOR_FORMAT_YCRCB444, 316 DPTX_VM_YCBCR444_8BIT, 8, 24}, 317 { MEDIA_BUS_FMT_YUYV10_1X20, DRM_COLOR_FORMAT_YCRCB422, 318 DPTX_VM_YCBCR422_10BIT, 10, 20 }, 319 { MEDIA_BUS_FMT_YUYV8_1X16, DRM_COLOR_FORMAT_YCRCB422, 320 DPTX_VM_YCBCR422_8BIT, 8, 16 }, 321 { MEDIA_BUS_FMT_UYYVYY10_0_5X30, DRM_COLOR_FORMAT_YCRCB420, 322 DPTX_VM_YCBCR420_10BIT, 10, 15 }, 323 { MEDIA_BUS_FMT_UYYVYY8_0_5X24, DRM_COLOR_FORMAT_YCRCB420, 324 DPTX_VM_YCBCR420_8BIT, 8, 12 }, 325 { MEDIA_BUS_FMT_RGB666_1X24_CPADHI, DRM_COLOR_FORMAT_RGB444, 326 DPTX_VM_RGB_6BIT, 6, 18 }, 327 }; 328 329 static int dw_dp_aux_write_data(struct dw_dp *dp, const u8 *buffer, size_t size) 330 { 331 size_t i, j; 332 333 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 334 size_t num = min_t(size_t, size - i * 4, 4); 335 u32 value = 0; 336 337 for (j = 0; j < num; j++) 338 value |= buffer[i * 4 + j] << (j * 8); 339 340 regmap_write(dp->regmap, DPTX_AUX_DATA0 + i * 4, value); 341 } 342 343 return size; 344 } 345 346 static int dw_dp_aux_read_data(struct dw_dp *dp, u8 *buffer, size_t size) 347 { 348 size_t i, j; 349 350 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 351 size_t num = min_t(size_t, size - i * 4, 4); 352 u32 value; 353 354 regmap_read(dp->regmap, DPTX_AUX_DATA0 + i * 4, &value); 355 356 for (j = 0; j < num; j++) 357 buffer[i * 4 + j] = value >> (j * 8); 358 } 359 360 return size; 361 } 362 363 static ssize_t dw_dp_aux_transfer(struct drm_dp_aux *aux, 364 struct drm_dp_aux_msg *msg) 365 { 366 u32 status, value; 367 ssize_t ret = 0; 368 int timeout = 0; 369 struct dw_dp *dp = dev_get_priv(aux->dev); 370 371 if (WARN_ON(msg->size > 16)) 372 return -E2BIG; 373 374 switch (msg->request & ~DP_AUX_I2C_MOT) { 375 case DP_AUX_NATIVE_WRITE: 376 case DP_AUX_I2C_WRITE: 377 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 378 ret = dw_dp_aux_write_data(dp, msg->buffer, msg->size); 379 if (ret < 0) 380 return ret; 381 break; 382 case DP_AUX_NATIVE_READ: 383 case DP_AUX_I2C_READ: 384 break; 385 default: 386 return -EINVAL; 387 } 388 389 if (msg->size > 0) 390 value = FIELD_PREP(AUX_LEN_REQ, msg->size - 1); 391 else 392 value = FIELD_PREP(I2C_ADDR_ONLY, 1); 393 394 value |= FIELD_PREP(AUX_CMD_TYPE, msg->request); 395 value |= FIELD_PREP(AUX_ADDR, msg->address); 396 regmap_write(dp->regmap, DPTX_AUX_CMD, value); 397 398 timeout = regmap_read_poll_timeout(dp->regmap, DPTX_GENERAL_INTERRUPT, 399 status, status & AUX_REPLY_EVENT, 400 200, 10); 401 402 if (timeout) { 403 printf("timeout waiting for AUX reply\n"); 404 return -ETIMEDOUT; 405 } 406 regmap_write(dp->regmap, DPTX_GENERAL_INTERRUPT, AUX_REPLY_EVENT); 407 408 regmap_read(dp->regmap, DPTX_AUX_STATUS, &value); 409 if (value & AUX_TIMEOUT) { 410 printf("aux timeout\n"); 411 return -ETIMEDOUT; 412 } 413 414 msg->reply = FIELD_GET(AUX_STATUS, value); 415 416 if (msg->size > 0 && msg->reply == DP_AUX_NATIVE_REPLY_ACK) { 417 if (msg->request & DP_AUX_I2C_READ) { 418 size_t count = FIELD_GET(AUX_BYTES_READ, value) - 1; 419 420 if (count != msg->size) { 421 printf("aux fail to read %lu bytes\n", count); 422 return -EBUSY; 423 } 424 425 ret = dw_dp_aux_read_data(dp, msg->buffer, count); 426 if (ret < 0) 427 return ret; 428 } 429 } 430 431 return ret; 432 } 433 434 static bool dw_dp_bandwidth_ok(struct dw_dp *dp, 435 const struct drm_display_mode *mode, u32 bpp, 436 unsigned int lanes, unsigned int rate) 437 { 438 u32 max_bw, req_bw; 439 440 req_bw = mode->clock * bpp / 8; 441 max_bw = lanes * rate; 442 if (req_bw > max_bw) 443 return false; 444 445 return true; 446 } 447 448 static void dw_dp_hpd_init(struct dw_dp *dp) 449 { 450 if (dm_gpio_is_valid(&dp->hpd_gpio) || dp->force_hpd) { 451 regmap_update_bits(dp->regmap, DPTX_CCTL, FORCE_HPD, 452 FIELD_PREP(FORCE_HPD, 1)); 453 return; 454 } 455 456 /* Enable all HPD interrupts */ 457 regmap_update_bits(dp->regmap, DPTX_HPD_INTERRUPT_ENABLE, 458 HPD_UNPLUG_EN | HPD_PLUG_EN | HPD_IRQ_EN, 459 FIELD_PREP(HPD_UNPLUG_EN, 1) | 460 FIELD_PREP(HPD_PLUG_EN, 1) | 461 FIELD_PREP(HPD_IRQ_EN, 1)); 462 463 /* Enable all top-level interrupts */ 464 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, 465 HPD_EVENT_EN, FIELD_PREP(HPD_EVENT_EN, 1)); 466 } 467 468 static void dw_dp_aux_init(struct dw_dp *dp) 469 { 470 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, 471 FIELD_PREP(AUX_RESET, 1)); 472 udelay(10); 473 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, 474 FIELD_PREP(AUX_RESET, 0)); 475 476 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, 477 AUX_REPLY_EVENT_EN, 478 FIELD_PREP(AUX_REPLY_EVENT_EN, 1)); 479 } 480 481 static void dw_dp_init(struct dw_dp *dp) 482 { 483 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, 484 FIELD_PREP(CONTROLLER_RESET, 1)); 485 udelay(10); 486 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, 487 FIELD_PREP(CONTROLLER_RESET, 0)); 488 489 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, 490 FIELD_PREP(PHY_SOFT_RESET, 1)); 491 udelay(10); 492 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, 493 FIELD_PREP(PHY_SOFT_RESET, 0)); 494 495 regmap_update_bits(dp->regmap, DPTX_CCTL, DEFAULT_FAST_LINK_TRAIN_EN, 496 FIELD_PREP(DEFAULT_FAST_LINK_TRAIN_EN, 0)); 497 498 dw_dp_hpd_init(dp); 499 dw_dp_aux_init(dp); 500 } 501 502 static void dw_dp_phy_set_pattern(struct dw_dp *dp, u32 pattern) 503 { 504 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, TPS_SEL, 505 FIELD_PREP(TPS_SEL, pattern)); 506 } 507 508 static void dw_dp_phy_xmit_enable(struct dw_dp *dp, u32 lanes) 509 { 510 u32 xmit_enable; 511 512 switch (lanes) { 513 case 4: 514 case 2: 515 case 1: 516 xmit_enable = GENMASK(lanes - 1, 0); 517 break; 518 case 0: 519 default: 520 xmit_enable = 0; 521 break; 522 } 523 524 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, XMIT_ENABLE, 525 FIELD_PREP(XMIT_ENABLE, xmit_enable)); 526 } 527 528 static int dw_dp_link_power_up(struct dw_dp *dp) 529 { 530 struct dw_dp_link *link = &dp->link; 531 u8 value; 532 int ret; 533 534 if (link->revision < 0x11) 535 return 0; 536 537 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value); 538 if (ret < 0) 539 return ret; 540 541 value &= ~DP_SET_POWER_MASK; 542 value |= DP_SET_POWER_D0; 543 544 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value); 545 if (ret < 0) 546 return ret; 547 548 udelay(1000); 549 return 0; 550 } 551 552 static int dw_dp_link_probe(struct dw_dp *dp) 553 { 554 struct dw_dp_link *link = &dp->link; 555 u8 dpcd; 556 int ret; 557 558 drm_dp_dpcd_writeb(&dp->aux, DP_MSTM_CTRL, 0); 559 ret = drm_dp_read_dpcd_caps(&dp->aux, link->dpcd); 560 if (ret < 0) 561 return ret; 562 563 ret = drm_dp_dpcd_readb(&dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, 564 &dpcd); 565 if (ret < 0) 566 return ret; 567 568 link->vsc_sdp_extension_for_colorimetry_supported = 569 !!(dpcd & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED); 570 571 link->revision = link->dpcd[DP_DPCD_REV]; 572 link->rate = min_t(u32, min(dp->max_link_rate, dp->phy.attrs.max_link_rate * 100), 573 drm_dp_max_link_rate(link->dpcd)); 574 link->lanes = min_t(u8, dp->phy.attrs.bus_width, 575 drm_dp_max_lane_count(link->dpcd)); 576 577 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(link->dpcd); 578 link->caps.tps3_supported = drm_dp_tps3_supported(link->dpcd); 579 link->caps.tps4_supported = drm_dp_tps4_supported(link->dpcd); 580 link->caps.channel_coding = drm_dp_channel_coding_supported(link->dpcd); 581 link->caps.ssc = !!(link->dpcd[DP_MAX_DOWNSPREAD] & 582 DP_MAX_DOWNSPREAD_0_5); 583 584 return 0; 585 } 586 587 static int dw_dp_link_train_update_vs_emph(struct dw_dp *dp) 588 { 589 struct dw_dp_link *link = &dp->link; 590 struct drm_dp_link_train_set *request = &link->train.request; 591 union phy_configure_opts phy_cfg; 592 unsigned int lanes = link->lanes, *vs, *pe; 593 u8 buf[4]; 594 int i, ret; 595 596 vs = request->voltage_swing; 597 pe = request->pre_emphasis; 598 599 for (i = 0; i < lanes; i++) { 600 phy_cfg.dp.voltage[i] = vs[i]; 601 phy_cfg.dp.pre[i] = pe[i]; 602 } 603 phy_cfg.dp.lanes = lanes; 604 phy_cfg.dp.link_rate = link->rate / 100; 605 phy_cfg.dp.set_lanes = false; 606 phy_cfg.dp.set_rate = false; 607 phy_cfg.dp.set_voltages = true; 608 ret = generic_phy_configure(&dp->phy, &phy_cfg); 609 if (ret) 610 return ret; 611 612 for (i = 0; i < lanes; i++) 613 buf[i] = (vs[i] << DP_TRAIN_VOLTAGE_SWING_SHIFT) | 614 (pe[i] << DP_TRAIN_PRE_EMPHASIS_SHIFT); 615 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, lanes); 616 if (ret < 0) 617 return ret; 618 619 return 0; 620 } 621 622 static int dw_dp_link_configure(struct dw_dp *dp) 623 { 624 struct dw_dp_link *link = &dp->link; 625 union phy_configure_opts phy_cfg; 626 u8 buf[2]; 627 int ret, phy_rate; 628 629 /* Move PHY to P3 */ 630 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 631 FIELD_PREP(PHY_POWERDOWN, 0x3)); 632 633 phy_cfg.dp.lanes = link->lanes; 634 phy_cfg.dp.link_rate = link->rate / 100; 635 phy_cfg.dp.ssc = link->caps.ssc; 636 phy_cfg.dp.set_lanes = true; 637 phy_cfg.dp.set_rate = true; 638 phy_cfg.dp.set_voltages = false; 639 ret = generic_phy_configure(&dp->phy, &phy_cfg); 640 if (ret) 641 return ret; 642 643 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, 644 FIELD_PREP(PHY_LANES, link->lanes / 2)); 645 646 switch (link->rate) { 647 case 810000: 648 phy_rate = DPTX_PHYRATE_HBR3; 649 break; 650 case 540000: 651 phy_rate = DPTX_PHYRATE_HBR2; 652 break; 653 case 270000: 654 phy_rate = DPTX_PHYRATE_HBR; 655 break; 656 case 162000: 657 default: 658 phy_rate = DPTX_PHYRATE_RBR; 659 break; 660 } 661 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_RATE, 662 FIELD_PREP(PHY_RATE, phy_rate)); 663 664 /* Move PHY to P0 */ 665 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 666 FIELD_PREP(PHY_POWERDOWN, 0x0)); 667 668 dw_dp_phy_xmit_enable(dp, link->lanes); 669 670 buf[0] = drm_dp_link_rate_to_bw_code(link->rate); 671 buf[1] = link->lanes; 672 673 if (link->caps.enhanced_framing) { 674 buf[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 675 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 676 FIELD_PREP(ENHANCE_FRAMING_EN, 1)); 677 } else { 678 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 679 FIELD_PREP(ENHANCE_FRAMING_EN, 0)); 680 } 681 682 ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, sizeof(buf)); 683 if (ret < 0) 684 return ret; 685 686 buf[0] = link->caps.ssc ? DP_SPREAD_AMP_0_5 : 0; 687 buf[1] = link->caps.channel_coding ? DP_SET_ANSI_8B10B : 0; 688 689 ret = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, 690 sizeof(buf)); 691 if (ret < 0) 692 return ret; 693 694 return 0; 695 } 696 697 static void dw_dp_link_train_init(struct drm_dp_link_train *train) 698 { 699 struct drm_dp_link_train_set *request = &train->request; 700 struct drm_dp_link_train_set *adjust = &train->adjust; 701 unsigned int i; 702 703 for (i = 0; i < 4; i++) { 704 request->voltage_swing[i] = 0; 705 adjust->voltage_swing[i] = 0; 706 707 request->pre_emphasis[i] = 0; 708 adjust->pre_emphasis[i] = 0; 709 } 710 711 train->clock_recovered = false; 712 train->channel_equalized = false; 713 } 714 715 static int dw_dp_link_train_set_pattern(struct dw_dp *dp, u32 pattern) 716 { 717 u8 buf = 0; 718 int ret; 719 720 if (pattern && pattern != DP_TRAINING_PATTERN_4) { 721 buf |= DP_LINK_SCRAMBLING_DISABLE; 722 723 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, 724 FIELD_PREP(SCRAMBLE_DIS, 1)); 725 } else { 726 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, 727 FIELD_PREP(SCRAMBLE_DIS, 0)); 728 } 729 730 switch (pattern) { 731 case DP_TRAINING_PATTERN_DISABLE: 732 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE); 733 break; 734 case DP_TRAINING_PATTERN_1: 735 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_1); 736 break; 737 case DP_TRAINING_PATTERN_2: 738 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_2); 739 break; 740 case DP_TRAINING_PATTERN_3: 741 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_3); 742 break; 743 case DP_TRAINING_PATTERN_4: 744 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_4); 745 break; 746 default: 747 return -EINVAL; 748 } 749 750 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 751 buf | pattern); 752 if (ret < 0) 753 return ret; 754 755 return 0; 756 } 757 758 static void dw_dp_link_get_adjustments(struct dw_dp_link *link, 759 u8 status[DP_LINK_STATUS_SIZE]) 760 { 761 struct drm_dp_link_train_set *adjust = &link->train.adjust; 762 unsigned int i; 763 764 for (i = 0; i < link->lanes; i++) { 765 adjust->voltage_swing[i] = 766 drm_dp_get_adjust_request_voltage(status, i) >> 767 DP_TRAIN_VOLTAGE_SWING_SHIFT; 768 769 adjust->pre_emphasis[i] = 770 drm_dp_get_adjust_request_pre_emphasis(status, i) >> 771 DP_TRAIN_PRE_EMPHASIS_SHIFT; 772 } 773 } 774 775 static void dw_dp_link_train_adjust(struct drm_dp_link_train *train) 776 { 777 struct drm_dp_link_train_set *request = &train->request; 778 struct drm_dp_link_train_set *adjust = &train->adjust; 779 unsigned int i; 780 781 for (i = 0; i < 4; i++) 782 if (request->voltage_swing[i] != adjust->voltage_swing[i]) 783 request->voltage_swing[i] = adjust->voltage_swing[i]; 784 785 for (i = 0; i < 4; i++) 786 if (request->pre_emphasis[i] != adjust->pre_emphasis[i]) 787 request->pre_emphasis[i] = adjust->pre_emphasis[i]; 788 } 789 790 static int dw_dp_link_clock_recovery(struct dw_dp *dp) 791 { 792 struct dw_dp_link *link = &dp->link; 793 u8 status[DP_LINK_STATUS_SIZE]; 794 unsigned int tries = 0; 795 int ret; 796 797 ret = dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_1); 798 if (ret) 799 return ret; 800 801 for (;;) { 802 ret = dw_dp_link_train_update_vs_emph(dp); 803 if (ret) 804 return ret; 805 806 drm_dp_link_train_clock_recovery_delay(link->dpcd); 807 808 ret = drm_dp_dpcd_read_link_status(&dp->aux, status); 809 if (ret < 0) { 810 dev_err(dp->dev, "failed to read link status: %d\n", 811 ret); 812 return ret; 813 } 814 815 if (drm_dp_clock_recovery_ok(status, link->lanes)) { 816 link->train.clock_recovered = true; 817 break; 818 } 819 820 dw_dp_link_get_adjustments(link, status); 821 822 if (link->train.request.voltage_swing[0] == 823 link->train.adjust.voltage_swing[0]) 824 tries++; 825 else 826 tries = 0; 827 828 if (tries == 5) 829 break; 830 831 dw_dp_link_train_adjust(&link->train); 832 } 833 834 return 0; 835 } 836 837 static int dw_dp_link_channel_equalization(struct dw_dp *dp) 838 { 839 struct dw_dp_link *link = &dp->link; 840 u8 status[DP_LINK_STATUS_SIZE], pattern; 841 unsigned int tries; 842 int ret; 843 844 if (link->caps.tps4_supported) 845 pattern = DP_TRAINING_PATTERN_4; 846 else if (link->caps.tps3_supported) 847 pattern = DP_TRAINING_PATTERN_3; 848 else 849 pattern = DP_TRAINING_PATTERN_2; 850 ret = dw_dp_link_train_set_pattern(dp, pattern); 851 if (ret) 852 return ret; 853 854 for (tries = 1; tries < 5; tries++) { 855 ret = dw_dp_link_train_update_vs_emph(dp); 856 if (ret) 857 return ret; 858 859 drm_dp_link_train_channel_eq_delay(link->dpcd); 860 861 ret = drm_dp_dpcd_read_link_status(&dp->aux, status); 862 if (ret < 0) 863 return ret; 864 865 if (!drm_dp_clock_recovery_ok(status, link->lanes)) { 866 dev_err(dp->dev, 867 "clock recovery lost while eq\n"); 868 link->train.clock_recovered = false; 869 break; 870 } 871 872 if (drm_dp_channel_eq_ok(status, link->lanes)) { 873 link->train.channel_equalized = true; 874 break; 875 } 876 877 dw_dp_link_get_adjustments(link, status); 878 dw_dp_link_train_adjust(&link->train); 879 } 880 881 return 0; 882 } 883 884 static int dw_dp_link_downgrade(struct dw_dp *dp) 885 { 886 struct dw_dp_link *link = &dp->link; 887 struct dw_dp_video *video = &dp->video; 888 889 switch (link->rate) { 890 case 162000: 891 return -EINVAL; 892 case 270000: 893 link->rate = 162000; 894 break; 895 case 540000: 896 link->rate = 270000; 897 break; 898 case 810000: 899 link->rate = 540000; 900 break; 901 } 902 903 if (!dw_dp_bandwidth_ok(dp, &video->mode, video->bpp, link->lanes, 904 link->rate)) 905 return -E2BIG; 906 907 return 0; 908 } 909 910 static int dw_dp_link_train(struct dw_dp *dp) 911 { 912 struct dw_dp_link *link = &dp->link; 913 int ret; 914 915 retry: 916 dw_dp_link_train_init(&link->train); 917 918 printf("training link: %u lane%s at %u MHz\n", 919 link->lanes, (link->lanes > 1) ? "s" : "", link->rate / 100); 920 921 ret = dw_dp_link_configure(dp); 922 if (ret < 0) { 923 dev_err(dp->dev, "failed to configure DP link: %d\n", ret); 924 return ret; 925 } 926 927 ret = dw_dp_link_clock_recovery(dp); 928 if (ret < 0) { 929 dev_err(dp->dev, "clock recovery failed: %d\n", ret); 930 goto out; 931 } 932 933 if (!link->train.clock_recovered) { 934 dev_err(dp->dev, "clock recovery failed, downgrading link\n"); 935 936 ret = dw_dp_link_downgrade(dp); 937 if (ret < 0) 938 goto out; 939 else 940 goto retry; 941 } 942 943 printf("clock recovery succeeded\n"); 944 945 ret = dw_dp_link_channel_equalization(dp); 946 if (ret < 0) { 947 dev_err(dp->dev, "channel equalization failed: %d\n", ret); 948 goto out; 949 } 950 951 if (!link->train.channel_equalized) { 952 dev_err(dp->dev, 953 "channel equalization failed, downgrading link\n"); 954 955 ret = dw_dp_link_downgrade(dp); 956 if (ret < 0) 957 goto out; 958 else 959 goto retry; 960 } 961 962 printf("channel equalization succeeded\n"); 963 964 out: 965 dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE); 966 return ret; 967 } 968 969 static int dw_dp_link_enable(struct dw_dp *dp) 970 { 971 int ret; 972 973 ret = dw_dp_link_power_up(dp); 974 if (ret < 0) 975 return ret; 976 977 ret = dw_dp_link_train(dp); 978 if (ret < 0) { 979 dev_err(dp->dev, "link training failed: %d\n", ret); 980 return ret; 981 } 982 983 return 0; 984 } 985 986 static int dw_dp_set_phy_default_config(struct dw_dp *dp) 987 { 988 struct dw_dp_link *link = &dp->link; 989 union phy_configure_opts phy_cfg; 990 int ret, i, phy_rate; 991 992 link->vsc_sdp_extension_for_colorimetry_supported = false; 993 link->rate = 270000; 994 link->lanes = dp->phy.attrs.bus_width; 995 996 link->caps.enhanced_framing = true; 997 link->caps.channel_coding = true; 998 link->caps.ssc = true; 999 1000 /* Move PHY to P3 */ 1001 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 1002 FIELD_PREP(PHY_POWERDOWN, 0x3)); 1003 1004 for (i = 0; i < link->lanes; i++) { 1005 phy_cfg.dp.voltage[i] = 3; 1006 phy_cfg.dp.pre[i] = 0; 1007 } 1008 phy_cfg.dp.lanes = link->lanes; 1009 phy_cfg.dp.link_rate = link->rate / 100; 1010 phy_cfg.dp.ssc = link->caps.ssc; 1011 phy_cfg.dp.set_lanes = true; 1012 phy_cfg.dp.set_rate = true; 1013 phy_cfg.dp.set_voltages = true; 1014 ret = generic_phy_configure(&dp->phy, &phy_cfg); 1015 if (ret) 1016 return ret; 1017 1018 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, 1019 FIELD_PREP(PHY_LANES, link->lanes / 2)); 1020 1021 switch (link->rate) { 1022 case 810000: 1023 phy_rate = DPTX_PHYRATE_HBR3; 1024 break; 1025 case 540000: 1026 phy_rate = DPTX_PHYRATE_HBR2; 1027 break; 1028 case 270000: 1029 phy_rate = DPTX_PHYRATE_HBR; 1030 break; 1031 case 162000: 1032 default: 1033 phy_rate = DPTX_PHYRATE_RBR; 1034 break; 1035 } 1036 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_RATE, 1037 FIELD_PREP(PHY_RATE, phy_rate)); 1038 1039 /* Move PHY to P0 */ 1040 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 1041 FIELD_PREP(PHY_POWERDOWN, 0x0)); 1042 1043 dw_dp_phy_xmit_enable(dp, link->lanes); 1044 1045 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 1046 FIELD_PREP(ENHANCE_FRAMING_EN, 1)); 1047 1048 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE); 1049 return 0; 1050 } 1051 1052 static int dw_dp_send_sdp(struct dw_dp *dp, struct dw_dp_sdp *sdp) 1053 { 1054 const u8 *payload = sdp->db; 1055 u32 reg; 1056 int i, nr = 0; 1057 1058 reg = DPTX_SDP_REGISTER_BANK + nr * 9 * 4; 1059 1060 /* SDP header */ 1061 regmap_write(dp->regmap, reg, get_unaligned_le32(&sdp->header)); 1062 1063 /* SDP data payload */ 1064 for (i = 1; i < 9; i++, payload += 4) 1065 regmap_write(dp->regmap, reg + i * 4, 1066 FIELD_PREP(SDP_REGS, get_unaligned_le32(payload))); 1067 1068 if (sdp->flags & DPTX_SDP_VERTICAL_INTERVAL) 1069 regmap_update_bits(dp->regmap, DPTX_SDP_VERTICAL_CTRL, 1070 EN_VERTICAL_SDP << nr, 1071 EN_VERTICAL_SDP << nr); 1072 1073 if (sdp->flags & DPTX_SDP_HORIZONTAL_INTERVAL) 1074 regmap_update_bits(dp->regmap, DPTX_SDP_HORIZONTAL_CTRL, 1075 EN_HORIZONTAL_SDP << nr, 1076 EN_HORIZONTAL_SDP << nr); 1077 1078 return 0; 1079 } 1080 1081 static void dw_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, 1082 struct dw_dp_sdp *sdp) 1083 { 1084 sdp->header.HB0 = 0; 1085 sdp->header.HB1 = DP_SDP_VSC; 1086 sdp->header.HB2 = vsc->revision; 1087 sdp->header.HB3 = vsc->length; 1088 1089 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; 1090 sdp->db[16] |= vsc->colorimetry & 0xf; 1091 1092 switch (vsc->bpc) { 1093 case 8: 1094 sdp->db[17] = 0x1; 1095 break; 1096 case 10: 1097 sdp->db[17] = 0x2; 1098 break; 1099 case 12: 1100 sdp->db[17] = 0x3; 1101 break; 1102 case 16: 1103 sdp->db[17] = 0x4; 1104 break; 1105 case 6: 1106 default: 1107 break; 1108 } 1109 1110 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) 1111 sdp->db[17] |= 0x80; 1112 1113 sdp->db[18] = vsc->content_type & 0x7; 1114 1115 sdp->flags |= DPTX_SDP_VERTICAL_INTERVAL; 1116 } 1117 1118 static int dw_dp_send_vsc_sdp(struct dw_dp *dp) 1119 { 1120 struct dw_dp_video *video = &dp->video; 1121 struct drm_dp_vsc_sdp vsc = {}; 1122 struct dw_dp_sdp sdp = {}; 1123 1124 vsc.revision = 0x5; 1125 vsc.length = 0x13; 1126 1127 switch (video->color_format) { 1128 case DRM_COLOR_FORMAT_YCRCB444: 1129 vsc.pixelformat = DP_PIXELFORMAT_YUV444; 1130 break; 1131 case DRM_COLOR_FORMAT_YCRCB420: 1132 vsc.pixelformat = DP_PIXELFORMAT_YUV420; 1133 break; 1134 case DRM_COLOR_FORMAT_YCRCB422: 1135 vsc.pixelformat = DP_PIXELFORMAT_YUV422; 1136 break; 1137 case DRM_COLOR_FORMAT_RGB444: 1138 default: 1139 vsc.pixelformat = DP_PIXELFORMAT_RGB; 1140 break; 1141 } 1142 1143 if (video->color_format == DRM_COLOR_FORMAT_RGB444) 1144 vsc.colorimetry = DP_COLORIMETRY_DEFAULT; 1145 else 1146 vsc.colorimetry = DP_COLORIMETRY_BT709_YCC; 1147 1148 vsc.bpc = video->bpc; 1149 vsc.dynamic_range = DP_DYNAMIC_RANGE_CTA; 1150 vsc.content_type = DP_CONTENT_TYPE_NOT_DEFINED; 1151 1152 dw_dp_vsc_sdp_pack(&vsc, &sdp); 1153 1154 return dw_dp_send_sdp(dp, &sdp); 1155 } 1156 1157 static int dw_dp_video_set_pixel_mode(struct dw_dp *dp, u8 pixel_mode) 1158 { 1159 switch (pixel_mode) { 1160 case DPTX_MP_SINGLE_PIXEL: 1161 case DPTX_MP_DUAL_PIXEL: 1162 case DPTX_MP_QUAD_PIXEL: 1163 break; 1164 default: 1165 return -EINVAL; 1166 } 1167 1168 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, PIXEL_MODE_SELECT, 1169 FIELD_PREP(PIXEL_MODE_SELECT, pixel_mode)); 1170 1171 return 0; 1172 } 1173 1174 static int dw_dp_video_set_msa(struct dw_dp *dp, u8 color_format, u8 bpc, 1175 u16 vstart, u16 hstart) 1176 { 1177 struct dw_dp_link *link = &dp->link; 1178 u16 misc = 0; 1179 1180 if (link->vsc_sdp_extension_for_colorimetry_supported) 1181 misc |= DP_MSA_MISC_COLOR_VSC_SDP; 1182 1183 switch (color_format) { 1184 case DRM_COLOR_FORMAT_RGB444: 1185 misc |= DP_MSA_MISC_COLOR_RGB; 1186 break; 1187 case DRM_COLOR_FORMAT_YCRCB444: 1188 misc |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 1189 break; 1190 case DRM_COLOR_FORMAT_YCRCB422: 1191 misc |= DP_MSA_MISC_COLOR_YCBCR_422_BT709; 1192 break; 1193 case DRM_COLOR_FORMAT_YCRCB420: 1194 break; 1195 default: 1196 return -EINVAL; 1197 } 1198 1199 switch (bpc) { 1200 case 6: 1201 misc |= DP_MSA_MISC_6_BPC; 1202 break; 1203 case 8: 1204 misc |= DP_MSA_MISC_8_BPC; 1205 break; 1206 case 10: 1207 misc |= DP_MSA_MISC_10_BPC; 1208 break; 1209 case 12: 1210 misc |= DP_MSA_MISC_12_BPC; 1211 break; 1212 case 16: 1213 misc |= DP_MSA_MISC_16_BPC; 1214 break; 1215 default: 1216 return -EINVAL; 1217 } 1218 1219 regmap_write(dp->regmap, DPTX_VIDEO_MSA1, 1220 FIELD_PREP(VSTART, vstart) | FIELD_PREP(HSTART, hstart)); 1221 regmap_write(dp->regmap, DPTX_VIDEO_MSA2, FIELD_PREP(MISC0, misc)); 1222 regmap_write(dp->regmap, DPTX_VIDEO_MSA3, FIELD_PREP(MISC1, misc >> 8)); 1223 1224 return 0; 1225 } 1226 1227 static int dw_dp_video_enable(struct dw_dp *dp) 1228 { 1229 struct dw_dp_video *video = &dp->video; 1230 struct dw_dp_link *link = &dp->link; 1231 struct drm_display_mode *mode = &video->mode; 1232 u8 color_format = video->color_format; 1233 u8 bpc = video->bpc; 1234 u8 pixel_mode = video->pixel_mode; 1235 u8 bpp = video->bpp, init_threshold, vic; 1236 u32 hactive, hblank, h_sync_width, h_front_porch; 1237 u32 vactive, vblank, v_sync_width, v_front_porch; 1238 u32 vstart = mode->vtotal - mode->vsync_start; 1239 u32 hstart = mode->htotal - mode->hsync_start; 1240 u32 peak_stream_bandwidth, link_bandwidth; 1241 u32 average_bytes_per_tu, average_bytes_per_tu_frac; 1242 u32 ts, hblank_interval; 1243 u32 value; 1244 int ret; 1245 1246 ret = dw_dp_video_set_pixel_mode(dp, pixel_mode); 1247 if (ret) 1248 return ret; 1249 1250 ret = dw_dp_video_set_msa(dp, color_format, bpc, vstart, hstart); 1251 if (ret) 1252 return ret; 1253 1254 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_MAPPING, 1255 FIELD_PREP(VIDEO_MAPPING, video->video_mapping)); 1256 1257 /* Configure DPTX_VINPUT_POLARITY_CTRL register */ 1258 value = 0; 1259 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1260 value |= FIELD_PREP(HSYNC_IN_POLARITY, 1); 1261 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1262 value |= FIELD_PREP(VSYNC_IN_POLARITY, 1); 1263 regmap_write(dp->regmap, DPTX_VINPUT_POLARITY_CTRL, value); 1264 1265 /* Configure DPTX_VIDEO_CONFIG1 register */ 1266 hactive = mode->hdisplay; 1267 hblank = mode->htotal - mode->hdisplay; 1268 value = FIELD_PREP(HACTIVE, hactive) | FIELD_PREP(HBLANK, hblank); 1269 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1270 value |= FIELD_PREP(I_P, 1); 1271 vic = drm_match_cea_mode(mode); 1272 if (vic == 5 || vic == 6 || vic == 7 || 1273 vic == 10 || vic == 11 || vic == 20 || 1274 vic == 21 || vic == 22 || vic == 39 || 1275 vic == 25 || vic == 26 || vic == 40 || 1276 vic == 44 || vic == 45 || vic == 46 || 1277 vic == 50 || vic == 51 || vic == 54 || 1278 vic == 55 || vic == 58 || vic == 59) 1279 value |= R_V_BLANK_IN_OSC; 1280 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG1, value); 1281 1282 /* Configure DPTX_VIDEO_CONFIG2 register */ 1283 vblank = mode->vtotal - mode->vdisplay; 1284 vactive = mode->vdisplay; 1285 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG2, 1286 FIELD_PREP(VBLANK, vblank) | FIELD_PREP(VACTIVE, vactive)); 1287 1288 /* Configure DPTX_VIDEO_CONFIG3 register */ 1289 h_sync_width = mode->hsync_end - mode->hsync_start; 1290 h_front_porch = mode->hsync_start - mode->hdisplay; 1291 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG3, 1292 FIELD_PREP(H_SYNC_WIDTH, h_sync_width) | 1293 FIELD_PREP(H_FRONT_PORCH, h_front_porch)); 1294 1295 /* Configure DPTX_VIDEO_CONFIG4 register */ 1296 v_sync_width = mode->vsync_end - mode->vsync_start; 1297 v_front_porch = mode->vsync_start - mode->vdisplay; 1298 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG4, 1299 FIELD_PREP(V_SYNC_WIDTH, v_sync_width) | 1300 FIELD_PREP(V_FRONT_PORCH, v_front_porch)); 1301 1302 /* Configure DPTX_VIDEO_CONFIG5 register */ 1303 peak_stream_bandwidth = mode->clock * bpp / 8; 1304 link_bandwidth = (link->rate / 1000) * link->lanes; 1305 ts = peak_stream_bandwidth * 64 / link_bandwidth; 1306 average_bytes_per_tu = ts / 1000; 1307 average_bytes_per_tu_frac = ts / 100 - average_bytes_per_tu * 10; 1308 if (pixel_mode == DPTX_MP_SINGLE_PIXEL) { 1309 if (average_bytes_per_tu < 6) 1310 init_threshold = 32; 1311 else if (hblank <= 80 && 1312 color_format != DRM_COLOR_FORMAT_YCRCB420) 1313 init_threshold = 12; 1314 else if (hblank <= 40 && 1315 color_format == DRM_COLOR_FORMAT_YCRCB420) 1316 init_threshold = 3; 1317 else 1318 init_threshold = 16; 1319 } else { 1320 u32 t1 = 0, t2 = 0, t3 = 0; 1321 1322 switch (bpc) { 1323 case 6: 1324 t1 = (4 * 1000 / 9) * link->lanes; 1325 break; 1326 case 8: 1327 if (color_format == DRM_COLOR_FORMAT_YCRCB422) { 1328 t1 = (1000 / 2) * link->lanes; 1329 } else { 1330 if (pixel_mode == DPTX_MP_DUAL_PIXEL) 1331 t1 = (1000 / 3) * link->lanes; 1332 else 1333 t1 = (3000 / 16) * link->lanes; 1334 } 1335 break; 1336 case 10: 1337 if (color_format == DRM_COLOR_FORMAT_YCRCB422) 1338 t1 = (2000 / 5) * link->lanes; 1339 else 1340 t1 = (4000 / 15) * link->lanes; 1341 break; 1342 case 12: 1343 if (color_format == DRM_COLOR_FORMAT_YCRCB422) { 1344 if (pixel_mode == DPTX_MP_DUAL_PIXEL) 1345 t1 = (1000 / 6) * link->lanes; 1346 else 1347 t1 = (1000 / 3) * link->lanes; 1348 } else { 1349 t1 = (2000 / 9) * link->lanes; 1350 } 1351 break; 1352 case 16: 1353 if (color_format != DRM_COLOR_FORMAT_YCRCB422 && 1354 pixel_mode == DPTX_MP_DUAL_PIXEL) 1355 t1 = (1000 / 6) * link->lanes; 1356 else 1357 t1 = (1000 / 4) * link->lanes; 1358 break; 1359 default: 1360 return -EINVAL; 1361 } 1362 1363 if (color_format == DRM_COLOR_FORMAT_YCRCB420) 1364 t2 = (link->rate / 4) * 1000 / (mode->clock / 2); 1365 else 1366 t2 = (link->rate / 4) * 1000 / mode->clock; 1367 1368 if (average_bytes_per_tu_frac) 1369 t3 = average_bytes_per_tu + 1; 1370 else 1371 t3 = average_bytes_per_tu; 1372 init_threshold = t1 * t2 * t3 / (1000 * 1000); 1373 if (init_threshold <= 16 || average_bytes_per_tu < 10) 1374 init_threshold = 40; 1375 } 1376 1377 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG5, 1378 FIELD_PREP(INIT_THRESHOLD_HI, init_threshold >> 6) | 1379 FIELD_PREP(AVERAGE_BYTES_PER_TU_FRAC, 1380 average_bytes_per_tu_frac) | 1381 FIELD_PREP(INIT_THRESHOLD, init_threshold) | 1382 FIELD_PREP(AVERAGE_BYTES_PER_TU, average_bytes_per_tu)); 1383 1384 /* Configure DPTX_VIDEO_HBLANK_INTERVAL register */ 1385 hblank_interval = hblank * (link->rate / 4) / mode->clock; 1386 regmap_write(dp->regmap, DPTX_VIDEO_HBLANK_INTERVAL, 1387 FIELD_PREP(HBLANK_INTERVAL_EN, 1) | 1388 FIELD_PREP(HBLANK_INTERVAL, hblank_interval)); 1389 1390 /* Video stream enable */ 1391 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_STREAM_ENABLE, 1392 FIELD_PREP(VIDEO_STREAM_ENABLE, 1)); 1393 1394 if (link->vsc_sdp_extension_for_colorimetry_supported) 1395 dw_dp_send_vsc_sdp(dp); 1396 1397 return 0; 1398 } 1399 1400 static bool dw_dp_detect(struct dw_dp *dp) 1401 { 1402 u32 value; 1403 1404 if (dm_gpio_is_valid(&dp->hpd_gpio)) 1405 return dm_gpio_get_value(&dp->hpd_gpio); 1406 1407 regmap_read(dp->regmap, DPTX_HPD_STATUS, &value); 1408 if (FIELD_GET(HPD_STATE, value) == SOURCE_STATE_PLUG) { 1409 regmap_write(dp->regmap, DPTX_HPD_STATUS, HPD_HOT_PLUG); 1410 return true; 1411 } 1412 1413 return false; 1414 } 1415 1416 static struct dw_dp *connector_to_dw_dp(struct rockchip_connector *conn) 1417 { 1418 struct dw_dp *dp; 1419 1420 if (dev_get_priv(conn->dev)) 1421 dp = dev_get_priv(conn->dev); 1422 else 1423 dp = dev_get_priv(conn->dev->parent); 1424 1425 return dp; 1426 } 1427 1428 static int dw_dp_connector_init(struct rockchip_connector *conn, struct display_state *state) 1429 { 1430 struct connector_state *conn_state = &state->conn_state; 1431 struct dw_dp *dp = connector_to_dw_dp(conn); 1432 int ret; 1433 1434 if (dev_get_priv(conn->dev)) 1435 dp = dev_get_priv(conn->dev); 1436 else 1437 dp = dev_get_priv(conn->dev->parent); 1438 conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_DP1 : VOP_OUTPUT_IF_DP0; 1439 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1440 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709; 1441 1442 clk_set_defaults(dp->dev); 1443 1444 reset_assert(&dp->reset); 1445 udelay(20); 1446 reset_deassert(&dp->reset); 1447 1448 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, 1449 dp->id); 1450 dw_dp_init(dp); 1451 ret = generic_phy_power_on(&dp->phy); 1452 1453 return ret; 1454 } 1455 1456 static int dw_dp_connector_get_edid(struct rockchip_connector *conn, struct display_state *state) 1457 { 1458 int ret; 1459 struct connector_state *conn_state = &state->conn_state; 1460 struct dw_dp *dp = connector_to_dw_dp(conn); 1461 1462 ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); 1463 1464 return ret; 1465 } 1466 1467 static int dw_dp_get_output_fmts_index(u32 bus_format) 1468 { 1469 int i; 1470 1471 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 1472 const struct dw_dp_output_format *fmt = &possible_output_fmts[i]; 1473 1474 if (fmt->bus_format == bus_format) 1475 break; 1476 } 1477 1478 if (i == ARRAY_SIZE(possible_output_fmts)) 1479 return 1; 1480 1481 return i; 1482 } 1483 1484 static int dw_dp_connector_prepare(struct rockchip_connector *conn, struct display_state *state) 1485 { 1486 struct connector_state *conn_state = &state->conn_state; 1487 struct dw_dp *dp = connector_to_dw_dp(conn); 1488 struct dw_dp_video *video = &dp->video; 1489 int bus_fmt; 1490 1491 bus_fmt = dw_dp_get_output_fmts_index(conn_state->bus_format); 1492 video->video_mapping = possible_output_fmts[bus_fmt].video_mapping; 1493 video->color_format = possible_output_fmts[bus_fmt].color_format; 1494 video->bus_format = possible_output_fmts[bus_fmt].bus_format; 1495 video->bpc = possible_output_fmts[bus_fmt].bpc; 1496 video->bpp = possible_output_fmts[bus_fmt].bpp; 1497 1498 return 0; 1499 } 1500 1501 static int dw_dp_connector_enable(struct rockchip_connector *conn, struct display_state *state) 1502 { 1503 struct connector_state *conn_state = &state->conn_state; 1504 struct drm_display_mode *mode = &conn_state->mode; 1505 struct dw_dp *dp = connector_to_dw_dp(conn); 1506 struct dw_dp_video *video = &dp->video; 1507 int ret; 1508 1509 memcpy(&video->mode, mode, sizeof(video->mode)); 1510 1511 if (dp->force_output) { 1512 ret = dw_dp_set_phy_default_config(dp); 1513 if (ret < 0) 1514 printf("failed to set phy_default config: %d\n", ret); 1515 } else { 1516 ret = dw_dp_link_enable(dp); 1517 if (ret < 0) { 1518 printf("failed to enable link: %d\n", ret); 1519 return ret; 1520 } 1521 } 1522 1523 ret = dw_dp_video_enable(dp); 1524 if (ret < 0) { 1525 printf("failed to enable video: %d\n", ret); 1526 return ret; 1527 } 1528 1529 return 0; 1530 } 1531 1532 static int dw_dp_connector_disable(struct rockchip_connector *conn, struct display_state *state) 1533 { 1534 /* TODO */ 1535 1536 return 0; 1537 } 1538 1539 static int dw_dp_connector_detect(struct rockchip_connector *conn, struct display_state *state) 1540 { 1541 struct dw_dp *dp = connector_to_dw_dp(conn); 1542 int status, tries, ret; 1543 1544 for (tries = 0; tries < 200; tries++) { 1545 status = dw_dp_detect(dp); 1546 if (status) 1547 break; 1548 mdelay(2); 1549 } 1550 1551 if (state->force_output && !status) 1552 dp->force_output = true; 1553 1554 if (!status && !dp->force_output) 1555 generic_phy_power_off(&dp->phy); 1556 1557 if (status && !dp->force_output) { 1558 ret = dw_dp_link_probe(dp); 1559 if (ret) 1560 printf("failed to probe DP link: %d\n", ret); 1561 } 1562 1563 return status; 1564 } 1565 1566 static int dw_dp_mode_valid(struct dw_dp *dp, struct hdmi_edid_data *edid_data) 1567 { 1568 struct dw_dp_link *link = &dp->link; 1569 struct drm_display_info *di = &edid_data->display_info; 1570 u32 min_bpp; 1571 int i; 1572 1573 if (di->color_formats & DRM_COLOR_FORMAT_YCRCB420 && 1574 link->vsc_sdp_extension_for_colorimetry_supported) 1575 min_bpp = 12; 1576 else if (di->color_formats & DRM_COLOR_FORMAT_YCRCB422) 1577 min_bpp = 16; 1578 else if (di->color_formats & DRM_COLOR_FORMAT_RGB444) 1579 min_bpp = 18; 1580 else 1581 min_bpp = 24; 1582 1583 for (i = 0; i < edid_data->modes; i++) { 1584 if (!dw_dp_bandwidth_ok(dp, &edid_data->mode_buf[i], min_bpp, link->lanes, 1585 link->rate)) 1586 edid_data->mode_buf[i].invalid = true; 1587 } 1588 1589 return 0; 1590 } 1591 1592 static u32 dw_dp_get_output_bus_fmts(struct dw_dp *dp, struct hdmi_edid_data *edid_data) 1593 { 1594 struct dw_dp_link *link = &dp->link; 1595 unsigned int i; 1596 1597 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 1598 const struct dw_dp_output_format *fmt = &possible_output_fmts[i]; 1599 1600 if (fmt->bpc > edid_data->display_info.bpc) 1601 continue; 1602 1603 if (!(edid_data->display_info.color_formats & fmt->color_format)) 1604 continue; 1605 1606 if (fmt->color_format == DRM_COLOR_FORMAT_YCRCB420 && 1607 !link->vsc_sdp_extension_for_colorimetry_supported) 1608 continue; 1609 1610 if (drm_mode_is_420(&edid_data->display_info, edid_data->preferred_mode) && 1611 fmt->color_format != DRM_COLOR_FORMAT_YCRCB420) 1612 continue; 1613 1614 if (!dw_dp_bandwidth_ok(dp, edid_data->preferred_mode, fmt->bpp, link->lanes, 1615 link->rate)) 1616 continue; 1617 1618 break; 1619 } 1620 1621 if (i == ARRAY_SIZE(possible_output_fmts)) 1622 return 1; 1623 1624 return i; 1625 } 1626 1627 static int dw_dp_connector_get_timing(struct rockchip_connector *conn, struct display_state *state) 1628 { 1629 int ret, i; 1630 struct connector_state *conn_state = &state->conn_state; 1631 struct dw_dp *dp = connector_to_dw_dp(conn); 1632 struct drm_display_mode *mode = &conn_state->mode; 1633 struct hdmi_edid_data edid_data; 1634 struct drm_display_mode *mode_buf; 1635 struct vop_rect rect; 1636 u32 bus_fmt; 1637 1638 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 1639 if (!mode_buf) 1640 return -ENOMEM; 1641 1642 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 1643 memset(&edid_data, 0, sizeof(struct hdmi_edid_data)); 1644 edid_data.mode_buf = mode_buf; 1645 1646 if (!dp->force_output) { 1647 ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); 1648 if (!ret) 1649 ret = drm_add_edid_modes(&edid_data, conn_state->edid); 1650 1651 if (ret < 0) { 1652 printf("failed to get edid\n"); 1653 goto err; 1654 } 1655 1656 //drm_rk_filter_whitelist(&edid_data); 1657 if (state->conn_state.secondary) { 1658 rect.width = state->crtc_state.max_output.width / 2; 1659 rect.height = state->crtc_state.max_output.height / 2; 1660 } else { 1661 rect.width = state->crtc_state.max_output.width; 1662 rect.height = state->crtc_state.max_output.height; 1663 } 1664 1665 drm_mode_max_resolution_filter(&edid_data, &rect); 1666 dw_dp_mode_valid(dp, &edid_data); 1667 1668 if (!drm_mode_prune_invalid(&edid_data)) { 1669 printf("can't find valid dp mode\n"); 1670 ret = -EINVAL; 1671 goto err; 1672 } 1673 1674 for (i = 0; i < edid_data.modes; i++) 1675 edid_data.mode_buf[i].vrefresh = 1676 drm_mode_vrefresh(&edid_data.mode_buf[i]); 1677 1678 drm_mode_sort(&edid_data); 1679 memcpy(mode, edid_data.preferred_mode, sizeof(struct drm_display_mode)); 1680 } 1681 1682 if (state->force_output) 1683 bus_fmt = dw_dp_get_output_fmts_index(state->force_bus_format); 1684 else 1685 bus_fmt = dw_dp_get_output_bus_fmts(dp, &edid_data); 1686 1687 conn_state->bus_format = possible_output_fmts[bus_fmt].bus_format; 1688 1689 switch (possible_output_fmts[bus_fmt].color_format) { 1690 case DRM_COLOR_FORMAT_YCRCB420: 1691 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420; 1692 break; 1693 case DRM_COLOR_FORMAT_YCRCB422: 1694 conn_state->output_mode = ROCKCHIP_OUT_MODE_S888_DUMMY; 1695 break; 1696 case DRM_COLOR_FORMAT_RGB444: 1697 case DRM_COLOR_FORMAT_YCRCB444: 1698 default: 1699 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1700 break; 1701 } 1702 1703 err: 1704 free(mode_buf); 1705 1706 return 0; 1707 } 1708 1709 static const struct rockchip_connector_funcs dw_dp_connector_funcs = { 1710 .init = dw_dp_connector_init, 1711 .get_edid = dw_dp_connector_get_edid, 1712 .prepare = dw_dp_connector_prepare, 1713 .enable = dw_dp_connector_enable, 1714 .disable = dw_dp_connector_disable, 1715 .detect = dw_dp_connector_detect, 1716 .get_timing = dw_dp_connector_get_timing, 1717 }; 1718 1719 static int dw_dp_ddc_init(struct dw_dp *dp) 1720 { 1721 dp->aux.name = "dw-dp"; 1722 dp->aux.dev = dp->dev; 1723 dp->aux.transfer = dw_dp_aux_transfer; 1724 dp->aux.ddc.ddc_xfer = drm_dp_i2c_xfer; 1725 1726 return 0; 1727 } 1728 1729 static u32 dw_dp_parse_link_frequencies(struct dw_dp *dp) 1730 { 1731 struct udevice *dev = dp->dev; 1732 const struct device_node *endpoint; 1733 u64 frequency = 0; 1734 1735 endpoint = rockchip_of_graph_get_endpoint_by_regs(dev->node, 1, 0); 1736 if (!endpoint) 1737 return 0; 1738 1739 if (of_property_read_u64(endpoint, "link-frequencies", &frequency) < 0) 1740 return 0; 1741 1742 if (!frequency) 1743 return 0; 1744 1745 do_div(frequency, 10 * 1000); /* symbol rate kbytes */ 1746 1747 switch (frequency) { 1748 case 162000: 1749 case 270000: 1750 case 540000: 1751 case 810000: 1752 break; 1753 default: 1754 dev_err(dev, "invalid link frequency value: %llu\n", frequency); 1755 return 0; 1756 } 1757 1758 return frequency; 1759 } 1760 1761 static int dw_dp_parse_dt(struct dw_dp *dp) 1762 { 1763 dp->force_hpd = dev_read_bool(dp->dev, "force-hpd"); 1764 1765 dp->max_link_rate = dw_dp_parse_link_frequencies(dp); 1766 if (!dp->max_link_rate) 1767 dp->max_link_rate = 810000; 1768 1769 return 0; 1770 } 1771 1772 static int dw_dp_probe(struct udevice *dev) 1773 { 1774 struct dw_dp *dp = dev_get_priv(dev); 1775 const struct dw_dp_chip_data *pdata = 1776 (const struct dw_dp_chip_data *)dev_get_driver_data(dev); 1777 int ret; 1778 1779 ret = regmap_init_mem(dev, &dp->regmap); 1780 if (ret) 1781 return ret; 1782 1783 dp->id = of_alias_get_id(ofnode_to_np(dev->node), "dp"); 1784 if (dp->id < 0) 1785 dp->id = 0; 1786 1787 dp->video.pixel_mode = pdata->pixel_mode; 1788 1789 ret = reset_get_by_index(dev, 0, &dp->reset); 1790 if (ret) { 1791 dev_err(dev, "failed to get reset control: %d\n", ret); 1792 return ret; 1793 } 1794 1795 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 1796 GPIOD_IS_IN); 1797 if (ret && ret != -ENOENT) { 1798 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 1799 return ret; 1800 } 1801 1802 generic_phy_get_by_index(dev, 0, &dp->phy); 1803 1804 dp->dev = dev; 1805 1806 ret = dw_dp_parse_dt(dp); 1807 if (ret) { 1808 dev_err(dev, "failed to parse DT\n"); 1809 return ret; 1810 } 1811 1812 dw_dp_ddc_init(dp); 1813 1814 rockchip_connector_bind(&dp->connector, dev, dp->id, &dw_dp_connector_funcs, NULL, 1815 DRM_MODE_CONNECTOR_DisplayPort); 1816 1817 return 0; 1818 } 1819 1820 static int dw_dp_bind(struct udevice *parent) 1821 { 1822 struct udevice *child; 1823 ofnode subnode; 1824 const char *node_name; 1825 int ret; 1826 1827 dev_for_each_subnode(subnode, parent) { 1828 if (!ofnode_valid(subnode)) { 1829 printf("%s: no subnode for %s\n", __func__, parent->name); 1830 return -ENXIO; 1831 } 1832 1833 node_name = ofnode_get_name(subnode); 1834 debug("%s: subnode %s\n", __func__, node_name); 1835 1836 if (!strcasecmp(node_name, "dp0")) { 1837 printf("%s zyb enter\n", __func__); 1838 ret = device_bind_driver_to_node(parent, 1839 "dw_dp_port0", 1840 node_name, subnode, &child); 1841 if (ret) { 1842 printf("%s: '%s' cannot bind its driver\n", 1843 __func__, node_name); 1844 return ret; 1845 } 1846 } 1847 } 1848 1849 return 0; 1850 } 1851 1852 static int dw_dp_port_probe(struct udevice *dev) 1853 { 1854 struct dw_dp *dp = dev_get_priv(dev->parent); 1855 1856 rockchip_connector_bind(&dp->connector, dev, dp->id, &dw_dp_connector_funcs, NULL, 1857 DRM_MODE_CONNECTOR_DisplayPort); 1858 1859 return 0; 1860 } 1861 1862 static const struct dw_dp_chip_data rk3588_dp = { 1863 .pixel_mode = DPTX_MP_QUAD_PIXEL, 1864 }; 1865 1866 static const struct dw_dp_chip_data rk3576_dp = { 1867 .pixel_mode = DPTX_MP_DUAL_PIXEL, 1868 }; 1869 1870 static const struct udevice_id dw_dp_ids[] = { 1871 { 1872 .compatible = "rockchip,rk3576-dp", 1873 .data = (ulong)&rk3576_dp, 1874 }, 1875 { 1876 .compatible = "rockchip,rk3588-dp", 1877 .data = (ulong)&rk3588_dp, 1878 }, 1879 {} 1880 }; 1881 1882 U_BOOT_DRIVER(dw_dp_port) = { 1883 .name = "dw_dp_port0", 1884 .id = UCLASS_DISPLAY, 1885 .probe = dw_dp_port_probe, 1886 }; 1887 1888 U_BOOT_DRIVER(dw_dp) = { 1889 .name = "dw_dp", 1890 .id = UCLASS_DISPLAY, 1891 .of_match = dw_dp_ids, 1892 .probe = dw_dp_probe, 1893 .bind = dw_dp_bind, 1894 .priv_auto_alloc_size = sizeof(struct dw_dp), 1895 }; 1896 1897