1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Rockchip USBDP Combo PHY with Samsung IP block driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd 6 */ 7 8 #include <config.h> 9 #include <common.h> 10 #include <errno.h> 11 #include <malloc.h> 12 #include <asm/unaligned.h> 13 #include <asm/io.h> 14 #include <clk.h> 15 #include <dm/device.h> 16 #include <dm/of_access.h> 17 #include <dm/read.h> 18 #include <generic-phy.h> 19 #include <linux/bitfield.h> 20 #include <linux/hdmi.h> 21 #include <linux/media-bus-format.h> 22 #include <linux/list.h> 23 #include <asm/gpio.h> 24 #include <generic-phy.h> 25 #include <regmap.h> 26 #include <reset.h> 27 #include <drm/drm_dp_helper.h> 28 29 #include "rockchip_display.h" 30 #include "rockchip_crtc.h" 31 #include "rockchip_connector.h" 32 33 #define DPTX_VERSION_NUMBER 0x0000 34 #define DPTX_VERSION_TYPE 0x0004 35 #define DPTX_ID 0x0008 36 37 #define DPTX_CONFIG_REG1 0x0100 38 #define DPTX_CONFIG_REG2 0x0104 39 #define DPTX_CONFIG_REG3 0x0108 40 41 #define DPTX_CCTL 0x0200 42 #define FORCE_HPD BIT(4) 43 #define DEFAULT_FAST_LINK_TRAIN_EN BIT(2) 44 #define ENHANCE_FRAMING_EN BIT(1) 45 #define SCRAMBLE_DIS BIT(0) 46 #define DPTX_SOFT_RESET_CTRL 0x0204 47 #define VIDEO_RESET BIT(5) 48 #define AUX_RESET BIT(4) 49 #define AUDIO_SAMPLER_RESET BIT(3) 50 #define PHY_SOFT_RESET BIT(1) 51 #define CONTROLLER_RESET BIT(0) 52 53 #define DPTX_VSAMPLE_CTRL 0x0300 54 #define PIXEL_MODE_SELECT GENMASK(22, 21) 55 #define VIDEO_MAPPING GENMASK(20, 16) 56 #define VIDEO_STREAM_ENABLE BIT(5) 57 #define DPTX_VSAMPLE_STUFF_CTRL1 0x0304 58 #define DPTX_VSAMPLE_STUFF_CTRL2 0x0308 59 #define DPTX_VINPUT_POLARITY_CTRL 0x030c 60 #define DE_IN_POLARITY BIT(2) 61 #define HSYNC_IN_POLARITY BIT(1) 62 #define VSYNC_IN_POLARITY BIT(0) 63 #define DPTX_VIDEO_CONFIG1 0x0310 64 #define HACTIVE GENMASK(31, 16) 65 #define HBLANK GENMASK(15, 2) 66 #define I_P BIT(1) 67 #define R_V_BLANK_IN_OSC BIT(0) 68 #define DPTX_VIDEO_CONFIG2 0x0314 69 #define VBLANK GENMASK(31, 16) 70 #define VACTIVE GENMASK(15, 0) 71 #define DPTX_VIDEO_CONFIG3 0x0318 72 #define H_SYNC_WIDTH GENMASK(31, 16) 73 #define H_FRONT_PORCH GENMASK(15, 0) 74 #define DPTX_VIDEO_CONFIG4 0x031c 75 #define V_SYNC_WIDTH GENMASK(31, 16) 76 #define V_FRONT_PORCH GENMASK(15, 0) 77 #define DPTX_VIDEO_CONFIG5 0x0320 78 #define INIT_THRESHOLD_HI GENMASK(22, 21) 79 #define AVERAGE_BYTES_PER_TU_FRAC GENMASK(19, 16) 80 #define INIT_THRESHOLD GENMASK(13, 7) 81 #define AVERAGE_BYTES_PER_TU GENMASK(6, 0) 82 #define DPTX_VIDEO_MSA1 0x0324 83 #define VSTART GENMASK(31, 16) 84 #define HSTART GENMASK(15, 0) 85 #define DPTX_VIDEO_MSA2 0x0328 86 #define MISC0 GENMASK(31, 24) 87 #define DPTX_VIDEO_MSA3 0x032c 88 #define MISC1 GENMASK(31, 24) 89 #define DPTX_VIDEO_HBLANK_INTERVAL 0x0330 90 #define HBLANK_INTERVAL_EN BIT(16) 91 #define HBLANK_INTERVAL GENMASK(15, 0) 92 93 #define DPTX_AUD_CONFIG1 0x0400 94 #define AUDIO_TIMESTAMP_VERSION_NUM GENMASK(29, 24) 95 #define AUDIO_PACKET_ID GENMASK(23, 16) 96 #define AUDIO_MUTE BIT(15) 97 #define NUM_CHANNELS GENMASK(14, 12) 98 #define HBR_MODE_ENABLE BIT(10) 99 #define AUDIO_DATA_WIDTH GENMASK(9, 5) 100 #define AUDIO_DATA_IN_EN GENMASK(4, 1) 101 #define AUDIO_INF_SELECT BIT(0) 102 103 #define DPTX_SDP_VERTICAL_CTRL 0x0500 104 #define EN_VERTICAL_SDP BIT(2) 105 #define EN_AUDIO_STREAM_SDP BIT(1) 106 #define EN_AUDIO_TIMESTAMP_SDP BIT(0) 107 #define DPTX_SDP_HORIZONTAL_CTRL 0x0504 108 #define EN_HORIZONTAL_SDP BIT(2) 109 #define DPTX_SDP_STATUS_REGISTER 0x0508 110 #define DPTX_SDP_MANUAL_CTRL 0x050c 111 #define DPTX_SDP_STATUS_EN 0x0510 112 113 #define DPTX_SDP_REGISTER_BANK 0x0600 114 #define SDP_REGS GENMASK(31, 0) 115 116 #define DPTX_PHYIF_CTRL 0x0a00 117 #define PHY_WIDTH BIT(25) 118 #define PHY_POWERDOWN GENMASK(20, 17) 119 #define PHY_BUSY GENMASK(15, 12) 120 #define SSC_DIS BIT(16) 121 #define XMIT_ENABLE GENMASK(11, 8) 122 #define PHY_LANES GENMASK(7, 6) 123 #define PHY_RATE GENMASK(5, 4) 124 #define TPS_SEL GENMASK(3, 0) 125 #define DPTX_PHY_TX_EQ 0x0a04 126 #define DPTX_CUSTOMPAT0 0x0a08 127 #define DPTX_CUSTOMPAT1 0x0a0c 128 #define DPTX_CUSTOMPAT2 0x0a10 129 #define DPTX_HBR2_COMPLIANCE_SCRAMBLER_RESET 0x0a14 130 #define DPTX_PHYIF_PWRDOWN_CTRL 0x0a18 131 132 #define DPTX_AUX_CMD 0x0b00 133 #define AUX_CMD_TYPE GENMASK(31, 28) 134 #define AUX_ADDR GENMASK(27, 8) 135 #define I2C_ADDR_ONLY BIT(4) 136 #define AUX_LEN_REQ GENMASK(3, 0) 137 #define DPTX_AUX_STATUS 0x0b04 138 #define AUX_TIMEOUT BIT(17) 139 #define AUX_BYTES_READ GENMASK(23, 19) 140 #define AUX_STATUS GENMASK(7, 4) 141 #define DPTX_AUX_DATA0 0x0b08 142 #define DPTX_AUX_DATA1 0x0b0c 143 #define DPTX_AUX_DATA2 0x0b10 144 #define DPTX_AUX_DATA3 0x0b14 145 146 #define DPTX_GENERAL_INTERRUPT 0x0d00 147 #define VIDEO_FIFO_OVERFLOW_STREAM0 BIT(6) 148 #define AUDIO_FIFO_OVERFLOW_STREAM0 BIT(5) 149 #define SDP_EVENT_STREAM0 BIT(4) 150 #define AUX_CMD_INVALID BIT(3) 151 #define AUX_REPLY_EVENT BIT(1) 152 #define HPD_EVENT BIT(0) 153 #define DPTX_GENERAL_INTERRUPT_ENABLE 0x0d04 154 #define AUX_REPLY_EVENT_EN BIT(1) 155 #define HPD_EVENT_EN BIT(0) 156 #define DPTX_HPD_STATUS 0x0d08 157 #define HPD_STATE GENMASK(11, 9) 158 #define HPD_STATUS BIT(8) 159 #define HPD_HOT_UNPLUG BIT(2) 160 #define HPD_HOT_PLUG BIT(1) 161 #define HPD_IRQ BIT(0) 162 #define DPTX_HPD_INTERRUPT_ENABLE 0x0d0c 163 #define HPD_UNPLUG_ERR_EN BIT(3) 164 #define HPD_UNPLUG_EN BIT(2) 165 #define HPD_PLUG_EN BIT(1) 166 #define HPD_IRQ_EN BIT(0) 167 168 #define DPTX_MAX_REGISTER DPTX_HPD_INTERRUPT_ENABLE 169 170 #define SDP_REG_BANK_SIZE 16 171 172 struct drm_dp_link_caps { 173 bool enhanced_framing; 174 bool tps3_supported; 175 bool tps4_supported; 176 bool channel_coding; 177 bool ssc; 178 }; 179 180 struct drm_dp_link_train_set { 181 unsigned int voltage_swing[4]; 182 unsigned int pre_emphasis[4]; 183 }; 184 185 struct drm_dp_link_train { 186 struct drm_dp_link_train_set request; 187 struct drm_dp_link_train_set adjust; 188 bool clock_recovered; 189 bool channel_equalized; 190 }; 191 192 struct dw_dp_link { 193 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 194 unsigned char revision; 195 unsigned int rate; 196 unsigned int lanes; 197 struct drm_dp_link_caps caps; 198 struct drm_dp_link_train train; 199 u8 sink_count; 200 u8 vsc_sdp_extension_for_colorimetry_supported; 201 }; 202 203 struct dw_dp_video { 204 struct drm_display_mode mode; 205 u32 bus_format; 206 u8 video_mapping; 207 u8 pixel_mode; 208 u8 color_format; 209 u8 bpc; 210 u8 bpp; 211 }; 212 213 struct dw_dp_sdp { 214 struct dp_sdp_header header; 215 u8 db[32]; 216 unsigned long flags; 217 }; 218 219 struct dw_dp { 220 struct udevice *dev; 221 struct regmap *regmap; 222 struct phy phy; 223 struct reset_ctl reset; 224 int id; 225 226 struct gpio_desc hpd_gpio; 227 struct drm_dp_aux aux; 228 struct dw_dp_link link; 229 struct dw_dp_video video; 230 231 bool force_hpd; 232 bool force_output; 233 }; 234 235 enum { 236 SOURCE_STATE_IDLE, 237 SOURCE_STATE_UNPLUG, 238 SOURCE_STATE_HPD_TIMEOUT = 4, 239 SOURCE_STATE_PLUG = 7 240 }; 241 242 enum { 243 DPTX_VM_RGB_6BIT, 244 DPTX_VM_RGB_8BIT, 245 DPTX_VM_RGB_10BIT, 246 DPTX_VM_RGB_12BIT, 247 DPTX_VM_RGB_16BIT, 248 DPTX_VM_YCBCR444_8BIT, 249 DPTX_VM_YCBCR444_10BIT, 250 DPTX_VM_YCBCR444_12BIT, 251 DPTX_VM_YCBCR444_16BIT, 252 DPTX_VM_YCBCR422_8BIT, 253 DPTX_VM_YCBCR422_10BIT, 254 DPTX_VM_YCBCR422_12BIT, 255 DPTX_VM_YCBCR422_16BIT, 256 DPTX_VM_YCBCR420_8BIT, 257 DPTX_VM_YCBCR420_10BIT, 258 DPTX_VM_YCBCR420_12BIT, 259 DPTX_VM_YCBCR420_16BIT, 260 }; 261 262 enum { 263 DPTX_MP_SINGLE_PIXEL, 264 DPTX_MP_DUAL_PIXEL, 265 DPTX_MP_QUAD_PIXEL, 266 }; 267 268 enum { 269 DPTX_SDP_VERTICAL_INTERVAL = BIT(0), 270 DPTX_SDP_HORIZONTAL_INTERVAL = BIT(1), 271 }; 272 273 enum { 274 DPTX_PHY_PATTERN_NONE, 275 DPTX_PHY_PATTERN_TPS_1, 276 DPTX_PHY_PATTERN_TPS_2, 277 DPTX_PHY_PATTERN_TPS_3, 278 DPTX_PHY_PATTERN_TPS_4, 279 DPTX_PHY_PATTERN_SERM, 280 DPTX_PHY_PATTERN_PBRS7, 281 DPTX_PHY_PATTERN_CUSTOM_80BIT, 282 DPTX_PHY_PATTERN_CP2520_1, 283 DPTX_PHY_PATTERN_CP2520_2, 284 }; 285 286 enum { 287 DPTX_PHYRATE_RBR, 288 DPTX_PHYRATE_HBR, 289 DPTX_PHYRATE_HBR2, 290 DPTX_PHYRATE_HBR3, 291 }; 292 293 struct dw_dp_output_format { 294 u32 bus_format; 295 u32 color_format; 296 u8 video_mapping; 297 u8 bpc; 298 u8 bpp; 299 }; 300 301 static const struct dw_dp_output_format possible_output_fmts[] = { 302 { MEDIA_BUS_FMT_RGB101010_1X30, DRM_COLOR_FORMAT_RGB444, 303 DPTX_VM_RGB_10BIT, 10, 30 }, 304 { MEDIA_BUS_FMT_RGB888_1X24, DRM_COLOR_FORMAT_RGB444, 305 DPTX_VM_RGB_8BIT, 8, 24 }, 306 { MEDIA_BUS_FMT_YUV10_1X30, DRM_COLOR_FORMAT_YCRCB444, 307 DPTX_VM_YCBCR444_10BIT, 10, 30 }, 308 { MEDIA_BUS_FMT_YUV8_1X24, DRM_COLOR_FORMAT_YCRCB444, 309 DPTX_VM_YCBCR444_8BIT, 8, 24}, 310 { MEDIA_BUS_FMT_YUYV10_1X20, DRM_COLOR_FORMAT_YCRCB422, 311 DPTX_VM_YCBCR422_10BIT, 10, 20 }, 312 { MEDIA_BUS_FMT_YUYV8_1X16, DRM_COLOR_FORMAT_YCRCB422, 313 DPTX_VM_YCBCR422_8BIT, 8, 16 }, 314 { MEDIA_BUS_FMT_UYYVYY10_0_5X30, DRM_COLOR_FORMAT_YCRCB420, 315 DPTX_VM_YCBCR420_10BIT, 10, 15 }, 316 { MEDIA_BUS_FMT_UYYVYY8_0_5X24, DRM_COLOR_FORMAT_YCRCB420, 317 DPTX_VM_YCBCR420_8BIT, 8, 12 }, 318 { MEDIA_BUS_FMT_RGB666_1X24_CPADHI, DRM_COLOR_FORMAT_RGB444, 319 DPTX_VM_RGB_6BIT, 6, 18 }, 320 }; 321 322 static int dw_dp_aux_write_data(struct dw_dp *dp, const u8 *buffer, size_t size) 323 { 324 size_t i, j; 325 326 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 327 size_t num = min_t(size_t, size - i * 4, 4); 328 u32 value = 0; 329 330 for (j = 0; j < num; j++) 331 value |= buffer[i * 4 + j] << (j * 8); 332 333 regmap_write(dp->regmap, DPTX_AUX_DATA0 + i * 4, value); 334 } 335 336 return size; 337 } 338 339 static int dw_dp_aux_read_data(struct dw_dp *dp, u8 *buffer, size_t size) 340 { 341 size_t i, j; 342 343 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 344 size_t num = min_t(size_t, size - i * 4, 4); 345 u32 value; 346 347 regmap_read(dp->regmap, DPTX_AUX_DATA0 + i * 4, &value); 348 349 for (j = 0; j < num; j++) 350 buffer[i * 4 + j] = value >> (j * 8); 351 } 352 353 return size; 354 } 355 356 static ssize_t dw_dp_aux_transfer(struct drm_dp_aux *aux, 357 struct drm_dp_aux_msg *msg) 358 { 359 u32 status, value; 360 ssize_t ret = 0; 361 int timeout = 0; 362 struct dw_dp *dp = dev_get_priv(aux->dev); 363 364 if (WARN_ON(msg->size > 16)) 365 return -E2BIG; 366 367 switch (msg->request & ~DP_AUX_I2C_MOT) { 368 case DP_AUX_NATIVE_WRITE: 369 case DP_AUX_I2C_WRITE: 370 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 371 ret = dw_dp_aux_write_data(dp, msg->buffer, msg->size); 372 if (ret < 0) 373 return ret; 374 break; 375 case DP_AUX_NATIVE_READ: 376 case DP_AUX_I2C_READ: 377 break; 378 default: 379 return -EINVAL; 380 } 381 382 if (msg->size > 0) 383 value = FIELD_PREP(AUX_LEN_REQ, msg->size - 1); 384 else 385 value = FIELD_PREP(I2C_ADDR_ONLY, 1); 386 387 value |= FIELD_PREP(AUX_CMD_TYPE, msg->request); 388 value |= FIELD_PREP(AUX_ADDR, msg->address); 389 regmap_write(dp->regmap, DPTX_AUX_CMD, value); 390 391 timeout = regmap_read_poll_timeout(dp->regmap, DPTX_GENERAL_INTERRUPT, 392 status, status & AUX_REPLY_EVENT, 393 200, 10); 394 395 if (timeout) { 396 printf("timeout waiting for AUX reply\n"); 397 return -ETIMEDOUT; 398 } 399 regmap_write(dp->regmap, DPTX_GENERAL_INTERRUPT, AUX_REPLY_EVENT); 400 401 regmap_read(dp->regmap, DPTX_AUX_STATUS, &value); 402 if (value & AUX_TIMEOUT) { 403 printf("aux timeout\n"); 404 return -ETIMEDOUT; 405 } 406 407 msg->reply = FIELD_GET(AUX_STATUS, value); 408 409 if (msg->size > 0 && msg->reply == DP_AUX_NATIVE_REPLY_ACK) { 410 if (msg->request & DP_AUX_I2C_READ) { 411 size_t count = FIELD_GET(AUX_BYTES_READ, value) - 1; 412 413 if (count != msg->size) { 414 printf("aux fail to read %lu bytes\n", count); 415 return -EBUSY; 416 } 417 418 ret = dw_dp_aux_read_data(dp, msg->buffer, count); 419 if (ret < 0) 420 return ret; 421 } 422 } 423 424 return ret; 425 } 426 427 static bool dw_dp_bandwidth_ok(struct dw_dp *dp, 428 const struct drm_display_mode *mode, u32 bpp, 429 unsigned int lanes, unsigned int rate) 430 { 431 u32 max_bw, req_bw; 432 433 req_bw = mode->clock * bpp / 8; 434 max_bw = lanes * rate; 435 if (req_bw > max_bw) 436 return false; 437 438 return true; 439 } 440 441 static void dw_dp_hpd_init(struct dw_dp *dp) 442 { 443 if (dm_gpio_is_valid(&dp->hpd_gpio) || dp->force_hpd) { 444 regmap_update_bits(dp->regmap, DPTX_CCTL, FORCE_HPD, 445 FIELD_PREP(FORCE_HPD, 1)); 446 return; 447 } 448 449 /* Enable all HPD interrupts */ 450 regmap_update_bits(dp->regmap, DPTX_HPD_INTERRUPT_ENABLE, 451 HPD_UNPLUG_EN | HPD_PLUG_EN | HPD_IRQ_EN, 452 FIELD_PREP(HPD_UNPLUG_EN, 1) | 453 FIELD_PREP(HPD_PLUG_EN, 1) | 454 FIELD_PREP(HPD_IRQ_EN, 1)); 455 456 /* Enable all top-level interrupts */ 457 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, 458 HPD_EVENT_EN, FIELD_PREP(HPD_EVENT_EN, 1)); 459 } 460 461 static void dw_dp_aux_init(struct dw_dp *dp) 462 { 463 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, 464 FIELD_PREP(AUX_RESET, 1)); 465 udelay(10); 466 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, 467 FIELD_PREP(AUX_RESET, 0)); 468 469 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, 470 AUX_REPLY_EVENT_EN, 471 FIELD_PREP(AUX_REPLY_EVENT_EN, 1)); 472 } 473 474 static void dw_dp_init(struct dw_dp *dp) 475 { 476 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, 477 FIELD_PREP(CONTROLLER_RESET, 1)); 478 udelay(10); 479 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, 480 FIELD_PREP(CONTROLLER_RESET, 0)); 481 482 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, 483 FIELD_PREP(PHY_SOFT_RESET, 1)); 484 udelay(10); 485 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, 486 FIELD_PREP(PHY_SOFT_RESET, 0)); 487 488 regmap_update_bits(dp->regmap, DPTX_CCTL, DEFAULT_FAST_LINK_TRAIN_EN, 489 FIELD_PREP(DEFAULT_FAST_LINK_TRAIN_EN, 0)); 490 491 dw_dp_hpd_init(dp); 492 dw_dp_aux_init(dp); 493 } 494 495 static void dw_dp_phy_set_pattern(struct dw_dp *dp, u32 pattern) 496 { 497 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, TPS_SEL, 498 FIELD_PREP(TPS_SEL, pattern)); 499 } 500 501 static void dw_dp_phy_xmit_enable(struct dw_dp *dp, u32 lanes) 502 { 503 u32 xmit_enable; 504 505 switch (lanes) { 506 case 4: 507 case 2: 508 case 1: 509 xmit_enable = GENMASK(lanes - 1, 0); 510 break; 511 case 0: 512 default: 513 xmit_enable = 0; 514 break; 515 } 516 517 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, XMIT_ENABLE, 518 FIELD_PREP(XMIT_ENABLE, xmit_enable)); 519 } 520 521 static int dw_dp_link_power_up(struct dw_dp *dp) 522 { 523 struct dw_dp_link *link = &dp->link; 524 u8 value; 525 int ret; 526 527 if (link->revision < 0x11) 528 return 0; 529 530 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value); 531 if (ret < 0) 532 return ret; 533 534 value &= ~DP_SET_POWER_MASK; 535 value |= DP_SET_POWER_D0; 536 537 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value); 538 if (ret < 0) 539 return ret; 540 541 udelay(1000); 542 return 0; 543 } 544 545 static int dw_dp_link_probe(struct dw_dp *dp) 546 { 547 struct dw_dp_link *link = &dp->link; 548 u8 dpcd; 549 int ret; 550 551 ret = drm_dp_read_dpcd_caps(&dp->aux, link->dpcd); 552 if (ret < 0) 553 return ret; 554 555 ret = drm_dp_dpcd_readb(&dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, 556 &dpcd); 557 if (ret < 0) 558 return ret; 559 560 link->vsc_sdp_extension_for_colorimetry_supported = 561 !!(dpcd & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED); 562 563 link->revision = link->dpcd[DP_DPCD_REV]; 564 link->rate = min_t(u32, dp->phy.attrs.max_link_rate * 100, 565 drm_dp_max_link_rate(link->dpcd)); 566 link->lanes = min_t(u8, dp->phy.attrs.bus_width, 567 drm_dp_max_lane_count(link->dpcd)); 568 569 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(link->dpcd); 570 link->caps.tps3_supported = drm_dp_tps3_supported(link->dpcd); 571 link->caps.tps4_supported = drm_dp_tps4_supported(link->dpcd); 572 link->caps.channel_coding = drm_dp_channel_coding_supported(link->dpcd); 573 link->caps.ssc = !!(link->dpcd[DP_MAX_DOWNSPREAD] & 574 DP_MAX_DOWNSPREAD_0_5); 575 576 return 0; 577 } 578 579 static int dw_dp_link_train_update_vs_emph(struct dw_dp *dp) 580 { 581 struct dw_dp_link *link = &dp->link; 582 struct drm_dp_link_train_set *request = &link->train.request; 583 union phy_configure_opts phy_cfg; 584 unsigned int lanes = link->lanes, *vs, *pe; 585 u8 buf[4]; 586 int i, ret; 587 588 vs = request->voltage_swing; 589 pe = request->pre_emphasis; 590 591 for (i = 0; i < lanes; i++) { 592 phy_cfg.dp.voltage[i] = vs[i]; 593 phy_cfg.dp.pre[i] = pe[i]; 594 } 595 phy_cfg.dp.lanes = lanes; 596 phy_cfg.dp.link_rate = link->rate / 100; 597 phy_cfg.dp.set_lanes = false; 598 phy_cfg.dp.set_rate = false; 599 phy_cfg.dp.set_voltages = true; 600 ret = generic_phy_configure(&dp->phy, &phy_cfg); 601 if (ret) 602 return ret; 603 604 for (i = 0; i < lanes; i++) 605 buf[i] = (vs[i] << DP_TRAIN_VOLTAGE_SWING_SHIFT) | 606 (pe[i] << DP_TRAIN_PRE_EMPHASIS_SHIFT); 607 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, lanes); 608 if (ret < 0) 609 return ret; 610 611 return 0; 612 } 613 614 static int dw_dp_link_configure(struct dw_dp *dp) 615 { 616 struct dw_dp_link *link = &dp->link; 617 union phy_configure_opts phy_cfg; 618 u8 buf[2]; 619 int ret, phy_rate; 620 621 /* Move PHY to P3 */ 622 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 623 FIELD_PREP(PHY_POWERDOWN, 0x3)); 624 625 phy_cfg.dp.lanes = link->lanes; 626 phy_cfg.dp.link_rate = link->rate / 100; 627 phy_cfg.dp.ssc = link->caps.ssc; 628 phy_cfg.dp.set_lanes = true; 629 phy_cfg.dp.set_rate = true; 630 phy_cfg.dp.set_voltages = false; 631 ret = generic_phy_configure(&dp->phy, &phy_cfg); 632 if (ret) 633 return ret; 634 635 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, 636 FIELD_PREP(PHY_LANES, link->lanes / 2)); 637 638 switch (link->rate) { 639 case 810000: 640 phy_rate = DPTX_PHYRATE_HBR3; 641 break; 642 case 540000: 643 phy_rate = DPTX_PHYRATE_HBR2; 644 break; 645 case 270000: 646 phy_rate = DPTX_PHYRATE_HBR; 647 break; 648 case 162000: 649 default: 650 phy_rate = DPTX_PHYRATE_RBR; 651 break; 652 } 653 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_RATE, 654 FIELD_PREP(PHY_RATE, phy_rate)); 655 656 /* Move PHY to P0 */ 657 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 658 FIELD_PREP(PHY_POWERDOWN, 0x0)); 659 660 dw_dp_phy_xmit_enable(dp, link->lanes); 661 662 buf[0] = drm_dp_link_rate_to_bw_code(link->rate); 663 buf[1] = link->lanes; 664 665 if (link->caps.enhanced_framing) { 666 buf[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 667 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 668 FIELD_PREP(ENHANCE_FRAMING_EN, 1)); 669 } else { 670 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 671 FIELD_PREP(ENHANCE_FRAMING_EN, 0)); 672 } 673 674 ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, sizeof(buf)); 675 if (ret < 0) 676 return ret; 677 678 buf[0] = link->caps.ssc ? DP_SPREAD_AMP_0_5 : 0; 679 buf[1] = link->caps.channel_coding ? DP_SET_ANSI_8B10B : 0; 680 681 ret = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, 682 sizeof(buf)); 683 if (ret < 0) 684 return ret; 685 686 return 0; 687 } 688 689 static void dw_dp_link_train_init(struct drm_dp_link_train *train) 690 { 691 struct drm_dp_link_train_set *request = &train->request; 692 struct drm_dp_link_train_set *adjust = &train->adjust; 693 unsigned int i; 694 695 for (i = 0; i < 4; i++) { 696 request->voltage_swing[i] = 0; 697 adjust->voltage_swing[i] = 0; 698 699 request->pre_emphasis[i] = 0; 700 adjust->pre_emphasis[i] = 0; 701 } 702 703 train->clock_recovered = false; 704 train->channel_equalized = false; 705 } 706 707 static int dw_dp_link_train_set_pattern(struct dw_dp *dp, u32 pattern) 708 { 709 u8 buf = 0; 710 int ret; 711 712 if (pattern && pattern != DP_TRAINING_PATTERN_4) { 713 buf |= DP_LINK_SCRAMBLING_DISABLE; 714 715 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, 716 FIELD_PREP(SCRAMBLE_DIS, 1)); 717 } else { 718 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, 719 FIELD_PREP(SCRAMBLE_DIS, 0)); 720 } 721 722 switch (pattern) { 723 case DP_TRAINING_PATTERN_DISABLE: 724 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE); 725 break; 726 case DP_TRAINING_PATTERN_1: 727 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_1); 728 break; 729 case DP_TRAINING_PATTERN_2: 730 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_2); 731 break; 732 case DP_TRAINING_PATTERN_3: 733 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_3); 734 break; 735 case DP_TRAINING_PATTERN_4: 736 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_4); 737 break; 738 default: 739 return -EINVAL; 740 } 741 742 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 743 buf | pattern); 744 if (ret < 0) 745 return ret; 746 747 return 0; 748 } 749 750 static void dw_dp_link_get_adjustments(struct dw_dp_link *link, 751 u8 status[DP_LINK_STATUS_SIZE]) 752 { 753 struct drm_dp_link_train_set *adjust = &link->train.adjust; 754 unsigned int i; 755 756 for (i = 0; i < link->lanes; i++) { 757 adjust->voltage_swing[i] = 758 drm_dp_get_adjust_request_voltage(status, i) >> 759 DP_TRAIN_VOLTAGE_SWING_SHIFT; 760 761 adjust->pre_emphasis[i] = 762 drm_dp_get_adjust_request_pre_emphasis(status, i) >> 763 DP_TRAIN_PRE_EMPHASIS_SHIFT; 764 } 765 } 766 767 static void dw_dp_link_train_adjust(struct drm_dp_link_train *train) 768 { 769 struct drm_dp_link_train_set *request = &train->request; 770 struct drm_dp_link_train_set *adjust = &train->adjust; 771 unsigned int i; 772 773 for (i = 0; i < 4; i++) 774 if (request->voltage_swing[i] != adjust->voltage_swing[i]) 775 request->voltage_swing[i] = adjust->voltage_swing[i]; 776 777 for (i = 0; i < 4; i++) 778 if (request->pre_emphasis[i] != adjust->pre_emphasis[i]) 779 request->pre_emphasis[i] = adjust->pre_emphasis[i]; 780 } 781 782 static int dw_dp_link_clock_recovery(struct dw_dp *dp) 783 { 784 struct dw_dp_link *link = &dp->link; 785 u8 status[DP_LINK_STATUS_SIZE]; 786 unsigned int tries = 0; 787 int ret; 788 789 ret = dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_1); 790 if (ret) 791 return ret; 792 793 for (;;) { 794 ret = dw_dp_link_train_update_vs_emph(dp); 795 if (ret) 796 return ret; 797 798 drm_dp_link_train_clock_recovery_delay(link->dpcd); 799 800 ret = drm_dp_dpcd_read_link_status(&dp->aux, status); 801 if (ret < 0) { 802 dev_err(dp->dev, "failed to read link status: %d\n", 803 ret); 804 return ret; 805 } 806 807 if (drm_dp_clock_recovery_ok(status, link->lanes)) { 808 link->train.clock_recovered = true; 809 break; 810 } 811 812 dw_dp_link_get_adjustments(link, status); 813 814 if (link->train.request.voltage_swing[0] == 815 link->train.adjust.voltage_swing[0]) 816 tries++; 817 else 818 tries = 0; 819 820 if (tries == 5) 821 break; 822 823 dw_dp_link_train_adjust(&link->train); 824 } 825 826 return 0; 827 } 828 829 static int dw_dp_link_channel_equalization(struct dw_dp *dp) 830 { 831 struct dw_dp_link *link = &dp->link; 832 u8 status[DP_LINK_STATUS_SIZE], pattern; 833 unsigned int tries; 834 int ret; 835 836 if (link->caps.tps4_supported) 837 pattern = DP_TRAINING_PATTERN_4; 838 else if (link->caps.tps3_supported) 839 pattern = DP_TRAINING_PATTERN_3; 840 else 841 pattern = DP_TRAINING_PATTERN_2; 842 ret = dw_dp_link_train_set_pattern(dp, pattern); 843 if (ret) 844 return ret; 845 846 for (tries = 1; tries < 5; tries++) { 847 ret = dw_dp_link_train_update_vs_emph(dp); 848 if (ret) 849 return ret; 850 851 drm_dp_link_train_channel_eq_delay(link->dpcd); 852 853 ret = drm_dp_dpcd_read_link_status(&dp->aux, status); 854 if (ret < 0) 855 return ret; 856 857 if (!drm_dp_clock_recovery_ok(status, link->lanes)) { 858 dev_err(dp->dev, 859 "clock recovery lost while eq\n"); 860 link->train.clock_recovered = false; 861 break; 862 } 863 864 if (drm_dp_channel_eq_ok(status, link->lanes)) { 865 link->train.channel_equalized = true; 866 break; 867 } 868 869 dw_dp_link_get_adjustments(link, status); 870 dw_dp_link_train_adjust(&link->train); 871 } 872 873 return 0; 874 } 875 876 static int dw_dp_link_downgrade(struct dw_dp *dp) 877 { 878 struct dw_dp_link *link = &dp->link; 879 struct dw_dp_video *video = &dp->video; 880 881 switch (link->rate) { 882 case 162000: 883 return -EINVAL; 884 case 270000: 885 link->rate = 162000; 886 break; 887 case 540000: 888 link->rate = 270000; 889 break; 890 case 810000: 891 link->rate = 540000; 892 break; 893 } 894 895 if (!dw_dp_bandwidth_ok(dp, &video->mode, video->bpp, link->lanes, 896 link->rate)) 897 return -E2BIG; 898 899 return 0; 900 } 901 902 static int dw_dp_link_train(struct dw_dp *dp) 903 { 904 struct dw_dp_link *link = &dp->link; 905 int ret; 906 907 retry: 908 dw_dp_link_train_init(&link->train); 909 910 printf("training link: %u lane%s at %u MHz\n", 911 link->lanes, (link->lanes > 1) ? "s" : "", link->rate / 100); 912 913 ret = dw_dp_link_configure(dp); 914 if (ret < 0) { 915 dev_err(dp->dev, "failed to configure DP link: %d\n", ret); 916 return ret; 917 } 918 919 ret = dw_dp_link_clock_recovery(dp); 920 if (ret < 0) { 921 dev_err(dp->dev, "clock recovery failed: %d\n", ret); 922 goto out; 923 } 924 925 if (!link->train.clock_recovered) { 926 dev_err(dp->dev, "clock recovery failed, downgrading link\n"); 927 928 ret = dw_dp_link_downgrade(dp); 929 if (ret < 0) 930 goto out; 931 else 932 goto retry; 933 } 934 935 printf("clock recovery succeeded\n"); 936 937 ret = dw_dp_link_channel_equalization(dp); 938 if (ret < 0) { 939 dev_err(dp->dev, "channel equalization failed: %d\n", ret); 940 goto out; 941 } 942 943 if (!link->train.channel_equalized) { 944 dev_err(dp->dev, 945 "channel equalization failed, downgrading link\n"); 946 947 ret = dw_dp_link_downgrade(dp); 948 if (ret < 0) 949 goto out; 950 else 951 goto retry; 952 } 953 954 printf("channel equalization succeeded\n"); 955 956 out: 957 dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE); 958 return ret; 959 } 960 961 static int dw_dp_link_enable(struct dw_dp *dp) 962 { 963 int ret; 964 965 ret = dw_dp_link_power_up(dp); 966 if (ret < 0) 967 return ret; 968 969 ret = dw_dp_link_train(dp); 970 if (ret < 0) { 971 dev_err(dp->dev, "link training failed: %d\n", ret); 972 return ret; 973 } 974 975 return 0; 976 } 977 978 static int dw_dp_set_phy_default_config(struct dw_dp *dp) 979 { 980 struct dw_dp_link *link = &dp->link; 981 union phy_configure_opts phy_cfg; 982 int ret, i, phy_rate; 983 984 link->vsc_sdp_extension_for_colorimetry_supported = false; 985 link->rate = 270000; 986 link->lanes = dp->phy.attrs.bus_width; 987 988 link->caps.enhanced_framing = true; 989 link->caps.channel_coding = true; 990 link->caps.ssc = true; 991 992 /* Move PHY to P3 */ 993 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 994 FIELD_PREP(PHY_POWERDOWN, 0x3)); 995 996 for (i = 0; i < link->lanes; i++) { 997 phy_cfg.dp.voltage[i] = 3; 998 phy_cfg.dp.pre[i] = 0; 999 } 1000 phy_cfg.dp.lanes = link->lanes; 1001 phy_cfg.dp.link_rate = link->rate / 100; 1002 phy_cfg.dp.ssc = link->caps.ssc; 1003 phy_cfg.dp.set_lanes = true; 1004 phy_cfg.dp.set_rate = true; 1005 phy_cfg.dp.set_voltages = true; 1006 ret = generic_phy_configure(&dp->phy, &phy_cfg); 1007 if (ret) 1008 return ret; 1009 1010 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, 1011 FIELD_PREP(PHY_LANES, link->lanes / 2)); 1012 1013 switch (link->rate) { 1014 case 810000: 1015 phy_rate = DPTX_PHYRATE_HBR3; 1016 break; 1017 case 540000: 1018 phy_rate = DPTX_PHYRATE_HBR2; 1019 break; 1020 case 270000: 1021 phy_rate = DPTX_PHYRATE_HBR; 1022 break; 1023 case 162000: 1024 default: 1025 phy_rate = DPTX_PHYRATE_RBR; 1026 break; 1027 } 1028 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_RATE, 1029 FIELD_PREP(PHY_RATE, phy_rate)); 1030 1031 /* Move PHY to P0 */ 1032 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 1033 FIELD_PREP(PHY_POWERDOWN, 0x0)); 1034 1035 dw_dp_phy_xmit_enable(dp, link->lanes); 1036 1037 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 1038 FIELD_PREP(ENHANCE_FRAMING_EN, 1)); 1039 1040 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE); 1041 return 0; 1042 } 1043 1044 static int dw_dp_send_sdp(struct dw_dp *dp, struct dw_dp_sdp *sdp) 1045 { 1046 const u8 *payload = sdp->db; 1047 u32 reg; 1048 int i, nr = 0; 1049 1050 reg = DPTX_SDP_REGISTER_BANK + nr * 9 * 4; 1051 1052 /* SDP header */ 1053 regmap_write(dp->regmap, reg, get_unaligned_le32(&sdp->header)); 1054 1055 /* SDP data payload */ 1056 for (i = 1; i < 9; i++, payload += 4) 1057 regmap_write(dp->regmap, reg + i * 4, 1058 FIELD_PREP(SDP_REGS, get_unaligned_le32(payload))); 1059 1060 if (sdp->flags & DPTX_SDP_VERTICAL_INTERVAL) 1061 regmap_update_bits(dp->regmap, DPTX_SDP_VERTICAL_CTRL, 1062 EN_VERTICAL_SDP << nr, 1063 EN_VERTICAL_SDP << nr); 1064 1065 if (sdp->flags & DPTX_SDP_HORIZONTAL_INTERVAL) 1066 regmap_update_bits(dp->regmap, DPTX_SDP_HORIZONTAL_CTRL, 1067 EN_HORIZONTAL_SDP << nr, 1068 EN_HORIZONTAL_SDP << nr); 1069 1070 return 0; 1071 } 1072 1073 static void dw_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, 1074 struct dw_dp_sdp *sdp) 1075 { 1076 sdp->header.HB0 = 0; 1077 sdp->header.HB1 = DP_SDP_VSC; 1078 sdp->header.HB2 = vsc->revision; 1079 sdp->header.HB3 = vsc->length; 1080 1081 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; 1082 sdp->db[16] |= vsc->colorimetry & 0xf; 1083 1084 switch (vsc->bpc) { 1085 case 8: 1086 sdp->db[17] = 0x1; 1087 break; 1088 case 10: 1089 sdp->db[17] = 0x2; 1090 break; 1091 case 12: 1092 sdp->db[17] = 0x3; 1093 break; 1094 case 16: 1095 sdp->db[17] = 0x4; 1096 break; 1097 case 6: 1098 default: 1099 break; 1100 } 1101 1102 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) 1103 sdp->db[17] |= 0x80; 1104 1105 sdp->db[18] = vsc->content_type & 0x7; 1106 1107 sdp->flags |= DPTX_SDP_VERTICAL_INTERVAL; 1108 } 1109 1110 static int dw_dp_send_vsc_sdp(struct dw_dp *dp) 1111 { 1112 struct dw_dp_video *video = &dp->video; 1113 struct drm_dp_vsc_sdp vsc = {}; 1114 struct dw_dp_sdp sdp = {}; 1115 1116 vsc.revision = 0x5; 1117 vsc.length = 0x13; 1118 1119 switch (video->color_format) { 1120 case DRM_COLOR_FORMAT_YCRCB444: 1121 vsc.pixelformat = DP_PIXELFORMAT_YUV444; 1122 break; 1123 case DRM_COLOR_FORMAT_YCRCB420: 1124 vsc.pixelformat = DP_PIXELFORMAT_YUV420; 1125 break; 1126 case DRM_COLOR_FORMAT_YCRCB422: 1127 vsc.pixelformat = DP_PIXELFORMAT_YUV422; 1128 break; 1129 case DRM_COLOR_FORMAT_RGB444: 1130 default: 1131 vsc.pixelformat = DP_PIXELFORMAT_RGB; 1132 break; 1133 } 1134 1135 if (video->color_format == DRM_COLOR_FORMAT_RGB444) 1136 vsc.colorimetry = DP_COLORIMETRY_DEFAULT; 1137 else 1138 vsc.colorimetry = DP_COLORIMETRY_BT709_YCC; 1139 1140 vsc.bpc = video->bpc; 1141 vsc.dynamic_range = DP_DYNAMIC_RANGE_CTA; 1142 vsc.content_type = DP_CONTENT_TYPE_NOT_DEFINED; 1143 1144 dw_dp_vsc_sdp_pack(&vsc, &sdp); 1145 1146 return dw_dp_send_sdp(dp, &sdp); 1147 } 1148 1149 static int dw_dp_video_set_pixel_mode(struct dw_dp *dp, u8 pixel_mode) 1150 { 1151 switch (pixel_mode) { 1152 case DPTX_MP_SINGLE_PIXEL: 1153 case DPTX_MP_DUAL_PIXEL: 1154 case DPTX_MP_QUAD_PIXEL: 1155 break; 1156 default: 1157 return -EINVAL; 1158 } 1159 1160 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, PIXEL_MODE_SELECT, 1161 FIELD_PREP(PIXEL_MODE_SELECT, pixel_mode)); 1162 1163 return 0; 1164 } 1165 1166 static int dw_dp_video_set_msa(struct dw_dp *dp, u8 color_format, u8 bpc, 1167 u16 vstart, u16 hstart) 1168 { 1169 struct dw_dp_link *link = &dp->link; 1170 u16 misc = 0; 1171 1172 if (link->vsc_sdp_extension_for_colorimetry_supported) 1173 misc |= DP_MSA_MISC_COLOR_VSC_SDP; 1174 1175 switch (color_format) { 1176 case DRM_COLOR_FORMAT_RGB444: 1177 misc |= DP_MSA_MISC_COLOR_RGB; 1178 break; 1179 case DRM_COLOR_FORMAT_YCRCB444: 1180 misc |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 1181 break; 1182 case DRM_COLOR_FORMAT_YCRCB422: 1183 misc |= DP_MSA_MISC_COLOR_YCBCR_422_BT709; 1184 break; 1185 case DRM_COLOR_FORMAT_YCRCB420: 1186 break; 1187 default: 1188 return -EINVAL; 1189 } 1190 1191 switch (bpc) { 1192 case 6: 1193 misc |= DP_MSA_MISC_6_BPC; 1194 break; 1195 case 8: 1196 misc |= DP_MSA_MISC_8_BPC; 1197 break; 1198 case 10: 1199 misc |= DP_MSA_MISC_10_BPC; 1200 break; 1201 case 12: 1202 misc |= DP_MSA_MISC_12_BPC; 1203 break; 1204 case 16: 1205 misc |= DP_MSA_MISC_16_BPC; 1206 break; 1207 default: 1208 return -EINVAL; 1209 } 1210 1211 regmap_write(dp->regmap, DPTX_VIDEO_MSA1, 1212 FIELD_PREP(VSTART, vstart) | FIELD_PREP(HSTART, hstart)); 1213 regmap_write(dp->regmap, DPTX_VIDEO_MSA2, FIELD_PREP(MISC0, misc)); 1214 regmap_write(dp->regmap, DPTX_VIDEO_MSA3, FIELD_PREP(MISC1, misc >> 8)); 1215 1216 return 0; 1217 } 1218 1219 static int dw_dp_video_enable(struct dw_dp *dp) 1220 { 1221 struct dw_dp_video *video = &dp->video; 1222 struct dw_dp_link *link = &dp->link; 1223 struct drm_display_mode *mode = &video->mode; 1224 u8 color_format = video->color_format; 1225 u8 bpc = video->bpc; 1226 u8 pixel_mode = video->pixel_mode; 1227 u8 bpp = video->bpp, init_threshold, vic; 1228 u32 hactive, hblank, h_sync_width, h_front_porch; 1229 u32 vactive, vblank, v_sync_width, v_front_porch; 1230 u32 vstart = mode->vtotal - mode->vsync_start; 1231 u32 hstart = mode->htotal - mode->hsync_start; 1232 u32 peak_stream_bandwidth, link_bandwidth; 1233 u32 average_bytes_per_tu, average_bytes_per_tu_frac; 1234 u32 ts, hblank_interval; 1235 u32 value; 1236 int ret; 1237 1238 ret = dw_dp_video_set_pixel_mode(dp, pixel_mode); 1239 if (ret) 1240 return ret; 1241 1242 ret = dw_dp_video_set_msa(dp, color_format, bpc, vstart, hstart); 1243 if (ret) 1244 return ret; 1245 1246 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_MAPPING, 1247 FIELD_PREP(VIDEO_MAPPING, video->video_mapping)); 1248 1249 /* Configure DPTX_VINPUT_POLARITY_CTRL register */ 1250 value = 0; 1251 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1252 value |= FIELD_PREP(HSYNC_IN_POLARITY, 1); 1253 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1254 value |= FIELD_PREP(VSYNC_IN_POLARITY, 1); 1255 regmap_write(dp->regmap, DPTX_VINPUT_POLARITY_CTRL, value); 1256 1257 /* Configure DPTX_VIDEO_CONFIG1 register */ 1258 hactive = mode->hdisplay; 1259 hblank = mode->htotal - mode->hdisplay; 1260 value = FIELD_PREP(HACTIVE, hactive) | FIELD_PREP(HBLANK, hblank); 1261 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1262 value |= FIELD_PREP(I_P, 1); 1263 vic = drm_match_cea_mode(mode); 1264 if (vic == 5 || vic == 6 || vic == 7 || 1265 vic == 10 || vic == 11 || vic == 20 || 1266 vic == 21 || vic == 22 || vic == 39 || 1267 vic == 25 || vic == 26 || vic == 40 || 1268 vic == 44 || vic == 45 || vic == 46 || 1269 vic == 50 || vic == 51 || vic == 54 || 1270 vic == 55 || vic == 58 || vic == 59) 1271 value |= R_V_BLANK_IN_OSC; 1272 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG1, value); 1273 1274 /* Configure DPTX_VIDEO_CONFIG2 register */ 1275 vblank = mode->vtotal - mode->vdisplay; 1276 vactive = mode->vdisplay; 1277 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG2, 1278 FIELD_PREP(VBLANK, vblank) | FIELD_PREP(VACTIVE, vactive)); 1279 1280 /* Configure DPTX_VIDEO_CONFIG3 register */ 1281 h_sync_width = mode->hsync_end - mode->hsync_start; 1282 h_front_porch = mode->hsync_start - mode->hdisplay; 1283 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG3, 1284 FIELD_PREP(H_SYNC_WIDTH, h_sync_width) | 1285 FIELD_PREP(H_FRONT_PORCH, h_front_porch)); 1286 1287 /* Configure DPTX_VIDEO_CONFIG4 register */ 1288 v_sync_width = mode->vsync_end - mode->vsync_start; 1289 v_front_porch = mode->vsync_start - mode->vdisplay; 1290 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG4, 1291 FIELD_PREP(V_SYNC_WIDTH, v_sync_width) | 1292 FIELD_PREP(V_FRONT_PORCH, v_front_porch)); 1293 1294 /* Configure DPTX_VIDEO_CONFIG5 register */ 1295 peak_stream_bandwidth = mode->clock * bpp / 8; 1296 link_bandwidth = (link->rate / 1000) * link->lanes; 1297 ts = peak_stream_bandwidth * 64 / link_bandwidth; 1298 average_bytes_per_tu = ts / 1000; 1299 average_bytes_per_tu_frac = ts / 100 - average_bytes_per_tu * 10; 1300 if (pixel_mode == DPTX_MP_SINGLE_PIXEL) { 1301 if (average_bytes_per_tu < 6) 1302 init_threshold = 32; 1303 else if (hblank <= 80 && 1304 color_format != DRM_COLOR_FORMAT_YCRCB420) 1305 init_threshold = 12; 1306 else if (hblank <= 40 && 1307 color_format == DRM_COLOR_FORMAT_YCRCB420) 1308 init_threshold = 3; 1309 else 1310 init_threshold = 16; 1311 } else { 1312 u32 t1 = 0, t2 = 0, t3 = 0; 1313 1314 switch (bpc) { 1315 case 6: 1316 t1 = (4 * 1000 / 9) * link->lanes; 1317 break; 1318 case 8: 1319 if (color_format == DRM_COLOR_FORMAT_YCRCB422) { 1320 t1 = (1000 / 2) * link->lanes; 1321 } else { 1322 if (pixel_mode == DPTX_MP_DUAL_PIXEL) 1323 t1 = (1000 / 3) * link->lanes; 1324 else 1325 t1 = (3000 / 16) * link->lanes; 1326 } 1327 break; 1328 case 10: 1329 if (color_format == DRM_COLOR_FORMAT_YCRCB422) 1330 t1 = (2000 / 5) * link->lanes; 1331 else 1332 t1 = (4000 / 15) * link->lanes; 1333 break; 1334 case 12: 1335 if (color_format == DRM_COLOR_FORMAT_YCRCB422) { 1336 if (pixel_mode == DPTX_MP_DUAL_PIXEL) 1337 t1 = (1000 / 6) * link->lanes; 1338 else 1339 t1 = (1000 / 3) * link->lanes; 1340 } else { 1341 t1 = (2000 / 9) * link->lanes; 1342 } 1343 break; 1344 case 16: 1345 if (color_format != DRM_COLOR_FORMAT_YCRCB422 && 1346 pixel_mode == DPTX_MP_DUAL_PIXEL) 1347 t1 = (1000 / 6) * link->lanes; 1348 else 1349 t1 = (1000 / 4) * link->lanes; 1350 break; 1351 default: 1352 return -EINVAL; 1353 } 1354 1355 if (color_format == DRM_COLOR_FORMAT_YCRCB420) 1356 t2 = (link->rate / 4) * 1000 / (mode->clock / 2); 1357 else 1358 t2 = (link->rate / 4) * 1000 / mode->clock; 1359 1360 if (average_bytes_per_tu_frac) 1361 t3 = average_bytes_per_tu + 1; 1362 else 1363 t3 = average_bytes_per_tu; 1364 init_threshold = t1 * t2 * t3 / (1000 * 1000); 1365 if (init_threshold <= 16 || average_bytes_per_tu < 10) 1366 init_threshold = 40; 1367 } 1368 1369 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG5, 1370 FIELD_PREP(INIT_THRESHOLD_HI, init_threshold >> 6) | 1371 FIELD_PREP(AVERAGE_BYTES_PER_TU_FRAC, 1372 average_bytes_per_tu_frac) | 1373 FIELD_PREP(INIT_THRESHOLD, init_threshold) | 1374 FIELD_PREP(AVERAGE_BYTES_PER_TU, average_bytes_per_tu)); 1375 1376 /* Configure DPTX_VIDEO_HBLANK_INTERVAL register */ 1377 hblank_interval = hblank * (link->rate / 4) / mode->clock; 1378 regmap_write(dp->regmap, DPTX_VIDEO_HBLANK_INTERVAL, 1379 FIELD_PREP(HBLANK_INTERVAL_EN, 1) | 1380 FIELD_PREP(HBLANK_INTERVAL, hblank_interval)); 1381 1382 /* Video stream enable */ 1383 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_STREAM_ENABLE, 1384 FIELD_PREP(VIDEO_STREAM_ENABLE, 1)); 1385 1386 if (link->vsc_sdp_extension_for_colorimetry_supported) 1387 dw_dp_send_vsc_sdp(dp); 1388 1389 return 0; 1390 } 1391 1392 static bool dw_dp_detect(struct dw_dp *dp) 1393 { 1394 u32 value; 1395 1396 if (dm_gpio_is_valid(&dp->hpd_gpio)) 1397 return dm_gpio_get_value(&dp->hpd_gpio); 1398 1399 regmap_read(dp->regmap, DPTX_HPD_STATUS, &value); 1400 if (FIELD_GET(HPD_STATE, value) == SOURCE_STATE_PLUG) { 1401 regmap_write(dp->regmap, DPTX_HPD_STATUS, HPD_HOT_PLUG); 1402 return true; 1403 } 1404 1405 return false; 1406 } 1407 1408 static int dw_dp_connector_pre_init(struct display_state *state) 1409 { 1410 struct connector_state *conn_state = &state->conn_state; 1411 1412 conn_state->type = DRM_MODE_CONNECTOR_DisplayPort; 1413 1414 return 0; 1415 } 1416 1417 static int dw_dp_connector_init(struct display_state *state) 1418 { 1419 struct connector_state *conn_state = &state->conn_state; 1420 struct dw_dp *dp = dev_get_priv(conn_state->dev); 1421 int ret; 1422 1423 conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_DP1 : VOP_OUTPUT_IF_DP0; 1424 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1425 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 1426 1427 clk_set_defaults(dp->dev); 1428 1429 reset_assert(&dp->reset); 1430 udelay(20); 1431 reset_deassert(&dp->reset); 1432 1433 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, 1434 dp->id); 1435 dw_dp_init(dp); 1436 ret = generic_phy_power_on(&dp->phy); 1437 1438 return ret; 1439 } 1440 1441 static int dw_dp_connector_get_edid(struct display_state *state) 1442 { 1443 int ret; 1444 struct connector_state *conn_state = &state->conn_state; 1445 struct dw_dp *dp = dev_get_priv(conn_state->dev); 1446 1447 ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); 1448 1449 return ret; 1450 } 1451 1452 static int dw_dp_get_output_fmts_index(u32 bus_format) 1453 { 1454 int i; 1455 1456 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 1457 const struct dw_dp_output_format *fmt = &possible_output_fmts[i]; 1458 1459 if (fmt->bus_format == bus_format) 1460 break; 1461 } 1462 1463 if (i == ARRAY_SIZE(possible_output_fmts)) 1464 return 1; 1465 1466 return i; 1467 } 1468 1469 static int dw_dp_connector_prepare(struct display_state *state) 1470 { 1471 struct connector_state *conn_state = &state->conn_state; 1472 struct dw_dp *dp = dev_get_priv(conn_state->dev); 1473 struct dw_dp_video *video = &dp->video; 1474 int bus_fmt; 1475 1476 bus_fmt = dw_dp_get_output_fmts_index(conn_state->bus_format); 1477 video->video_mapping = possible_output_fmts[bus_fmt].video_mapping; 1478 video->color_format = possible_output_fmts[bus_fmt].color_format; 1479 video->bus_format = possible_output_fmts[bus_fmt].bus_format; 1480 video->bpc = possible_output_fmts[bus_fmt].bpc; 1481 video->bpp = possible_output_fmts[bus_fmt].bpp; 1482 1483 return 0; 1484 } 1485 1486 static int dw_dp_connector_enable(struct display_state *state) 1487 { 1488 struct connector_state *conn_state = &state->conn_state; 1489 struct drm_display_mode *mode = &conn_state->mode; 1490 struct dw_dp *dp = dev_get_priv(conn_state->dev); 1491 struct dw_dp_video *video = &dp->video; 1492 int ret; 1493 1494 memcpy(&video->mode, mode, sizeof(video->mode)); 1495 video->pixel_mode = DPTX_MP_QUAD_PIXEL; 1496 1497 if (dp->force_output) { 1498 ret = dw_dp_set_phy_default_config(dp); 1499 if (ret < 0) 1500 printf("failed to set phy_default config: %d\n", ret); 1501 } else { 1502 ret = dw_dp_link_enable(dp); 1503 if (ret < 0) { 1504 printf("failed to enable link: %d\n", ret); 1505 return ret; 1506 } 1507 } 1508 1509 ret = dw_dp_video_enable(dp); 1510 if (ret < 0) { 1511 printf("failed to enable video: %d\n", ret); 1512 return ret; 1513 } 1514 1515 return 0; 1516 } 1517 1518 static int dw_dp_connector_disable(struct display_state *state) 1519 { 1520 /* TODO */ 1521 1522 return 0; 1523 } 1524 1525 static int dw_dp_connector_detect(struct display_state *state) 1526 { 1527 struct connector_state *conn_state = &state->conn_state; 1528 struct dw_dp *dp = dev_get_priv(conn_state->dev); 1529 int status, tries, ret; 1530 1531 for (tries = 0; tries < 200; tries++) { 1532 status = dw_dp_detect(dp); 1533 if (status) 1534 break; 1535 mdelay(2); 1536 } 1537 1538 if (state->force_output && !status) 1539 dp->force_output = true; 1540 1541 if (!status && !dp->force_output) 1542 generic_phy_power_off(&dp->phy); 1543 1544 if (status && !dp->force_output) { 1545 ret = dw_dp_link_probe(dp); 1546 if (ret) 1547 printf("failed to probe DP link: %d\n", ret); 1548 } 1549 1550 return status; 1551 } 1552 1553 static int dw_dp_mode_valid(struct dw_dp *dp, struct hdmi_edid_data *edid_data) 1554 { 1555 struct dw_dp_link *link = &dp->link; 1556 struct drm_display_info *di = &edid_data->display_info; 1557 u32 min_bpp; 1558 int i; 1559 1560 if (di->color_formats & DRM_COLOR_FORMAT_YCRCB420 && 1561 link->vsc_sdp_extension_for_colorimetry_supported) 1562 min_bpp = 12; 1563 else if (di->color_formats & DRM_COLOR_FORMAT_YCRCB422) 1564 min_bpp = 16; 1565 else if (di->color_formats & DRM_COLOR_FORMAT_RGB444) 1566 min_bpp = 18; 1567 else 1568 min_bpp = 24; 1569 1570 for (i = 0; i < edid_data->modes; i++) { 1571 if (!dw_dp_bandwidth_ok(dp, &edid_data->mode_buf[i], min_bpp, link->lanes, 1572 link->rate)) 1573 edid_data->mode_buf[i].invalid = true; 1574 } 1575 1576 return 0; 1577 } 1578 1579 static u32 dw_dp_get_output_bus_fmts(struct dw_dp *dp, struct hdmi_edid_data *edid_data) 1580 { 1581 struct dw_dp_link *link = &dp->link; 1582 unsigned int i; 1583 1584 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 1585 const struct dw_dp_output_format *fmt = &possible_output_fmts[i]; 1586 1587 if (fmt->bpc > edid_data->display_info.bpc) 1588 continue; 1589 1590 if (!(edid_data->display_info.color_formats & fmt->color_format)) 1591 continue; 1592 1593 if (fmt->color_format == DRM_COLOR_FORMAT_YCRCB420 && 1594 !link->vsc_sdp_extension_for_colorimetry_supported) 1595 continue; 1596 1597 if (drm_mode_is_420(&edid_data->display_info, edid_data->preferred_mode) && 1598 fmt->color_format != DRM_COLOR_FORMAT_YCRCB420) 1599 continue; 1600 1601 if (!dw_dp_bandwidth_ok(dp, edid_data->preferred_mode, fmt->bpp, link->lanes, 1602 link->rate)) 1603 continue; 1604 1605 break; 1606 } 1607 1608 if (i == ARRAY_SIZE(possible_output_fmts)) 1609 return 1; 1610 1611 return i; 1612 } 1613 1614 static int dw_dp_connector_get_timing(struct display_state *state) 1615 { 1616 int ret, i; 1617 struct connector_state *conn_state = &state->conn_state; 1618 struct dw_dp *dp = dev_get_priv(conn_state->dev); 1619 struct drm_display_mode *mode = &conn_state->mode; 1620 struct hdmi_edid_data edid_data; 1621 struct drm_display_mode *mode_buf; 1622 u32 bus_fmt; 1623 1624 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 1625 if (!mode_buf) 1626 return -ENOMEM; 1627 1628 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 1629 memset(&edid_data, 0, sizeof(struct hdmi_edid_data)); 1630 edid_data.mode_buf = mode_buf; 1631 1632 if (!dp->force_output) { 1633 ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); 1634 if (!ret) 1635 ret = drm_add_edid_modes(&edid_data, conn_state->edid); 1636 1637 if (ret < 0) { 1638 printf("failed to get edid\n"); 1639 goto err; 1640 } 1641 1642 drm_rk_filter_whitelist(&edid_data); 1643 drm_mode_max_resolution_filter(&edid_data, 1644 &state->crtc_state.max_output); 1645 dw_dp_mode_valid(dp, &edid_data); 1646 1647 if (!drm_mode_prune_invalid(&edid_data)) { 1648 printf("can't find valid hdmi mode\n"); 1649 ret = -EINVAL; 1650 goto err; 1651 } 1652 1653 for (i = 0; i < edid_data.modes; i++) 1654 edid_data.mode_buf[i].vrefresh = 1655 drm_mode_vrefresh(&edid_data.mode_buf[i]); 1656 1657 drm_mode_sort(&edid_data); 1658 memcpy(mode, edid_data.preferred_mode, sizeof(struct drm_display_mode)); 1659 } 1660 1661 if (state->force_output) 1662 bus_fmt = dw_dp_get_output_fmts_index(state->force_bus_format); 1663 else 1664 bus_fmt = dw_dp_get_output_bus_fmts(dp, &edid_data); 1665 1666 conn_state->bus_format = possible_output_fmts[bus_fmt].bus_format; 1667 1668 switch (possible_output_fmts[bus_fmt].color_format) { 1669 case DRM_COLOR_FORMAT_YCRCB420: 1670 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420; 1671 break; 1672 case DRM_COLOR_FORMAT_YCRCB422: 1673 conn_state->output_mode = ROCKCHIP_OUT_MODE_S888_DUMMY; 1674 break; 1675 case DRM_COLOR_FORMAT_RGB444: 1676 case DRM_COLOR_FORMAT_YCRCB444: 1677 default: 1678 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1679 break; 1680 } 1681 1682 err: 1683 free(mode_buf); 1684 1685 return 0; 1686 } 1687 1688 static const struct rockchip_connector_funcs dw_dp_connector_funcs = { 1689 .pre_init = dw_dp_connector_pre_init, 1690 .init = dw_dp_connector_init, 1691 .get_edid = dw_dp_connector_get_edid, 1692 .prepare = dw_dp_connector_prepare, 1693 .enable = dw_dp_connector_enable, 1694 .disable = dw_dp_connector_disable, 1695 .detect = dw_dp_connector_detect, 1696 .get_timing = dw_dp_connector_get_timing, 1697 }; 1698 1699 static int dw_dp_ddc_init(struct dw_dp *dp) 1700 { 1701 dp->aux.name = "dw-dp"; 1702 dp->aux.dev = dp->dev; 1703 dp->aux.transfer = dw_dp_aux_transfer; 1704 dp->aux.ddc.ddc_xfer = drm_dp_i2c_xfer; 1705 1706 return 0; 1707 } 1708 1709 static int dw_dp_probe(struct udevice *dev) 1710 { 1711 struct dw_dp *dp = dev_get_priv(dev); 1712 int ret; 1713 1714 ret = regmap_init_mem(dev, &dp->regmap); 1715 if (ret) 1716 return ret; 1717 1718 dp->id = of_alias_get_id(ofnode_to_np(dev->node), "dp"); 1719 if (dp->id < 0) 1720 dp->id = 0; 1721 1722 ret = reset_get_by_index(dev, 0, &dp->reset); 1723 if (ret) { 1724 dev_err(dev, "failed to get reset control: %d\n", ret); 1725 return ret; 1726 } 1727 1728 dp->force_hpd = dev_read_bool(dev, "force-hpd"); 1729 1730 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 1731 GPIOD_IS_IN); 1732 if (ret && ret != -ENOENT) { 1733 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 1734 return ret; 1735 } 1736 1737 generic_phy_get_by_index(dev, 0, &dp->phy); 1738 1739 dp->dev = dev; 1740 1741 dw_dp_ddc_init(dp); 1742 1743 return 0; 1744 } 1745 1746 static const struct rockchip_connector rk3588_dp_driver_data = { 1747 .funcs = &dw_dp_connector_funcs, 1748 }; 1749 1750 static const struct udevice_id dw_dp_ids[] = { 1751 { 1752 .compatible = "rockchip,rk3588-dp", 1753 .data = (ulong)&rk3588_dp_driver_data 1754 }, 1755 {} 1756 }; 1757 1758 U_BOOT_DRIVER(dw_dp) = { 1759 .name = "dw_dp", 1760 .id = UCLASS_DISPLAY, 1761 .of_match = dw_dp_ids, 1762 .probe = dw_dp_probe, 1763 .priv_auto_alloc_size = sizeof(struct dw_dp), 1764 }; 1765 1766