1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Rockchip USBDP Combo PHY with Samsung IP block driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd 6 */ 7 8 #include <config.h> 9 #include <common.h> 10 #include <errno.h> 11 #include <malloc.h> 12 #include <asm/unaligned.h> 13 #include <asm/io.h> 14 #include <clk.h> 15 #include <dm/device.h> 16 #include <dm/of_access.h> 17 #include <dm/read.h> 18 #include <generic-phy.h> 19 #include <linux/bitfield.h> 20 #include <linux/hdmi.h> 21 #include <linux/media-bus-format.h> 22 #include <linux/list.h> 23 #include <asm/gpio.h> 24 #include <generic-phy.h> 25 #include <regmap.h> 26 #include <reset.h> 27 #include <drm/drm_dp_helper.h> 28 29 #include "rockchip_display.h" 30 #include "rockchip_crtc.h" 31 #include "rockchip_connector.h" 32 33 #define DPTX_VERSION_NUMBER 0x0000 34 #define DPTX_VERSION_TYPE 0x0004 35 #define DPTX_ID 0x0008 36 37 #define DPTX_CONFIG_REG1 0x0100 38 #define DPTX_CONFIG_REG2 0x0104 39 #define DPTX_CONFIG_REG3 0x0108 40 41 #define DPTX_CCTL 0x0200 42 #define FORCE_HPD BIT(4) 43 #define DEFAULT_FAST_LINK_TRAIN_EN BIT(2) 44 #define ENHANCE_FRAMING_EN BIT(1) 45 #define SCRAMBLE_DIS BIT(0) 46 #define DPTX_SOFT_RESET_CTRL 0x0204 47 #define VIDEO_RESET BIT(5) 48 #define AUX_RESET BIT(4) 49 #define AUDIO_SAMPLER_RESET BIT(3) 50 #define PHY_SOFT_RESET BIT(1) 51 #define CONTROLLER_RESET BIT(0) 52 53 #define DPTX_VSAMPLE_CTRL 0x0300 54 #define PIXEL_MODE_SELECT GENMASK(22, 21) 55 #define VIDEO_MAPPING GENMASK(20, 16) 56 #define VIDEO_STREAM_ENABLE BIT(5) 57 #define DPTX_VSAMPLE_STUFF_CTRL1 0x0304 58 #define DPTX_VSAMPLE_STUFF_CTRL2 0x0308 59 #define DPTX_VINPUT_POLARITY_CTRL 0x030c 60 #define DE_IN_POLARITY BIT(2) 61 #define HSYNC_IN_POLARITY BIT(1) 62 #define VSYNC_IN_POLARITY BIT(0) 63 #define DPTX_VIDEO_CONFIG1 0x0310 64 #define HACTIVE GENMASK(31, 16) 65 #define HBLANK GENMASK(15, 2) 66 #define I_P BIT(1) 67 #define R_V_BLANK_IN_OSC BIT(0) 68 #define DPTX_VIDEO_CONFIG2 0x0314 69 #define VBLANK GENMASK(31, 16) 70 #define VACTIVE GENMASK(15, 0) 71 #define DPTX_VIDEO_CONFIG3 0x0318 72 #define H_SYNC_WIDTH GENMASK(31, 16) 73 #define H_FRONT_PORCH GENMASK(15, 0) 74 #define DPTX_VIDEO_CONFIG4 0x031c 75 #define V_SYNC_WIDTH GENMASK(31, 16) 76 #define V_FRONT_PORCH GENMASK(15, 0) 77 #define DPTX_VIDEO_CONFIG5 0x0320 78 #define INIT_THRESHOLD_HI GENMASK(22, 21) 79 #define AVERAGE_BYTES_PER_TU_FRAC GENMASK(19, 16) 80 #define INIT_THRESHOLD GENMASK(13, 7) 81 #define AVERAGE_BYTES_PER_TU GENMASK(6, 0) 82 #define DPTX_VIDEO_MSA1 0x0324 83 #define VSTART GENMASK(31, 16) 84 #define HSTART GENMASK(15, 0) 85 #define DPTX_VIDEO_MSA2 0x0328 86 #define MISC0 GENMASK(31, 24) 87 #define DPTX_VIDEO_MSA3 0x032c 88 #define MISC1 GENMASK(31, 24) 89 #define DPTX_VIDEO_HBLANK_INTERVAL 0x0330 90 #define HBLANK_INTERVAL_EN BIT(16) 91 #define HBLANK_INTERVAL GENMASK(15, 0) 92 93 #define DPTX_AUD_CONFIG1 0x0400 94 #define AUDIO_TIMESTAMP_VERSION_NUM GENMASK(29, 24) 95 #define AUDIO_PACKET_ID GENMASK(23, 16) 96 #define AUDIO_MUTE BIT(15) 97 #define NUM_CHANNELS GENMASK(14, 12) 98 #define HBR_MODE_ENABLE BIT(10) 99 #define AUDIO_DATA_WIDTH GENMASK(9, 5) 100 #define AUDIO_DATA_IN_EN GENMASK(4, 1) 101 #define AUDIO_INF_SELECT BIT(0) 102 103 #define DPTX_SDP_VERTICAL_CTRL 0x0500 104 #define EN_VERTICAL_SDP BIT(2) 105 #define EN_AUDIO_STREAM_SDP BIT(1) 106 #define EN_AUDIO_TIMESTAMP_SDP BIT(0) 107 #define DPTX_SDP_HORIZONTAL_CTRL 0x0504 108 #define EN_HORIZONTAL_SDP BIT(2) 109 #define DPTX_SDP_STATUS_REGISTER 0x0508 110 #define DPTX_SDP_MANUAL_CTRL 0x050c 111 #define DPTX_SDP_STATUS_EN 0x0510 112 113 #define DPTX_SDP_REGISTER_BANK 0x0600 114 #define SDP_REGS GENMASK(31, 0) 115 116 #define DPTX_PHYIF_CTRL 0x0a00 117 #define PHY_WIDTH BIT(25) 118 #define PHY_POWERDOWN GENMASK(20, 17) 119 #define PHY_BUSY GENMASK(15, 12) 120 #define SSC_DIS BIT(16) 121 #define XMIT_ENABLE GENMASK(11, 8) 122 #define PHY_LANES GENMASK(7, 6) 123 #define PHY_RATE GENMASK(5, 4) 124 #define TPS_SEL GENMASK(3, 0) 125 #define DPTX_PHY_TX_EQ 0x0a04 126 #define DPTX_CUSTOMPAT0 0x0a08 127 #define DPTX_CUSTOMPAT1 0x0a0c 128 #define DPTX_CUSTOMPAT2 0x0a10 129 #define DPTX_HBR2_COMPLIANCE_SCRAMBLER_RESET 0x0a14 130 #define DPTX_PHYIF_PWRDOWN_CTRL 0x0a18 131 132 #define DPTX_AUX_CMD 0x0b00 133 #define AUX_CMD_TYPE GENMASK(31, 28) 134 #define AUX_ADDR GENMASK(27, 8) 135 #define I2C_ADDR_ONLY BIT(4) 136 #define AUX_LEN_REQ GENMASK(3, 0) 137 #define DPTX_AUX_STATUS 0x0b04 138 #define AUX_TIMEOUT BIT(17) 139 #define AUX_BYTES_READ GENMASK(23, 19) 140 #define AUX_STATUS GENMASK(7, 4) 141 #define DPTX_AUX_DATA0 0x0b08 142 #define DPTX_AUX_DATA1 0x0b0c 143 #define DPTX_AUX_DATA2 0x0b10 144 #define DPTX_AUX_DATA3 0x0b14 145 146 #define DPTX_GENERAL_INTERRUPT 0x0d00 147 #define VIDEO_FIFO_OVERFLOW_STREAM0 BIT(6) 148 #define AUDIO_FIFO_OVERFLOW_STREAM0 BIT(5) 149 #define SDP_EVENT_STREAM0 BIT(4) 150 #define AUX_CMD_INVALID BIT(3) 151 #define AUX_REPLY_EVENT BIT(1) 152 #define HPD_EVENT BIT(0) 153 #define DPTX_GENERAL_INTERRUPT_ENABLE 0x0d04 154 #define AUX_REPLY_EVENT_EN BIT(1) 155 #define HPD_EVENT_EN BIT(0) 156 #define DPTX_HPD_STATUS 0x0d08 157 #define HPD_STATE GENMASK(11, 9) 158 #define HPD_STATUS BIT(8) 159 #define HPD_HOT_UNPLUG BIT(2) 160 #define HPD_HOT_PLUG BIT(1) 161 #define HPD_IRQ BIT(0) 162 #define DPTX_HPD_INTERRUPT_ENABLE 0x0d0c 163 #define HPD_UNPLUG_ERR_EN BIT(3) 164 #define HPD_UNPLUG_EN BIT(2) 165 #define HPD_PLUG_EN BIT(1) 166 #define HPD_IRQ_EN BIT(0) 167 168 #define DPTX_MAX_REGISTER DPTX_HPD_INTERRUPT_ENABLE 169 170 #define SDP_REG_BANK_SIZE 16 171 172 struct drm_dp_link_caps { 173 bool enhanced_framing; 174 bool tps3_supported; 175 bool tps4_supported; 176 bool channel_coding; 177 bool ssc; 178 }; 179 180 struct drm_dp_link_train_set { 181 unsigned int voltage_swing[4]; 182 unsigned int pre_emphasis[4]; 183 }; 184 185 struct drm_dp_link_train { 186 struct drm_dp_link_train_set request; 187 struct drm_dp_link_train_set adjust; 188 bool clock_recovered; 189 bool channel_equalized; 190 }; 191 192 struct dw_dp_link { 193 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 194 unsigned char revision; 195 unsigned int rate; 196 unsigned int lanes; 197 struct drm_dp_link_caps caps; 198 struct drm_dp_link_train train; 199 u8 sink_count; 200 u8 vsc_sdp_extension_for_colorimetry_supported; 201 }; 202 203 struct dw_dp_video { 204 struct drm_display_mode mode; 205 u32 bus_format; 206 u8 video_mapping; 207 u8 pixel_mode; 208 u8 color_format; 209 u8 bpc; 210 u8 bpp; 211 }; 212 213 struct dw_dp_sdp { 214 struct dp_sdp_header header; 215 u8 db[32]; 216 unsigned long flags; 217 }; 218 219 struct dw_dp_chip_data { 220 int pixel_mode; 221 }; 222 223 struct dw_dp { 224 struct rockchip_connector connector; 225 struct udevice *dev; 226 struct regmap *regmap; 227 struct phy phy; 228 struct reset_ctl reset; 229 int id; 230 231 struct gpio_desc hpd_gpio; 232 struct drm_dp_aux aux; 233 struct dw_dp_link link; 234 struct dw_dp_video video; 235 236 bool force_hpd; 237 bool force_output; 238 u32 max_link_rate; 239 }; 240 241 enum { 242 SOURCE_STATE_IDLE, 243 SOURCE_STATE_UNPLUG, 244 SOURCE_STATE_HPD_TIMEOUT = 4, 245 SOURCE_STATE_PLUG = 7 246 }; 247 248 enum { 249 DPTX_VM_RGB_6BIT, 250 DPTX_VM_RGB_8BIT, 251 DPTX_VM_RGB_10BIT, 252 DPTX_VM_RGB_12BIT, 253 DPTX_VM_RGB_16BIT, 254 DPTX_VM_YCBCR444_8BIT, 255 DPTX_VM_YCBCR444_10BIT, 256 DPTX_VM_YCBCR444_12BIT, 257 DPTX_VM_YCBCR444_16BIT, 258 DPTX_VM_YCBCR422_8BIT, 259 DPTX_VM_YCBCR422_10BIT, 260 DPTX_VM_YCBCR422_12BIT, 261 DPTX_VM_YCBCR422_16BIT, 262 DPTX_VM_YCBCR420_8BIT, 263 DPTX_VM_YCBCR420_10BIT, 264 DPTX_VM_YCBCR420_12BIT, 265 DPTX_VM_YCBCR420_16BIT, 266 }; 267 268 enum { 269 DPTX_MP_SINGLE_PIXEL, 270 DPTX_MP_DUAL_PIXEL, 271 DPTX_MP_QUAD_PIXEL, 272 }; 273 274 enum { 275 DPTX_SDP_VERTICAL_INTERVAL = BIT(0), 276 DPTX_SDP_HORIZONTAL_INTERVAL = BIT(1), 277 }; 278 279 enum { 280 DPTX_PHY_PATTERN_NONE, 281 DPTX_PHY_PATTERN_TPS_1, 282 DPTX_PHY_PATTERN_TPS_2, 283 DPTX_PHY_PATTERN_TPS_3, 284 DPTX_PHY_PATTERN_TPS_4, 285 DPTX_PHY_PATTERN_SERM, 286 DPTX_PHY_PATTERN_PBRS7, 287 DPTX_PHY_PATTERN_CUSTOM_80BIT, 288 DPTX_PHY_PATTERN_CP2520_1, 289 DPTX_PHY_PATTERN_CP2520_2, 290 }; 291 292 enum { 293 DPTX_PHYRATE_RBR, 294 DPTX_PHYRATE_HBR, 295 DPTX_PHYRATE_HBR2, 296 DPTX_PHYRATE_HBR3, 297 }; 298 299 struct dw_dp_output_format { 300 u32 bus_format; 301 u32 color_format; 302 u8 video_mapping; 303 u8 bpc; 304 u8 bpp; 305 }; 306 307 static const struct dw_dp_output_format possible_output_fmts[] = { 308 { MEDIA_BUS_FMT_RGB101010_1X30, DRM_COLOR_FORMAT_RGB444, 309 DPTX_VM_RGB_10BIT, 10, 30 }, 310 { MEDIA_BUS_FMT_RGB888_1X24, DRM_COLOR_FORMAT_RGB444, 311 DPTX_VM_RGB_8BIT, 8, 24 }, 312 { MEDIA_BUS_FMT_YUV10_1X30, DRM_COLOR_FORMAT_YCRCB444, 313 DPTX_VM_YCBCR444_10BIT, 10, 30 }, 314 { MEDIA_BUS_FMT_YUV8_1X24, DRM_COLOR_FORMAT_YCRCB444, 315 DPTX_VM_YCBCR444_8BIT, 8, 24}, 316 { MEDIA_BUS_FMT_YUYV10_1X20, DRM_COLOR_FORMAT_YCRCB422, 317 DPTX_VM_YCBCR422_10BIT, 10, 20 }, 318 { MEDIA_BUS_FMT_YUYV8_1X16, DRM_COLOR_FORMAT_YCRCB422, 319 DPTX_VM_YCBCR422_8BIT, 8, 16 }, 320 { MEDIA_BUS_FMT_UYYVYY10_0_5X30, DRM_COLOR_FORMAT_YCRCB420, 321 DPTX_VM_YCBCR420_10BIT, 10, 15 }, 322 { MEDIA_BUS_FMT_UYYVYY8_0_5X24, DRM_COLOR_FORMAT_YCRCB420, 323 DPTX_VM_YCBCR420_8BIT, 8, 12 }, 324 { MEDIA_BUS_FMT_RGB666_1X24_CPADHI, DRM_COLOR_FORMAT_RGB444, 325 DPTX_VM_RGB_6BIT, 6, 18 }, 326 }; 327 328 static int dw_dp_aux_write_data(struct dw_dp *dp, const u8 *buffer, size_t size) 329 { 330 size_t i, j; 331 332 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 333 size_t num = min_t(size_t, size - i * 4, 4); 334 u32 value = 0; 335 336 for (j = 0; j < num; j++) 337 value |= buffer[i * 4 + j] << (j * 8); 338 339 regmap_write(dp->regmap, DPTX_AUX_DATA0 + i * 4, value); 340 } 341 342 return size; 343 } 344 345 static int dw_dp_aux_read_data(struct dw_dp *dp, u8 *buffer, size_t size) 346 { 347 size_t i, j; 348 349 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 350 size_t num = min_t(size_t, size - i * 4, 4); 351 u32 value; 352 353 regmap_read(dp->regmap, DPTX_AUX_DATA0 + i * 4, &value); 354 355 for (j = 0; j < num; j++) 356 buffer[i * 4 + j] = value >> (j * 8); 357 } 358 359 return size; 360 } 361 362 static ssize_t dw_dp_aux_transfer(struct drm_dp_aux *aux, 363 struct drm_dp_aux_msg *msg) 364 { 365 u32 status, value; 366 ssize_t ret = 0; 367 int timeout = 0; 368 struct dw_dp *dp = dev_get_priv(aux->dev); 369 370 if (WARN_ON(msg->size > 16)) 371 return -E2BIG; 372 373 switch (msg->request & ~DP_AUX_I2C_MOT) { 374 case DP_AUX_NATIVE_WRITE: 375 case DP_AUX_I2C_WRITE: 376 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 377 ret = dw_dp_aux_write_data(dp, msg->buffer, msg->size); 378 if (ret < 0) 379 return ret; 380 break; 381 case DP_AUX_NATIVE_READ: 382 case DP_AUX_I2C_READ: 383 break; 384 default: 385 return -EINVAL; 386 } 387 388 if (msg->size > 0) 389 value = FIELD_PREP(AUX_LEN_REQ, msg->size - 1); 390 else 391 value = FIELD_PREP(I2C_ADDR_ONLY, 1); 392 393 value |= FIELD_PREP(AUX_CMD_TYPE, msg->request); 394 value |= FIELD_PREP(AUX_ADDR, msg->address); 395 regmap_write(dp->regmap, DPTX_AUX_CMD, value); 396 397 timeout = regmap_read_poll_timeout(dp->regmap, DPTX_GENERAL_INTERRUPT, 398 status, status & AUX_REPLY_EVENT, 399 200, 10); 400 401 if (timeout) { 402 printf("timeout waiting for AUX reply\n"); 403 return -ETIMEDOUT; 404 } 405 regmap_write(dp->regmap, DPTX_GENERAL_INTERRUPT, AUX_REPLY_EVENT); 406 407 regmap_read(dp->regmap, DPTX_AUX_STATUS, &value); 408 if (value & AUX_TIMEOUT) { 409 printf("aux timeout\n"); 410 return -ETIMEDOUT; 411 } 412 413 msg->reply = FIELD_GET(AUX_STATUS, value); 414 415 if (msg->size > 0 && msg->reply == DP_AUX_NATIVE_REPLY_ACK) { 416 if (msg->request & DP_AUX_I2C_READ) { 417 size_t count = FIELD_GET(AUX_BYTES_READ, value) - 1; 418 419 if (count != msg->size) { 420 printf("aux fail to read %lu bytes\n", count); 421 return -EBUSY; 422 } 423 424 ret = dw_dp_aux_read_data(dp, msg->buffer, count); 425 if (ret < 0) 426 return ret; 427 } 428 } 429 430 return ret; 431 } 432 433 static bool dw_dp_bandwidth_ok(struct dw_dp *dp, 434 const struct drm_display_mode *mode, u32 bpp, 435 unsigned int lanes, unsigned int rate) 436 { 437 u32 max_bw, req_bw; 438 439 req_bw = mode->clock * bpp / 8; 440 max_bw = lanes * rate; 441 if (req_bw > max_bw) 442 return false; 443 444 return true; 445 } 446 447 static void dw_dp_hpd_init(struct dw_dp *dp) 448 { 449 if (dm_gpio_is_valid(&dp->hpd_gpio) || dp->force_hpd) { 450 regmap_update_bits(dp->regmap, DPTX_CCTL, FORCE_HPD, 451 FIELD_PREP(FORCE_HPD, 1)); 452 return; 453 } 454 455 /* Enable all HPD interrupts */ 456 regmap_update_bits(dp->regmap, DPTX_HPD_INTERRUPT_ENABLE, 457 HPD_UNPLUG_EN | HPD_PLUG_EN | HPD_IRQ_EN, 458 FIELD_PREP(HPD_UNPLUG_EN, 1) | 459 FIELD_PREP(HPD_PLUG_EN, 1) | 460 FIELD_PREP(HPD_IRQ_EN, 1)); 461 462 /* Enable all top-level interrupts */ 463 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, 464 HPD_EVENT_EN, FIELD_PREP(HPD_EVENT_EN, 1)); 465 } 466 467 static void dw_dp_aux_init(struct dw_dp *dp) 468 { 469 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, 470 FIELD_PREP(AUX_RESET, 1)); 471 udelay(10); 472 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, 473 FIELD_PREP(AUX_RESET, 0)); 474 475 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, 476 AUX_REPLY_EVENT_EN, 477 FIELD_PREP(AUX_REPLY_EVENT_EN, 1)); 478 } 479 480 static void dw_dp_init(struct dw_dp *dp) 481 { 482 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, 483 FIELD_PREP(CONTROLLER_RESET, 1)); 484 udelay(10); 485 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, 486 FIELD_PREP(CONTROLLER_RESET, 0)); 487 488 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, 489 FIELD_PREP(PHY_SOFT_RESET, 1)); 490 udelay(10); 491 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, 492 FIELD_PREP(PHY_SOFT_RESET, 0)); 493 494 regmap_update_bits(dp->regmap, DPTX_CCTL, DEFAULT_FAST_LINK_TRAIN_EN, 495 FIELD_PREP(DEFAULT_FAST_LINK_TRAIN_EN, 0)); 496 497 dw_dp_hpd_init(dp); 498 dw_dp_aux_init(dp); 499 } 500 501 static void dw_dp_phy_set_pattern(struct dw_dp *dp, u32 pattern) 502 { 503 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, TPS_SEL, 504 FIELD_PREP(TPS_SEL, pattern)); 505 } 506 507 static void dw_dp_phy_xmit_enable(struct dw_dp *dp, u32 lanes) 508 { 509 u32 xmit_enable; 510 511 switch (lanes) { 512 case 4: 513 case 2: 514 case 1: 515 xmit_enable = GENMASK(lanes - 1, 0); 516 break; 517 case 0: 518 default: 519 xmit_enable = 0; 520 break; 521 } 522 523 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, XMIT_ENABLE, 524 FIELD_PREP(XMIT_ENABLE, xmit_enable)); 525 } 526 527 static int dw_dp_link_power_up(struct dw_dp *dp) 528 { 529 struct dw_dp_link *link = &dp->link; 530 u8 value; 531 int ret; 532 533 if (link->revision < 0x11) 534 return 0; 535 536 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value); 537 if (ret < 0) 538 return ret; 539 540 value &= ~DP_SET_POWER_MASK; 541 value |= DP_SET_POWER_D0; 542 543 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value); 544 if (ret < 0) 545 return ret; 546 547 udelay(1000); 548 return 0; 549 } 550 551 static int dw_dp_link_probe(struct dw_dp *dp) 552 { 553 struct dw_dp_link *link = &dp->link; 554 u8 dpcd; 555 int ret; 556 557 ret = drm_dp_read_dpcd_caps(&dp->aux, link->dpcd); 558 if (ret < 0) 559 return ret; 560 561 ret = drm_dp_dpcd_readb(&dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, 562 &dpcd); 563 if (ret < 0) 564 return ret; 565 566 link->vsc_sdp_extension_for_colorimetry_supported = 567 !!(dpcd & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED); 568 569 link->revision = link->dpcd[DP_DPCD_REV]; 570 link->rate = min_t(u32, min(dp->max_link_rate, dp->phy.attrs.max_link_rate * 100), 571 drm_dp_max_link_rate(link->dpcd)); 572 link->lanes = min_t(u8, dp->phy.attrs.bus_width, 573 drm_dp_max_lane_count(link->dpcd)); 574 575 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(link->dpcd); 576 link->caps.tps3_supported = drm_dp_tps3_supported(link->dpcd); 577 link->caps.tps4_supported = drm_dp_tps4_supported(link->dpcd); 578 link->caps.channel_coding = drm_dp_channel_coding_supported(link->dpcd); 579 link->caps.ssc = !!(link->dpcd[DP_MAX_DOWNSPREAD] & 580 DP_MAX_DOWNSPREAD_0_5); 581 582 return 0; 583 } 584 585 static int dw_dp_link_train_update_vs_emph(struct dw_dp *dp) 586 { 587 struct dw_dp_link *link = &dp->link; 588 struct drm_dp_link_train_set *request = &link->train.request; 589 union phy_configure_opts phy_cfg; 590 unsigned int lanes = link->lanes, *vs, *pe; 591 u8 buf[4]; 592 int i, ret; 593 594 vs = request->voltage_swing; 595 pe = request->pre_emphasis; 596 597 for (i = 0; i < lanes; i++) { 598 phy_cfg.dp.voltage[i] = vs[i]; 599 phy_cfg.dp.pre[i] = pe[i]; 600 } 601 phy_cfg.dp.lanes = lanes; 602 phy_cfg.dp.link_rate = link->rate / 100; 603 phy_cfg.dp.set_lanes = false; 604 phy_cfg.dp.set_rate = false; 605 phy_cfg.dp.set_voltages = true; 606 ret = generic_phy_configure(&dp->phy, &phy_cfg); 607 if (ret) 608 return ret; 609 610 for (i = 0; i < lanes; i++) 611 buf[i] = (vs[i] << DP_TRAIN_VOLTAGE_SWING_SHIFT) | 612 (pe[i] << DP_TRAIN_PRE_EMPHASIS_SHIFT); 613 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, lanes); 614 if (ret < 0) 615 return ret; 616 617 return 0; 618 } 619 620 static int dw_dp_link_configure(struct dw_dp *dp) 621 { 622 struct dw_dp_link *link = &dp->link; 623 union phy_configure_opts phy_cfg; 624 u8 buf[2]; 625 int ret, phy_rate; 626 627 /* Move PHY to P3 */ 628 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 629 FIELD_PREP(PHY_POWERDOWN, 0x3)); 630 631 phy_cfg.dp.lanes = link->lanes; 632 phy_cfg.dp.link_rate = link->rate / 100; 633 phy_cfg.dp.ssc = link->caps.ssc; 634 phy_cfg.dp.set_lanes = true; 635 phy_cfg.dp.set_rate = true; 636 phy_cfg.dp.set_voltages = false; 637 ret = generic_phy_configure(&dp->phy, &phy_cfg); 638 if (ret) 639 return ret; 640 641 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, 642 FIELD_PREP(PHY_LANES, link->lanes / 2)); 643 644 switch (link->rate) { 645 case 810000: 646 phy_rate = DPTX_PHYRATE_HBR3; 647 break; 648 case 540000: 649 phy_rate = DPTX_PHYRATE_HBR2; 650 break; 651 case 270000: 652 phy_rate = DPTX_PHYRATE_HBR; 653 break; 654 case 162000: 655 default: 656 phy_rate = DPTX_PHYRATE_RBR; 657 break; 658 } 659 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_RATE, 660 FIELD_PREP(PHY_RATE, phy_rate)); 661 662 /* Move PHY to P0 */ 663 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 664 FIELD_PREP(PHY_POWERDOWN, 0x0)); 665 666 dw_dp_phy_xmit_enable(dp, link->lanes); 667 668 buf[0] = drm_dp_link_rate_to_bw_code(link->rate); 669 buf[1] = link->lanes; 670 671 if (link->caps.enhanced_framing) { 672 buf[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 673 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 674 FIELD_PREP(ENHANCE_FRAMING_EN, 1)); 675 } else { 676 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 677 FIELD_PREP(ENHANCE_FRAMING_EN, 0)); 678 } 679 680 ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, sizeof(buf)); 681 if (ret < 0) 682 return ret; 683 684 buf[0] = link->caps.ssc ? DP_SPREAD_AMP_0_5 : 0; 685 buf[1] = link->caps.channel_coding ? DP_SET_ANSI_8B10B : 0; 686 687 ret = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, 688 sizeof(buf)); 689 if (ret < 0) 690 return ret; 691 692 return 0; 693 } 694 695 static void dw_dp_link_train_init(struct drm_dp_link_train *train) 696 { 697 struct drm_dp_link_train_set *request = &train->request; 698 struct drm_dp_link_train_set *adjust = &train->adjust; 699 unsigned int i; 700 701 for (i = 0; i < 4; i++) { 702 request->voltage_swing[i] = 0; 703 adjust->voltage_swing[i] = 0; 704 705 request->pre_emphasis[i] = 0; 706 adjust->pre_emphasis[i] = 0; 707 } 708 709 train->clock_recovered = false; 710 train->channel_equalized = false; 711 } 712 713 static int dw_dp_link_train_set_pattern(struct dw_dp *dp, u32 pattern) 714 { 715 u8 buf = 0; 716 int ret; 717 718 if (pattern && pattern != DP_TRAINING_PATTERN_4) { 719 buf |= DP_LINK_SCRAMBLING_DISABLE; 720 721 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, 722 FIELD_PREP(SCRAMBLE_DIS, 1)); 723 } else { 724 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, 725 FIELD_PREP(SCRAMBLE_DIS, 0)); 726 } 727 728 switch (pattern) { 729 case DP_TRAINING_PATTERN_DISABLE: 730 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE); 731 break; 732 case DP_TRAINING_PATTERN_1: 733 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_1); 734 break; 735 case DP_TRAINING_PATTERN_2: 736 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_2); 737 break; 738 case DP_TRAINING_PATTERN_3: 739 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_3); 740 break; 741 case DP_TRAINING_PATTERN_4: 742 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_4); 743 break; 744 default: 745 return -EINVAL; 746 } 747 748 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 749 buf | pattern); 750 if (ret < 0) 751 return ret; 752 753 return 0; 754 } 755 756 static void dw_dp_link_get_adjustments(struct dw_dp_link *link, 757 u8 status[DP_LINK_STATUS_SIZE]) 758 { 759 struct drm_dp_link_train_set *adjust = &link->train.adjust; 760 unsigned int i; 761 762 for (i = 0; i < link->lanes; i++) { 763 adjust->voltage_swing[i] = 764 drm_dp_get_adjust_request_voltage(status, i) >> 765 DP_TRAIN_VOLTAGE_SWING_SHIFT; 766 767 adjust->pre_emphasis[i] = 768 drm_dp_get_adjust_request_pre_emphasis(status, i) >> 769 DP_TRAIN_PRE_EMPHASIS_SHIFT; 770 } 771 } 772 773 static void dw_dp_link_train_adjust(struct drm_dp_link_train *train) 774 { 775 struct drm_dp_link_train_set *request = &train->request; 776 struct drm_dp_link_train_set *adjust = &train->adjust; 777 unsigned int i; 778 779 for (i = 0; i < 4; i++) 780 if (request->voltage_swing[i] != adjust->voltage_swing[i]) 781 request->voltage_swing[i] = adjust->voltage_swing[i]; 782 783 for (i = 0; i < 4; i++) 784 if (request->pre_emphasis[i] != adjust->pre_emphasis[i]) 785 request->pre_emphasis[i] = adjust->pre_emphasis[i]; 786 } 787 788 static int dw_dp_link_clock_recovery(struct dw_dp *dp) 789 { 790 struct dw_dp_link *link = &dp->link; 791 u8 status[DP_LINK_STATUS_SIZE]; 792 unsigned int tries = 0; 793 int ret; 794 795 ret = dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_1); 796 if (ret) 797 return ret; 798 799 for (;;) { 800 ret = dw_dp_link_train_update_vs_emph(dp); 801 if (ret) 802 return ret; 803 804 drm_dp_link_train_clock_recovery_delay(link->dpcd); 805 806 ret = drm_dp_dpcd_read_link_status(&dp->aux, status); 807 if (ret < 0) { 808 dev_err(dp->dev, "failed to read link status: %d\n", 809 ret); 810 return ret; 811 } 812 813 if (drm_dp_clock_recovery_ok(status, link->lanes)) { 814 link->train.clock_recovered = true; 815 break; 816 } 817 818 dw_dp_link_get_adjustments(link, status); 819 820 if (link->train.request.voltage_swing[0] == 821 link->train.adjust.voltage_swing[0]) 822 tries++; 823 else 824 tries = 0; 825 826 if (tries == 5) 827 break; 828 829 dw_dp_link_train_adjust(&link->train); 830 } 831 832 return 0; 833 } 834 835 static int dw_dp_link_channel_equalization(struct dw_dp *dp) 836 { 837 struct dw_dp_link *link = &dp->link; 838 u8 status[DP_LINK_STATUS_SIZE], pattern; 839 unsigned int tries; 840 int ret; 841 842 if (link->caps.tps4_supported) 843 pattern = DP_TRAINING_PATTERN_4; 844 else if (link->caps.tps3_supported) 845 pattern = DP_TRAINING_PATTERN_3; 846 else 847 pattern = DP_TRAINING_PATTERN_2; 848 ret = dw_dp_link_train_set_pattern(dp, pattern); 849 if (ret) 850 return ret; 851 852 for (tries = 1; tries < 5; tries++) { 853 ret = dw_dp_link_train_update_vs_emph(dp); 854 if (ret) 855 return ret; 856 857 drm_dp_link_train_channel_eq_delay(link->dpcd); 858 859 ret = drm_dp_dpcd_read_link_status(&dp->aux, status); 860 if (ret < 0) 861 return ret; 862 863 if (!drm_dp_clock_recovery_ok(status, link->lanes)) { 864 dev_err(dp->dev, 865 "clock recovery lost while eq\n"); 866 link->train.clock_recovered = false; 867 break; 868 } 869 870 if (drm_dp_channel_eq_ok(status, link->lanes)) { 871 link->train.channel_equalized = true; 872 break; 873 } 874 875 dw_dp_link_get_adjustments(link, status); 876 dw_dp_link_train_adjust(&link->train); 877 } 878 879 return 0; 880 } 881 882 static int dw_dp_link_downgrade(struct dw_dp *dp) 883 { 884 struct dw_dp_link *link = &dp->link; 885 struct dw_dp_video *video = &dp->video; 886 887 switch (link->rate) { 888 case 162000: 889 return -EINVAL; 890 case 270000: 891 link->rate = 162000; 892 break; 893 case 540000: 894 link->rate = 270000; 895 break; 896 case 810000: 897 link->rate = 540000; 898 break; 899 } 900 901 if (!dw_dp_bandwidth_ok(dp, &video->mode, video->bpp, link->lanes, 902 link->rate)) 903 return -E2BIG; 904 905 return 0; 906 } 907 908 static int dw_dp_link_train(struct dw_dp *dp) 909 { 910 struct dw_dp_link *link = &dp->link; 911 int ret; 912 913 retry: 914 dw_dp_link_train_init(&link->train); 915 916 printf("training link: %u lane%s at %u MHz\n", 917 link->lanes, (link->lanes > 1) ? "s" : "", link->rate / 100); 918 919 ret = dw_dp_link_configure(dp); 920 if (ret < 0) { 921 dev_err(dp->dev, "failed to configure DP link: %d\n", ret); 922 return ret; 923 } 924 925 ret = dw_dp_link_clock_recovery(dp); 926 if (ret < 0) { 927 dev_err(dp->dev, "clock recovery failed: %d\n", ret); 928 goto out; 929 } 930 931 if (!link->train.clock_recovered) { 932 dev_err(dp->dev, "clock recovery failed, downgrading link\n"); 933 934 ret = dw_dp_link_downgrade(dp); 935 if (ret < 0) 936 goto out; 937 else 938 goto retry; 939 } 940 941 printf("clock recovery succeeded\n"); 942 943 ret = dw_dp_link_channel_equalization(dp); 944 if (ret < 0) { 945 dev_err(dp->dev, "channel equalization failed: %d\n", ret); 946 goto out; 947 } 948 949 if (!link->train.channel_equalized) { 950 dev_err(dp->dev, 951 "channel equalization failed, downgrading link\n"); 952 953 ret = dw_dp_link_downgrade(dp); 954 if (ret < 0) 955 goto out; 956 else 957 goto retry; 958 } 959 960 printf("channel equalization succeeded\n"); 961 962 out: 963 dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE); 964 return ret; 965 } 966 967 static int dw_dp_link_enable(struct dw_dp *dp) 968 { 969 int ret; 970 971 ret = dw_dp_link_power_up(dp); 972 if (ret < 0) 973 return ret; 974 975 ret = dw_dp_link_train(dp); 976 if (ret < 0) { 977 dev_err(dp->dev, "link training failed: %d\n", ret); 978 return ret; 979 } 980 981 return 0; 982 } 983 984 static int dw_dp_set_phy_default_config(struct dw_dp *dp) 985 { 986 struct dw_dp_link *link = &dp->link; 987 union phy_configure_opts phy_cfg; 988 int ret, i, phy_rate; 989 990 link->vsc_sdp_extension_for_colorimetry_supported = false; 991 link->rate = 270000; 992 link->lanes = dp->phy.attrs.bus_width; 993 994 link->caps.enhanced_framing = true; 995 link->caps.channel_coding = true; 996 link->caps.ssc = true; 997 998 /* Move PHY to P3 */ 999 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 1000 FIELD_PREP(PHY_POWERDOWN, 0x3)); 1001 1002 for (i = 0; i < link->lanes; i++) { 1003 phy_cfg.dp.voltage[i] = 3; 1004 phy_cfg.dp.pre[i] = 0; 1005 } 1006 phy_cfg.dp.lanes = link->lanes; 1007 phy_cfg.dp.link_rate = link->rate / 100; 1008 phy_cfg.dp.ssc = link->caps.ssc; 1009 phy_cfg.dp.set_lanes = true; 1010 phy_cfg.dp.set_rate = true; 1011 phy_cfg.dp.set_voltages = true; 1012 ret = generic_phy_configure(&dp->phy, &phy_cfg); 1013 if (ret) 1014 return ret; 1015 1016 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, 1017 FIELD_PREP(PHY_LANES, link->lanes / 2)); 1018 1019 switch (link->rate) { 1020 case 810000: 1021 phy_rate = DPTX_PHYRATE_HBR3; 1022 break; 1023 case 540000: 1024 phy_rate = DPTX_PHYRATE_HBR2; 1025 break; 1026 case 270000: 1027 phy_rate = DPTX_PHYRATE_HBR; 1028 break; 1029 case 162000: 1030 default: 1031 phy_rate = DPTX_PHYRATE_RBR; 1032 break; 1033 } 1034 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_RATE, 1035 FIELD_PREP(PHY_RATE, phy_rate)); 1036 1037 /* Move PHY to P0 */ 1038 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 1039 FIELD_PREP(PHY_POWERDOWN, 0x0)); 1040 1041 dw_dp_phy_xmit_enable(dp, link->lanes); 1042 1043 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 1044 FIELD_PREP(ENHANCE_FRAMING_EN, 1)); 1045 1046 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE); 1047 return 0; 1048 } 1049 1050 static int dw_dp_send_sdp(struct dw_dp *dp, struct dw_dp_sdp *sdp) 1051 { 1052 const u8 *payload = sdp->db; 1053 u32 reg; 1054 int i, nr = 0; 1055 1056 reg = DPTX_SDP_REGISTER_BANK + nr * 9 * 4; 1057 1058 /* SDP header */ 1059 regmap_write(dp->regmap, reg, get_unaligned_le32(&sdp->header)); 1060 1061 /* SDP data payload */ 1062 for (i = 1; i < 9; i++, payload += 4) 1063 regmap_write(dp->regmap, reg + i * 4, 1064 FIELD_PREP(SDP_REGS, get_unaligned_le32(payload))); 1065 1066 if (sdp->flags & DPTX_SDP_VERTICAL_INTERVAL) 1067 regmap_update_bits(dp->regmap, DPTX_SDP_VERTICAL_CTRL, 1068 EN_VERTICAL_SDP << nr, 1069 EN_VERTICAL_SDP << nr); 1070 1071 if (sdp->flags & DPTX_SDP_HORIZONTAL_INTERVAL) 1072 regmap_update_bits(dp->regmap, DPTX_SDP_HORIZONTAL_CTRL, 1073 EN_HORIZONTAL_SDP << nr, 1074 EN_HORIZONTAL_SDP << nr); 1075 1076 return 0; 1077 } 1078 1079 static void dw_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, 1080 struct dw_dp_sdp *sdp) 1081 { 1082 sdp->header.HB0 = 0; 1083 sdp->header.HB1 = DP_SDP_VSC; 1084 sdp->header.HB2 = vsc->revision; 1085 sdp->header.HB3 = vsc->length; 1086 1087 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; 1088 sdp->db[16] |= vsc->colorimetry & 0xf; 1089 1090 switch (vsc->bpc) { 1091 case 8: 1092 sdp->db[17] = 0x1; 1093 break; 1094 case 10: 1095 sdp->db[17] = 0x2; 1096 break; 1097 case 12: 1098 sdp->db[17] = 0x3; 1099 break; 1100 case 16: 1101 sdp->db[17] = 0x4; 1102 break; 1103 case 6: 1104 default: 1105 break; 1106 } 1107 1108 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) 1109 sdp->db[17] |= 0x80; 1110 1111 sdp->db[18] = vsc->content_type & 0x7; 1112 1113 sdp->flags |= DPTX_SDP_VERTICAL_INTERVAL; 1114 } 1115 1116 static int dw_dp_send_vsc_sdp(struct dw_dp *dp) 1117 { 1118 struct dw_dp_video *video = &dp->video; 1119 struct drm_dp_vsc_sdp vsc = {}; 1120 struct dw_dp_sdp sdp = {}; 1121 1122 vsc.revision = 0x5; 1123 vsc.length = 0x13; 1124 1125 switch (video->color_format) { 1126 case DRM_COLOR_FORMAT_YCRCB444: 1127 vsc.pixelformat = DP_PIXELFORMAT_YUV444; 1128 break; 1129 case DRM_COLOR_FORMAT_YCRCB420: 1130 vsc.pixelformat = DP_PIXELFORMAT_YUV420; 1131 break; 1132 case DRM_COLOR_FORMAT_YCRCB422: 1133 vsc.pixelformat = DP_PIXELFORMAT_YUV422; 1134 break; 1135 case DRM_COLOR_FORMAT_RGB444: 1136 default: 1137 vsc.pixelformat = DP_PIXELFORMAT_RGB; 1138 break; 1139 } 1140 1141 if (video->color_format == DRM_COLOR_FORMAT_RGB444) 1142 vsc.colorimetry = DP_COLORIMETRY_DEFAULT; 1143 else 1144 vsc.colorimetry = DP_COLORIMETRY_BT709_YCC; 1145 1146 vsc.bpc = video->bpc; 1147 vsc.dynamic_range = DP_DYNAMIC_RANGE_CTA; 1148 vsc.content_type = DP_CONTENT_TYPE_NOT_DEFINED; 1149 1150 dw_dp_vsc_sdp_pack(&vsc, &sdp); 1151 1152 return dw_dp_send_sdp(dp, &sdp); 1153 } 1154 1155 static int dw_dp_video_set_pixel_mode(struct dw_dp *dp, u8 pixel_mode) 1156 { 1157 switch (pixel_mode) { 1158 case DPTX_MP_SINGLE_PIXEL: 1159 case DPTX_MP_DUAL_PIXEL: 1160 case DPTX_MP_QUAD_PIXEL: 1161 break; 1162 default: 1163 return -EINVAL; 1164 } 1165 1166 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, PIXEL_MODE_SELECT, 1167 FIELD_PREP(PIXEL_MODE_SELECT, pixel_mode)); 1168 1169 return 0; 1170 } 1171 1172 static int dw_dp_video_set_msa(struct dw_dp *dp, u8 color_format, u8 bpc, 1173 u16 vstart, u16 hstart) 1174 { 1175 struct dw_dp_link *link = &dp->link; 1176 u16 misc = 0; 1177 1178 if (link->vsc_sdp_extension_for_colorimetry_supported) 1179 misc |= DP_MSA_MISC_COLOR_VSC_SDP; 1180 1181 switch (color_format) { 1182 case DRM_COLOR_FORMAT_RGB444: 1183 misc |= DP_MSA_MISC_COLOR_RGB; 1184 break; 1185 case DRM_COLOR_FORMAT_YCRCB444: 1186 misc |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 1187 break; 1188 case DRM_COLOR_FORMAT_YCRCB422: 1189 misc |= DP_MSA_MISC_COLOR_YCBCR_422_BT709; 1190 break; 1191 case DRM_COLOR_FORMAT_YCRCB420: 1192 break; 1193 default: 1194 return -EINVAL; 1195 } 1196 1197 switch (bpc) { 1198 case 6: 1199 misc |= DP_MSA_MISC_6_BPC; 1200 break; 1201 case 8: 1202 misc |= DP_MSA_MISC_8_BPC; 1203 break; 1204 case 10: 1205 misc |= DP_MSA_MISC_10_BPC; 1206 break; 1207 case 12: 1208 misc |= DP_MSA_MISC_12_BPC; 1209 break; 1210 case 16: 1211 misc |= DP_MSA_MISC_16_BPC; 1212 break; 1213 default: 1214 return -EINVAL; 1215 } 1216 1217 regmap_write(dp->regmap, DPTX_VIDEO_MSA1, 1218 FIELD_PREP(VSTART, vstart) | FIELD_PREP(HSTART, hstart)); 1219 regmap_write(dp->regmap, DPTX_VIDEO_MSA2, FIELD_PREP(MISC0, misc)); 1220 regmap_write(dp->regmap, DPTX_VIDEO_MSA3, FIELD_PREP(MISC1, misc >> 8)); 1221 1222 return 0; 1223 } 1224 1225 static int dw_dp_video_enable(struct dw_dp *dp) 1226 { 1227 struct dw_dp_video *video = &dp->video; 1228 struct dw_dp_link *link = &dp->link; 1229 struct drm_display_mode *mode = &video->mode; 1230 u8 color_format = video->color_format; 1231 u8 bpc = video->bpc; 1232 u8 pixel_mode = video->pixel_mode; 1233 u8 bpp = video->bpp, init_threshold, vic; 1234 u32 hactive, hblank, h_sync_width, h_front_porch; 1235 u32 vactive, vblank, v_sync_width, v_front_porch; 1236 u32 vstart = mode->vtotal - mode->vsync_start; 1237 u32 hstart = mode->htotal - mode->hsync_start; 1238 u32 peak_stream_bandwidth, link_bandwidth; 1239 u32 average_bytes_per_tu, average_bytes_per_tu_frac; 1240 u32 ts, hblank_interval; 1241 u32 value; 1242 int ret; 1243 1244 ret = dw_dp_video_set_pixel_mode(dp, pixel_mode); 1245 if (ret) 1246 return ret; 1247 1248 ret = dw_dp_video_set_msa(dp, color_format, bpc, vstart, hstart); 1249 if (ret) 1250 return ret; 1251 1252 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_MAPPING, 1253 FIELD_PREP(VIDEO_MAPPING, video->video_mapping)); 1254 1255 /* Configure DPTX_VINPUT_POLARITY_CTRL register */ 1256 value = 0; 1257 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1258 value |= FIELD_PREP(HSYNC_IN_POLARITY, 1); 1259 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1260 value |= FIELD_PREP(VSYNC_IN_POLARITY, 1); 1261 regmap_write(dp->regmap, DPTX_VINPUT_POLARITY_CTRL, value); 1262 1263 /* Configure DPTX_VIDEO_CONFIG1 register */ 1264 hactive = mode->hdisplay; 1265 hblank = mode->htotal - mode->hdisplay; 1266 value = FIELD_PREP(HACTIVE, hactive) | FIELD_PREP(HBLANK, hblank); 1267 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1268 value |= FIELD_PREP(I_P, 1); 1269 vic = drm_match_cea_mode(mode); 1270 if (vic == 5 || vic == 6 || vic == 7 || 1271 vic == 10 || vic == 11 || vic == 20 || 1272 vic == 21 || vic == 22 || vic == 39 || 1273 vic == 25 || vic == 26 || vic == 40 || 1274 vic == 44 || vic == 45 || vic == 46 || 1275 vic == 50 || vic == 51 || vic == 54 || 1276 vic == 55 || vic == 58 || vic == 59) 1277 value |= R_V_BLANK_IN_OSC; 1278 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG1, value); 1279 1280 /* Configure DPTX_VIDEO_CONFIG2 register */ 1281 vblank = mode->vtotal - mode->vdisplay; 1282 vactive = mode->vdisplay; 1283 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG2, 1284 FIELD_PREP(VBLANK, vblank) | FIELD_PREP(VACTIVE, vactive)); 1285 1286 /* Configure DPTX_VIDEO_CONFIG3 register */ 1287 h_sync_width = mode->hsync_end - mode->hsync_start; 1288 h_front_porch = mode->hsync_start - mode->hdisplay; 1289 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG3, 1290 FIELD_PREP(H_SYNC_WIDTH, h_sync_width) | 1291 FIELD_PREP(H_FRONT_PORCH, h_front_porch)); 1292 1293 /* Configure DPTX_VIDEO_CONFIG4 register */ 1294 v_sync_width = mode->vsync_end - mode->vsync_start; 1295 v_front_porch = mode->vsync_start - mode->vdisplay; 1296 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG4, 1297 FIELD_PREP(V_SYNC_WIDTH, v_sync_width) | 1298 FIELD_PREP(V_FRONT_PORCH, v_front_porch)); 1299 1300 /* Configure DPTX_VIDEO_CONFIG5 register */ 1301 peak_stream_bandwidth = mode->clock * bpp / 8; 1302 link_bandwidth = (link->rate / 1000) * link->lanes; 1303 ts = peak_stream_bandwidth * 64 / link_bandwidth; 1304 average_bytes_per_tu = ts / 1000; 1305 average_bytes_per_tu_frac = ts / 100 - average_bytes_per_tu * 10; 1306 if (pixel_mode == DPTX_MP_SINGLE_PIXEL) { 1307 if (average_bytes_per_tu < 6) 1308 init_threshold = 32; 1309 else if (hblank <= 80 && 1310 color_format != DRM_COLOR_FORMAT_YCRCB420) 1311 init_threshold = 12; 1312 else if (hblank <= 40 && 1313 color_format == DRM_COLOR_FORMAT_YCRCB420) 1314 init_threshold = 3; 1315 else 1316 init_threshold = 16; 1317 } else { 1318 u32 t1 = 0, t2 = 0, t3 = 0; 1319 1320 switch (bpc) { 1321 case 6: 1322 t1 = (4 * 1000 / 9) * link->lanes; 1323 break; 1324 case 8: 1325 if (color_format == DRM_COLOR_FORMAT_YCRCB422) { 1326 t1 = (1000 / 2) * link->lanes; 1327 } else { 1328 if (pixel_mode == DPTX_MP_DUAL_PIXEL) 1329 t1 = (1000 / 3) * link->lanes; 1330 else 1331 t1 = (3000 / 16) * link->lanes; 1332 } 1333 break; 1334 case 10: 1335 if (color_format == DRM_COLOR_FORMAT_YCRCB422) 1336 t1 = (2000 / 5) * link->lanes; 1337 else 1338 t1 = (4000 / 15) * link->lanes; 1339 break; 1340 case 12: 1341 if (color_format == DRM_COLOR_FORMAT_YCRCB422) { 1342 if (pixel_mode == DPTX_MP_DUAL_PIXEL) 1343 t1 = (1000 / 6) * link->lanes; 1344 else 1345 t1 = (1000 / 3) * link->lanes; 1346 } else { 1347 t1 = (2000 / 9) * link->lanes; 1348 } 1349 break; 1350 case 16: 1351 if (color_format != DRM_COLOR_FORMAT_YCRCB422 && 1352 pixel_mode == DPTX_MP_DUAL_PIXEL) 1353 t1 = (1000 / 6) * link->lanes; 1354 else 1355 t1 = (1000 / 4) * link->lanes; 1356 break; 1357 default: 1358 return -EINVAL; 1359 } 1360 1361 if (color_format == DRM_COLOR_FORMAT_YCRCB420) 1362 t2 = (link->rate / 4) * 1000 / (mode->clock / 2); 1363 else 1364 t2 = (link->rate / 4) * 1000 / mode->clock; 1365 1366 if (average_bytes_per_tu_frac) 1367 t3 = average_bytes_per_tu + 1; 1368 else 1369 t3 = average_bytes_per_tu; 1370 init_threshold = t1 * t2 * t3 / (1000 * 1000); 1371 if (init_threshold <= 16 || average_bytes_per_tu < 10) 1372 init_threshold = 40; 1373 } 1374 1375 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG5, 1376 FIELD_PREP(INIT_THRESHOLD_HI, init_threshold >> 6) | 1377 FIELD_PREP(AVERAGE_BYTES_PER_TU_FRAC, 1378 average_bytes_per_tu_frac) | 1379 FIELD_PREP(INIT_THRESHOLD, init_threshold) | 1380 FIELD_PREP(AVERAGE_BYTES_PER_TU, average_bytes_per_tu)); 1381 1382 /* Configure DPTX_VIDEO_HBLANK_INTERVAL register */ 1383 hblank_interval = hblank * (link->rate / 4) / mode->clock; 1384 regmap_write(dp->regmap, DPTX_VIDEO_HBLANK_INTERVAL, 1385 FIELD_PREP(HBLANK_INTERVAL_EN, 1) | 1386 FIELD_PREP(HBLANK_INTERVAL, hblank_interval)); 1387 1388 /* Video stream enable */ 1389 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_STREAM_ENABLE, 1390 FIELD_PREP(VIDEO_STREAM_ENABLE, 1)); 1391 1392 if (link->vsc_sdp_extension_for_colorimetry_supported) 1393 dw_dp_send_vsc_sdp(dp); 1394 1395 return 0; 1396 } 1397 1398 static bool dw_dp_detect(struct dw_dp *dp) 1399 { 1400 u32 value; 1401 1402 if (dm_gpio_is_valid(&dp->hpd_gpio)) 1403 return dm_gpio_get_value(&dp->hpd_gpio); 1404 1405 regmap_read(dp->regmap, DPTX_HPD_STATUS, &value); 1406 if (FIELD_GET(HPD_STATE, value) == SOURCE_STATE_PLUG) { 1407 regmap_write(dp->regmap, DPTX_HPD_STATUS, HPD_HOT_PLUG); 1408 return true; 1409 } 1410 1411 return false; 1412 } 1413 1414 static int dw_dp_connector_init(struct rockchip_connector *conn, struct display_state *state) 1415 { 1416 struct connector_state *conn_state = &state->conn_state; 1417 struct dw_dp *dp = dev_get_priv(conn->dev); 1418 int ret; 1419 1420 conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_DP1 : VOP_OUTPUT_IF_DP0; 1421 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1422 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709; 1423 1424 clk_set_defaults(dp->dev); 1425 1426 reset_assert(&dp->reset); 1427 udelay(20); 1428 reset_deassert(&dp->reset); 1429 1430 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, 1431 dp->id); 1432 dw_dp_init(dp); 1433 ret = generic_phy_power_on(&dp->phy); 1434 1435 return ret; 1436 } 1437 1438 static int dw_dp_connector_get_edid(struct rockchip_connector *conn, struct display_state *state) 1439 { 1440 int ret; 1441 struct connector_state *conn_state = &state->conn_state; 1442 struct dw_dp *dp = dev_get_priv(conn->dev); 1443 1444 ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); 1445 1446 return ret; 1447 } 1448 1449 static int dw_dp_get_output_fmts_index(u32 bus_format) 1450 { 1451 int i; 1452 1453 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 1454 const struct dw_dp_output_format *fmt = &possible_output_fmts[i]; 1455 1456 if (fmt->bus_format == bus_format) 1457 break; 1458 } 1459 1460 if (i == ARRAY_SIZE(possible_output_fmts)) 1461 return 1; 1462 1463 return i; 1464 } 1465 1466 static int dw_dp_connector_prepare(struct rockchip_connector *conn, struct display_state *state) 1467 { 1468 struct connector_state *conn_state = &state->conn_state; 1469 struct dw_dp *dp = dev_get_priv(conn->dev); 1470 struct dw_dp_video *video = &dp->video; 1471 int bus_fmt; 1472 1473 bus_fmt = dw_dp_get_output_fmts_index(conn_state->bus_format); 1474 video->video_mapping = possible_output_fmts[bus_fmt].video_mapping; 1475 video->color_format = possible_output_fmts[bus_fmt].color_format; 1476 video->bus_format = possible_output_fmts[bus_fmt].bus_format; 1477 video->bpc = possible_output_fmts[bus_fmt].bpc; 1478 video->bpp = possible_output_fmts[bus_fmt].bpp; 1479 1480 return 0; 1481 } 1482 1483 static int dw_dp_connector_enable(struct rockchip_connector *conn, struct display_state *state) 1484 { 1485 struct connector_state *conn_state = &state->conn_state; 1486 struct drm_display_mode *mode = &conn_state->mode; 1487 struct dw_dp *dp = dev_get_priv(conn->dev); 1488 struct dw_dp_video *video = &dp->video; 1489 int ret; 1490 1491 memcpy(&video->mode, mode, sizeof(video->mode)); 1492 1493 if (dp->force_output) { 1494 ret = dw_dp_set_phy_default_config(dp); 1495 if (ret < 0) 1496 printf("failed to set phy_default config: %d\n", ret); 1497 } else { 1498 ret = dw_dp_link_enable(dp); 1499 if (ret < 0) { 1500 printf("failed to enable link: %d\n", ret); 1501 return ret; 1502 } 1503 } 1504 1505 ret = dw_dp_video_enable(dp); 1506 if (ret < 0) { 1507 printf("failed to enable video: %d\n", ret); 1508 return ret; 1509 } 1510 1511 return 0; 1512 } 1513 1514 static int dw_dp_connector_disable(struct rockchip_connector *conn, struct display_state *state) 1515 { 1516 /* TODO */ 1517 1518 return 0; 1519 } 1520 1521 static int dw_dp_connector_detect(struct rockchip_connector *conn, struct display_state *state) 1522 { 1523 struct dw_dp *dp = dev_get_priv(conn->dev); 1524 int status, tries, ret; 1525 1526 for (tries = 0; tries < 200; tries++) { 1527 status = dw_dp_detect(dp); 1528 if (status) 1529 break; 1530 mdelay(2); 1531 } 1532 1533 if (state->force_output && !status) 1534 dp->force_output = true; 1535 1536 if (!status && !dp->force_output) 1537 generic_phy_power_off(&dp->phy); 1538 1539 if (status && !dp->force_output) { 1540 ret = dw_dp_link_probe(dp); 1541 if (ret) 1542 printf("failed to probe DP link: %d\n", ret); 1543 } 1544 1545 return status; 1546 } 1547 1548 static int dw_dp_mode_valid(struct dw_dp *dp, struct hdmi_edid_data *edid_data) 1549 { 1550 struct dw_dp_link *link = &dp->link; 1551 struct drm_display_info *di = &edid_data->display_info; 1552 u32 min_bpp; 1553 int i; 1554 1555 if (di->color_formats & DRM_COLOR_FORMAT_YCRCB420 && 1556 link->vsc_sdp_extension_for_colorimetry_supported) 1557 min_bpp = 12; 1558 else if (di->color_formats & DRM_COLOR_FORMAT_YCRCB422) 1559 min_bpp = 16; 1560 else if (di->color_formats & DRM_COLOR_FORMAT_RGB444) 1561 min_bpp = 18; 1562 else 1563 min_bpp = 24; 1564 1565 for (i = 0; i < edid_data->modes; i++) { 1566 if (!dw_dp_bandwidth_ok(dp, &edid_data->mode_buf[i], min_bpp, link->lanes, 1567 link->rate)) 1568 edid_data->mode_buf[i].invalid = true; 1569 } 1570 1571 return 0; 1572 } 1573 1574 static u32 dw_dp_get_output_bus_fmts(struct dw_dp *dp, struct hdmi_edid_data *edid_data) 1575 { 1576 struct dw_dp_link *link = &dp->link; 1577 unsigned int i; 1578 1579 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 1580 const struct dw_dp_output_format *fmt = &possible_output_fmts[i]; 1581 1582 if (fmt->bpc > edid_data->display_info.bpc) 1583 continue; 1584 1585 if (!(edid_data->display_info.color_formats & fmt->color_format)) 1586 continue; 1587 1588 if (fmt->color_format == DRM_COLOR_FORMAT_YCRCB420 && 1589 !link->vsc_sdp_extension_for_colorimetry_supported) 1590 continue; 1591 1592 if (drm_mode_is_420(&edid_data->display_info, edid_data->preferred_mode) && 1593 fmt->color_format != DRM_COLOR_FORMAT_YCRCB420) 1594 continue; 1595 1596 if (!dw_dp_bandwidth_ok(dp, edid_data->preferred_mode, fmt->bpp, link->lanes, 1597 link->rate)) 1598 continue; 1599 1600 break; 1601 } 1602 1603 if (i == ARRAY_SIZE(possible_output_fmts)) 1604 return 1; 1605 1606 return i; 1607 } 1608 1609 static int dw_dp_connector_get_timing(struct rockchip_connector *conn, struct display_state *state) 1610 { 1611 int ret, i; 1612 struct connector_state *conn_state = &state->conn_state; 1613 struct dw_dp *dp = dev_get_priv(conn->dev); 1614 struct drm_display_mode *mode = &conn_state->mode; 1615 struct hdmi_edid_data edid_data; 1616 struct drm_display_mode *mode_buf; 1617 struct vop_rect rect; 1618 u32 bus_fmt; 1619 1620 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 1621 if (!mode_buf) 1622 return -ENOMEM; 1623 1624 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 1625 memset(&edid_data, 0, sizeof(struct hdmi_edid_data)); 1626 edid_data.mode_buf = mode_buf; 1627 1628 if (!dp->force_output) { 1629 ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); 1630 if (!ret) 1631 ret = drm_add_edid_modes(&edid_data, conn_state->edid); 1632 1633 if (ret < 0) { 1634 printf("failed to get edid\n"); 1635 goto err; 1636 } 1637 1638 drm_rk_filter_whitelist(&edid_data); 1639 if (state->conn_state.secondary) { 1640 rect.width = state->crtc_state.max_output.width / 2; 1641 rect.height = state->crtc_state.max_output.height / 2; 1642 } else { 1643 rect.width = state->crtc_state.max_output.width; 1644 rect.height = state->crtc_state.max_output.height; 1645 } 1646 1647 drm_mode_max_resolution_filter(&edid_data, &rect); 1648 dw_dp_mode_valid(dp, &edid_data); 1649 1650 if (!drm_mode_prune_invalid(&edid_data)) { 1651 printf("can't find valid hdmi mode\n"); 1652 ret = -EINVAL; 1653 goto err; 1654 } 1655 1656 for (i = 0; i < edid_data.modes; i++) 1657 edid_data.mode_buf[i].vrefresh = 1658 drm_mode_vrefresh(&edid_data.mode_buf[i]); 1659 1660 drm_mode_sort(&edid_data); 1661 memcpy(mode, edid_data.preferred_mode, sizeof(struct drm_display_mode)); 1662 } 1663 1664 if (state->force_output) 1665 bus_fmt = dw_dp_get_output_fmts_index(state->force_bus_format); 1666 else 1667 bus_fmt = dw_dp_get_output_bus_fmts(dp, &edid_data); 1668 1669 conn_state->bus_format = possible_output_fmts[bus_fmt].bus_format; 1670 1671 switch (possible_output_fmts[bus_fmt].color_format) { 1672 case DRM_COLOR_FORMAT_YCRCB420: 1673 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420; 1674 break; 1675 case DRM_COLOR_FORMAT_YCRCB422: 1676 conn_state->output_mode = ROCKCHIP_OUT_MODE_S888_DUMMY; 1677 break; 1678 case DRM_COLOR_FORMAT_RGB444: 1679 case DRM_COLOR_FORMAT_YCRCB444: 1680 default: 1681 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1682 break; 1683 } 1684 1685 err: 1686 free(mode_buf); 1687 1688 return 0; 1689 } 1690 1691 static const struct rockchip_connector_funcs dw_dp_connector_funcs = { 1692 .init = dw_dp_connector_init, 1693 .get_edid = dw_dp_connector_get_edid, 1694 .prepare = dw_dp_connector_prepare, 1695 .enable = dw_dp_connector_enable, 1696 .disable = dw_dp_connector_disable, 1697 .detect = dw_dp_connector_detect, 1698 .get_timing = dw_dp_connector_get_timing, 1699 }; 1700 1701 static int dw_dp_ddc_init(struct dw_dp *dp) 1702 { 1703 dp->aux.name = "dw-dp"; 1704 dp->aux.dev = dp->dev; 1705 dp->aux.transfer = dw_dp_aux_transfer; 1706 dp->aux.ddc.ddc_xfer = drm_dp_i2c_xfer; 1707 1708 return 0; 1709 } 1710 1711 static u32 dw_dp_parse_link_frequencies(struct dw_dp *dp) 1712 { 1713 struct udevice *dev = dp->dev; 1714 const struct device_node *endpoint; 1715 u64 frequency = 0; 1716 1717 endpoint = rockchip_of_graph_get_endpoint_by_regs(dev->node, 1, 0); 1718 if (!endpoint) 1719 return 0; 1720 1721 if (of_property_read_u64(endpoint, "link-frequencies", &frequency) < 0) 1722 return 0; 1723 1724 if (!frequency) 1725 return 0; 1726 1727 do_div(frequency, 10 * 1000); /* symbol rate kbytes */ 1728 1729 switch (frequency) { 1730 case 162000: 1731 case 270000: 1732 case 540000: 1733 case 810000: 1734 break; 1735 default: 1736 dev_err(dev, "invalid link frequency value: %llu\n", frequency); 1737 return 0; 1738 } 1739 1740 return frequency; 1741 } 1742 1743 static int dw_dp_parse_dt(struct dw_dp *dp) 1744 { 1745 dp->force_hpd = dev_read_bool(dp->dev, "force-hpd"); 1746 1747 dp->max_link_rate = dw_dp_parse_link_frequencies(dp); 1748 if (!dp->max_link_rate) 1749 dp->max_link_rate = 810000; 1750 1751 return 0; 1752 } 1753 1754 static int dw_dp_probe(struct udevice *dev) 1755 { 1756 struct dw_dp *dp = dev_get_priv(dev); 1757 const struct dw_dp_chip_data *pdata = 1758 (const struct dw_dp_chip_data *)dev_get_driver_data(dev); 1759 int ret; 1760 1761 ret = regmap_init_mem(dev, &dp->regmap); 1762 if (ret) 1763 return ret; 1764 1765 dp->id = of_alias_get_id(ofnode_to_np(dev->node), "dp"); 1766 if (dp->id < 0) 1767 dp->id = 0; 1768 1769 dp->video.pixel_mode = pdata->pixel_mode; 1770 1771 ret = reset_get_by_index(dev, 0, &dp->reset); 1772 if (ret) { 1773 dev_err(dev, "failed to get reset control: %d\n", ret); 1774 return ret; 1775 } 1776 1777 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 1778 GPIOD_IS_IN); 1779 if (ret && ret != -ENOENT) { 1780 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 1781 return ret; 1782 } 1783 1784 generic_phy_get_by_index(dev, 0, &dp->phy); 1785 1786 dp->dev = dev; 1787 1788 ret = dw_dp_parse_dt(dp); 1789 if (ret) { 1790 dev_err(dev, "failed to parse DT\n"); 1791 return ret; 1792 } 1793 1794 dw_dp_ddc_init(dp); 1795 1796 rockchip_connector_bind(&dp->connector, dev, dp->id, &dw_dp_connector_funcs, NULL, 1797 DRM_MODE_CONNECTOR_DisplayPort); 1798 1799 return 0; 1800 } 1801 1802 static const struct dw_dp_chip_data rk3588_dp = { 1803 .pixel_mode = DPTX_MP_QUAD_PIXEL, 1804 }; 1805 1806 static const struct dw_dp_chip_data rk3576_dp = { 1807 .pixel_mode = DPTX_MP_DUAL_PIXEL, 1808 }; 1809 1810 static const struct udevice_id dw_dp_ids[] = { 1811 { 1812 .compatible = "rockchip,rk3576-dp", 1813 .data = (ulong)&rk3576_dp, 1814 }, 1815 { 1816 .compatible = "rockchip,rk3588-dp", 1817 .data = (ulong)&rk3588_dp, 1818 }, 1819 {} 1820 }; 1821 1822 U_BOOT_DRIVER(dw_dp) = { 1823 .name = "dw_dp", 1824 .id = UCLASS_DISPLAY, 1825 .of_match = dw_dp_ids, 1826 .probe = dw_dp_probe, 1827 .priv_auto_alloc_size = sizeof(struct dw_dp), 1828 }; 1829 1830