1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Rockchip USBDP Combo PHY with Samsung IP block driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd 6 */ 7 8 #include <config.h> 9 #include <common.h> 10 #include <errno.h> 11 #include <malloc.h> 12 #include <asm/unaligned.h> 13 #include <asm/io.h> 14 #include <clk.h> 15 #include <dm/device.h> 16 #include <dm/of_access.h> 17 #include <dm/lists.h> 18 #include <dm/read.h> 19 #include <generic-phy.h> 20 #include <linux/bitfield.h> 21 #include <linux/hdmi.h> 22 #include <linux/media-bus-format.h> 23 #include <linux/list.h> 24 #include <asm/gpio.h> 25 #include <generic-phy.h> 26 #include <power-domain.h> 27 #include <regmap.h> 28 #include <reset.h> 29 #include <drm/drm_dp_helper.h> 30 31 #include "rockchip_display.h" 32 #include "rockchip_crtc.h" 33 #include "rockchip_connector.h" 34 35 #define DPTX_VERSION_NUMBER 0x0000 36 #define DPTX_VERSION_TYPE 0x0004 37 #define DPTX_ID 0x0008 38 39 #define DPTX_CONFIG_REG1 0x0100 40 #define DPTX_CONFIG_REG2 0x0104 41 #define DPTX_CONFIG_REG3 0x0108 42 43 #define DPTX_CCTL 0x0200 44 #define FORCE_HPD BIT(4) 45 #define DEFAULT_FAST_LINK_TRAIN_EN BIT(2) 46 #define ENHANCE_FRAMING_EN BIT(1) 47 #define SCRAMBLE_DIS BIT(0) 48 #define DPTX_SOFT_RESET_CTRL 0x0204 49 #define VIDEO_RESET BIT(5) 50 #define AUX_RESET BIT(4) 51 #define AUDIO_SAMPLER_RESET BIT(3) 52 #define PHY_SOFT_RESET BIT(1) 53 #define CONTROLLER_RESET BIT(0) 54 55 #define DPTX_VSAMPLE_CTRL 0x0300 56 #define PIXEL_MODE_SELECT GENMASK(22, 21) 57 #define VIDEO_MAPPING GENMASK(20, 16) 58 #define VIDEO_STREAM_ENABLE BIT(5) 59 #define DPTX_VSAMPLE_STUFF_CTRL1 0x0304 60 #define DPTX_VSAMPLE_STUFF_CTRL2 0x0308 61 #define DPTX_VINPUT_POLARITY_CTRL 0x030c 62 #define DE_IN_POLARITY BIT(2) 63 #define HSYNC_IN_POLARITY BIT(1) 64 #define VSYNC_IN_POLARITY BIT(0) 65 #define DPTX_VIDEO_CONFIG1 0x0310 66 #define HACTIVE GENMASK(31, 16) 67 #define HBLANK GENMASK(15, 2) 68 #define I_P BIT(1) 69 #define R_V_BLANK_IN_OSC BIT(0) 70 #define DPTX_VIDEO_CONFIG2 0x0314 71 #define VBLANK GENMASK(31, 16) 72 #define VACTIVE GENMASK(15, 0) 73 #define DPTX_VIDEO_CONFIG3 0x0318 74 #define H_SYNC_WIDTH GENMASK(31, 16) 75 #define H_FRONT_PORCH GENMASK(15, 0) 76 #define DPTX_VIDEO_CONFIG4 0x031c 77 #define V_SYNC_WIDTH GENMASK(31, 16) 78 #define V_FRONT_PORCH GENMASK(15, 0) 79 #define DPTX_VIDEO_CONFIG5 0x0320 80 #define INIT_THRESHOLD_HI GENMASK(22, 21) 81 #define AVERAGE_BYTES_PER_TU_FRAC GENMASK(19, 16) 82 #define INIT_THRESHOLD GENMASK(13, 7) 83 #define AVERAGE_BYTES_PER_TU GENMASK(6, 0) 84 #define DPTX_VIDEO_MSA1 0x0324 85 #define VSTART GENMASK(31, 16) 86 #define HSTART GENMASK(15, 0) 87 #define DPTX_VIDEO_MSA2 0x0328 88 #define MISC0 GENMASK(31, 24) 89 #define DPTX_VIDEO_MSA3 0x032c 90 #define MISC1 GENMASK(31, 24) 91 #define DPTX_VIDEO_HBLANK_INTERVAL 0x0330 92 #define HBLANK_INTERVAL_EN BIT(16) 93 #define HBLANK_INTERVAL GENMASK(15, 0) 94 95 #define DPTX_AUD_CONFIG1 0x0400 96 #define AUDIO_TIMESTAMP_VERSION_NUM GENMASK(29, 24) 97 #define AUDIO_PACKET_ID GENMASK(23, 16) 98 #define AUDIO_MUTE BIT(15) 99 #define NUM_CHANNELS GENMASK(14, 12) 100 #define HBR_MODE_ENABLE BIT(10) 101 #define AUDIO_DATA_WIDTH GENMASK(9, 5) 102 #define AUDIO_DATA_IN_EN GENMASK(4, 1) 103 #define AUDIO_INF_SELECT BIT(0) 104 105 #define DPTX_SDP_VERTICAL_CTRL 0x0500 106 #define EN_VERTICAL_SDP BIT(2) 107 #define EN_AUDIO_STREAM_SDP BIT(1) 108 #define EN_AUDIO_TIMESTAMP_SDP BIT(0) 109 #define DPTX_SDP_HORIZONTAL_CTRL 0x0504 110 #define EN_HORIZONTAL_SDP BIT(2) 111 #define DPTX_SDP_STATUS_REGISTER 0x0508 112 #define DPTX_SDP_MANUAL_CTRL 0x050c 113 #define DPTX_SDP_STATUS_EN 0x0510 114 115 #define DPTX_SDP_REGISTER_BANK 0x0600 116 #define SDP_REGS GENMASK(31, 0) 117 118 #define DPTX_PHYIF_CTRL 0x0a00 119 #define PHY_WIDTH BIT(25) 120 #define PHY_POWERDOWN GENMASK(20, 17) 121 #define PHY_BUSY GENMASK(15, 12) 122 #define SSC_DIS BIT(16) 123 #define XMIT_ENABLE GENMASK(11, 8) 124 #define PHY_LANES GENMASK(7, 6) 125 #define PHY_RATE GENMASK(5, 4) 126 #define TPS_SEL GENMASK(3, 0) 127 #define DPTX_PHY_TX_EQ 0x0a04 128 #define DPTX_CUSTOMPAT0 0x0a08 129 #define DPTX_CUSTOMPAT1 0x0a0c 130 #define DPTX_CUSTOMPAT2 0x0a10 131 #define DPTX_HBR2_COMPLIANCE_SCRAMBLER_RESET 0x0a14 132 #define DPTX_PHYIF_PWRDOWN_CTRL 0x0a18 133 134 #define DPTX_AUX_CMD 0x0b00 135 #define AUX_CMD_TYPE GENMASK(31, 28) 136 #define AUX_ADDR GENMASK(27, 8) 137 #define I2C_ADDR_ONLY BIT(4) 138 #define AUX_LEN_REQ GENMASK(3, 0) 139 #define DPTX_AUX_STATUS 0x0b04 140 #define AUX_TIMEOUT BIT(17) 141 #define AUX_BYTES_READ GENMASK(23, 19) 142 #define AUX_STATUS GENMASK(7, 4) 143 #define DPTX_AUX_DATA0 0x0b08 144 #define DPTX_AUX_DATA1 0x0b0c 145 #define DPTX_AUX_DATA2 0x0b10 146 #define DPTX_AUX_DATA3 0x0b14 147 148 #define DPTX_GENERAL_INTERRUPT 0x0d00 149 #define VIDEO_FIFO_OVERFLOW_STREAM0 BIT(6) 150 #define AUDIO_FIFO_OVERFLOW_STREAM0 BIT(5) 151 #define SDP_EVENT_STREAM0 BIT(4) 152 #define AUX_CMD_INVALID BIT(3) 153 #define AUX_REPLY_EVENT BIT(1) 154 #define HPD_EVENT BIT(0) 155 #define DPTX_GENERAL_INTERRUPT_ENABLE 0x0d04 156 #define AUX_REPLY_EVENT_EN BIT(1) 157 #define HPD_EVENT_EN BIT(0) 158 #define DPTX_HPD_STATUS 0x0d08 159 #define HPD_STATE GENMASK(11, 9) 160 #define HPD_STATUS BIT(8) 161 #define HPD_HOT_UNPLUG BIT(2) 162 #define HPD_HOT_PLUG BIT(1) 163 #define HPD_IRQ BIT(0) 164 #define DPTX_HPD_INTERRUPT_ENABLE 0x0d0c 165 #define HPD_UNPLUG_ERR_EN BIT(3) 166 #define HPD_UNPLUG_EN BIT(2) 167 #define HPD_PLUG_EN BIT(1) 168 #define HPD_IRQ_EN BIT(0) 169 170 #define DPTX_MAX_REGISTER DPTX_HPD_INTERRUPT_ENABLE 171 172 #define SDP_REG_BANK_SIZE 16 173 174 struct drm_dp_link_caps { 175 bool enhanced_framing; 176 bool tps3_supported; 177 bool tps4_supported; 178 bool channel_coding; 179 bool ssc; 180 }; 181 182 struct drm_dp_link_train_set { 183 unsigned int voltage_swing[4]; 184 unsigned int pre_emphasis[4]; 185 }; 186 187 struct drm_dp_link_train { 188 struct drm_dp_link_train_set request; 189 struct drm_dp_link_train_set adjust; 190 bool clock_recovered; 191 bool channel_equalized; 192 }; 193 194 struct dw_dp_link { 195 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 196 unsigned char revision; 197 unsigned int rate; 198 unsigned int lanes; 199 struct drm_dp_link_caps caps; 200 struct drm_dp_link_train train; 201 u8 sink_count; 202 u8 vsc_sdp_extension_for_colorimetry_supported; 203 }; 204 205 struct dw_dp_video { 206 struct drm_display_mode mode; 207 u32 bus_format; 208 u8 video_mapping; 209 u8 pixel_mode; 210 u8 color_format; 211 u8 bpc; 212 u8 bpp; 213 }; 214 215 struct dw_dp_sdp { 216 struct dp_sdp_header header; 217 u8 db[32]; 218 unsigned long flags; 219 }; 220 221 struct dw_dp_chip_data { 222 int pixel_mode; 223 }; 224 225 struct dw_dp { 226 struct rockchip_connector connector; 227 struct udevice *dev; 228 struct regmap *regmap; 229 struct phy phy; 230 #if defined(CONFIG_MOS_SUPPORT) && !defined(CONFIG_SPL_BUILD) 231 struct power_domain pwrdom; 232 struct clk_bulk clks; 233 #endif 234 struct reset_ctl reset; 235 int id; 236 237 struct gpio_desc hpd_gpio; 238 struct drm_dp_aux aux; 239 struct dw_dp_link link; 240 struct dw_dp_video video; 241 242 bool force_hpd; 243 bool force_output; 244 u32 max_link_rate; 245 }; 246 247 enum { 248 SOURCE_STATE_IDLE, 249 SOURCE_STATE_UNPLUG, 250 SOURCE_STATE_HPD_TIMEOUT = 4, 251 SOURCE_STATE_PLUG = 7 252 }; 253 254 enum { 255 DPTX_VM_RGB_6BIT, 256 DPTX_VM_RGB_8BIT, 257 DPTX_VM_RGB_10BIT, 258 DPTX_VM_RGB_12BIT, 259 DPTX_VM_RGB_16BIT, 260 DPTX_VM_YCBCR444_8BIT, 261 DPTX_VM_YCBCR444_10BIT, 262 DPTX_VM_YCBCR444_12BIT, 263 DPTX_VM_YCBCR444_16BIT, 264 DPTX_VM_YCBCR422_8BIT, 265 DPTX_VM_YCBCR422_10BIT, 266 DPTX_VM_YCBCR422_12BIT, 267 DPTX_VM_YCBCR422_16BIT, 268 DPTX_VM_YCBCR420_8BIT, 269 DPTX_VM_YCBCR420_10BIT, 270 DPTX_VM_YCBCR420_12BIT, 271 DPTX_VM_YCBCR420_16BIT, 272 }; 273 274 enum { 275 DPTX_MP_SINGLE_PIXEL, 276 DPTX_MP_DUAL_PIXEL, 277 DPTX_MP_QUAD_PIXEL, 278 }; 279 280 enum { 281 DPTX_SDP_VERTICAL_INTERVAL = BIT(0), 282 DPTX_SDP_HORIZONTAL_INTERVAL = BIT(1), 283 }; 284 285 enum { 286 DPTX_PHY_PATTERN_NONE, 287 DPTX_PHY_PATTERN_TPS_1, 288 DPTX_PHY_PATTERN_TPS_2, 289 DPTX_PHY_PATTERN_TPS_3, 290 DPTX_PHY_PATTERN_TPS_4, 291 DPTX_PHY_PATTERN_SERM, 292 DPTX_PHY_PATTERN_PBRS7, 293 DPTX_PHY_PATTERN_CUSTOM_80BIT, 294 DPTX_PHY_PATTERN_CP2520_1, 295 DPTX_PHY_PATTERN_CP2520_2, 296 }; 297 298 enum { 299 DPTX_PHYRATE_RBR, 300 DPTX_PHYRATE_HBR, 301 DPTX_PHYRATE_HBR2, 302 DPTX_PHYRATE_HBR3, 303 }; 304 305 struct dw_dp_output_format { 306 u32 bus_format; 307 u32 color_format; 308 u8 video_mapping; 309 u8 bpc; 310 u8 bpp; 311 }; 312 313 static const struct dw_dp_output_format possible_output_fmts[] = { 314 { MEDIA_BUS_FMT_RGB101010_1X30, DRM_COLOR_FORMAT_RGB444, 315 DPTX_VM_RGB_10BIT, 10, 30 }, 316 { MEDIA_BUS_FMT_RGB888_1X24, DRM_COLOR_FORMAT_RGB444, 317 DPTX_VM_RGB_8BIT, 8, 24 }, 318 { MEDIA_BUS_FMT_YUV10_1X30, DRM_COLOR_FORMAT_YCRCB444, 319 DPTX_VM_YCBCR444_10BIT, 10, 30 }, 320 { MEDIA_BUS_FMT_YUV8_1X24, DRM_COLOR_FORMAT_YCRCB444, 321 DPTX_VM_YCBCR444_8BIT, 8, 24}, 322 { MEDIA_BUS_FMT_YUYV10_1X20, DRM_COLOR_FORMAT_YCRCB422, 323 DPTX_VM_YCBCR422_10BIT, 10, 20 }, 324 { MEDIA_BUS_FMT_YUYV8_1X16, DRM_COLOR_FORMAT_YCRCB422, 325 DPTX_VM_YCBCR422_8BIT, 8, 16 }, 326 { MEDIA_BUS_FMT_UYYVYY10_0_5X30, DRM_COLOR_FORMAT_YCRCB420, 327 DPTX_VM_YCBCR420_10BIT, 10, 15 }, 328 { MEDIA_BUS_FMT_UYYVYY8_0_5X24, DRM_COLOR_FORMAT_YCRCB420, 329 DPTX_VM_YCBCR420_8BIT, 8, 12 }, 330 { MEDIA_BUS_FMT_RGB666_1X24_CPADHI, DRM_COLOR_FORMAT_RGB444, 331 DPTX_VM_RGB_6BIT, 6, 18 }, 332 }; 333 334 static int dw_dp_aux_write_data(struct dw_dp *dp, const u8 *buffer, size_t size) 335 { 336 size_t i, j; 337 338 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 339 size_t num = min_t(size_t, size - i * 4, 4); 340 u32 value = 0; 341 342 for (j = 0; j < num; j++) 343 value |= buffer[i * 4 + j] << (j * 8); 344 345 regmap_write(dp->regmap, DPTX_AUX_DATA0 + i * 4, value); 346 } 347 348 return size; 349 } 350 351 static int dw_dp_aux_read_data(struct dw_dp *dp, u8 *buffer, size_t size) 352 { 353 size_t i, j; 354 355 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 356 size_t num = min_t(size_t, size - i * 4, 4); 357 u32 value; 358 359 regmap_read(dp->regmap, DPTX_AUX_DATA0 + i * 4, &value); 360 361 for (j = 0; j < num; j++) 362 buffer[i * 4 + j] = value >> (j * 8); 363 } 364 365 return size; 366 } 367 368 static ssize_t dw_dp_aux_transfer(struct drm_dp_aux *aux, 369 struct drm_dp_aux_msg *msg) 370 { 371 u32 status, value; 372 ssize_t ret = 0; 373 int timeout = 0; 374 struct dw_dp *dp = dev_get_priv(aux->dev); 375 376 if (WARN_ON(msg->size > 16)) 377 return -E2BIG; 378 379 switch (msg->request & ~DP_AUX_I2C_MOT) { 380 case DP_AUX_NATIVE_WRITE: 381 case DP_AUX_I2C_WRITE: 382 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 383 ret = dw_dp_aux_write_data(dp, msg->buffer, msg->size); 384 if (ret < 0) 385 return ret; 386 break; 387 case DP_AUX_NATIVE_READ: 388 case DP_AUX_I2C_READ: 389 break; 390 default: 391 return -EINVAL; 392 } 393 394 if (msg->size > 0) 395 value = FIELD_PREP(AUX_LEN_REQ, msg->size - 1); 396 else 397 value = FIELD_PREP(I2C_ADDR_ONLY, 1); 398 399 value |= FIELD_PREP(AUX_CMD_TYPE, msg->request); 400 value |= FIELD_PREP(AUX_ADDR, msg->address); 401 regmap_write(dp->regmap, DPTX_AUX_CMD, value); 402 403 timeout = regmap_read_poll_timeout(dp->regmap, DPTX_GENERAL_INTERRUPT, 404 status, status & AUX_REPLY_EVENT, 405 200, 10); 406 407 if (timeout) { 408 printf("timeout waiting for AUX reply\n"); 409 return -ETIMEDOUT; 410 } 411 regmap_write(dp->regmap, DPTX_GENERAL_INTERRUPT, AUX_REPLY_EVENT); 412 413 regmap_read(dp->regmap, DPTX_AUX_STATUS, &value); 414 if (value & AUX_TIMEOUT) { 415 printf("aux timeout\n"); 416 return -ETIMEDOUT; 417 } 418 419 msg->reply = FIELD_GET(AUX_STATUS, value); 420 421 if (msg->size > 0 && msg->reply == DP_AUX_NATIVE_REPLY_ACK) { 422 if (msg->request & DP_AUX_I2C_READ) { 423 size_t count = FIELD_GET(AUX_BYTES_READ, value) - 1; 424 425 if (count != msg->size) { 426 printf("aux fail to read %lu bytes\n", count); 427 return -EBUSY; 428 } 429 430 ret = dw_dp_aux_read_data(dp, msg->buffer, count); 431 if (ret < 0) 432 return ret; 433 } 434 } 435 436 return ret; 437 } 438 439 static bool dw_dp_bandwidth_ok(struct dw_dp *dp, 440 const struct drm_display_mode *mode, u32 bpp, 441 unsigned int lanes, unsigned int rate) 442 { 443 u32 max_bw, req_bw; 444 445 req_bw = mode->clock * bpp / 8; 446 max_bw = lanes * rate; 447 if (req_bw > max_bw) 448 return false; 449 450 return true; 451 } 452 453 static void dw_dp_hpd_init(struct dw_dp *dp) 454 { 455 if (dm_gpio_is_valid(&dp->hpd_gpio) || dp->force_hpd) { 456 regmap_update_bits(dp->regmap, DPTX_CCTL, FORCE_HPD, 457 FIELD_PREP(FORCE_HPD, 1)); 458 return; 459 } 460 461 /* Enable all HPD interrupts */ 462 regmap_update_bits(dp->regmap, DPTX_HPD_INTERRUPT_ENABLE, 463 HPD_UNPLUG_EN | HPD_PLUG_EN | HPD_IRQ_EN, 464 FIELD_PREP(HPD_UNPLUG_EN, 1) | 465 FIELD_PREP(HPD_PLUG_EN, 1) | 466 FIELD_PREP(HPD_IRQ_EN, 1)); 467 468 /* Enable all top-level interrupts */ 469 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, 470 HPD_EVENT_EN, FIELD_PREP(HPD_EVENT_EN, 1)); 471 } 472 473 static void dw_dp_aux_init(struct dw_dp *dp) 474 { 475 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, 476 FIELD_PREP(AUX_RESET, 1)); 477 udelay(10); 478 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, 479 FIELD_PREP(AUX_RESET, 0)); 480 481 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, 482 AUX_REPLY_EVENT_EN, 483 FIELD_PREP(AUX_REPLY_EVENT_EN, 1)); 484 } 485 486 static void dw_dp_init(struct dw_dp *dp) 487 { 488 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, 489 FIELD_PREP(CONTROLLER_RESET, 1)); 490 udelay(10); 491 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, 492 FIELD_PREP(CONTROLLER_RESET, 0)); 493 494 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, 495 FIELD_PREP(PHY_SOFT_RESET, 1)); 496 udelay(10); 497 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, 498 FIELD_PREP(PHY_SOFT_RESET, 0)); 499 500 regmap_update_bits(dp->regmap, DPTX_CCTL, DEFAULT_FAST_LINK_TRAIN_EN, 501 FIELD_PREP(DEFAULT_FAST_LINK_TRAIN_EN, 0)); 502 503 dw_dp_hpd_init(dp); 504 dw_dp_aux_init(dp); 505 } 506 507 static void dw_dp_phy_set_pattern(struct dw_dp *dp, u32 pattern) 508 { 509 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, TPS_SEL, 510 FIELD_PREP(TPS_SEL, pattern)); 511 } 512 513 static void dw_dp_phy_xmit_enable(struct dw_dp *dp, u32 lanes) 514 { 515 u32 xmit_enable; 516 517 switch (lanes) { 518 case 4: 519 case 2: 520 case 1: 521 xmit_enable = GENMASK(lanes - 1, 0); 522 break; 523 case 0: 524 default: 525 xmit_enable = 0; 526 break; 527 } 528 529 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, XMIT_ENABLE, 530 FIELD_PREP(XMIT_ENABLE, xmit_enable)); 531 } 532 533 static int dw_dp_link_power_up(struct dw_dp *dp) 534 { 535 struct dw_dp_link *link = &dp->link; 536 u8 value; 537 int ret; 538 539 if (link->revision < 0x11) 540 return 0; 541 542 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value); 543 if (ret < 0) 544 return ret; 545 546 value &= ~DP_SET_POWER_MASK; 547 value |= DP_SET_POWER_D0; 548 549 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value); 550 if (ret < 0) 551 return ret; 552 553 udelay(1000); 554 return 0; 555 } 556 557 static int dw_dp_link_probe(struct dw_dp *dp) 558 { 559 struct dw_dp_link *link = &dp->link; 560 u8 dpcd; 561 int ret; 562 563 drm_dp_dpcd_writeb(&dp->aux, DP_MSTM_CTRL, 0); 564 ret = drm_dp_read_dpcd_caps(&dp->aux, link->dpcd); 565 if (ret < 0) 566 return ret; 567 568 ret = drm_dp_dpcd_readb(&dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, 569 &dpcd); 570 if (ret < 0) 571 return ret; 572 573 link->vsc_sdp_extension_for_colorimetry_supported = 574 !!(dpcd & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED); 575 576 link->revision = link->dpcd[DP_DPCD_REV]; 577 link->rate = min_t(u32, min(dp->max_link_rate, dp->phy.attrs.max_link_rate * 100), 578 drm_dp_max_link_rate(link->dpcd)); 579 link->lanes = min_t(u8, dp->phy.attrs.bus_width, 580 drm_dp_max_lane_count(link->dpcd)); 581 582 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(link->dpcd); 583 link->caps.tps3_supported = drm_dp_tps3_supported(link->dpcd); 584 link->caps.tps4_supported = drm_dp_tps4_supported(link->dpcd); 585 link->caps.channel_coding = drm_dp_channel_coding_supported(link->dpcd); 586 link->caps.ssc = !!(link->dpcd[DP_MAX_DOWNSPREAD] & 587 DP_MAX_DOWNSPREAD_0_5); 588 589 return 0; 590 } 591 592 static int dw_dp_link_train_update_vs_emph(struct dw_dp *dp) 593 { 594 struct dw_dp_link *link = &dp->link; 595 struct drm_dp_link_train_set *request = &link->train.request; 596 union phy_configure_opts phy_cfg; 597 unsigned int lanes = link->lanes, *vs, *pe; 598 u8 buf[4]; 599 int i, ret; 600 601 vs = request->voltage_swing; 602 pe = request->pre_emphasis; 603 604 for (i = 0; i < lanes; i++) { 605 phy_cfg.dp.voltage[i] = vs[i]; 606 phy_cfg.dp.pre[i] = pe[i]; 607 } 608 phy_cfg.dp.lanes = lanes; 609 phy_cfg.dp.link_rate = link->rate / 100; 610 phy_cfg.dp.set_lanes = false; 611 phy_cfg.dp.set_rate = false; 612 phy_cfg.dp.set_voltages = true; 613 ret = generic_phy_configure(&dp->phy, &phy_cfg); 614 if (ret) 615 return ret; 616 617 for (i = 0; i < lanes; i++) 618 buf[i] = (vs[i] << DP_TRAIN_VOLTAGE_SWING_SHIFT) | 619 (pe[i] << DP_TRAIN_PRE_EMPHASIS_SHIFT); 620 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, lanes); 621 if (ret < 0) 622 return ret; 623 624 return 0; 625 } 626 627 static int dw_dp_link_configure(struct dw_dp *dp) 628 { 629 struct dw_dp_link *link = &dp->link; 630 union phy_configure_opts phy_cfg; 631 u8 buf[2]; 632 int ret, phy_rate; 633 634 /* Move PHY to P3 */ 635 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 636 FIELD_PREP(PHY_POWERDOWN, 0x3)); 637 638 phy_cfg.dp.lanes = link->lanes; 639 phy_cfg.dp.link_rate = link->rate / 100; 640 phy_cfg.dp.ssc = link->caps.ssc; 641 phy_cfg.dp.set_lanes = true; 642 phy_cfg.dp.set_rate = true; 643 phy_cfg.dp.set_voltages = false; 644 ret = generic_phy_configure(&dp->phy, &phy_cfg); 645 if (ret) 646 return ret; 647 648 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, 649 FIELD_PREP(PHY_LANES, link->lanes / 2)); 650 651 switch (link->rate) { 652 case 810000: 653 phy_rate = DPTX_PHYRATE_HBR3; 654 break; 655 case 540000: 656 phy_rate = DPTX_PHYRATE_HBR2; 657 break; 658 case 270000: 659 phy_rate = DPTX_PHYRATE_HBR; 660 break; 661 case 162000: 662 default: 663 phy_rate = DPTX_PHYRATE_RBR; 664 break; 665 } 666 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_RATE, 667 FIELD_PREP(PHY_RATE, phy_rate)); 668 669 /* Move PHY to P0 */ 670 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 671 FIELD_PREP(PHY_POWERDOWN, 0x0)); 672 673 dw_dp_phy_xmit_enable(dp, link->lanes); 674 675 buf[0] = drm_dp_link_rate_to_bw_code(link->rate); 676 buf[1] = link->lanes; 677 678 if (link->caps.enhanced_framing) { 679 buf[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 680 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 681 FIELD_PREP(ENHANCE_FRAMING_EN, 1)); 682 } else { 683 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 684 FIELD_PREP(ENHANCE_FRAMING_EN, 0)); 685 } 686 687 ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, sizeof(buf)); 688 if (ret < 0) 689 return ret; 690 691 buf[0] = link->caps.ssc ? DP_SPREAD_AMP_0_5 : 0; 692 buf[1] = link->caps.channel_coding ? DP_SET_ANSI_8B10B : 0; 693 694 ret = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, 695 sizeof(buf)); 696 if (ret < 0) 697 return ret; 698 699 return 0; 700 } 701 702 static void dw_dp_link_train_init(struct drm_dp_link_train *train) 703 { 704 struct drm_dp_link_train_set *request = &train->request; 705 struct drm_dp_link_train_set *adjust = &train->adjust; 706 unsigned int i; 707 708 for (i = 0; i < 4; i++) { 709 request->voltage_swing[i] = 0; 710 adjust->voltage_swing[i] = 0; 711 712 request->pre_emphasis[i] = 0; 713 adjust->pre_emphasis[i] = 0; 714 } 715 716 train->clock_recovered = false; 717 train->channel_equalized = false; 718 } 719 720 static int dw_dp_link_train_set_pattern(struct dw_dp *dp, u32 pattern) 721 { 722 u8 buf = 0; 723 int ret; 724 725 if (pattern && pattern != DP_TRAINING_PATTERN_4) { 726 buf |= DP_LINK_SCRAMBLING_DISABLE; 727 728 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, 729 FIELD_PREP(SCRAMBLE_DIS, 1)); 730 } else { 731 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, 732 FIELD_PREP(SCRAMBLE_DIS, 0)); 733 } 734 735 switch (pattern) { 736 case DP_TRAINING_PATTERN_DISABLE: 737 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE); 738 break; 739 case DP_TRAINING_PATTERN_1: 740 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_1); 741 break; 742 case DP_TRAINING_PATTERN_2: 743 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_2); 744 break; 745 case DP_TRAINING_PATTERN_3: 746 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_3); 747 break; 748 case DP_TRAINING_PATTERN_4: 749 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_4); 750 break; 751 default: 752 return -EINVAL; 753 } 754 755 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 756 buf | pattern); 757 if (ret < 0) 758 return ret; 759 760 return 0; 761 } 762 763 static void dw_dp_link_get_adjustments(struct dw_dp_link *link, 764 u8 status[DP_LINK_STATUS_SIZE]) 765 { 766 struct drm_dp_link_train_set *adjust = &link->train.adjust; 767 unsigned int i; 768 769 for (i = 0; i < link->lanes; i++) { 770 adjust->voltage_swing[i] = 771 drm_dp_get_adjust_request_voltage(status, i) >> 772 DP_TRAIN_VOLTAGE_SWING_SHIFT; 773 774 adjust->pre_emphasis[i] = 775 drm_dp_get_adjust_request_pre_emphasis(status, i) >> 776 DP_TRAIN_PRE_EMPHASIS_SHIFT; 777 } 778 } 779 780 static void dw_dp_link_train_adjust(struct drm_dp_link_train *train) 781 { 782 struct drm_dp_link_train_set *request = &train->request; 783 struct drm_dp_link_train_set *adjust = &train->adjust; 784 unsigned int i; 785 786 for (i = 0; i < 4; i++) 787 if (request->voltage_swing[i] != adjust->voltage_swing[i]) 788 request->voltage_swing[i] = adjust->voltage_swing[i]; 789 790 for (i = 0; i < 4; i++) 791 if (request->pre_emphasis[i] != adjust->pre_emphasis[i]) 792 request->pre_emphasis[i] = adjust->pre_emphasis[i]; 793 } 794 795 static int dw_dp_link_clock_recovery(struct dw_dp *dp) 796 { 797 struct dw_dp_link *link = &dp->link; 798 u8 status[DP_LINK_STATUS_SIZE]; 799 unsigned int tries = 0; 800 int ret; 801 802 ret = dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_1); 803 if (ret) 804 return ret; 805 806 for (;;) { 807 ret = dw_dp_link_train_update_vs_emph(dp); 808 if (ret) 809 return ret; 810 811 drm_dp_link_train_clock_recovery_delay(link->dpcd); 812 813 ret = drm_dp_dpcd_read_link_status(&dp->aux, status); 814 if (ret < 0) { 815 dev_err(dp->dev, "failed to read link status: %d\n", 816 ret); 817 return ret; 818 } 819 820 if (drm_dp_clock_recovery_ok(status, link->lanes)) { 821 link->train.clock_recovered = true; 822 break; 823 } 824 825 dw_dp_link_get_adjustments(link, status); 826 827 if (link->train.request.voltage_swing[0] == 828 link->train.adjust.voltage_swing[0]) 829 tries++; 830 else 831 tries = 0; 832 833 if (tries == 5) 834 break; 835 836 dw_dp_link_train_adjust(&link->train); 837 } 838 839 return 0; 840 } 841 842 static int dw_dp_link_channel_equalization(struct dw_dp *dp) 843 { 844 struct dw_dp_link *link = &dp->link; 845 u8 status[DP_LINK_STATUS_SIZE], pattern; 846 unsigned int tries; 847 int ret; 848 849 if (link->caps.tps4_supported) 850 pattern = DP_TRAINING_PATTERN_4; 851 else if (link->caps.tps3_supported) 852 pattern = DP_TRAINING_PATTERN_3; 853 else 854 pattern = DP_TRAINING_PATTERN_2; 855 ret = dw_dp_link_train_set_pattern(dp, pattern); 856 if (ret) 857 return ret; 858 859 for (tries = 1; tries < 5; tries++) { 860 ret = dw_dp_link_train_update_vs_emph(dp); 861 if (ret) 862 return ret; 863 864 drm_dp_link_train_channel_eq_delay(link->dpcd); 865 866 ret = drm_dp_dpcd_read_link_status(&dp->aux, status); 867 if (ret < 0) 868 return ret; 869 870 if (!drm_dp_clock_recovery_ok(status, link->lanes)) { 871 dev_err(dp->dev, 872 "clock recovery lost while eq\n"); 873 link->train.clock_recovered = false; 874 break; 875 } 876 877 if (drm_dp_channel_eq_ok(status, link->lanes)) { 878 link->train.channel_equalized = true; 879 break; 880 } 881 882 dw_dp_link_get_adjustments(link, status); 883 dw_dp_link_train_adjust(&link->train); 884 } 885 886 return 0; 887 } 888 889 static int dw_dp_link_downgrade(struct dw_dp *dp) 890 { 891 struct dw_dp_link *link = &dp->link; 892 struct dw_dp_video *video = &dp->video; 893 894 switch (link->rate) { 895 case 162000: 896 return -EINVAL; 897 case 270000: 898 link->rate = 162000; 899 break; 900 case 540000: 901 link->rate = 270000; 902 break; 903 case 810000: 904 link->rate = 540000; 905 break; 906 } 907 908 if (!dw_dp_bandwidth_ok(dp, &video->mode, video->bpp, link->lanes, 909 link->rate)) 910 return -E2BIG; 911 912 return 0; 913 } 914 915 static int dw_dp_link_train(struct dw_dp *dp) 916 { 917 struct dw_dp_link *link = &dp->link; 918 int ret; 919 920 retry: 921 dw_dp_link_train_init(&link->train); 922 923 printf("training link: %u lane%s at %u MHz\n", 924 link->lanes, (link->lanes > 1) ? "s" : "", link->rate / 100); 925 926 ret = dw_dp_link_configure(dp); 927 if (ret < 0) { 928 dev_err(dp->dev, "failed to configure DP link: %d\n", ret); 929 return ret; 930 } 931 932 ret = dw_dp_link_clock_recovery(dp); 933 if (ret < 0) { 934 dev_err(dp->dev, "clock recovery failed: %d\n", ret); 935 goto out; 936 } 937 938 if (!link->train.clock_recovered) { 939 dev_err(dp->dev, "clock recovery failed, downgrading link\n"); 940 941 ret = dw_dp_link_downgrade(dp); 942 if (ret < 0) 943 goto out; 944 else 945 goto retry; 946 } 947 948 printf("clock recovery succeeded\n"); 949 950 ret = dw_dp_link_channel_equalization(dp); 951 if (ret < 0) { 952 dev_err(dp->dev, "channel equalization failed: %d\n", ret); 953 goto out; 954 } 955 956 if (!link->train.channel_equalized) { 957 dev_err(dp->dev, 958 "channel equalization failed, downgrading link\n"); 959 960 ret = dw_dp_link_downgrade(dp); 961 if (ret < 0) 962 goto out; 963 else 964 goto retry; 965 } 966 967 printf("channel equalization succeeded\n"); 968 969 out: 970 dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE); 971 return ret; 972 } 973 974 static int dw_dp_link_enable(struct dw_dp *dp) 975 { 976 int ret; 977 978 ret = dw_dp_link_power_up(dp); 979 if (ret < 0) 980 return ret; 981 982 ret = dw_dp_link_train(dp); 983 if (ret < 0) { 984 dev_err(dp->dev, "link training failed: %d\n", ret); 985 return ret; 986 } 987 988 return 0; 989 } 990 991 static int dw_dp_set_phy_default_config(struct dw_dp *dp) 992 { 993 struct dw_dp_link *link = &dp->link; 994 union phy_configure_opts phy_cfg; 995 int ret, i, phy_rate; 996 997 link->vsc_sdp_extension_for_colorimetry_supported = false; 998 link->rate = 270000; 999 link->lanes = dp->phy.attrs.bus_width; 1000 1001 link->caps.enhanced_framing = true; 1002 link->caps.channel_coding = true; 1003 link->caps.ssc = true; 1004 1005 /* Move PHY to P3 */ 1006 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 1007 FIELD_PREP(PHY_POWERDOWN, 0x3)); 1008 1009 for (i = 0; i < link->lanes; i++) { 1010 phy_cfg.dp.voltage[i] = 3; 1011 phy_cfg.dp.pre[i] = 0; 1012 } 1013 phy_cfg.dp.lanes = link->lanes; 1014 phy_cfg.dp.link_rate = link->rate / 100; 1015 phy_cfg.dp.ssc = link->caps.ssc; 1016 phy_cfg.dp.set_lanes = true; 1017 phy_cfg.dp.set_rate = true; 1018 phy_cfg.dp.set_voltages = true; 1019 ret = generic_phy_configure(&dp->phy, &phy_cfg); 1020 if (ret) 1021 return ret; 1022 1023 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, 1024 FIELD_PREP(PHY_LANES, link->lanes / 2)); 1025 1026 switch (link->rate) { 1027 case 810000: 1028 phy_rate = DPTX_PHYRATE_HBR3; 1029 break; 1030 case 540000: 1031 phy_rate = DPTX_PHYRATE_HBR2; 1032 break; 1033 case 270000: 1034 phy_rate = DPTX_PHYRATE_HBR; 1035 break; 1036 case 162000: 1037 default: 1038 phy_rate = DPTX_PHYRATE_RBR; 1039 break; 1040 } 1041 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_RATE, 1042 FIELD_PREP(PHY_RATE, phy_rate)); 1043 1044 /* Move PHY to P0 */ 1045 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 1046 FIELD_PREP(PHY_POWERDOWN, 0x0)); 1047 1048 dw_dp_phy_xmit_enable(dp, link->lanes); 1049 1050 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 1051 FIELD_PREP(ENHANCE_FRAMING_EN, 1)); 1052 1053 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE); 1054 return 0; 1055 } 1056 1057 static int dw_dp_send_sdp(struct dw_dp *dp, struct dw_dp_sdp *sdp) 1058 { 1059 const u8 *payload = sdp->db; 1060 u32 reg; 1061 int i, nr = 0; 1062 1063 reg = DPTX_SDP_REGISTER_BANK + nr * 9 * 4; 1064 1065 /* SDP header */ 1066 regmap_write(dp->regmap, reg, get_unaligned_le32(&sdp->header)); 1067 1068 /* SDP data payload */ 1069 for (i = 1; i < 9; i++, payload += 4) 1070 regmap_write(dp->regmap, reg + i * 4, 1071 FIELD_PREP(SDP_REGS, get_unaligned_le32(payload))); 1072 1073 if (sdp->flags & DPTX_SDP_VERTICAL_INTERVAL) 1074 regmap_update_bits(dp->regmap, DPTX_SDP_VERTICAL_CTRL, 1075 EN_VERTICAL_SDP << nr, 1076 EN_VERTICAL_SDP << nr); 1077 1078 if (sdp->flags & DPTX_SDP_HORIZONTAL_INTERVAL) 1079 regmap_update_bits(dp->regmap, DPTX_SDP_HORIZONTAL_CTRL, 1080 EN_HORIZONTAL_SDP << nr, 1081 EN_HORIZONTAL_SDP << nr); 1082 1083 return 0; 1084 } 1085 1086 static void dw_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, 1087 struct dw_dp_sdp *sdp) 1088 { 1089 sdp->header.HB0 = 0; 1090 sdp->header.HB1 = DP_SDP_VSC; 1091 sdp->header.HB2 = vsc->revision; 1092 sdp->header.HB3 = vsc->length; 1093 1094 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; 1095 sdp->db[16] |= vsc->colorimetry & 0xf; 1096 1097 switch (vsc->bpc) { 1098 case 8: 1099 sdp->db[17] = 0x1; 1100 break; 1101 case 10: 1102 sdp->db[17] = 0x2; 1103 break; 1104 case 12: 1105 sdp->db[17] = 0x3; 1106 break; 1107 case 16: 1108 sdp->db[17] = 0x4; 1109 break; 1110 case 6: 1111 default: 1112 break; 1113 } 1114 1115 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) 1116 sdp->db[17] |= 0x80; 1117 1118 sdp->db[18] = vsc->content_type & 0x7; 1119 1120 sdp->flags |= DPTX_SDP_VERTICAL_INTERVAL; 1121 } 1122 1123 static int dw_dp_send_vsc_sdp(struct dw_dp *dp) 1124 { 1125 struct dw_dp_video *video = &dp->video; 1126 struct drm_dp_vsc_sdp vsc = {}; 1127 struct dw_dp_sdp sdp = {}; 1128 1129 vsc.revision = 0x5; 1130 vsc.length = 0x13; 1131 1132 switch (video->color_format) { 1133 case DRM_COLOR_FORMAT_YCRCB444: 1134 vsc.pixelformat = DP_PIXELFORMAT_YUV444; 1135 break; 1136 case DRM_COLOR_FORMAT_YCRCB420: 1137 vsc.pixelformat = DP_PIXELFORMAT_YUV420; 1138 break; 1139 case DRM_COLOR_FORMAT_YCRCB422: 1140 vsc.pixelformat = DP_PIXELFORMAT_YUV422; 1141 break; 1142 case DRM_COLOR_FORMAT_RGB444: 1143 default: 1144 vsc.pixelformat = DP_PIXELFORMAT_RGB; 1145 break; 1146 } 1147 1148 if (video->color_format == DRM_COLOR_FORMAT_RGB444) 1149 vsc.colorimetry = DP_COLORIMETRY_DEFAULT; 1150 else 1151 vsc.colorimetry = DP_COLORIMETRY_BT709_YCC; 1152 1153 vsc.bpc = video->bpc; 1154 vsc.dynamic_range = DP_DYNAMIC_RANGE_CTA; 1155 vsc.content_type = DP_CONTENT_TYPE_NOT_DEFINED; 1156 1157 dw_dp_vsc_sdp_pack(&vsc, &sdp); 1158 1159 return dw_dp_send_sdp(dp, &sdp); 1160 } 1161 1162 static int dw_dp_video_set_pixel_mode(struct dw_dp *dp, u8 pixel_mode) 1163 { 1164 switch (pixel_mode) { 1165 case DPTX_MP_SINGLE_PIXEL: 1166 case DPTX_MP_DUAL_PIXEL: 1167 case DPTX_MP_QUAD_PIXEL: 1168 break; 1169 default: 1170 return -EINVAL; 1171 } 1172 1173 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, PIXEL_MODE_SELECT, 1174 FIELD_PREP(PIXEL_MODE_SELECT, pixel_mode)); 1175 1176 return 0; 1177 } 1178 1179 static int dw_dp_video_set_msa(struct dw_dp *dp, u8 color_format, u8 bpc, 1180 u16 vstart, u16 hstart) 1181 { 1182 struct dw_dp_link *link = &dp->link; 1183 u16 misc = 0; 1184 1185 if (link->vsc_sdp_extension_for_colorimetry_supported) 1186 misc |= DP_MSA_MISC_COLOR_VSC_SDP; 1187 1188 switch (color_format) { 1189 case DRM_COLOR_FORMAT_RGB444: 1190 misc |= DP_MSA_MISC_COLOR_RGB; 1191 break; 1192 case DRM_COLOR_FORMAT_YCRCB444: 1193 misc |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 1194 break; 1195 case DRM_COLOR_FORMAT_YCRCB422: 1196 misc |= DP_MSA_MISC_COLOR_YCBCR_422_BT709; 1197 break; 1198 case DRM_COLOR_FORMAT_YCRCB420: 1199 break; 1200 default: 1201 return -EINVAL; 1202 } 1203 1204 switch (bpc) { 1205 case 6: 1206 misc |= DP_MSA_MISC_6_BPC; 1207 break; 1208 case 8: 1209 misc |= DP_MSA_MISC_8_BPC; 1210 break; 1211 case 10: 1212 misc |= DP_MSA_MISC_10_BPC; 1213 break; 1214 case 12: 1215 misc |= DP_MSA_MISC_12_BPC; 1216 break; 1217 case 16: 1218 misc |= DP_MSA_MISC_16_BPC; 1219 break; 1220 default: 1221 return -EINVAL; 1222 } 1223 1224 regmap_write(dp->regmap, DPTX_VIDEO_MSA1, 1225 FIELD_PREP(VSTART, vstart) | FIELD_PREP(HSTART, hstart)); 1226 regmap_write(dp->regmap, DPTX_VIDEO_MSA2, FIELD_PREP(MISC0, misc)); 1227 regmap_write(dp->regmap, DPTX_VIDEO_MSA3, FIELD_PREP(MISC1, misc >> 8)); 1228 1229 return 0; 1230 } 1231 1232 static int dw_dp_video_enable(struct dw_dp *dp) 1233 { 1234 struct dw_dp_video *video = &dp->video; 1235 struct dw_dp_link *link = &dp->link; 1236 struct drm_display_mode *mode = &video->mode; 1237 u8 color_format = video->color_format; 1238 u8 bpc = video->bpc; 1239 u8 pixel_mode = video->pixel_mode; 1240 u8 bpp = video->bpp, init_threshold, vic; 1241 u32 hactive, hblank, h_sync_width, h_front_porch; 1242 u32 vactive, vblank, v_sync_width, v_front_porch; 1243 u32 vstart = mode->vtotal - mode->vsync_start; 1244 u32 hstart = mode->htotal - mode->hsync_start; 1245 u32 peak_stream_bandwidth, link_bandwidth; 1246 u32 average_bytes_per_tu, average_bytes_per_tu_frac; 1247 u32 ts, hblank_interval; 1248 u32 value; 1249 int ret; 1250 1251 ret = dw_dp_video_set_pixel_mode(dp, pixel_mode); 1252 if (ret) 1253 return ret; 1254 1255 ret = dw_dp_video_set_msa(dp, color_format, bpc, vstart, hstart); 1256 if (ret) 1257 return ret; 1258 1259 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_MAPPING, 1260 FIELD_PREP(VIDEO_MAPPING, video->video_mapping)); 1261 1262 /* Configure DPTX_VINPUT_POLARITY_CTRL register */ 1263 value = 0; 1264 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1265 value |= FIELD_PREP(HSYNC_IN_POLARITY, 1); 1266 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1267 value |= FIELD_PREP(VSYNC_IN_POLARITY, 1); 1268 regmap_write(dp->regmap, DPTX_VINPUT_POLARITY_CTRL, value); 1269 1270 /* Configure DPTX_VIDEO_CONFIG1 register */ 1271 hactive = mode->hdisplay; 1272 hblank = mode->htotal - mode->hdisplay; 1273 value = FIELD_PREP(HACTIVE, hactive) | FIELD_PREP(HBLANK, hblank); 1274 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1275 value |= FIELD_PREP(I_P, 1); 1276 vic = drm_match_cea_mode(mode); 1277 if (vic == 5 || vic == 6 || vic == 7 || 1278 vic == 10 || vic == 11 || vic == 20 || 1279 vic == 21 || vic == 22 || vic == 39 || 1280 vic == 25 || vic == 26 || vic == 40 || 1281 vic == 44 || vic == 45 || vic == 46 || 1282 vic == 50 || vic == 51 || vic == 54 || 1283 vic == 55 || vic == 58 || vic == 59) 1284 value |= R_V_BLANK_IN_OSC; 1285 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG1, value); 1286 1287 /* Configure DPTX_VIDEO_CONFIG2 register */ 1288 vblank = mode->vtotal - mode->vdisplay; 1289 vactive = mode->vdisplay; 1290 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG2, 1291 FIELD_PREP(VBLANK, vblank) | FIELD_PREP(VACTIVE, vactive)); 1292 1293 /* Configure DPTX_VIDEO_CONFIG3 register */ 1294 h_sync_width = mode->hsync_end - mode->hsync_start; 1295 h_front_porch = mode->hsync_start - mode->hdisplay; 1296 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG3, 1297 FIELD_PREP(H_SYNC_WIDTH, h_sync_width) | 1298 FIELD_PREP(H_FRONT_PORCH, h_front_porch)); 1299 1300 /* Configure DPTX_VIDEO_CONFIG4 register */ 1301 v_sync_width = mode->vsync_end - mode->vsync_start; 1302 v_front_porch = mode->vsync_start - mode->vdisplay; 1303 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG4, 1304 FIELD_PREP(V_SYNC_WIDTH, v_sync_width) | 1305 FIELD_PREP(V_FRONT_PORCH, v_front_porch)); 1306 1307 /* Configure DPTX_VIDEO_CONFIG5 register */ 1308 peak_stream_bandwidth = mode->clock * bpp / 8; 1309 link_bandwidth = (link->rate / 1000) * link->lanes; 1310 ts = peak_stream_bandwidth * 64 / link_bandwidth; 1311 average_bytes_per_tu = ts / 1000; 1312 average_bytes_per_tu_frac = ts / 100 - average_bytes_per_tu * 10; 1313 if (pixel_mode == DPTX_MP_SINGLE_PIXEL) { 1314 if (average_bytes_per_tu < 6) 1315 init_threshold = 32; 1316 else if (hblank <= 80 && 1317 color_format != DRM_COLOR_FORMAT_YCRCB420) 1318 init_threshold = 12; 1319 else if (hblank <= 40 && 1320 color_format == DRM_COLOR_FORMAT_YCRCB420) 1321 init_threshold = 3; 1322 else 1323 init_threshold = 16; 1324 } else { 1325 u32 t1 = 0, t2 = 0, t3 = 0; 1326 1327 switch (bpc) { 1328 case 6: 1329 t1 = (4 * 1000 / 9) * link->lanes; 1330 break; 1331 case 8: 1332 if (color_format == DRM_COLOR_FORMAT_YCRCB422) { 1333 t1 = (1000 / 2) * link->lanes; 1334 } else { 1335 if (pixel_mode == DPTX_MP_DUAL_PIXEL) 1336 t1 = (1000 / 3) * link->lanes; 1337 else 1338 t1 = (3000 / 16) * link->lanes; 1339 } 1340 break; 1341 case 10: 1342 if (color_format == DRM_COLOR_FORMAT_YCRCB422) 1343 t1 = (2000 / 5) * link->lanes; 1344 else 1345 t1 = (4000 / 15) * link->lanes; 1346 break; 1347 case 12: 1348 if (color_format == DRM_COLOR_FORMAT_YCRCB422) { 1349 if (pixel_mode == DPTX_MP_DUAL_PIXEL) 1350 t1 = (1000 / 6) * link->lanes; 1351 else 1352 t1 = (1000 / 3) * link->lanes; 1353 } else { 1354 t1 = (2000 / 9) * link->lanes; 1355 } 1356 break; 1357 case 16: 1358 if (color_format != DRM_COLOR_FORMAT_YCRCB422 && 1359 pixel_mode == DPTX_MP_DUAL_PIXEL) 1360 t1 = (1000 / 6) * link->lanes; 1361 else 1362 t1 = (1000 / 4) * link->lanes; 1363 break; 1364 default: 1365 return -EINVAL; 1366 } 1367 1368 if (color_format == DRM_COLOR_FORMAT_YCRCB420) 1369 t2 = (link->rate / 4) * 1000 / (mode->clock / 2); 1370 else 1371 t2 = (link->rate / 4) * 1000 / mode->clock; 1372 1373 if (average_bytes_per_tu_frac) 1374 t3 = average_bytes_per_tu + 1; 1375 else 1376 t3 = average_bytes_per_tu; 1377 init_threshold = t1 * t2 * t3 / (1000 * 1000); 1378 if (init_threshold <= 16 || average_bytes_per_tu < 10) 1379 init_threshold = 40; 1380 } 1381 1382 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG5, 1383 FIELD_PREP(INIT_THRESHOLD_HI, init_threshold >> 6) | 1384 FIELD_PREP(AVERAGE_BYTES_PER_TU_FRAC, 1385 average_bytes_per_tu_frac) | 1386 FIELD_PREP(INIT_THRESHOLD, init_threshold) | 1387 FIELD_PREP(AVERAGE_BYTES_PER_TU, average_bytes_per_tu)); 1388 1389 /* Configure DPTX_VIDEO_HBLANK_INTERVAL register */ 1390 hblank_interval = hblank * (link->rate / 4) / mode->clock; 1391 regmap_write(dp->regmap, DPTX_VIDEO_HBLANK_INTERVAL, 1392 FIELD_PREP(HBLANK_INTERVAL_EN, 1) | 1393 FIELD_PREP(HBLANK_INTERVAL, hblank_interval)); 1394 1395 /* Video stream enable */ 1396 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_STREAM_ENABLE, 1397 FIELD_PREP(VIDEO_STREAM_ENABLE, 1)); 1398 1399 if (link->vsc_sdp_extension_for_colorimetry_supported) 1400 dw_dp_send_vsc_sdp(dp); 1401 1402 return 0; 1403 } 1404 1405 static bool dw_dp_detect(struct dw_dp *dp) 1406 { 1407 u32 value; 1408 1409 if (dm_gpio_is_valid(&dp->hpd_gpio)) 1410 return dm_gpio_get_value(&dp->hpd_gpio); 1411 1412 regmap_read(dp->regmap, DPTX_HPD_STATUS, &value); 1413 if (FIELD_GET(HPD_STATE, value) == SOURCE_STATE_PLUG) { 1414 regmap_write(dp->regmap, DPTX_HPD_STATUS, HPD_HOT_PLUG); 1415 return true; 1416 } 1417 1418 return false; 1419 } 1420 1421 static struct dw_dp *connector_to_dw_dp(struct rockchip_connector *conn) 1422 { 1423 struct dw_dp *dp; 1424 1425 if (dev_get_priv(conn->dev)) 1426 dp = dev_get_priv(conn->dev); 1427 else 1428 dp = dev_get_priv(conn->dev->parent); 1429 1430 return dp; 1431 } 1432 1433 static int dw_dp_connector_init(struct rockchip_connector *conn, struct display_state *state) 1434 { 1435 struct connector_state *conn_state = &state->conn_state; 1436 struct dw_dp *dp = connector_to_dw_dp(conn); 1437 int ret; 1438 1439 if (dev_get_priv(conn->dev)) 1440 dp = dev_get_priv(conn->dev); 1441 else 1442 dp = dev_get_priv(conn->dev->parent); 1443 conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_DP1 : VOP_OUTPUT_IF_DP0; 1444 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1445 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709; 1446 1447 clk_set_defaults(dp->dev); 1448 1449 reset_assert(&dp->reset); 1450 udelay(20); 1451 reset_deassert(&dp->reset); 1452 1453 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, 1454 dp->id); 1455 dw_dp_init(dp); 1456 ret = generic_phy_power_on(&dp->phy); 1457 1458 return ret; 1459 } 1460 1461 static int dw_dp_connector_get_edid(struct rockchip_connector *conn, struct display_state *state) 1462 { 1463 int ret; 1464 struct connector_state *conn_state = &state->conn_state; 1465 struct dw_dp *dp = connector_to_dw_dp(conn); 1466 1467 conn_state->edid = drm_do_get_edid(&dp->aux.ddc); 1468 if (!conn_state->edid) 1469 ret = -EINVAL; 1470 1471 return ret; 1472 } 1473 1474 static int dw_dp_get_output_fmts_index(u32 bus_format) 1475 { 1476 int i; 1477 1478 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 1479 const struct dw_dp_output_format *fmt = &possible_output_fmts[i]; 1480 1481 if (fmt->bus_format == bus_format) 1482 break; 1483 } 1484 1485 if (i == ARRAY_SIZE(possible_output_fmts)) 1486 return 1; 1487 1488 return i; 1489 } 1490 1491 static int dw_dp_connector_prepare(struct rockchip_connector *conn, struct display_state *state) 1492 { 1493 struct connector_state *conn_state = &state->conn_state; 1494 struct dw_dp *dp = connector_to_dw_dp(conn); 1495 struct dw_dp_video *video = &dp->video; 1496 int bus_fmt; 1497 1498 bus_fmt = dw_dp_get_output_fmts_index(conn_state->bus_format); 1499 video->video_mapping = possible_output_fmts[bus_fmt].video_mapping; 1500 video->color_format = possible_output_fmts[bus_fmt].color_format; 1501 video->bus_format = possible_output_fmts[bus_fmt].bus_format; 1502 video->bpc = possible_output_fmts[bus_fmt].bpc; 1503 video->bpp = possible_output_fmts[bus_fmt].bpp; 1504 1505 return 0; 1506 } 1507 1508 static int dw_dp_connector_enable(struct rockchip_connector *conn, struct display_state *state) 1509 { 1510 struct connector_state *conn_state = &state->conn_state; 1511 struct drm_display_mode *mode = &conn_state->mode; 1512 struct dw_dp *dp = connector_to_dw_dp(conn); 1513 struct dw_dp_video *video = &dp->video; 1514 int ret; 1515 1516 memcpy(&video->mode, mode, sizeof(video->mode)); 1517 1518 if (dp->force_output) { 1519 ret = dw_dp_set_phy_default_config(dp); 1520 if (ret < 0) 1521 printf("failed to set phy_default config: %d\n", ret); 1522 } else { 1523 ret = dw_dp_link_enable(dp); 1524 if (ret < 0) { 1525 printf("failed to enable link: %d\n", ret); 1526 return ret; 1527 } 1528 } 1529 1530 ret = dw_dp_video_enable(dp); 1531 if (ret < 0) { 1532 printf("failed to enable video: %d\n", ret); 1533 return ret; 1534 } 1535 1536 return 0; 1537 } 1538 1539 static int dw_dp_connector_disable(struct rockchip_connector *conn, struct display_state *state) 1540 { 1541 /* TODO */ 1542 1543 return 0; 1544 } 1545 1546 static int dw_dp_connector_detect(struct rockchip_connector *conn, struct display_state *state) 1547 { 1548 struct dw_dp *dp = connector_to_dw_dp(conn); 1549 int status, tries, ret; 1550 1551 for (tries = 0; tries < 200; tries++) { 1552 status = dw_dp_detect(dp); 1553 if (status) 1554 break; 1555 mdelay(2); 1556 } 1557 1558 if (state->force_output && !status) 1559 dp->force_output = true; 1560 1561 if (!status && !dp->force_output) 1562 generic_phy_power_off(&dp->phy); 1563 1564 if (status && !dp->force_output) { 1565 ret = dw_dp_link_probe(dp); 1566 if (ret) 1567 printf("failed to probe DP link: %d\n", ret); 1568 } 1569 1570 return status; 1571 } 1572 1573 static int dw_dp_mode_valid(struct dw_dp *dp, struct hdmi_edid_data *edid_data) 1574 { 1575 struct dw_dp_link *link = &dp->link; 1576 struct drm_display_info *di = &edid_data->display_info; 1577 u32 min_bpp; 1578 int i; 1579 1580 if (di->color_formats & DRM_COLOR_FORMAT_YCRCB420 && 1581 link->vsc_sdp_extension_for_colorimetry_supported) 1582 min_bpp = 12; 1583 else if (di->color_formats & DRM_COLOR_FORMAT_YCRCB422) 1584 min_bpp = 16; 1585 else if (di->color_formats & DRM_COLOR_FORMAT_RGB444) 1586 min_bpp = 18; 1587 else 1588 min_bpp = 24; 1589 1590 for (i = 0; i < edid_data->modes; i++) { 1591 if (!dw_dp_bandwidth_ok(dp, &edid_data->mode_buf[i], min_bpp, link->lanes, 1592 link->rate)) 1593 edid_data->mode_buf[i].invalid = true; 1594 } 1595 1596 return 0; 1597 } 1598 1599 static u32 dw_dp_get_output_bus_fmts(struct dw_dp *dp, struct hdmi_edid_data *edid_data) 1600 { 1601 struct dw_dp_link *link = &dp->link; 1602 unsigned int i; 1603 1604 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 1605 const struct dw_dp_output_format *fmt = &possible_output_fmts[i]; 1606 1607 if (fmt->bpc > edid_data->display_info.bpc) 1608 continue; 1609 1610 if (!(edid_data->display_info.color_formats & fmt->color_format)) 1611 continue; 1612 1613 if (fmt->color_format == DRM_COLOR_FORMAT_YCRCB420 && 1614 !link->vsc_sdp_extension_for_colorimetry_supported) 1615 continue; 1616 1617 if (drm_mode_is_420(&edid_data->display_info, edid_data->preferred_mode) && 1618 fmt->color_format != DRM_COLOR_FORMAT_YCRCB420) 1619 continue; 1620 1621 if (!dw_dp_bandwidth_ok(dp, edid_data->preferred_mode, fmt->bpp, link->lanes, 1622 link->rate)) 1623 continue; 1624 1625 break; 1626 } 1627 1628 if (i == ARRAY_SIZE(possible_output_fmts)) 1629 return 1; 1630 1631 return i; 1632 } 1633 1634 static int dw_dp_connector_get_timing(struct rockchip_connector *conn, struct display_state *state) 1635 { 1636 int ret = 0, i; 1637 struct connector_state *conn_state = &state->conn_state; 1638 struct dw_dp *dp = connector_to_dw_dp(conn); 1639 struct drm_display_mode *mode = &conn_state->mode; 1640 struct hdmi_edid_data edid_data; 1641 struct drm_display_mode *mode_buf; 1642 struct vop_rect rect; 1643 u32 bus_fmt; 1644 1645 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 1646 if (!mode_buf) 1647 return -ENOMEM; 1648 1649 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 1650 memset(&edid_data, 0, sizeof(struct hdmi_edid_data)); 1651 edid_data.mode_buf = mode_buf; 1652 1653 if (!dp->force_output) { 1654 conn_state->edid = drm_do_get_edid(&dp->aux.ddc); 1655 if (conn_state->edid) 1656 ret = drm_add_edid_modes(&edid_data, conn_state->edid); 1657 1658 if (ret <= 0) { 1659 printf("failed to get edid\n"); 1660 goto err; 1661 } 1662 1663 //drm_rk_filter_whitelist(&edid_data); 1664 if (state->conn_state.secondary) { 1665 rect.width = state->crtc_state.max_output.width / 2; 1666 rect.height = state->crtc_state.max_output.height / 2; 1667 } else { 1668 rect.width = state->crtc_state.max_output.width; 1669 rect.height = state->crtc_state.max_output.height; 1670 } 1671 1672 drm_mode_max_resolution_filter(&edid_data, &rect); 1673 dw_dp_mode_valid(dp, &edid_data); 1674 1675 if (!drm_mode_prune_invalid(&edid_data)) { 1676 printf("can't find valid dp mode\n"); 1677 ret = -EINVAL; 1678 goto err; 1679 } 1680 1681 for (i = 0; i < edid_data.modes; i++) 1682 edid_data.mode_buf[i].vrefresh = 1683 drm_mode_vrefresh(&edid_data.mode_buf[i]); 1684 1685 drm_mode_sort(&edid_data); 1686 memcpy(mode, edid_data.preferred_mode, sizeof(struct drm_display_mode)); 1687 } 1688 1689 if (state->force_output) 1690 bus_fmt = dw_dp_get_output_fmts_index(state->force_bus_format); 1691 else 1692 bus_fmt = dw_dp_get_output_bus_fmts(dp, &edid_data); 1693 1694 conn_state->bus_format = possible_output_fmts[bus_fmt].bus_format; 1695 1696 switch (possible_output_fmts[bus_fmt].color_format) { 1697 case DRM_COLOR_FORMAT_YCRCB420: 1698 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420; 1699 break; 1700 case DRM_COLOR_FORMAT_YCRCB422: 1701 conn_state->output_mode = ROCKCHIP_OUT_MODE_S888_DUMMY; 1702 break; 1703 case DRM_COLOR_FORMAT_RGB444: 1704 case DRM_COLOR_FORMAT_YCRCB444: 1705 default: 1706 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1707 break; 1708 } 1709 1710 err: 1711 free(mode_buf); 1712 1713 return 0; 1714 } 1715 1716 static const struct rockchip_connector_funcs dw_dp_connector_funcs = { 1717 .init = dw_dp_connector_init, 1718 .get_edid = dw_dp_connector_get_edid, 1719 .prepare = dw_dp_connector_prepare, 1720 .enable = dw_dp_connector_enable, 1721 .disable = dw_dp_connector_disable, 1722 .detect = dw_dp_connector_detect, 1723 .get_timing = dw_dp_connector_get_timing, 1724 }; 1725 1726 static int dw_dp_ddc_init(struct dw_dp *dp) 1727 { 1728 dp->aux.name = "dw-dp"; 1729 dp->aux.dev = dp->dev; 1730 dp->aux.transfer = dw_dp_aux_transfer; 1731 dp->aux.ddc.ddc_xfer = drm_dp_i2c_xfer; 1732 1733 return 0; 1734 } 1735 1736 static u32 dw_dp_parse_link_frequencies(struct dw_dp *dp) 1737 { 1738 struct udevice *dev = dp->dev; 1739 const struct device_node *endpoint; 1740 u64 frequency = 0; 1741 1742 endpoint = rockchip_of_graph_get_endpoint_by_regs(dev->node, 1, 0); 1743 if (!endpoint) 1744 return 0; 1745 1746 if (of_property_read_u64(endpoint, "link-frequencies", &frequency) < 0) 1747 return 0; 1748 1749 if (!frequency) 1750 return 0; 1751 1752 do_div(frequency, 10 * 1000); /* symbol rate kbytes */ 1753 1754 switch (frequency) { 1755 case 162000: 1756 case 270000: 1757 case 540000: 1758 case 810000: 1759 break; 1760 default: 1761 dev_err(dev, "invalid link frequency value: %llu\n", frequency); 1762 return 0; 1763 } 1764 1765 return frequency; 1766 } 1767 1768 static int dw_dp_parse_dt(struct dw_dp *dp) 1769 { 1770 dp->force_hpd = dev_read_bool(dp->dev, "force-hpd"); 1771 1772 dp->max_link_rate = dw_dp_parse_link_frequencies(dp); 1773 if (!dp->max_link_rate) 1774 dp->max_link_rate = 810000; 1775 1776 return 0; 1777 } 1778 1779 static int dw_dp_probe(struct udevice *dev) 1780 { 1781 struct dw_dp *dp = dev_get_priv(dev); 1782 const struct dw_dp_chip_data *pdata = 1783 (const struct dw_dp_chip_data *)dev_get_driver_data(dev); 1784 int ret; 1785 1786 ret = regmap_init_mem(dev, &dp->regmap); 1787 if (ret) 1788 return ret; 1789 1790 dp->id = of_alias_get_id(ofnode_to_np(dev->node), "dp"); 1791 if (dp->id < 0) 1792 dp->id = 0; 1793 1794 dp->video.pixel_mode = pdata->pixel_mode; 1795 1796 #if defined(CONFIG_MOS_SUPPORT) && !defined(CONFIG_SPL_BUILD) 1797 ret = power_domain_get(dev, &dp->pwrdom); 1798 if (ret) { 1799 dev_err(dev, "failed to get pwrdom: %d\n", ret); 1800 return ret; 1801 } 1802 ret = power_domain_on(&dp->pwrdom); 1803 if (ret) { 1804 dev_err(dev, "failed to power on pd: %d\n", ret); 1805 return ret; 1806 } 1807 ret = clk_get_bulk(dev, &dp->clks); 1808 if (ret) { 1809 dev_err(dev, "failed to get clk: %d\n", ret); 1810 return ret; 1811 } 1812 ret = clk_enable_bulk(&dp->clks); 1813 if (ret) { 1814 dev_err(dev, "failed to enable clk: %d\n", ret); 1815 return ret; 1816 } 1817 #endif 1818 1819 ret = reset_get_by_index(dev, 0, &dp->reset); 1820 if (ret) { 1821 dev_err(dev, "failed to get reset control: %d\n", ret); 1822 return ret; 1823 } 1824 1825 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 1826 GPIOD_IS_IN); 1827 if (ret && ret != -ENOENT) { 1828 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 1829 return ret; 1830 } 1831 1832 generic_phy_get_by_index(dev, 0, &dp->phy); 1833 1834 dp->dev = dev; 1835 1836 ret = dw_dp_parse_dt(dp); 1837 if (ret) { 1838 dev_err(dev, "failed to parse DT\n"); 1839 return ret; 1840 } 1841 1842 dw_dp_ddc_init(dp); 1843 1844 rockchip_connector_bind(&dp->connector, dev, dp->id, &dw_dp_connector_funcs, NULL, 1845 DRM_MODE_CONNECTOR_DisplayPort); 1846 1847 return 0; 1848 } 1849 1850 static int dw_dp_bind(struct udevice *parent) 1851 { 1852 struct udevice *child; 1853 ofnode subnode; 1854 const char *node_name; 1855 int ret; 1856 1857 dev_for_each_subnode(subnode, parent) { 1858 if (!ofnode_valid(subnode)) { 1859 printf("%s: no subnode for %s\n", __func__, parent->name); 1860 return -ENXIO; 1861 } 1862 1863 node_name = ofnode_get_name(subnode); 1864 debug("%s: subnode %s\n", __func__, node_name); 1865 1866 if (!strcasecmp(node_name, "dp0")) { 1867 ret = device_bind_driver_to_node(parent, 1868 "dw_dp_port0", 1869 node_name, subnode, &child); 1870 if (ret) { 1871 printf("%s: '%s' cannot bind its driver\n", 1872 __func__, node_name); 1873 return ret; 1874 } 1875 } 1876 } 1877 1878 return 0; 1879 } 1880 1881 static int dw_dp_port_probe(struct udevice *dev) 1882 { 1883 struct dw_dp *dp = dev_get_priv(dev->parent); 1884 1885 rockchip_connector_bind(&dp->connector, dev, dp->id, &dw_dp_connector_funcs, NULL, 1886 DRM_MODE_CONNECTOR_DisplayPort); 1887 1888 return 0; 1889 } 1890 1891 static const struct dw_dp_chip_data rk3588_dp = { 1892 .pixel_mode = DPTX_MP_QUAD_PIXEL, 1893 }; 1894 1895 static const struct dw_dp_chip_data rk3576_dp = { 1896 .pixel_mode = DPTX_MP_DUAL_PIXEL, 1897 }; 1898 1899 static const struct udevice_id dw_dp_ids[] = { 1900 { 1901 .compatible = "rockchip,rk3576-dp", 1902 .data = (ulong)&rk3576_dp, 1903 }, 1904 { 1905 .compatible = "rockchip,rk3588-dp", 1906 .data = (ulong)&rk3588_dp, 1907 }, 1908 {} 1909 }; 1910 1911 U_BOOT_DRIVER(dw_dp_port) = { 1912 .name = "dw_dp_port0", 1913 .id = UCLASS_DISPLAY, 1914 .probe = dw_dp_port_probe, 1915 }; 1916 1917 U_BOOT_DRIVER(dw_dp) = { 1918 .name = "dw_dp", 1919 .id = UCLASS_DISPLAY, 1920 .of_match = dw_dp_ids, 1921 .probe = dw_dp_probe, 1922 .bind = dw_dp_bind, 1923 .priv_auto_alloc_size = sizeof(struct dw_dp), 1924 }; 1925 1926