1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Rockchip USBDP Combo PHY with Samsung IP block driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd 6 */ 7 8 #include <config.h> 9 #include <common.h> 10 #include <errno.h> 11 #include <malloc.h> 12 #include <asm/unaligned.h> 13 #include <asm/io.h> 14 #include <clk.h> 15 #include <dm/device.h> 16 #include <dm/of_access.h> 17 #include <dm/read.h> 18 #include <generic-phy.h> 19 #include <linux/bitfield.h> 20 #include <linux/hdmi.h> 21 #include <linux/media-bus-format.h> 22 #include <linux/list.h> 23 #include <asm/gpio.h> 24 #include <generic-phy.h> 25 #include <regmap.h> 26 #include <reset.h> 27 #include <drm/drm_dp_helper.h> 28 29 #include "rockchip_display.h" 30 #include "rockchip_crtc.h" 31 #include "rockchip_connector.h" 32 33 #define DPTX_VERSION_NUMBER 0x0000 34 #define DPTX_VERSION_TYPE 0x0004 35 #define DPTX_ID 0x0008 36 37 #define DPTX_CONFIG_REG1 0x0100 38 #define DPTX_CONFIG_REG2 0x0104 39 #define DPTX_CONFIG_REG3 0x0108 40 41 #define DPTX_CCTL 0x0200 42 #define FORCE_HPD BIT(4) 43 #define DEFAULT_FAST_LINK_TRAIN_EN BIT(2) 44 #define ENHANCE_FRAMING_EN BIT(1) 45 #define SCRAMBLE_DIS BIT(0) 46 #define DPTX_SOFT_RESET_CTRL 0x0204 47 #define VIDEO_RESET BIT(5) 48 #define AUX_RESET BIT(4) 49 #define AUDIO_SAMPLER_RESET BIT(3) 50 #define PHY_SOFT_RESET BIT(1) 51 #define CONTROLLER_RESET BIT(0) 52 53 #define DPTX_VSAMPLE_CTRL 0x0300 54 #define PIXEL_MODE_SELECT GENMASK(22, 21) 55 #define VIDEO_MAPPING GENMASK(20, 16) 56 #define VIDEO_STREAM_ENABLE BIT(5) 57 #define DPTX_VSAMPLE_STUFF_CTRL1 0x0304 58 #define DPTX_VSAMPLE_STUFF_CTRL2 0x0308 59 #define DPTX_VINPUT_POLARITY_CTRL 0x030c 60 #define DE_IN_POLARITY BIT(2) 61 #define HSYNC_IN_POLARITY BIT(1) 62 #define VSYNC_IN_POLARITY BIT(0) 63 #define DPTX_VIDEO_CONFIG1 0x0310 64 #define HACTIVE GENMASK(31, 16) 65 #define HBLANK GENMASK(15, 2) 66 #define I_P BIT(1) 67 #define R_V_BLANK_IN_OSC BIT(0) 68 #define DPTX_VIDEO_CONFIG2 0x0314 69 #define VBLANK GENMASK(31, 16) 70 #define VACTIVE GENMASK(15, 0) 71 #define DPTX_VIDEO_CONFIG3 0x0318 72 #define H_SYNC_WIDTH GENMASK(31, 16) 73 #define H_FRONT_PORCH GENMASK(15, 0) 74 #define DPTX_VIDEO_CONFIG4 0x031c 75 #define V_SYNC_WIDTH GENMASK(31, 16) 76 #define V_FRONT_PORCH GENMASK(15, 0) 77 #define DPTX_VIDEO_CONFIG5 0x0320 78 #define INIT_THRESHOLD_HI GENMASK(22, 21) 79 #define AVERAGE_BYTES_PER_TU_FRAC GENMASK(19, 16) 80 #define INIT_THRESHOLD GENMASK(13, 7) 81 #define AVERAGE_BYTES_PER_TU GENMASK(6, 0) 82 #define DPTX_VIDEO_MSA1 0x0324 83 #define VSTART GENMASK(31, 16) 84 #define HSTART GENMASK(15, 0) 85 #define DPTX_VIDEO_MSA2 0x0328 86 #define MISC0 GENMASK(31, 24) 87 #define DPTX_VIDEO_MSA3 0x032c 88 #define MISC1 GENMASK(31, 24) 89 #define DPTX_VIDEO_HBLANK_INTERVAL 0x0330 90 #define HBLANK_INTERVAL_EN BIT(16) 91 #define HBLANK_INTERVAL GENMASK(15, 0) 92 93 #define DPTX_AUD_CONFIG1 0x0400 94 #define AUDIO_TIMESTAMP_VERSION_NUM GENMASK(29, 24) 95 #define AUDIO_PACKET_ID GENMASK(23, 16) 96 #define AUDIO_MUTE BIT(15) 97 #define NUM_CHANNELS GENMASK(14, 12) 98 #define HBR_MODE_ENABLE BIT(10) 99 #define AUDIO_DATA_WIDTH GENMASK(9, 5) 100 #define AUDIO_DATA_IN_EN GENMASK(4, 1) 101 #define AUDIO_INF_SELECT BIT(0) 102 103 #define DPTX_SDP_VERTICAL_CTRL 0x0500 104 #define EN_VERTICAL_SDP BIT(2) 105 #define EN_AUDIO_STREAM_SDP BIT(1) 106 #define EN_AUDIO_TIMESTAMP_SDP BIT(0) 107 #define DPTX_SDP_HORIZONTAL_CTRL 0x0504 108 #define EN_HORIZONTAL_SDP BIT(2) 109 #define DPTX_SDP_STATUS_REGISTER 0x0508 110 #define DPTX_SDP_MANUAL_CTRL 0x050c 111 #define DPTX_SDP_STATUS_EN 0x0510 112 113 #define DPTX_SDP_REGISTER_BANK 0x0600 114 #define SDP_REGS GENMASK(31, 0) 115 116 #define DPTX_PHYIF_CTRL 0x0a00 117 #define PHY_WIDTH BIT(25) 118 #define PHY_POWERDOWN GENMASK(20, 17) 119 #define PHY_BUSY GENMASK(15, 12) 120 #define SSC_DIS BIT(16) 121 #define XMIT_ENABLE GENMASK(11, 8) 122 #define PHY_LANES GENMASK(7, 6) 123 #define PHY_RATE GENMASK(5, 4) 124 #define TPS_SEL GENMASK(3, 0) 125 #define DPTX_PHY_TX_EQ 0x0a04 126 #define DPTX_CUSTOMPAT0 0x0a08 127 #define DPTX_CUSTOMPAT1 0x0a0c 128 #define DPTX_CUSTOMPAT2 0x0a10 129 #define DPTX_HBR2_COMPLIANCE_SCRAMBLER_RESET 0x0a14 130 #define DPTX_PHYIF_PWRDOWN_CTRL 0x0a18 131 132 #define DPTX_AUX_CMD 0x0b00 133 #define AUX_CMD_TYPE GENMASK(31, 28) 134 #define AUX_ADDR GENMASK(27, 8) 135 #define I2C_ADDR_ONLY BIT(4) 136 #define AUX_LEN_REQ GENMASK(3, 0) 137 #define DPTX_AUX_STATUS 0x0b04 138 #define AUX_TIMEOUT BIT(17) 139 #define AUX_BYTES_READ GENMASK(23, 19) 140 #define AUX_STATUS GENMASK(7, 4) 141 #define DPTX_AUX_DATA0 0x0b08 142 #define DPTX_AUX_DATA1 0x0b0c 143 #define DPTX_AUX_DATA2 0x0b10 144 #define DPTX_AUX_DATA3 0x0b14 145 146 #define DPTX_GENERAL_INTERRUPT 0x0d00 147 #define VIDEO_FIFO_OVERFLOW_STREAM0 BIT(6) 148 #define AUDIO_FIFO_OVERFLOW_STREAM0 BIT(5) 149 #define SDP_EVENT_STREAM0 BIT(4) 150 #define AUX_CMD_INVALID BIT(3) 151 #define AUX_REPLY_EVENT BIT(1) 152 #define HPD_EVENT BIT(0) 153 #define DPTX_GENERAL_INTERRUPT_ENABLE 0x0d04 154 #define AUX_REPLY_EVENT_EN BIT(1) 155 #define HPD_EVENT_EN BIT(0) 156 #define DPTX_HPD_STATUS 0x0d08 157 #define HPD_STATE GENMASK(11, 9) 158 #define HPD_STATUS BIT(8) 159 #define HPD_HOT_UNPLUG BIT(2) 160 #define HPD_HOT_PLUG BIT(1) 161 #define HPD_IRQ BIT(0) 162 #define DPTX_HPD_INTERRUPT_ENABLE 0x0d0c 163 #define HPD_UNPLUG_ERR_EN BIT(3) 164 #define HPD_UNPLUG_EN BIT(2) 165 #define HPD_PLUG_EN BIT(1) 166 #define HPD_IRQ_EN BIT(0) 167 168 #define DPTX_MAX_REGISTER DPTX_HPD_INTERRUPT_ENABLE 169 170 #define SDP_REG_BANK_SIZE 16 171 172 struct drm_dp_link_caps { 173 bool enhanced_framing; 174 bool tps3_supported; 175 bool tps4_supported; 176 bool channel_coding; 177 bool ssc; 178 }; 179 180 struct drm_dp_link_train_set { 181 unsigned int voltage_swing[4]; 182 unsigned int pre_emphasis[4]; 183 }; 184 185 struct drm_dp_link_train { 186 struct drm_dp_link_train_set request; 187 struct drm_dp_link_train_set adjust; 188 bool clock_recovered; 189 bool channel_equalized; 190 }; 191 192 struct dw_dp_link { 193 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 194 unsigned char revision; 195 unsigned int rate; 196 unsigned int lanes; 197 struct drm_dp_link_caps caps; 198 struct drm_dp_link_train train; 199 u8 sink_count; 200 u8 vsc_sdp_extension_for_colorimetry_supported; 201 }; 202 203 struct dw_dp_video { 204 struct drm_display_mode mode; 205 u32 bus_format; 206 u8 video_mapping; 207 u8 pixel_mode; 208 u8 color_format; 209 u8 bpc; 210 u8 bpp; 211 }; 212 213 struct dw_dp_sdp { 214 struct dp_sdp_header header; 215 u8 db[32]; 216 unsigned long flags; 217 }; 218 219 struct dw_dp { 220 struct udevice *dev; 221 struct regmap *regmap; 222 struct phy phy; 223 struct reset_ctl reset; 224 int id; 225 226 struct gpio_desc hpd_gpio; 227 struct drm_dp_aux aux; 228 struct dw_dp_link link; 229 struct dw_dp_video video; 230 231 bool force_output; 232 }; 233 234 enum { 235 SOURCE_STATE_IDLE, 236 SOURCE_STATE_UNPLUG, 237 SOURCE_STATE_HPD_TIMEOUT = 4, 238 SOURCE_STATE_PLUG = 7 239 }; 240 241 enum { 242 DPTX_VM_RGB_6BIT, 243 DPTX_VM_RGB_8BIT, 244 DPTX_VM_RGB_10BIT, 245 DPTX_VM_RGB_12BIT, 246 DPTX_VM_RGB_16BIT, 247 DPTX_VM_YCBCR444_8BIT, 248 DPTX_VM_YCBCR444_10BIT, 249 DPTX_VM_YCBCR444_12BIT, 250 DPTX_VM_YCBCR444_16BIT, 251 DPTX_VM_YCBCR422_8BIT, 252 DPTX_VM_YCBCR422_10BIT, 253 DPTX_VM_YCBCR422_12BIT, 254 DPTX_VM_YCBCR422_16BIT, 255 DPTX_VM_YCBCR420_8BIT, 256 DPTX_VM_YCBCR420_10BIT, 257 DPTX_VM_YCBCR420_12BIT, 258 DPTX_VM_YCBCR420_16BIT, 259 }; 260 261 enum { 262 DPTX_MP_SINGLE_PIXEL, 263 DPTX_MP_DUAL_PIXEL, 264 DPTX_MP_QUAD_PIXEL, 265 }; 266 267 enum { 268 DPTX_SDP_VERTICAL_INTERVAL = BIT(0), 269 DPTX_SDP_HORIZONTAL_INTERVAL = BIT(1), 270 }; 271 272 enum { 273 DPTX_PHY_PATTERN_NONE, 274 DPTX_PHY_PATTERN_TPS_1, 275 DPTX_PHY_PATTERN_TPS_2, 276 DPTX_PHY_PATTERN_TPS_3, 277 DPTX_PHY_PATTERN_TPS_4, 278 DPTX_PHY_PATTERN_SERM, 279 DPTX_PHY_PATTERN_PBRS7, 280 DPTX_PHY_PATTERN_CUSTOM_80BIT, 281 DPTX_PHY_PATTERN_CP2520_1, 282 DPTX_PHY_PATTERN_CP2520_2, 283 }; 284 285 enum { 286 DPTX_PHYRATE_RBR, 287 DPTX_PHYRATE_HBR, 288 DPTX_PHYRATE_HBR2, 289 DPTX_PHYRATE_HBR3, 290 }; 291 292 struct dw_dp_output_format { 293 u32 bus_format; 294 u32 color_format; 295 u8 video_mapping; 296 u8 bpc; 297 u8 bpp; 298 }; 299 300 static const struct dw_dp_output_format possible_output_fmts[] = { 301 { MEDIA_BUS_FMT_RGB101010_1X30, DRM_COLOR_FORMAT_RGB444, 302 DPTX_VM_RGB_10BIT, 10, 30 }, 303 { MEDIA_BUS_FMT_RGB888_1X24, DRM_COLOR_FORMAT_RGB444, 304 DPTX_VM_RGB_8BIT, 8, 24 }, 305 { MEDIA_BUS_FMT_YUV10_1X30, DRM_COLOR_FORMAT_YCRCB444, 306 DPTX_VM_YCBCR444_10BIT, 10, 30 }, 307 { MEDIA_BUS_FMT_YUV8_1X24, DRM_COLOR_FORMAT_YCRCB444, 308 DPTX_VM_YCBCR444_8BIT, 8, 24}, 309 { MEDIA_BUS_FMT_YUYV10_1X20, DRM_COLOR_FORMAT_YCRCB422, 310 DPTX_VM_YCBCR422_10BIT, 10, 20 }, 311 { MEDIA_BUS_FMT_YUYV8_1X16, DRM_COLOR_FORMAT_YCRCB422, 312 DPTX_VM_YCBCR422_8BIT, 8, 16 }, 313 { MEDIA_BUS_FMT_UYYVYY10_0_5X30, DRM_COLOR_FORMAT_YCRCB420, 314 DPTX_VM_YCBCR420_10BIT, 10, 15 }, 315 { MEDIA_BUS_FMT_UYYVYY8_0_5X24, DRM_COLOR_FORMAT_YCRCB420, 316 DPTX_VM_YCBCR420_8BIT, 8, 12 }, 317 { MEDIA_BUS_FMT_RGB666_1X24_CPADHI, DRM_COLOR_FORMAT_RGB444, 318 DPTX_VM_RGB_6BIT, 6, 18 }, 319 }; 320 321 static int dw_dp_aux_write_data(struct dw_dp *dp, const u8 *buffer, size_t size) 322 { 323 size_t i, j; 324 325 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 326 size_t num = min_t(size_t, size - i * 4, 4); 327 u32 value = 0; 328 329 for (j = 0; j < num; j++) 330 value |= buffer[i * 4 + j] << (j * 8); 331 332 regmap_write(dp->regmap, DPTX_AUX_DATA0 + i * 4, value); 333 } 334 335 return size; 336 } 337 338 static int dw_dp_aux_read_data(struct dw_dp *dp, u8 *buffer, size_t size) 339 { 340 size_t i, j; 341 342 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 343 size_t num = min_t(size_t, size - i * 4, 4); 344 u32 value; 345 346 regmap_read(dp->regmap, DPTX_AUX_DATA0 + i * 4, &value); 347 348 for (j = 0; j < num; j++) 349 buffer[i * 4 + j] = value >> (j * 8); 350 } 351 352 return size; 353 } 354 355 static ssize_t dw_dp_aux_transfer(struct drm_dp_aux *aux, 356 struct drm_dp_aux_msg *msg) 357 { 358 u32 status, value; 359 ssize_t ret = 0; 360 int timeout = 0; 361 struct dw_dp *dp = dev_get_priv(aux->dev); 362 363 if (WARN_ON(msg->size > 16)) 364 return -E2BIG; 365 366 switch (msg->request & ~DP_AUX_I2C_MOT) { 367 case DP_AUX_NATIVE_WRITE: 368 case DP_AUX_I2C_WRITE: 369 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 370 ret = dw_dp_aux_write_data(dp, msg->buffer, msg->size); 371 if (ret < 0) 372 return ret; 373 break; 374 case DP_AUX_NATIVE_READ: 375 case DP_AUX_I2C_READ: 376 break; 377 default: 378 return -EINVAL; 379 } 380 381 if (msg->size > 0) 382 value = FIELD_PREP(AUX_LEN_REQ, msg->size - 1); 383 else 384 value = FIELD_PREP(I2C_ADDR_ONLY, 1); 385 386 value |= FIELD_PREP(AUX_CMD_TYPE, msg->request); 387 value |= FIELD_PREP(AUX_ADDR, msg->address); 388 regmap_write(dp->regmap, DPTX_AUX_CMD, value); 389 390 timeout = regmap_read_poll_timeout(dp->regmap, DPTX_GENERAL_INTERRUPT, 391 status, status & AUX_REPLY_EVENT, 392 200, 10); 393 394 if (timeout) { 395 printf("timeout waiting for AUX reply\n"); 396 return -ETIMEDOUT; 397 } 398 regmap_write(dp->regmap, DPTX_GENERAL_INTERRUPT, AUX_REPLY_EVENT); 399 400 regmap_read(dp->regmap, DPTX_AUX_STATUS, &value); 401 if (value & AUX_TIMEOUT) { 402 printf("aux timeout\n"); 403 return -ETIMEDOUT; 404 } 405 406 msg->reply = FIELD_GET(AUX_STATUS, value); 407 408 if (msg->size > 0 && msg->reply == DP_AUX_NATIVE_REPLY_ACK) { 409 if (msg->request & DP_AUX_I2C_READ) { 410 size_t count = FIELD_GET(AUX_BYTES_READ, value) - 1; 411 412 if (count != msg->size) { 413 printf("aux fail to read %lu bytes\n", count); 414 return -EBUSY; 415 } 416 417 ret = dw_dp_aux_read_data(dp, msg->buffer, count); 418 if (ret < 0) 419 return ret; 420 } 421 } 422 423 return ret; 424 } 425 426 static bool dw_dp_bandwidth_ok(struct dw_dp *dp, 427 const struct drm_display_mode *mode, u32 bpp, 428 unsigned int lanes, unsigned int rate) 429 { 430 u32 max_bw, req_bw; 431 432 req_bw = mode->clock * bpp / 8; 433 max_bw = lanes * rate; 434 if (req_bw > max_bw) 435 return false; 436 437 return true; 438 } 439 440 static void dw_dp_hpd_init(struct dw_dp *dp) 441 { 442 if (dm_gpio_is_valid(&dp->hpd_gpio)) { 443 regmap_update_bits(dp->regmap, DPTX_CCTL, FORCE_HPD, 444 FIELD_PREP(FORCE_HPD, 1)); 445 return; 446 } 447 448 /* Enable all HPD interrupts */ 449 regmap_update_bits(dp->regmap, DPTX_HPD_INTERRUPT_ENABLE, 450 HPD_UNPLUG_EN | HPD_PLUG_EN | HPD_IRQ_EN, 451 FIELD_PREP(HPD_UNPLUG_EN, 1) | 452 FIELD_PREP(HPD_PLUG_EN, 1) | 453 FIELD_PREP(HPD_IRQ_EN, 1)); 454 455 /* Enable all top-level interrupts */ 456 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, 457 HPD_EVENT_EN, FIELD_PREP(HPD_EVENT_EN, 1)); 458 } 459 460 static void dw_dp_aux_init(struct dw_dp *dp) 461 { 462 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, 463 FIELD_PREP(AUX_RESET, 1)); 464 udelay(10); 465 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, 466 FIELD_PREP(AUX_RESET, 0)); 467 468 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, 469 AUX_REPLY_EVENT_EN, 470 FIELD_PREP(AUX_REPLY_EVENT_EN, 1)); 471 } 472 473 static void dw_dp_init(struct dw_dp *dp) 474 { 475 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, 476 FIELD_PREP(CONTROLLER_RESET, 1)); 477 udelay(10); 478 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, 479 FIELD_PREP(CONTROLLER_RESET, 0)); 480 481 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, 482 FIELD_PREP(PHY_SOFT_RESET, 1)); 483 udelay(10); 484 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, 485 FIELD_PREP(PHY_SOFT_RESET, 0)); 486 487 regmap_update_bits(dp->regmap, DPTX_CCTL, DEFAULT_FAST_LINK_TRAIN_EN, 488 FIELD_PREP(DEFAULT_FAST_LINK_TRAIN_EN, 0)); 489 490 dw_dp_hpd_init(dp); 491 dw_dp_aux_init(dp); 492 } 493 494 static void dw_dp_phy_set_pattern(struct dw_dp *dp, u32 pattern) 495 { 496 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, TPS_SEL, 497 FIELD_PREP(TPS_SEL, pattern)); 498 } 499 500 static void dw_dp_phy_xmit_enable(struct dw_dp *dp, u32 lanes) 501 { 502 u32 xmit_enable; 503 504 switch (lanes) { 505 case 4: 506 case 2: 507 case 1: 508 xmit_enable = GENMASK(lanes - 1, 0); 509 break; 510 case 0: 511 default: 512 xmit_enable = 0; 513 break; 514 } 515 516 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, XMIT_ENABLE, 517 FIELD_PREP(XMIT_ENABLE, xmit_enable)); 518 } 519 520 static int dw_dp_link_power_up(struct dw_dp *dp) 521 { 522 struct dw_dp_link *link = &dp->link; 523 u8 value; 524 int ret; 525 526 if (link->revision < 0x11) 527 return 0; 528 529 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value); 530 if (ret < 0) 531 return ret; 532 533 value &= ~DP_SET_POWER_MASK; 534 value |= DP_SET_POWER_D0; 535 536 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value); 537 if (ret < 0) 538 return ret; 539 540 udelay(1000); 541 return 0; 542 } 543 544 static int dw_dp_link_probe(struct dw_dp *dp) 545 { 546 struct dw_dp_link *link = &dp->link; 547 u8 dpcd; 548 int ret; 549 550 ret = drm_dp_read_dpcd_caps(&dp->aux, link->dpcd); 551 if (ret < 0) 552 return ret; 553 554 ret = drm_dp_dpcd_readb(&dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, 555 &dpcd); 556 if (ret < 0) 557 return ret; 558 559 link->vsc_sdp_extension_for_colorimetry_supported = 560 !!(dpcd & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED); 561 562 link->revision = link->dpcd[DP_DPCD_REV]; 563 link->rate = drm_dp_max_link_rate(link->dpcd); 564 link->lanes = min_t(u8, dp->phy.attrs.bus_width, 565 drm_dp_max_lane_count(link->dpcd)); 566 567 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(link->dpcd); 568 link->caps.tps3_supported = drm_dp_tps3_supported(link->dpcd); 569 link->caps.tps4_supported = drm_dp_tps4_supported(link->dpcd); 570 link->caps.channel_coding = drm_dp_channel_coding_supported(link->dpcd); 571 link->caps.ssc = !!(link->dpcd[DP_MAX_DOWNSPREAD] & 572 DP_MAX_DOWNSPREAD_0_5); 573 574 return 0; 575 } 576 577 static int dw_dp_link_train_update_vs_emph(struct dw_dp *dp) 578 { 579 struct dw_dp_link *link = &dp->link; 580 struct drm_dp_link_train_set *request = &link->train.request; 581 union phy_configure_opts phy_cfg; 582 unsigned int lanes = link->lanes, *vs, *pe; 583 u8 buf[4]; 584 int i, ret; 585 586 vs = request->voltage_swing; 587 pe = request->pre_emphasis; 588 589 for (i = 0; i < lanes; i++) { 590 phy_cfg.dp.voltage[i] = vs[i]; 591 phy_cfg.dp.pre[i] = pe[i]; 592 } 593 phy_cfg.dp.lanes = lanes; 594 phy_cfg.dp.link_rate = link->rate / 100; 595 phy_cfg.dp.set_lanes = false; 596 phy_cfg.dp.set_rate = false; 597 phy_cfg.dp.set_voltages = true; 598 ret = generic_phy_configure(&dp->phy, &phy_cfg); 599 if (ret) 600 return ret; 601 602 for (i = 0; i < lanes; i++) 603 buf[i] = (vs[i] << DP_TRAIN_VOLTAGE_SWING_SHIFT) | 604 (pe[i] << DP_TRAIN_PRE_EMPHASIS_SHIFT); 605 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, lanes); 606 if (ret < 0) 607 return ret; 608 609 return 0; 610 } 611 612 static int dw_dp_link_configure(struct dw_dp *dp) 613 { 614 struct dw_dp_link *link = &dp->link; 615 union phy_configure_opts phy_cfg; 616 u8 buf[2]; 617 int ret, phy_rate; 618 619 /* Move PHY to P3 */ 620 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 621 FIELD_PREP(PHY_POWERDOWN, 0x3)); 622 623 phy_cfg.dp.lanes = link->lanes; 624 phy_cfg.dp.link_rate = link->rate / 100; 625 phy_cfg.dp.ssc = link->caps.ssc; 626 phy_cfg.dp.set_lanes = true; 627 phy_cfg.dp.set_rate = true; 628 phy_cfg.dp.set_voltages = false; 629 ret = generic_phy_configure(&dp->phy, &phy_cfg); 630 if (ret) 631 return ret; 632 633 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, 634 FIELD_PREP(PHY_LANES, link->lanes / 2)); 635 636 switch (link->rate) { 637 case 810000: 638 phy_rate = DPTX_PHYRATE_HBR3; 639 break; 640 case 540000: 641 phy_rate = DPTX_PHYRATE_HBR2; 642 break; 643 case 270000: 644 phy_rate = DPTX_PHYRATE_HBR; 645 break; 646 case 162000: 647 default: 648 phy_rate = DPTX_PHYRATE_RBR; 649 break; 650 } 651 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_RATE, 652 FIELD_PREP(PHY_RATE, phy_rate)); 653 654 /* Move PHY to P0 */ 655 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 656 FIELD_PREP(PHY_POWERDOWN, 0x0)); 657 658 dw_dp_phy_xmit_enable(dp, link->lanes); 659 660 buf[0] = drm_dp_link_rate_to_bw_code(link->rate); 661 buf[1] = link->lanes; 662 663 if (link->caps.enhanced_framing) { 664 buf[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 665 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 666 FIELD_PREP(ENHANCE_FRAMING_EN, 1)); 667 } else { 668 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 669 FIELD_PREP(ENHANCE_FRAMING_EN, 0)); 670 } 671 672 ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, sizeof(buf)); 673 if (ret < 0) 674 return ret; 675 676 buf[0] = link->caps.ssc ? DP_SPREAD_AMP_0_5 : 0; 677 buf[1] = link->caps.channel_coding ? DP_SET_ANSI_8B10B : 0; 678 679 ret = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, 680 sizeof(buf)); 681 if (ret < 0) 682 return ret; 683 684 return 0; 685 } 686 687 static void dw_dp_link_train_init(struct drm_dp_link_train *train) 688 { 689 struct drm_dp_link_train_set *request = &train->request; 690 struct drm_dp_link_train_set *adjust = &train->adjust; 691 unsigned int i; 692 693 for (i = 0; i < 4; i++) { 694 request->voltage_swing[i] = 0; 695 adjust->voltage_swing[i] = 0; 696 697 request->pre_emphasis[i] = 0; 698 adjust->pre_emphasis[i] = 0; 699 } 700 701 train->clock_recovered = false; 702 train->channel_equalized = false; 703 } 704 705 static int dw_dp_link_train_set_pattern(struct dw_dp *dp, u32 pattern) 706 { 707 u8 buf = 0; 708 int ret; 709 710 if (pattern && pattern != DP_TRAINING_PATTERN_4) { 711 buf |= DP_LINK_SCRAMBLING_DISABLE; 712 713 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, 714 FIELD_PREP(SCRAMBLE_DIS, 1)); 715 } else { 716 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, 717 FIELD_PREP(SCRAMBLE_DIS, 0)); 718 } 719 720 switch (pattern) { 721 case DP_TRAINING_PATTERN_DISABLE: 722 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE); 723 break; 724 case DP_TRAINING_PATTERN_1: 725 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_1); 726 break; 727 case DP_TRAINING_PATTERN_2: 728 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_2); 729 break; 730 case DP_TRAINING_PATTERN_3: 731 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_3); 732 break; 733 case DP_TRAINING_PATTERN_4: 734 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_4); 735 break; 736 default: 737 return -EINVAL; 738 } 739 740 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 741 buf | pattern); 742 if (ret < 0) 743 return ret; 744 745 return 0; 746 } 747 748 static void dw_dp_link_get_adjustments(struct dw_dp_link *link, 749 u8 status[DP_LINK_STATUS_SIZE]) 750 { 751 struct drm_dp_link_train_set *adjust = &link->train.adjust; 752 unsigned int i; 753 754 for (i = 0; i < link->lanes; i++) { 755 adjust->voltage_swing[i] = 756 drm_dp_get_adjust_request_voltage(status, i) >> 757 DP_TRAIN_VOLTAGE_SWING_SHIFT; 758 759 adjust->pre_emphasis[i] = 760 drm_dp_get_adjust_request_pre_emphasis(status, i) >> 761 DP_TRAIN_PRE_EMPHASIS_SHIFT; 762 } 763 } 764 765 static void dw_dp_link_train_adjust(struct drm_dp_link_train *train) 766 { 767 struct drm_dp_link_train_set *request = &train->request; 768 struct drm_dp_link_train_set *adjust = &train->adjust; 769 unsigned int i; 770 771 for (i = 0; i < 4; i++) 772 if (request->voltage_swing[i] != adjust->voltage_swing[i]) 773 request->voltage_swing[i] = adjust->voltage_swing[i]; 774 775 for (i = 0; i < 4; i++) 776 if (request->pre_emphasis[i] != adjust->pre_emphasis[i]) 777 request->pre_emphasis[i] = adjust->pre_emphasis[i]; 778 } 779 780 static int dw_dp_link_clock_recovery(struct dw_dp *dp) 781 { 782 struct dw_dp_link *link = &dp->link; 783 u8 status[DP_LINK_STATUS_SIZE]; 784 unsigned int tries = 0; 785 int ret; 786 787 ret = dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_1); 788 if (ret) 789 return ret; 790 791 for (;;) { 792 ret = dw_dp_link_train_update_vs_emph(dp); 793 if (ret) 794 return ret; 795 796 drm_dp_link_train_clock_recovery_delay(link->dpcd); 797 798 ret = drm_dp_dpcd_read_link_status(&dp->aux, status); 799 if (ret < 0) { 800 dev_err(dp->dev, "failed to read link status: %d\n", 801 ret); 802 return ret; 803 } 804 805 if (drm_dp_clock_recovery_ok(status, link->lanes)) { 806 link->train.clock_recovered = true; 807 break; 808 } 809 810 dw_dp_link_get_adjustments(link, status); 811 812 if (link->train.request.voltage_swing[0] == 813 link->train.adjust.voltage_swing[0]) 814 tries++; 815 else 816 tries = 0; 817 818 if (tries == 5) 819 break; 820 821 dw_dp_link_train_adjust(&link->train); 822 } 823 824 return 0; 825 } 826 827 static int dw_dp_link_channel_equalization(struct dw_dp *dp) 828 { 829 struct dw_dp_link *link = &dp->link; 830 u8 status[DP_LINK_STATUS_SIZE], pattern; 831 unsigned int tries; 832 int ret; 833 834 if (link->caps.tps4_supported) 835 pattern = DP_TRAINING_PATTERN_4; 836 else if (link->caps.tps3_supported) 837 pattern = DP_TRAINING_PATTERN_3; 838 else 839 pattern = DP_TRAINING_PATTERN_2; 840 ret = dw_dp_link_train_set_pattern(dp, pattern); 841 if (ret) 842 return ret; 843 844 for (tries = 1; tries < 5; tries++) { 845 ret = dw_dp_link_train_update_vs_emph(dp); 846 if (ret) 847 return ret; 848 849 drm_dp_link_train_channel_eq_delay(link->dpcd); 850 851 ret = drm_dp_dpcd_read_link_status(&dp->aux, status); 852 if (ret < 0) 853 return ret; 854 855 if (!drm_dp_clock_recovery_ok(status, link->lanes)) { 856 dev_err(dp->dev, 857 "clock recovery lost while eq\n"); 858 link->train.clock_recovered = false; 859 break; 860 } 861 862 if (drm_dp_channel_eq_ok(status, link->lanes)) { 863 link->train.channel_equalized = true; 864 break; 865 } 866 867 dw_dp_link_get_adjustments(link, status); 868 dw_dp_link_train_adjust(&link->train); 869 } 870 871 return 0; 872 } 873 874 static int dw_dp_link_downgrade(struct dw_dp *dp) 875 { 876 struct dw_dp_link *link = &dp->link; 877 struct dw_dp_video *video = &dp->video; 878 879 switch (link->rate) { 880 case 162000: 881 return -EINVAL; 882 case 270000: 883 link->rate = 162000; 884 break; 885 case 540000: 886 link->rate = 270000; 887 break; 888 case 810000: 889 link->rate = 540000; 890 break; 891 } 892 893 if (!dw_dp_bandwidth_ok(dp, &video->mode, video->bpp, link->lanes, 894 link->rate)) 895 return -E2BIG; 896 897 return 0; 898 } 899 900 static int dw_dp_link_train(struct dw_dp *dp) 901 { 902 struct dw_dp_link *link = &dp->link; 903 int ret; 904 905 retry: 906 dw_dp_link_train_init(&link->train); 907 908 printf("training link: %u lane%s at %u MHz\n", 909 link->lanes, (link->lanes > 1) ? "s" : "", link->rate / 100); 910 911 ret = dw_dp_link_configure(dp); 912 if (ret < 0) { 913 dev_err(dp->dev, "failed to configure DP link: %d\n", ret); 914 return ret; 915 } 916 917 ret = dw_dp_link_clock_recovery(dp); 918 if (ret < 0) { 919 dev_err(dp->dev, "clock recovery failed: %d\n", ret); 920 goto out; 921 } 922 923 if (!link->train.clock_recovered) { 924 dev_err(dp->dev, "clock recovery failed, downgrading link\n"); 925 926 ret = dw_dp_link_downgrade(dp); 927 if (ret < 0) 928 goto out; 929 else 930 goto retry; 931 } 932 933 printf("clock recovery succeeded\n"); 934 935 ret = dw_dp_link_channel_equalization(dp); 936 if (ret < 0) { 937 dev_err(dp->dev, "channel equalization failed: %d\n", ret); 938 goto out; 939 } 940 941 if (!link->train.channel_equalized) { 942 dev_err(dp->dev, 943 "channel equalization failed, downgrading link\n"); 944 945 ret = dw_dp_link_downgrade(dp); 946 if (ret < 0) 947 goto out; 948 else 949 goto retry; 950 } 951 952 printf("channel equalization succeeded\n"); 953 954 out: 955 dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE); 956 return ret; 957 } 958 959 static int dw_dp_link_enable(struct dw_dp *dp) 960 { 961 int ret; 962 963 ret = dw_dp_link_power_up(dp); 964 if (ret < 0) 965 return ret; 966 967 ret = dw_dp_link_train(dp); 968 if (ret < 0) { 969 dev_err(dp->dev, "link training failed: %d\n", ret); 970 return ret; 971 } 972 973 return 0; 974 } 975 976 static int dw_dp_set_phy_default_config(struct dw_dp *dp) 977 { 978 struct dw_dp_link *link = &dp->link; 979 union phy_configure_opts phy_cfg; 980 int ret, i, phy_rate; 981 982 link->vsc_sdp_extension_for_colorimetry_supported = false; 983 link->rate = 270000; 984 link->lanes = dp->phy.attrs.bus_width; 985 986 link->caps.enhanced_framing = true; 987 link->caps.channel_coding = true; 988 link->caps.ssc = true; 989 990 /* Move PHY to P3 */ 991 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 992 FIELD_PREP(PHY_POWERDOWN, 0x3)); 993 994 for (i = 0; i < link->lanes; i++) { 995 phy_cfg.dp.voltage[i] = 3; 996 phy_cfg.dp.pre[i] = 0; 997 } 998 phy_cfg.dp.lanes = link->lanes; 999 phy_cfg.dp.link_rate = link->rate / 100; 1000 phy_cfg.dp.ssc = link->caps.ssc; 1001 phy_cfg.dp.set_lanes = true; 1002 phy_cfg.dp.set_rate = true; 1003 phy_cfg.dp.set_voltages = true; 1004 ret = generic_phy_configure(&dp->phy, &phy_cfg); 1005 if (ret) 1006 return ret; 1007 1008 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, 1009 FIELD_PREP(PHY_LANES, link->lanes / 2)); 1010 1011 switch (link->rate) { 1012 case 810000: 1013 phy_rate = DPTX_PHYRATE_HBR3; 1014 break; 1015 case 540000: 1016 phy_rate = DPTX_PHYRATE_HBR2; 1017 break; 1018 case 270000: 1019 phy_rate = DPTX_PHYRATE_HBR; 1020 break; 1021 case 162000: 1022 default: 1023 phy_rate = DPTX_PHYRATE_RBR; 1024 break; 1025 } 1026 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_RATE, 1027 FIELD_PREP(PHY_RATE, phy_rate)); 1028 1029 /* Move PHY to P0 */ 1030 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 1031 FIELD_PREP(PHY_POWERDOWN, 0x0)); 1032 1033 dw_dp_phy_xmit_enable(dp, link->lanes); 1034 1035 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 1036 FIELD_PREP(ENHANCE_FRAMING_EN, 1)); 1037 1038 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE); 1039 return 0; 1040 } 1041 1042 static int dw_dp_send_sdp(struct dw_dp *dp, struct dw_dp_sdp *sdp) 1043 { 1044 const u8 *payload = sdp->db; 1045 u32 reg; 1046 int i, nr = 0; 1047 1048 reg = DPTX_SDP_REGISTER_BANK + nr * 9 * 4; 1049 1050 /* SDP header */ 1051 regmap_write(dp->regmap, reg, get_unaligned_le32(&sdp->header)); 1052 1053 /* SDP data payload */ 1054 for (i = 1; i < 9; i++, payload += 4) 1055 regmap_write(dp->regmap, reg + i * 4, 1056 FIELD_PREP(SDP_REGS, get_unaligned_le32(payload))); 1057 1058 if (sdp->flags & DPTX_SDP_VERTICAL_INTERVAL) 1059 regmap_update_bits(dp->regmap, DPTX_SDP_VERTICAL_CTRL, 1060 EN_VERTICAL_SDP << nr, 1061 EN_VERTICAL_SDP << nr); 1062 1063 if (sdp->flags & DPTX_SDP_HORIZONTAL_INTERVAL) 1064 regmap_update_bits(dp->regmap, DPTX_SDP_HORIZONTAL_CTRL, 1065 EN_HORIZONTAL_SDP << nr, 1066 EN_HORIZONTAL_SDP << nr); 1067 1068 return 0; 1069 } 1070 1071 static void dw_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, 1072 struct dw_dp_sdp *sdp) 1073 { 1074 sdp->header.HB0 = 0; 1075 sdp->header.HB1 = DP_SDP_VSC; 1076 sdp->header.HB2 = vsc->revision; 1077 sdp->header.HB3 = vsc->length; 1078 1079 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; 1080 sdp->db[16] |= vsc->colorimetry & 0xf; 1081 1082 switch (vsc->bpc) { 1083 case 8: 1084 sdp->db[17] = 0x1; 1085 break; 1086 case 10: 1087 sdp->db[17] = 0x2; 1088 break; 1089 case 12: 1090 sdp->db[17] = 0x3; 1091 break; 1092 case 16: 1093 sdp->db[17] = 0x4; 1094 break; 1095 case 6: 1096 default: 1097 break; 1098 } 1099 1100 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) 1101 sdp->db[17] |= 0x80; 1102 1103 sdp->db[18] = vsc->content_type & 0x7; 1104 1105 sdp->flags |= DPTX_SDP_VERTICAL_INTERVAL; 1106 } 1107 1108 static int dw_dp_send_vsc_sdp(struct dw_dp *dp) 1109 { 1110 struct dw_dp_video *video = &dp->video; 1111 struct drm_dp_vsc_sdp vsc = {}; 1112 struct dw_dp_sdp sdp = {}; 1113 1114 vsc.revision = 0x5; 1115 vsc.length = 0x13; 1116 1117 switch (video->color_format) { 1118 case DRM_COLOR_FORMAT_YCRCB444: 1119 vsc.pixelformat = DP_PIXELFORMAT_YUV444; 1120 break; 1121 case DRM_COLOR_FORMAT_YCRCB420: 1122 vsc.pixelformat = DP_PIXELFORMAT_YUV420; 1123 break; 1124 case DRM_COLOR_FORMAT_YCRCB422: 1125 vsc.pixelformat = DP_PIXELFORMAT_YUV422; 1126 break; 1127 case DRM_COLOR_FORMAT_RGB444: 1128 default: 1129 vsc.pixelformat = DP_PIXELFORMAT_RGB; 1130 break; 1131 } 1132 1133 if (video->color_format == DRM_COLOR_FORMAT_RGB444) 1134 vsc.colorimetry = DP_COLORIMETRY_DEFAULT; 1135 else 1136 vsc.colorimetry = DP_COLORIMETRY_BT709_YCC; 1137 1138 vsc.bpc = video->bpc; 1139 vsc.dynamic_range = DP_DYNAMIC_RANGE_CTA; 1140 vsc.content_type = DP_CONTENT_TYPE_NOT_DEFINED; 1141 1142 dw_dp_vsc_sdp_pack(&vsc, &sdp); 1143 1144 return dw_dp_send_sdp(dp, &sdp); 1145 } 1146 1147 static int dw_dp_video_set_pixel_mode(struct dw_dp *dp, u8 pixel_mode) 1148 { 1149 switch (pixel_mode) { 1150 case DPTX_MP_SINGLE_PIXEL: 1151 case DPTX_MP_DUAL_PIXEL: 1152 case DPTX_MP_QUAD_PIXEL: 1153 break; 1154 default: 1155 return -EINVAL; 1156 } 1157 1158 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, PIXEL_MODE_SELECT, 1159 FIELD_PREP(PIXEL_MODE_SELECT, pixel_mode)); 1160 1161 return 0; 1162 } 1163 1164 static int dw_dp_video_set_msa(struct dw_dp *dp, u8 color_format, u8 bpc, 1165 u16 vstart, u16 hstart) 1166 { 1167 struct dw_dp_link *link = &dp->link; 1168 u16 misc = 0; 1169 1170 if (link->vsc_sdp_extension_for_colorimetry_supported) 1171 misc |= DP_MSA_MISC_COLOR_VSC_SDP; 1172 1173 switch (color_format) { 1174 case DRM_COLOR_FORMAT_RGB444: 1175 misc |= DP_MSA_MISC_COLOR_RGB; 1176 break; 1177 case DRM_COLOR_FORMAT_YCRCB444: 1178 misc |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 1179 break; 1180 case DRM_COLOR_FORMAT_YCRCB422: 1181 misc |= DP_MSA_MISC_COLOR_YCBCR_422_BT709; 1182 break; 1183 case DRM_COLOR_FORMAT_YCRCB420: 1184 break; 1185 default: 1186 return -EINVAL; 1187 } 1188 1189 switch (bpc) { 1190 case 6: 1191 misc |= DP_MSA_MISC_6_BPC; 1192 break; 1193 case 8: 1194 misc |= DP_MSA_MISC_8_BPC; 1195 break; 1196 case 10: 1197 misc |= DP_MSA_MISC_10_BPC; 1198 break; 1199 case 12: 1200 misc |= DP_MSA_MISC_12_BPC; 1201 break; 1202 case 16: 1203 misc |= DP_MSA_MISC_16_BPC; 1204 break; 1205 default: 1206 return -EINVAL; 1207 } 1208 1209 regmap_write(dp->regmap, DPTX_VIDEO_MSA1, 1210 FIELD_PREP(VSTART, vstart) | FIELD_PREP(HSTART, hstart)); 1211 regmap_write(dp->regmap, DPTX_VIDEO_MSA2, FIELD_PREP(MISC0, misc)); 1212 regmap_write(dp->regmap, DPTX_VIDEO_MSA3, FIELD_PREP(MISC1, misc >> 8)); 1213 1214 return 0; 1215 } 1216 1217 static int dw_dp_video_enable(struct dw_dp *dp) 1218 { 1219 struct dw_dp_video *video = &dp->video; 1220 struct dw_dp_link *link = &dp->link; 1221 struct drm_display_mode *mode = &video->mode; 1222 u8 color_format = video->color_format; 1223 u8 bpc = video->bpc; 1224 u8 pixel_mode = video->pixel_mode; 1225 u8 bpp = video->bpp, init_threshold, vic; 1226 u32 hactive, hblank, h_sync_width, h_front_porch; 1227 u32 vactive, vblank, v_sync_width, v_front_porch; 1228 u32 vstart = mode->vtotal - mode->vsync_start; 1229 u32 hstart = mode->htotal - mode->hsync_start; 1230 u32 peak_stream_bandwidth, link_bandwidth; 1231 u32 average_bytes_per_tu, average_bytes_per_tu_frac; 1232 u32 ts, hblank_interval; 1233 u32 value; 1234 int ret; 1235 1236 ret = dw_dp_video_set_pixel_mode(dp, pixel_mode); 1237 if (ret) 1238 return ret; 1239 1240 ret = dw_dp_video_set_msa(dp, color_format, bpc, vstart, hstart); 1241 if (ret) 1242 return ret; 1243 1244 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_MAPPING, 1245 FIELD_PREP(VIDEO_MAPPING, video->video_mapping)); 1246 1247 /* Configure DPTX_VINPUT_POLARITY_CTRL register */ 1248 value = 0; 1249 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1250 value |= FIELD_PREP(HSYNC_IN_POLARITY, 1); 1251 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1252 value |= FIELD_PREP(VSYNC_IN_POLARITY, 1); 1253 regmap_write(dp->regmap, DPTX_VINPUT_POLARITY_CTRL, value); 1254 1255 /* Configure DPTX_VIDEO_CONFIG1 register */ 1256 hactive = mode->hdisplay; 1257 hblank = mode->htotal - mode->hdisplay; 1258 value = FIELD_PREP(HACTIVE, hactive) | FIELD_PREP(HBLANK, hblank); 1259 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1260 value |= FIELD_PREP(I_P, 1); 1261 vic = drm_match_cea_mode(mode); 1262 if (vic == 5 || vic == 6 || vic == 7 || 1263 vic == 10 || vic == 11 || vic == 20 || 1264 vic == 21 || vic == 22 || vic == 39 || 1265 vic == 25 || vic == 26 || vic == 40 || 1266 vic == 44 || vic == 45 || vic == 46 || 1267 vic == 50 || vic == 51 || vic == 54 || 1268 vic == 55 || vic == 58 || vic == 59) 1269 value |= R_V_BLANK_IN_OSC; 1270 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG1, value); 1271 1272 /* Configure DPTX_VIDEO_CONFIG2 register */ 1273 vblank = mode->vtotal - mode->vdisplay; 1274 vactive = mode->vdisplay; 1275 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG2, 1276 FIELD_PREP(VBLANK, vblank) | FIELD_PREP(VACTIVE, vactive)); 1277 1278 /* Configure DPTX_VIDEO_CONFIG3 register */ 1279 h_sync_width = mode->hsync_end - mode->hsync_start; 1280 h_front_porch = mode->hsync_start - mode->hdisplay; 1281 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG3, 1282 FIELD_PREP(H_SYNC_WIDTH, h_sync_width) | 1283 FIELD_PREP(H_FRONT_PORCH, h_front_porch)); 1284 1285 /* Configure DPTX_VIDEO_CONFIG4 register */ 1286 v_sync_width = mode->vsync_end - mode->vsync_start; 1287 v_front_porch = mode->vsync_start - mode->vdisplay; 1288 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG4, 1289 FIELD_PREP(V_SYNC_WIDTH, v_sync_width) | 1290 FIELD_PREP(V_FRONT_PORCH, v_front_porch)); 1291 1292 /* Configure DPTX_VIDEO_CONFIG5 register */ 1293 peak_stream_bandwidth = mode->clock * bpp / 8; 1294 link_bandwidth = (link->rate / 1000) * link->lanes; 1295 ts = peak_stream_bandwidth * 64 / link_bandwidth; 1296 average_bytes_per_tu = ts / 1000; 1297 average_bytes_per_tu_frac = ts / 100 - average_bytes_per_tu * 10; 1298 if (pixel_mode == DPTX_MP_SINGLE_PIXEL) { 1299 if (average_bytes_per_tu < 6) 1300 init_threshold = 32; 1301 else if (hblank <= 80 && 1302 color_format != DRM_COLOR_FORMAT_YCRCB420) 1303 init_threshold = 12; 1304 else if (hblank <= 40 && 1305 color_format == DRM_COLOR_FORMAT_YCRCB420) 1306 init_threshold = 3; 1307 else 1308 init_threshold = 16; 1309 } else { 1310 u32 t1 = 0, t2 = 0, t3 = 0; 1311 1312 switch (bpc) { 1313 case 6: 1314 t1 = (4 * 1000 / 9) * link->lanes; 1315 break; 1316 case 8: 1317 if (color_format == DRM_COLOR_FORMAT_YCRCB422) { 1318 t1 = (1000 / 2) * link->lanes; 1319 } else { 1320 if (pixel_mode == DPTX_MP_DUAL_PIXEL) 1321 t1 = (1000 / 3) * link->lanes; 1322 else 1323 t1 = (3000 / 16) * link->lanes; 1324 } 1325 break; 1326 case 10: 1327 if (color_format == DRM_COLOR_FORMAT_YCRCB422) 1328 t1 = (2000 / 5) * link->lanes; 1329 else 1330 t1 = (4000 / 15) * link->lanes; 1331 break; 1332 case 12: 1333 if (color_format == DRM_COLOR_FORMAT_YCRCB422) { 1334 if (pixel_mode == DPTX_MP_DUAL_PIXEL) 1335 t1 = (1000 / 6) * link->lanes; 1336 else 1337 t1 = (1000 / 3) * link->lanes; 1338 } else { 1339 t1 = (2000 / 9) * link->lanes; 1340 } 1341 break; 1342 case 16: 1343 if (color_format != DRM_COLOR_FORMAT_YCRCB422 && 1344 pixel_mode == DPTX_MP_DUAL_PIXEL) 1345 t1 = (1000 / 6) * link->lanes; 1346 else 1347 t1 = (1000 / 4) * link->lanes; 1348 break; 1349 default: 1350 return -EINVAL; 1351 } 1352 1353 if (color_format == DRM_COLOR_FORMAT_YCRCB420) 1354 t2 = (link->rate / 4) * 1000 / (mode->clock / 2); 1355 else 1356 t2 = (link->rate / 4) * 1000 / mode->clock; 1357 1358 if (average_bytes_per_tu_frac) 1359 t3 = average_bytes_per_tu + 1; 1360 else 1361 t3 = average_bytes_per_tu; 1362 init_threshold = t1 * t2 * t3 / (1000 * 1000); 1363 if (init_threshold <= 16 || average_bytes_per_tu < 10) 1364 init_threshold = 40; 1365 } 1366 1367 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG5, 1368 FIELD_PREP(INIT_THRESHOLD_HI, init_threshold >> 6) | 1369 FIELD_PREP(AVERAGE_BYTES_PER_TU_FRAC, 1370 average_bytes_per_tu_frac) | 1371 FIELD_PREP(INIT_THRESHOLD, init_threshold) | 1372 FIELD_PREP(AVERAGE_BYTES_PER_TU, average_bytes_per_tu)); 1373 1374 /* Configure DPTX_VIDEO_HBLANK_INTERVAL register */ 1375 hblank_interval = hblank * (link->rate / 4) / mode->clock; 1376 regmap_write(dp->regmap, DPTX_VIDEO_HBLANK_INTERVAL, 1377 FIELD_PREP(HBLANK_INTERVAL_EN, 1) | 1378 FIELD_PREP(HBLANK_INTERVAL, hblank_interval)); 1379 1380 /* Video stream enable */ 1381 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_STREAM_ENABLE, 1382 FIELD_PREP(VIDEO_STREAM_ENABLE, 1)); 1383 1384 if (link->vsc_sdp_extension_for_colorimetry_supported) 1385 dw_dp_send_vsc_sdp(dp); 1386 1387 return 0; 1388 } 1389 1390 static bool dw_dp_detect(struct dw_dp *dp) 1391 { 1392 u32 value; 1393 1394 if (dm_gpio_is_valid(&dp->hpd_gpio)) 1395 return dm_gpio_get_value(&dp->hpd_gpio); 1396 1397 regmap_read(dp->regmap, DPTX_GENERAL_INTERRUPT, &value); 1398 if (value & HPD_EVENT) { 1399 regmap_read(dp->regmap, DPTX_HPD_STATUS, &value); 1400 if ((value & HPD_HOT_PLUG) && 1401 (FIELD_GET(HPD_STATE, value) == SOURCE_STATE_PLUG)) { 1402 regmap_write(dp->regmap, DPTX_HPD_STATUS, HPD_HOT_PLUG); 1403 return true; 1404 } 1405 } 1406 1407 return false; 1408 } 1409 1410 static int dw_dp_connector_pre_init(struct display_state *state) 1411 { 1412 struct connector_state *conn_state = &state->conn_state; 1413 1414 conn_state->type = DRM_MODE_CONNECTOR_DisplayPort; 1415 1416 return 0; 1417 } 1418 1419 static int dw_dp_connector_init(struct display_state *state) 1420 { 1421 struct connector_state *conn_state = &state->conn_state; 1422 struct dw_dp *dp = dev_get_priv(conn_state->dev); 1423 int ret; 1424 1425 conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_DP1 : VOP_OUTPUT_IF_DP0; 1426 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1427 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 1428 1429 clk_set_defaults(dp->dev); 1430 1431 reset_assert(&dp->reset); 1432 udelay(20); 1433 reset_deassert(&dp->reset); 1434 1435 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, 1436 dp->id); 1437 dw_dp_init(dp); 1438 ret = generic_phy_power_on(&dp->phy); 1439 1440 return ret; 1441 } 1442 1443 static int dw_dp_connector_get_edid(struct display_state *state) 1444 { 1445 int ret; 1446 struct connector_state *conn_state = &state->conn_state; 1447 struct dw_dp *dp = dev_get_priv(conn_state->dev); 1448 1449 ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); 1450 1451 return ret; 1452 } 1453 1454 static int dw_dp_connector_enable(struct display_state *state) 1455 { 1456 struct connector_state *conn_state = &state->conn_state; 1457 struct drm_display_mode *mode = &conn_state->mode; 1458 struct dw_dp *dp = dev_get_priv(conn_state->dev); 1459 struct dw_dp_video *video = &dp->video; 1460 int ret; 1461 1462 memcpy(&video->mode, mode, sizeof(video->mode)); 1463 video->pixel_mode = DPTX_MP_QUAD_PIXEL; 1464 1465 if (dp->force_output) { 1466 ret = dw_dp_set_phy_default_config(dp); 1467 if (ret < 0) 1468 printf("failed to set phy_default config: %d\n", ret); 1469 } else { 1470 ret = dw_dp_link_enable(dp); 1471 if (ret < 0) { 1472 printf("failed to enable link: %d\n", ret); 1473 return ret; 1474 } 1475 } 1476 1477 ret = dw_dp_video_enable(dp); 1478 if (ret < 0) { 1479 printf("failed to enable video: %d\n", ret); 1480 return ret; 1481 } 1482 1483 return 0; 1484 } 1485 1486 static int dw_dp_connector_disable(struct display_state *state) 1487 { 1488 /* TODO */ 1489 1490 return 0; 1491 } 1492 1493 static int dw_dp_connector_detect(struct display_state *state) 1494 { 1495 struct connector_state *conn_state = &state->conn_state; 1496 struct dw_dp *dp = dev_get_priv(conn_state->dev); 1497 int status, tries; 1498 1499 for (tries = 0; tries < 100; tries++) { 1500 status = dw_dp_detect(dp); 1501 if (status) 1502 break; 1503 mdelay(2); 1504 } 1505 1506 if (state->force_output && !status) 1507 dp->force_output = true; 1508 1509 if (!status && !dp->force_output) 1510 generic_phy_power_off(&dp->phy); 1511 1512 return status; 1513 } 1514 1515 static int dw_dp_mode_valid(struct dw_dp *dp, struct hdmi_edid_data *edid_data) 1516 { 1517 struct dw_dp_link *link = &dp->link; 1518 struct drm_display_info *di = &edid_data->display_info; 1519 u32 min_bpp; 1520 int i; 1521 1522 if (di->color_formats & DRM_COLOR_FORMAT_YCRCB420 && 1523 link->vsc_sdp_extension_for_colorimetry_supported) 1524 min_bpp = 12; 1525 else if (di->color_formats & DRM_COLOR_FORMAT_YCRCB422) 1526 min_bpp = 16; 1527 else if (di->color_formats & DRM_COLOR_FORMAT_RGB444) 1528 min_bpp = 18; 1529 else 1530 min_bpp = 24; 1531 1532 for (i = 0; i < edid_data->modes; i++) { 1533 if (!dw_dp_bandwidth_ok(dp, &edid_data->mode_buf[i], min_bpp, link->lanes, 1534 link->rate)) 1535 edid_data->mode_buf[i].invalid = true; 1536 } 1537 1538 return 0; 1539 } 1540 1541 static u32 dw_dp_get_output_bus_fmts(struct dw_dp *dp, struct hdmi_edid_data *edid_data) 1542 { 1543 struct dw_dp_link *link = &dp->link; 1544 unsigned int i; 1545 1546 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 1547 const struct dw_dp_output_format *fmt = &possible_output_fmts[i]; 1548 1549 if (fmt->bpc > edid_data->display_info.bpc) 1550 continue; 1551 1552 if (!(edid_data->display_info.color_formats & fmt->color_format)) 1553 continue; 1554 1555 if (fmt->color_format == DRM_COLOR_FORMAT_YCRCB420 && 1556 !link->vsc_sdp_extension_for_colorimetry_supported) 1557 continue; 1558 1559 if (drm_mode_is_420(&edid_data->display_info, edid_data->preferred_mode) && 1560 fmt->color_format != DRM_COLOR_FORMAT_YCRCB420) 1561 continue; 1562 1563 if (!dw_dp_bandwidth_ok(dp, edid_data->preferred_mode, fmt->bpp, link->lanes, 1564 link->rate)) 1565 continue; 1566 1567 break; 1568 } 1569 1570 if (i == ARRAY_SIZE(possible_output_fmts)) 1571 return 1; 1572 1573 return i; 1574 } 1575 1576 static int dw_dp_get_force_output_fmts(struct display_state *state) 1577 { 1578 int i; 1579 1580 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 1581 const struct dw_dp_output_format *fmt = &possible_output_fmts[i]; 1582 1583 if (fmt->bus_format == state->force_bus_format) 1584 break; 1585 } 1586 1587 if (i == ARRAY_SIZE(possible_output_fmts)) 1588 return 1; 1589 1590 return i; 1591 } 1592 1593 static int dw_dp_connector_get_timing(struct display_state *state) 1594 { 1595 int ret, i; 1596 struct connector_state *conn_state = &state->conn_state; 1597 struct dw_dp *dp = dev_get_priv(conn_state->dev); 1598 struct dw_dp_video *video = &dp->video; 1599 struct drm_display_mode *mode = &conn_state->mode; 1600 struct hdmi_edid_data edid_data; 1601 struct drm_display_mode *mode_buf; 1602 u32 bus_fmt; 1603 1604 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 1605 if (!mode_buf) 1606 return -ENOMEM; 1607 1608 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 1609 memset(&edid_data, 0, sizeof(struct hdmi_edid_data)); 1610 edid_data.mode_buf = mode_buf; 1611 1612 if (!dp->force_output) { 1613 ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); 1614 if (!ret) 1615 ret = drm_add_edid_modes(&edid_data, conn_state->edid); 1616 1617 if (ret < 0) { 1618 printf("failed to get edid\n"); 1619 goto err; 1620 } 1621 1622 ret = dw_dp_link_probe(dp); 1623 if (ret) { 1624 printf("failed to probe DP link: %d\n", ret); 1625 ret = -EINVAL; 1626 goto err; 1627 } 1628 1629 drm_rk_filter_whitelist(&edid_data); 1630 drm_mode_max_resolution_filter(&edid_data, 1631 &state->crtc_state.max_output); 1632 dw_dp_mode_valid(dp, &edid_data); 1633 1634 if (!drm_mode_prune_invalid(&edid_data)) { 1635 printf("can't find valid hdmi mode\n"); 1636 ret = -EINVAL; 1637 goto err; 1638 } 1639 1640 for (i = 0; i < edid_data.modes; i++) 1641 edid_data.mode_buf[i].vrefresh = 1642 drm_mode_vrefresh(&edid_data.mode_buf[i]); 1643 1644 drm_mode_sort(&edid_data); 1645 memcpy(mode, edid_data.preferred_mode, sizeof(struct drm_display_mode)); 1646 } 1647 1648 if (state->force_output) 1649 bus_fmt = dw_dp_get_force_output_fmts(state); 1650 else 1651 bus_fmt = dw_dp_get_output_bus_fmts(dp, &edid_data); 1652 1653 video->video_mapping = possible_output_fmts[bus_fmt].video_mapping; 1654 video->color_format = possible_output_fmts[bus_fmt].color_format; 1655 video->bus_format = possible_output_fmts[bus_fmt].bus_format; 1656 video->bpc = possible_output_fmts[bus_fmt].bpc; 1657 video->bpp = possible_output_fmts[bus_fmt].bpp; 1658 1659 switch (video->color_format) { 1660 case DRM_COLOR_FORMAT_YCRCB420: 1661 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420; 1662 break; 1663 case DRM_COLOR_FORMAT_YCRCB422: 1664 conn_state->output_mode = ROCKCHIP_OUT_MODE_S888_DUMMY; 1665 break; 1666 case DRM_COLOR_FORMAT_RGB444: 1667 case DRM_COLOR_FORMAT_YCRCB444: 1668 default: 1669 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1670 break; 1671 } 1672 1673 conn_state->bus_format = video->bus_format; 1674 err: 1675 free(mode_buf); 1676 1677 return 0; 1678 } 1679 1680 static const struct rockchip_connector_funcs dw_dp_connector_funcs = { 1681 .pre_init = dw_dp_connector_pre_init, 1682 .init = dw_dp_connector_init, 1683 .get_edid = dw_dp_connector_get_edid, 1684 .enable = dw_dp_connector_enable, 1685 .disable = dw_dp_connector_disable, 1686 .detect = dw_dp_connector_detect, 1687 .get_timing = dw_dp_connector_get_timing, 1688 }; 1689 1690 static int dw_dp_ddc_init(struct dw_dp *dp) 1691 { 1692 dp->aux.name = "dw-dp"; 1693 dp->aux.dev = dp->dev; 1694 dp->aux.transfer = dw_dp_aux_transfer; 1695 dp->aux.ddc.ddc_xfer = drm_dp_i2c_xfer; 1696 1697 return 0; 1698 } 1699 1700 static int dw_dp_probe(struct udevice *dev) 1701 { 1702 struct dw_dp *dp = dev_get_priv(dev); 1703 int ret; 1704 1705 ret = regmap_init_mem(dev, &dp->regmap); 1706 if (ret) 1707 return ret; 1708 1709 dp->id = of_alias_get_id(ofnode_to_np(dev->node), "dp"); 1710 if (dp->id < 0) 1711 dp->id = 0; 1712 1713 ret = reset_get_by_index(dev, 0, &dp->reset); 1714 if (ret) { 1715 dev_err(dev, "failed to get reset control: %d\n", ret); 1716 return ret; 1717 } 1718 1719 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 1720 GPIOD_IS_IN); 1721 if (ret && ret != -ENOENT) { 1722 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 1723 return ret; 1724 } 1725 1726 generic_phy_get_by_index(dev, 0, &dp->phy); 1727 1728 dp->dev = dev; 1729 1730 dw_dp_ddc_init(dp); 1731 1732 return 0; 1733 } 1734 1735 static const struct rockchip_connector rk3588_dp_driver_data = { 1736 .funcs = &dw_dp_connector_funcs, 1737 }; 1738 1739 static const struct udevice_id dw_dp_ids[] = { 1740 { 1741 .compatible = "rockchip,rk3588-dp", 1742 .data = (ulong)&rk3588_dp_driver_data 1743 }, 1744 {} 1745 }; 1746 1747 U_BOOT_DRIVER(dw_dp) = { 1748 .name = "dw_dp", 1749 .id = UCLASS_DISPLAY, 1750 .of_match = dw_dp_ids, 1751 .probe = dw_dp_probe, 1752 .priv_auto_alloc_size = sizeof(struct dw_dp), 1753 }; 1754 1755