1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Rockchip USBDP Combo PHY with Samsung IP block driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd 6 */ 7 8 #include <config.h> 9 #include <common.h> 10 #include <errno.h> 11 #include <malloc.h> 12 #include <asm/unaligned.h> 13 #include <asm/io.h> 14 #include <clk.h> 15 #include <dm/device.h> 16 #include <dm/of_access.h> 17 #include <dm/read.h> 18 #include <generic-phy.h> 19 #include <linux/bitfield.h> 20 #include <linux/hdmi.h> 21 #include <linux/media-bus-format.h> 22 #include <linux/list.h> 23 #include <asm/gpio.h> 24 #include <generic-phy.h> 25 #include <regmap.h> 26 #include <reset.h> 27 #include <drm/drm_dp_helper.h> 28 29 #include "rockchip_display.h" 30 #include "rockchip_crtc.h" 31 #include "rockchip_connector.h" 32 33 #define DPTX_VERSION_NUMBER 0x0000 34 #define DPTX_VERSION_TYPE 0x0004 35 #define DPTX_ID 0x0008 36 37 #define DPTX_CONFIG_REG1 0x0100 38 #define DPTX_CONFIG_REG2 0x0104 39 #define DPTX_CONFIG_REG3 0x0108 40 41 #define DPTX_CCTL 0x0200 42 #define FORCE_HPD BIT(4) 43 #define DEFAULT_FAST_LINK_TRAIN_EN BIT(2) 44 #define ENHANCE_FRAMING_EN BIT(1) 45 #define SCRAMBLE_DIS BIT(0) 46 #define DPTX_SOFT_RESET_CTRL 0x0204 47 #define VIDEO_RESET BIT(5) 48 #define AUX_RESET BIT(4) 49 #define AUDIO_SAMPLER_RESET BIT(3) 50 #define PHY_SOFT_RESET BIT(1) 51 #define CONTROLLER_RESET BIT(0) 52 53 #define DPTX_VSAMPLE_CTRL 0x0300 54 #define PIXEL_MODE_SELECT GENMASK(22, 21) 55 #define VIDEO_MAPPING GENMASK(20, 16) 56 #define VIDEO_STREAM_ENABLE BIT(5) 57 #define DPTX_VSAMPLE_STUFF_CTRL1 0x0304 58 #define DPTX_VSAMPLE_STUFF_CTRL2 0x0308 59 #define DPTX_VINPUT_POLARITY_CTRL 0x030c 60 #define DE_IN_POLARITY BIT(2) 61 #define HSYNC_IN_POLARITY BIT(1) 62 #define VSYNC_IN_POLARITY BIT(0) 63 #define DPTX_VIDEO_CONFIG1 0x0310 64 #define HACTIVE GENMASK(31, 16) 65 #define HBLANK GENMASK(15, 2) 66 #define I_P BIT(1) 67 #define R_V_BLANK_IN_OSC BIT(0) 68 #define DPTX_VIDEO_CONFIG2 0x0314 69 #define VBLANK GENMASK(31, 16) 70 #define VACTIVE GENMASK(15, 0) 71 #define DPTX_VIDEO_CONFIG3 0x0318 72 #define H_SYNC_WIDTH GENMASK(31, 16) 73 #define H_FRONT_PORCH GENMASK(15, 0) 74 #define DPTX_VIDEO_CONFIG4 0x031c 75 #define V_SYNC_WIDTH GENMASK(31, 16) 76 #define V_FRONT_PORCH GENMASK(15, 0) 77 #define DPTX_VIDEO_CONFIG5 0x0320 78 #define INIT_THRESHOLD_HI GENMASK(22, 21) 79 #define AVERAGE_BYTES_PER_TU_FRAC GENMASK(19, 16) 80 #define INIT_THRESHOLD GENMASK(13, 7) 81 #define AVERAGE_BYTES_PER_TU GENMASK(6, 0) 82 #define DPTX_VIDEO_MSA1 0x0324 83 #define VSTART GENMASK(31, 16) 84 #define HSTART GENMASK(15, 0) 85 #define DPTX_VIDEO_MSA2 0x0328 86 #define MISC0 GENMASK(31, 24) 87 #define DPTX_VIDEO_MSA3 0x032c 88 #define MISC1 GENMASK(31, 24) 89 #define DPTX_VIDEO_HBLANK_INTERVAL 0x0330 90 #define HBLANK_INTERVAL_EN BIT(16) 91 #define HBLANK_INTERVAL GENMASK(15, 0) 92 93 #define DPTX_AUD_CONFIG1 0x0400 94 #define AUDIO_TIMESTAMP_VERSION_NUM GENMASK(29, 24) 95 #define AUDIO_PACKET_ID GENMASK(23, 16) 96 #define AUDIO_MUTE BIT(15) 97 #define NUM_CHANNELS GENMASK(14, 12) 98 #define HBR_MODE_ENABLE BIT(10) 99 #define AUDIO_DATA_WIDTH GENMASK(9, 5) 100 #define AUDIO_DATA_IN_EN GENMASK(4, 1) 101 #define AUDIO_INF_SELECT BIT(0) 102 103 #define DPTX_SDP_VERTICAL_CTRL 0x0500 104 #define EN_VERTICAL_SDP BIT(2) 105 #define EN_AUDIO_STREAM_SDP BIT(1) 106 #define EN_AUDIO_TIMESTAMP_SDP BIT(0) 107 #define DPTX_SDP_HORIZONTAL_CTRL 0x0504 108 #define EN_HORIZONTAL_SDP BIT(2) 109 #define DPTX_SDP_STATUS_REGISTER 0x0508 110 #define DPTX_SDP_MANUAL_CTRL 0x050c 111 #define DPTX_SDP_STATUS_EN 0x0510 112 113 #define DPTX_SDP_REGISTER_BANK 0x0600 114 #define SDP_REGS GENMASK(31, 0) 115 116 #define DPTX_PHYIF_CTRL 0x0a00 117 #define PHY_WIDTH BIT(25) 118 #define PHY_POWERDOWN GENMASK(20, 17) 119 #define PHY_BUSY GENMASK(15, 12) 120 #define SSC_DIS BIT(16) 121 #define XMIT_ENABLE GENMASK(11, 8) 122 #define PHY_LANES GENMASK(7, 6) 123 #define PHY_RATE GENMASK(5, 4) 124 #define TPS_SEL GENMASK(3, 0) 125 #define DPTX_PHY_TX_EQ 0x0a04 126 #define DPTX_CUSTOMPAT0 0x0a08 127 #define DPTX_CUSTOMPAT1 0x0a0c 128 #define DPTX_CUSTOMPAT2 0x0a10 129 #define DPTX_HBR2_COMPLIANCE_SCRAMBLER_RESET 0x0a14 130 #define DPTX_PHYIF_PWRDOWN_CTRL 0x0a18 131 132 #define DPTX_AUX_CMD 0x0b00 133 #define AUX_CMD_TYPE GENMASK(31, 28) 134 #define AUX_ADDR GENMASK(27, 8) 135 #define I2C_ADDR_ONLY BIT(4) 136 #define AUX_LEN_REQ GENMASK(3, 0) 137 #define DPTX_AUX_STATUS 0x0b04 138 #define AUX_TIMEOUT BIT(17) 139 #define AUX_BYTES_READ GENMASK(23, 19) 140 #define AUX_STATUS GENMASK(7, 4) 141 #define DPTX_AUX_DATA0 0x0b08 142 #define DPTX_AUX_DATA1 0x0b0c 143 #define DPTX_AUX_DATA2 0x0b10 144 #define DPTX_AUX_DATA3 0x0b14 145 146 #define DPTX_GENERAL_INTERRUPT 0x0d00 147 #define VIDEO_FIFO_OVERFLOW_STREAM0 BIT(6) 148 #define AUDIO_FIFO_OVERFLOW_STREAM0 BIT(5) 149 #define SDP_EVENT_STREAM0 BIT(4) 150 #define AUX_CMD_INVALID BIT(3) 151 #define AUX_REPLY_EVENT BIT(1) 152 #define HPD_EVENT BIT(0) 153 #define DPTX_GENERAL_INTERRUPT_ENABLE 0x0d04 154 #define AUX_REPLY_EVENT_EN BIT(1) 155 #define HPD_EVENT_EN BIT(0) 156 #define DPTX_HPD_STATUS 0x0d08 157 #define HPD_STATE GENMASK(11, 9) 158 #define HPD_STATUS BIT(8) 159 #define HPD_HOT_UNPLUG BIT(2) 160 #define HPD_HOT_PLUG BIT(1) 161 #define HPD_IRQ BIT(0) 162 #define DPTX_HPD_INTERRUPT_ENABLE 0x0d0c 163 #define HPD_UNPLUG_ERR_EN BIT(3) 164 #define HPD_UNPLUG_EN BIT(2) 165 #define HPD_PLUG_EN BIT(1) 166 #define HPD_IRQ_EN BIT(0) 167 168 #define DPTX_MAX_REGISTER DPTX_HPD_INTERRUPT_ENABLE 169 170 #define SDP_REG_BANK_SIZE 16 171 172 struct drm_dp_link_caps { 173 bool enhanced_framing; 174 bool tps3_supported; 175 bool tps4_supported; 176 bool channel_coding; 177 bool ssc; 178 }; 179 180 struct drm_dp_link_train_set { 181 unsigned int voltage_swing[4]; 182 unsigned int pre_emphasis[4]; 183 }; 184 185 struct drm_dp_link_train { 186 struct drm_dp_link_train_set request; 187 struct drm_dp_link_train_set adjust; 188 bool clock_recovered; 189 bool channel_equalized; 190 }; 191 192 struct dw_dp_link { 193 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 194 unsigned char revision; 195 unsigned int rate; 196 unsigned int lanes; 197 struct drm_dp_link_caps caps; 198 struct drm_dp_link_train train; 199 u8 sink_count; 200 u8 vsc_sdp_extension_for_colorimetry_supported; 201 }; 202 203 struct dw_dp_video { 204 struct drm_display_mode mode; 205 u32 bus_format; 206 u8 video_mapping; 207 u8 pixel_mode; 208 u8 color_format; 209 u8 bpc; 210 u8 bpp; 211 }; 212 213 struct dw_dp_sdp { 214 struct dp_sdp_header header; 215 u8 db[32]; 216 unsigned long flags; 217 }; 218 219 struct dw_dp { 220 struct udevice *dev; 221 struct regmap *regmap; 222 struct phy phy; 223 struct reset_ctl reset; 224 int id; 225 226 struct gpio_desc hpd_gpio; 227 struct drm_dp_aux aux; 228 struct dw_dp_link link; 229 struct dw_dp_video video; 230 231 bool force_hpd; 232 bool force_output; 233 }; 234 235 enum { 236 SOURCE_STATE_IDLE, 237 SOURCE_STATE_UNPLUG, 238 SOURCE_STATE_HPD_TIMEOUT = 4, 239 SOURCE_STATE_PLUG = 7 240 }; 241 242 enum { 243 DPTX_VM_RGB_6BIT, 244 DPTX_VM_RGB_8BIT, 245 DPTX_VM_RGB_10BIT, 246 DPTX_VM_RGB_12BIT, 247 DPTX_VM_RGB_16BIT, 248 DPTX_VM_YCBCR444_8BIT, 249 DPTX_VM_YCBCR444_10BIT, 250 DPTX_VM_YCBCR444_12BIT, 251 DPTX_VM_YCBCR444_16BIT, 252 DPTX_VM_YCBCR422_8BIT, 253 DPTX_VM_YCBCR422_10BIT, 254 DPTX_VM_YCBCR422_12BIT, 255 DPTX_VM_YCBCR422_16BIT, 256 DPTX_VM_YCBCR420_8BIT, 257 DPTX_VM_YCBCR420_10BIT, 258 DPTX_VM_YCBCR420_12BIT, 259 DPTX_VM_YCBCR420_16BIT, 260 }; 261 262 enum { 263 DPTX_MP_SINGLE_PIXEL, 264 DPTX_MP_DUAL_PIXEL, 265 DPTX_MP_QUAD_PIXEL, 266 }; 267 268 enum { 269 DPTX_SDP_VERTICAL_INTERVAL = BIT(0), 270 DPTX_SDP_HORIZONTAL_INTERVAL = BIT(1), 271 }; 272 273 enum { 274 DPTX_PHY_PATTERN_NONE, 275 DPTX_PHY_PATTERN_TPS_1, 276 DPTX_PHY_PATTERN_TPS_2, 277 DPTX_PHY_PATTERN_TPS_3, 278 DPTX_PHY_PATTERN_TPS_4, 279 DPTX_PHY_PATTERN_SERM, 280 DPTX_PHY_PATTERN_PBRS7, 281 DPTX_PHY_PATTERN_CUSTOM_80BIT, 282 DPTX_PHY_PATTERN_CP2520_1, 283 DPTX_PHY_PATTERN_CP2520_2, 284 }; 285 286 enum { 287 DPTX_PHYRATE_RBR, 288 DPTX_PHYRATE_HBR, 289 DPTX_PHYRATE_HBR2, 290 DPTX_PHYRATE_HBR3, 291 }; 292 293 struct dw_dp_output_format { 294 u32 bus_format; 295 u32 color_format; 296 u8 video_mapping; 297 u8 bpc; 298 u8 bpp; 299 }; 300 301 static const struct dw_dp_output_format possible_output_fmts[] = { 302 { MEDIA_BUS_FMT_RGB101010_1X30, DRM_COLOR_FORMAT_RGB444, 303 DPTX_VM_RGB_10BIT, 10, 30 }, 304 { MEDIA_BUS_FMT_RGB888_1X24, DRM_COLOR_FORMAT_RGB444, 305 DPTX_VM_RGB_8BIT, 8, 24 }, 306 { MEDIA_BUS_FMT_YUV10_1X30, DRM_COLOR_FORMAT_YCRCB444, 307 DPTX_VM_YCBCR444_10BIT, 10, 30 }, 308 { MEDIA_BUS_FMT_YUV8_1X24, DRM_COLOR_FORMAT_YCRCB444, 309 DPTX_VM_YCBCR444_8BIT, 8, 24}, 310 { MEDIA_BUS_FMT_YUYV10_1X20, DRM_COLOR_FORMAT_YCRCB422, 311 DPTX_VM_YCBCR422_10BIT, 10, 20 }, 312 { MEDIA_BUS_FMT_YUYV8_1X16, DRM_COLOR_FORMAT_YCRCB422, 313 DPTX_VM_YCBCR422_8BIT, 8, 16 }, 314 { MEDIA_BUS_FMT_UYYVYY10_0_5X30, DRM_COLOR_FORMAT_YCRCB420, 315 DPTX_VM_YCBCR420_10BIT, 10, 15 }, 316 { MEDIA_BUS_FMT_UYYVYY8_0_5X24, DRM_COLOR_FORMAT_YCRCB420, 317 DPTX_VM_YCBCR420_8BIT, 8, 12 }, 318 { MEDIA_BUS_FMT_RGB666_1X24_CPADHI, DRM_COLOR_FORMAT_RGB444, 319 DPTX_VM_RGB_6BIT, 6, 18 }, 320 }; 321 322 static int dw_dp_aux_write_data(struct dw_dp *dp, const u8 *buffer, size_t size) 323 { 324 size_t i, j; 325 326 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 327 size_t num = min_t(size_t, size - i * 4, 4); 328 u32 value = 0; 329 330 for (j = 0; j < num; j++) 331 value |= buffer[i * 4 + j] << (j * 8); 332 333 regmap_write(dp->regmap, DPTX_AUX_DATA0 + i * 4, value); 334 } 335 336 return size; 337 } 338 339 static int dw_dp_aux_read_data(struct dw_dp *dp, u8 *buffer, size_t size) 340 { 341 size_t i, j; 342 343 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 344 size_t num = min_t(size_t, size - i * 4, 4); 345 u32 value; 346 347 regmap_read(dp->regmap, DPTX_AUX_DATA0 + i * 4, &value); 348 349 for (j = 0; j < num; j++) 350 buffer[i * 4 + j] = value >> (j * 8); 351 } 352 353 return size; 354 } 355 356 static ssize_t dw_dp_aux_transfer(struct drm_dp_aux *aux, 357 struct drm_dp_aux_msg *msg) 358 { 359 u32 status, value; 360 ssize_t ret = 0; 361 int timeout = 0; 362 struct dw_dp *dp = dev_get_priv(aux->dev); 363 364 if (WARN_ON(msg->size > 16)) 365 return -E2BIG; 366 367 switch (msg->request & ~DP_AUX_I2C_MOT) { 368 case DP_AUX_NATIVE_WRITE: 369 case DP_AUX_I2C_WRITE: 370 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 371 ret = dw_dp_aux_write_data(dp, msg->buffer, msg->size); 372 if (ret < 0) 373 return ret; 374 break; 375 case DP_AUX_NATIVE_READ: 376 case DP_AUX_I2C_READ: 377 break; 378 default: 379 return -EINVAL; 380 } 381 382 if (msg->size > 0) 383 value = FIELD_PREP(AUX_LEN_REQ, msg->size - 1); 384 else 385 value = FIELD_PREP(I2C_ADDR_ONLY, 1); 386 387 value |= FIELD_PREP(AUX_CMD_TYPE, msg->request); 388 value |= FIELD_PREP(AUX_ADDR, msg->address); 389 regmap_write(dp->regmap, DPTX_AUX_CMD, value); 390 391 timeout = regmap_read_poll_timeout(dp->regmap, DPTX_GENERAL_INTERRUPT, 392 status, status & AUX_REPLY_EVENT, 393 200, 10); 394 395 if (timeout) { 396 printf("timeout waiting for AUX reply\n"); 397 return -ETIMEDOUT; 398 } 399 regmap_write(dp->regmap, DPTX_GENERAL_INTERRUPT, AUX_REPLY_EVENT); 400 401 regmap_read(dp->regmap, DPTX_AUX_STATUS, &value); 402 if (value & AUX_TIMEOUT) { 403 printf("aux timeout\n"); 404 return -ETIMEDOUT; 405 } 406 407 msg->reply = FIELD_GET(AUX_STATUS, value); 408 409 if (msg->size > 0 && msg->reply == DP_AUX_NATIVE_REPLY_ACK) { 410 if (msg->request & DP_AUX_I2C_READ) { 411 size_t count = FIELD_GET(AUX_BYTES_READ, value) - 1; 412 413 if (count != msg->size) { 414 printf("aux fail to read %lu bytes\n", count); 415 return -EBUSY; 416 } 417 418 ret = dw_dp_aux_read_data(dp, msg->buffer, count); 419 if (ret < 0) 420 return ret; 421 } 422 } 423 424 return ret; 425 } 426 427 static bool dw_dp_bandwidth_ok(struct dw_dp *dp, 428 const struct drm_display_mode *mode, u32 bpp, 429 unsigned int lanes, unsigned int rate) 430 { 431 u32 max_bw, req_bw; 432 433 req_bw = mode->clock * bpp / 8; 434 max_bw = lanes * rate; 435 if (req_bw > max_bw) 436 return false; 437 438 return true; 439 } 440 441 static void dw_dp_hpd_init(struct dw_dp *dp) 442 { 443 if (dm_gpio_is_valid(&dp->hpd_gpio) || dp->force_hpd) { 444 regmap_update_bits(dp->regmap, DPTX_CCTL, FORCE_HPD, 445 FIELD_PREP(FORCE_HPD, 1)); 446 return; 447 } 448 449 /* Enable all HPD interrupts */ 450 regmap_update_bits(dp->regmap, DPTX_HPD_INTERRUPT_ENABLE, 451 HPD_UNPLUG_EN | HPD_PLUG_EN | HPD_IRQ_EN, 452 FIELD_PREP(HPD_UNPLUG_EN, 1) | 453 FIELD_PREP(HPD_PLUG_EN, 1) | 454 FIELD_PREP(HPD_IRQ_EN, 1)); 455 456 /* Enable all top-level interrupts */ 457 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, 458 HPD_EVENT_EN, FIELD_PREP(HPD_EVENT_EN, 1)); 459 } 460 461 static void dw_dp_aux_init(struct dw_dp *dp) 462 { 463 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, 464 FIELD_PREP(AUX_RESET, 1)); 465 udelay(10); 466 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, 467 FIELD_PREP(AUX_RESET, 0)); 468 469 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, 470 AUX_REPLY_EVENT_EN, 471 FIELD_PREP(AUX_REPLY_EVENT_EN, 1)); 472 } 473 474 static void dw_dp_init(struct dw_dp *dp) 475 { 476 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, 477 FIELD_PREP(CONTROLLER_RESET, 1)); 478 udelay(10); 479 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, 480 FIELD_PREP(CONTROLLER_RESET, 0)); 481 482 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, 483 FIELD_PREP(PHY_SOFT_RESET, 1)); 484 udelay(10); 485 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, 486 FIELD_PREP(PHY_SOFT_RESET, 0)); 487 488 regmap_update_bits(dp->regmap, DPTX_CCTL, DEFAULT_FAST_LINK_TRAIN_EN, 489 FIELD_PREP(DEFAULT_FAST_LINK_TRAIN_EN, 0)); 490 491 dw_dp_hpd_init(dp); 492 dw_dp_aux_init(dp); 493 } 494 495 static void dw_dp_phy_set_pattern(struct dw_dp *dp, u32 pattern) 496 { 497 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, TPS_SEL, 498 FIELD_PREP(TPS_SEL, pattern)); 499 } 500 501 static void dw_dp_phy_xmit_enable(struct dw_dp *dp, u32 lanes) 502 { 503 u32 xmit_enable; 504 505 switch (lanes) { 506 case 4: 507 case 2: 508 case 1: 509 xmit_enable = GENMASK(lanes - 1, 0); 510 break; 511 case 0: 512 default: 513 xmit_enable = 0; 514 break; 515 } 516 517 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, XMIT_ENABLE, 518 FIELD_PREP(XMIT_ENABLE, xmit_enable)); 519 } 520 521 static int dw_dp_link_power_up(struct dw_dp *dp) 522 { 523 struct dw_dp_link *link = &dp->link; 524 u8 value; 525 int ret; 526 527 if (link->revision < 0x11) 528 return 0; 529 530 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value); 531 if (ret < 0) 532 return ret; 533 534 value &= ~DP_SET_POWER_MASK; 535 value |= DP_SET_POWER_D0; 536 537 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value); 538 if (ret < 0) 539 return ret; 540 541 udelay(1000); 542 return 0; 543 } 544 545 static int dw_dp_link_probe(struct dw_dp *dp) 546 { 547 struct dw_dp_link *link = &dp->link; 548 u8 dpcd; 549 int ret; 550 551 ret = drm_dp_read_dpcd_caps(&dp->aux, link->dpcd); 552 if (ret < 0) 553 return ret; 554 555 ret = drm_dp_dpcd_readb(&dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, 556 &dpcd); 557 if (ret < 0) 558 return ret; 559 560 link->vsc_sdp_extension_for_colorimetry_supported = 561 !!(dpcd & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED); 562 563 link->revision = link->dpcd[DP_DPCD_REV]; 564 link->rate = drm_dp_max_link_rate(link->dpcd); 565 link->lanes = min_t(u8, dp->phy.attrs.bus_width, 566 drm_dp_max_lane_count(link->dpcd)); 567 568 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(link->dpcd); 569 link->caps.tps3_supported = drm_dp_tps3_supported(link->dpcd); 570 link->caps.tps4_supported = drm_dp_tps4_supported(link->dpcd); 571 link->caps.channel_coding = drm_dp_channel_coding_supported(link->dpcd); 572 link->caps.ssc = !!(link->dpcd[DP_MAX_DOWNSPREAD] & 573 DP_MAX_DOWNSPREAD_0_5); 574 575 return 0; 576 } 577 578 static int dw_dp_link_train_update_vs_emph(struct dw_dp *dp) 579 { 580 struct dw_dp_link *link = &dp->link; 581 struct drm_dp_link_train_set *request = &link->train.request; 582 union phy_configure_opts phy_cfg; 583 unsigned int lanes = link->lanes, *vs, *pe; 584 u8 buf[4]; 585 int i, ret; 586 587 vs = request->voltage_swing; 588 pe = request->pre_emphasis; 589 590 for (i = 0; i < lanes; i++) { 591 phy_cfg.dp.voltage[i] = vs[i]; 592 phy_cfg.dp.pre[i] = pe[i]; 593 } 594 phy_cfg.dp.lanes = lanes; 595 phy_cfg.dp.link_rate = link->rate / 100; 596 phy_cfg.dp.set_lanes = false; 597 phy_cfg.dp.set_rate = false; 598 phy_cfg.dp.set_voltages = true; 599 ret = generic_phy_configure(&dp->phy, &phy_cfg); 600 if (ret) 601 return ret; 602 603 for (i = 0; i < lanes; i++) 604 buf[i] = (vs[i] << DP_TRAIN_VOLTAGE_SWING_SHIFT) | 605 (pe[i] << DP_TRAIN_PRE_EMPHASIS_SHIFT); 606 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, lanes); 607 if (ret < 0) 608 return ret; 609 610 return 0; 611 } 612 613 static int dw_dp_link_configure(struct dw_dp *dp) 614 { 615 struct dw_dp_link *link = &dp->link; 616 union phy_configure_opts phy_cfg; 617 u8 buf[2]; 618 int ret, phy_rate; 619 620 /* Move PHY to P3 */ 621 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 622 FIELD_PREP(PHY_POWERDOWN, 0x3)); 623 624 phy_cfg.dp.lanes = link->lanes; 625 phy_cfg.dp.link_rate = link->rate / 100; 626 phy_cfg.dp.ssc = link->caps.ssc; 627 phy_cfg.dp.set_lanes = true; 628 phy_cfg.dp.set_rate = true; 629 phy_cfg.dp.set_voltages = false; 630 ret = generic_phy_configure(&dp->phy, &phy_cfg); 631 if (ret) 632 return ret; 633 634 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, 635 FIELD_PREP(PHY_LANES, link->lanes / 2)); 636 637 switch (link->rate) { 638 case 810000: 639 phy_rate = DPTX_PHYRATE_HBR3; 640 break; 641 case 540000: 642 phy_rate = DPTX_PHYRATE_HBR2; 643 break; 644 case 270000: 645 phy_rate = DPTX_PHYRATE_HBR; 646 break; 647 case 162000: 648 default: 649 phy_rate = DPTX_PHYRATE_RBR; 650 break; 651 } 652 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_RATE, 653 FIELD_PREP(PHY_RATE, phy_rate)); 654 655 /* Move PHY to P0 */ 656 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 657 FIELD_PREP(PHY_POWERDOWN, 0x0)); 658 659 dw_dp_phy_xmit_enable(dp, link->lanes); 660 661 buf[0] = drm_dp_link_rate_to_bw_code(link->rate); 662 buf[1] = link->lanes; 663 664 if (link->caps.enhanced_framing) { 665 buf[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 666 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 667 FIELD_PREP(ENHANCE_FRAMING_EN, 1)); 668 } else { 669 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 670 FIELD_PREP(ENHANCE_FRAMING_EN, 0)); 671 } 672 673 ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, sizeof(buf)); 674 if (ret < 0) 675 return ret; 676 677 buf[0] = link->caps.ssc ? DP_SPREAD_AMP_0_5 : 0; 678 buf[1] = link->caps.channel_coding ? DP_SET_ANSI_8B10B : 0; 679 680 ret = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, 681 sizeof(buf)); 682 if (ret < 0) 683 return ret; 684 685 return 0; 686 } 687 688 static void dw_dp_link_train_init(struct drm_dp_link_train *train) 689 { 690 struct drm_dp_link_train_set *request = &train->request; 691 struct drm_dp_link_train_set *adjust = &train->adjust; 692 unsigned int i; 693 694 for (i = 0; i < 4; i++) { 695 request->voltage_swing[i] = 0; 696 adjust->voltage_swing[i] = 0; 697 698 request->pre_emphasis[i] = 0; 699 adjust->pre_emphasis[i] = 0; 700 } 701 702 train->clock_recovered = false; 703 train->channel_equalized = false; 704 } 705 706 static int dw_dp_link_train_set_pattern(struct dw_dp *dp, u32 pattern) 707 { 708 u8 buf = 0; 709 int ret; 710 711 if (pattern && pattern != DP_TRAINING_PATTERN_4) { 712 buf |= DP_LINK_SCRAMBLING_DISABLE; 713 714 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, 715 FIELD_PREP(SCRAMBLE_DIS, 1)); 716 } else { 717 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, 718 FIELD_PREP(SCRAMBLE_DIS, 0)); 719 } 720 721 switch (pattern) { 722 case DP_TRAINING_PATTERN_DISABLE: 723 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE); 724 break; 725 case DP_TRAINING_PATTERN_1: 726 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_1); 727 break; 728 case DP_TRAINING_PATTERN_2: 729 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_2); 730 break; 731 case DP_TRAINING_PATTERN_3: 732 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_3); 733 break; 734 case DP_TRAINING_PATTERN_4: 735 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_4); 736 break; 737 default: 738 return -EINVAL; 739 } 740 741 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 742 buf | pattern); 743 if (ret < 0) 744 return ret; 745 746 return 0; 747 } 748 749 static void dw_dp_link_get_adjustments(struct dw_dp_link *link, 750 u8 status[DP_LINK_STATUS_SIZE]) 751 { 752 struct drm_dp_link_train_set *adjust = &link->train.adjust; 753 unsigned int i; 754 755 for (i = 0; i < link->lanes; i++) { 756 adjust->voltage_swing[i] = 757 drm_dp_get_adjust_request_voltage(status, i) >> 758 DP_TRAIN_VOLTAGE_SWING_SHIFT; 759 760 adjust->pre_emphasis[i] = 761 drm_dp_get_adjust_request_pre_emphasis(status, i) >> 762 DP_TRAIN_PRE_EMPHASIS_SHIFT; 763 } 764 } 765 766 static void dw_dp_link_train_adjust(struct drm_dp_link_train *train) 767 { 768 struct drm_dp_link_train_set *request = &train->request; 769 struct drm_dp_link_train_set *adjust = &train->adjust; 770 unsigned int i; 771 772 for (i = 0; i < 4; i++) 773 if (request->voltage_swing[i] != adjust->voltage_swing[i]) 774 request->voltage_swing[i] = adjust->voltage_swing[i]; 775 776 for (i = 0; i < 4; i++) 777 if (request->pre_emphasis[i] != adjust->pre_emphasis[i]) 778 request->pre_emphasis[i] = adjust->pre_emphasis[i]; 779 } 780 781 static int dw_dp_link_clock_recovery(struct dw_dp *dp) 782 { 783 struct dw_dp_link *link = &dp->link; 784 u8 status[DP_LINK_STATUS_SIZE]; 785 unsigned int tries = 0; 786 int ret; 787 788 ret = dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_1); 789 if (ret) 790 return ret; 791 792 for (;;) { 793 ret = dw_dp_link_train_update_vs_emph(dp); 794 if (ret) 795 return ret; 796 797 drm_dp_link_train_clock_recovery_delay(link->dpcd); 798 799 ret = drm_dp_dpcd_read_link_status(&dp->aux, status); 800 if (ret < 0) { 801 dev_err(dp->dev, "failed to read link status: %d\n", 802 ret); 803 return ret; 804 } 805 806 if (drm_dp_clock_recovery_ok(status, link->lanes)) { 807 link->train.clock_recovered = true; 808 break; 809 } 810 811 dw_dp_link_get_adjustments(link, status); 812 813 if (link->train.request.voltage_swing[0] == 814 link->train.adjust.voltage_swing[0]) 815 tries++; 816 else 817 tries = 0; 818 819 if (tries == 5) 820 break; 821 822 dw_dp_link_train_adjust(&link->train); 823 } 824 825 return 0; 826 } 827 828 static int dw_dp_link_channel_equalization(struct dw_dp *dp) 829 { 830 struct dw_dp_link *link = &dp->link; 831 u8 status[DP_LINK_STATUS_SIZE], pattern; 832 unsigned int tries; 833 int ret; 834 835 if (link->caps.tps4_supported) 836 pattern = DP_TRAINING_PATTERN_4; 837 else if (link->caps.tps3_supported) 838 pattern = DP_TRAINING_PATTERN_3; 839 else 840 pattern = DP_TRAINING_PATTERN_2; 841 ret = dw_dp_link_train_set_pattern(dp, pattern); 842 if (ret) 843 return ret; 844 845 for (tries = 1; tries < 5; tries++) { 846 ret = dw_dp_link_train_update_vs_emph(dp); 847 if (ret) 848 return ret; 849 850 drm_dp_link_train_channel_eq_delay(link->dpcd); 851 852 ret = drm_dp_dpcd_read_link_status(&dp->aux, status); 853 if (ret < 0) 854 return ret; 855 856 if (!drm_dp_clock_recovery_ok(status, link->lanes)) { 857 dev_err(dp->dev, 858 "clock recovery lost while eq\n"); 859 link->train.clock_recovered = false; 860 break; 861 } 862 863 if (drm_dp_channel_eq_ok(status, link->lanes)) { 864 link->train.channel_equalized = true; 865 break; 866 } 867 868 dw_dp_link_get_adjustments(link, status); 869 dw_dp_link_train_adjust(&link->train); 870 } 871 872 return 0; 873 } 874 875 static int dw_dp_link_downgrade(struct dw_dp *dp) 876 { 877 struct dw_dp_link *link = &dp->link; 878 struct dw_dp_video *video = &dp->video; 879 880 switch (link->rate) { 881 case 162000: 882 return -EINVAL; 883 case 270000: 884 link->rate = 162000; 885 break; 886 case 540000: 887 link->rate = 270000; 888 break; 889 case 810000: 890 link->rate = 540000; 891 break; 892 } 893 894 if (!dw_dp_bandwidth_ok(dp, &video->mode, video->bpp, link->lanes, 895 link->rate)) 896 return -E2BIG; 897 898 return 0; 899 } 900 901 static int dw_dp_link_train(struct dw_dp *dp) 902 { 903 struct dw_dp_link *link = &dp->link; 904 int ret; 905 906 retry: 907 dw_dp_link_train_init(&link->train); 908 909 printf("training link: %u lane%s at %u MHz\n", 910 link->lanes, (link->lanes > 1) ? "s" : "", link->rate / 100); 911 912 ret = dw_dp_link_configure(dp); 913 if (ret < 0) { 914 dev_err(dp->dev, "failed to configure DP link: %d\n", ret); 915 return ret; 916 } 917 918 ret = dw_dp_link_clock_recovery(dp); 919 if (ret < 0) { 920 dev_err(dp->dev, "clock recovery failed: %d\n", ret); 921 goto out; 922 } 923 924 if (!link->train.clock_recovered) { 925 dev_err(dp->dev, "clock recovery failed, downgrading link\n"); 926 927 ret = dw_dp_link_downgrade(dp); 928 if (ret < 0) 929 goto out; 930 else 931 goto retry; 932 } 933 934 printf("clock recovery succeeded\n"); 935 936 ret = dw_dp_link_channel_equalization(dp); 937 if (ret < 0) { 938 dev_err(dp->dev, "channel equalization failed: %d\n", ret); 939 goto out; 940 } 941 942 if (!link->train.channel_equalized) { 943 dev_err(dp->dev, 944 "channel equalization failed, downgrading link\n"); 945 946 ret = dw_dp_link_downgrade(dp); 947 if (ret < 0) 948 goto out; 949 else 950 goto retry; 951 } 952 953 printf("channel equalization succeeded\n"); 954 955 out: 956 dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE); 957 return ret; 958 } 959 960 static int dw_dp_link_enable(struct dw_dp *dp) 961 { 962 int ret; 963 964 ret = dw_dp_link_power_up(dp); 965 if (ret < 0) 966 return ret; 967 968 ret = dw_dp_link_train(dp); 969 if (ret < 0) { 970 dev_err(dp->dev, "link training failed: %d\n", ret); 971 return ret; 972 } 973 974 return 0; 975 } 976 977 static int dw_dp_set_phy_default_config(struct dw_dp *dp) 978 { 979 struct dw_dp_link *link = &dp->link; 980 union phy_configure_opts phy_cfg; 981 int ret, i, phy_rate; 982 983 link->vsc_sdp_extension_for_colorimetry_supported = false; 984 link->rate = 270000; 985 link->lanes = dp->phy.attrs.bus_width; 986 987 link->caps.enhanced_framing = true; 988 link->caps.channel_coding = true; 989 link->caps.ssc = true; 990 991 /* Move PHY to P3 */ 992 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 993 FIELD_PREP(PHY_POWERDOWN, 0x3)); 994 995 for (i = 0; i < link->lanes; i++) { 996 phy_cfg.dp.voltage[i] = 3; 997 phy_cfg.dp.pre[i] = 0; 998 } 999 phy_cfg.dp.lanes = link->lanes; 1000 phy_cfg.dp.link_rate = link->rate / 100; 1001 phy_cfg.dp.ssc = link->caps.ssc; 1002 phy_cfg.dp.set_lanes = true; 1003 phy_cfg.dp.set_rate = true; 1004 phy_cfg.dp.set_voltages = true; 1005 ret = generic_phy_configure(&dp->phy, &phy_cfg); 1006 if (ret) 1007 return ret; 1008 1009 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, 1010 FIELD_PREP(PHY_LANES, link->lanes / 2)); 1011 1012 switch (link->rate) { 1013 case 810000: 1014 phy_rate = DPTX_PHYRATE_HBR3; 1015 break; 1016 case 540000: 1017 phy_rate = DPTX_PHYRATE_HBR2; 1018 break; 1019 case 270000: 1020 phy_rate = DPTX_PHYRATE_HBR; 1021 break; 1022 case 162000: 1023 default: 1024 phy_rate = DPTX_PHYRATE_RBR; 1025 break; 1026 } 1027 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_RATE, 1028 FIELD_PREP(PHY_RATE, phy_rate)); 1029 1030 /* Move PHY to P0 */ 1031 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 1032 FIELD_PREP(PHY_POWERDOWN, 0x0)); 1033 1034 dw_dp_phy_xmit_enable(dp, link->lanes); 1035 1036 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 1037 FIELD_PREP(ENHANCE_FRAMING_EN, 1)); 1038 1039 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE); 1040 return 0; 1041 } 1042 1043 static int dw_dp_send_sdp(struct dw_dp *dp, struct dw_dp_sdp *sdp) 1044 { 1045 const u8 *payload = sdp->db; 1046 u32 reg; 1047 int i, nr = 0; 1048 1049 reg = DPTX_SDP_REGISTER_BANK + nr * 9 * 4; 1050 1051 /* SDP header */ 1052 regmap_write(dp->regmap, reg, get_unaligned_le32(&sdp->header)); 1053 1054 /* SDP data payload */ 1055 for (i = 1; i < 9; i++, payload += 4) 1056 regmap_write(dp->regmap, reg + i * 4, 1057 FIELD_PREP(SDP_REGS, get_unaligned_le32(payload))); 1058 1059 if (sdp->flags & DPTX_SDP_VERTICAL_INTERVAL) 1060 regmap_update_bits(dp->regmap, DPTX_SDP_VERTICAL_CTRL, 1061 EN_VERTICAL_SDP << nr, 1062 EN_VERTICAL_SDP << nr); 1063 1064 if (sdp->flags & DPTX_SDP_HORIZONTAL_INTERVAL) 1065 regmap_update_bits(dp->regmap, DPTX_SDP_HORIZONTAL_CTRL, 1066 EN_HORIZONTAL_SDP << nr, 1067 EN_HORIZONTAL_SDP << nr); 1068 1069 return 0; 1070 } 1071 1072 static void dw_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, 1073 struct dw_dp_sdp *sdp) 1074 { 1075 sdp->header.HB0 = 0; 1076 sdp->header.HB1 = DP_SDP_VSC; 1077 sdp->header.HB2 = vsc->revision; 1078 sdp->header.HB3 = vsc->length; 1079 1080 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; 1081 sdp->db[16] |= vsc->colorimetry & 0xf; 1082 1083 switch (vsc->bpc) { 1084 case 8: 1085 sdp->db[17] = 0x1; 1086 break; 1087 case 10: 1088 sdp->db[17] = 0x2; 1089 break; 1090 case 12: 1091 sdp->db[17] = 0x3; 1092 break; 1093 case 16: 1094 sdp->db[17] = 0x4; 1095 break; 1096 case 6: 1097 default: 1098 break; 1099 } 1100 1101 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) 1102 sdp->db[17] |= 0x80; 1103 1104 sdp->db[18] = vsc->content_type & 0x7; 1105 1106 sdp->flags |= DPTX_SDP_VERTICAL_INTERVAL; 1107 } 1108 1109 static int dw_dp_send_vsc_sdp(struct dw_dp *dp) 1110 { 1111 struct dw_dp_video *video = &dp->video; 1112 struct drm_dp_vsc_sdp vsc = {}; 1113 struct dw_dp_sdp sdp = {}; 1114 1115 vsc.revision = 0x5; 1116 vsc.length = 0x13; 1117 1118 switch (video->color_format) { 1119 case DRM_COLOR_FORMAT_YCRCB444: 1120 vsc.pixelformat = DP_PIXELFORMAT_YUV444; 1121 break; 1122 case DRM_COLOR_FORMAT_YCRCB420: 1123 vsc.pixelformat = DP_PIXELFORMAT_YUV420; 1124 break; 1125 case DRM_COLOR_FORMAT_YCRCB422: 1126 vsc.pixelformat = DP_PIXELFORMAT_YUV422; 1127 break; 1128 case DRM_COLOR_FORMAT_RGB444: 1129 default: 1130 vsc.pixelformat = DP_PIXELFORMAT_RGB; 1131 break; 1132 } 1133 1134 if (video->color_format == DRM_COLOR_FORMAT_RGB444) 1135 vsc.colorimetry = DP_COLORIMETRY_DEFAULT; 1136 else 1137 vsc.colorimetry = DP_COLORIMETRY_BT709_YCC; 1138 1139 vsc.bpc = video->bpc; 1140 vsc.dynamic_range = DP_DYNAMIC_RANGE_CTA; 1141 vsc.content_type = DP_CONTENT_TYPE_NOT_DEFINED; 1142 1143 dw_dp_vsc_sdp_pack(&vsc, &sdp); 1144 1145 return dw_dp_send_sdp(dp, &sdp); 1146 } 1147 1148 static int dw_dp_video_set_pixel_mode(struct dw_dp *dp, u8 pixel_mode) 1149 { 1150 switch (pixel_mode) { 1151 case DPTX_MP_SINGLE_PIXEL: 1152 case DPTX_MP_DUAL_PIXEL: 1153 case DPTX_MP_QUAD_PIXEL: 1154 break; 1155 default: 1156 return -EINVAL; 1157 } 1158 1159 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, PIXEL_MODE_SELECT, 1160 FIELD_PREP(PIXEL_MODE_SELECT, pixel_mode)); 1161 1162 return 0; 1163 } 1164 1165 static int dw_dp_video_set_msa(struct dw_dp *dp, u8 color_format, u8 bpc, 1166 u16 vstart, u16 hstart) 1167 { 1168 struct dw_dp_link *link = &dp->link; 1169 u16 misc = 0; 1170 1171 if (link->vsc_sdp_extension_for_colorimetry_supported) 1172 misc |= DP_MSA_MISC_COLOR_VSC_SDP; 1173 1174 switch (color_format) { 1175 case DRM_COLOR_FORMAT_RGB444: 1176 misc |= DP_MSA_MISC_COLOR_RGB; 1177 break; 1178 case DRM_COLOR_FORMAT_YCRCB444: 1179 misc |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 1180 break; 1181 case DRM_COLOR_FORMAT_YCRCB422: 1182 misc |= DP_MSA_MISC_COLOR_YCBCR_422_BT709; 1183 break; 1184 case DRM_COLOR_FORMAT_YCRCB420: 1185 break; 1186 default: 1187 return -EINVAL; 1188 } 1189 1190 switch (bpc) { 1191 case 6: 1192 misc |= DP_MSA_MISC_6_BPC; 1193 break; 1194 case 8: 1195 misc |= DP_MSA_MISC_8_BPC; 1196 break; 1197 case 10: 1198 misc |= DP_MSA_MISC_10_BPC; 1199 break; 1200 case 12: 1201 misc |= DP_MSA_MISC_12_BPC; 1202 break; 1203 case 16: 1204 misc |= DP_MSA_MISC_16_BPC; 1205 break; 1206 default: 1207 return -EINVAL; 1208 } 1209 1210 regmap_write(dp->regmap, DPTX_VIDEO_MSA1, 1211 FIELD_PREP(VSTART, vstart) | FIELD_PREP(HSTART, hstart)); 1212 regmap_write(dp->regmap, DPTX_VIDEO_MSA2, FIELD_PREP(MISC0, misc)); 1213 regmap_write(dp->regmap, DPTX_VIDEO_MSA3, FIELD_PREP(MISC1, misc >> 8)); 1214 1215 return 0; 1216 } 1217 1218 static int dw_dp_video_enable(struct dw_dp *dp) 1219 { 1220 struct dw_dp_video *video = &dp->video; 1221 struct dw_dp_link *link = &dp->link; 1222 struct drm_display_mode *mode = &video->mode; 1223 u8 color_format = video->color_format; 1224 u8 bpc = video->bpc; 1225 u8 pixel_mode = video->pixel_mode; 1226 u8 bpp = video->bpp, init_threshold, vic; 1227 u32 hactive, hblank, h_sync_width, h_front_porch; 1228 u32 vactive, vblank, v_sync_width, v_front_porch; 1229 u32 vstart = mode->vtotal - mode->vsync_start; 1230 u32 hstart = mode->htotal - mode->hsync_start; 1231 u32 peak_stream_bandwidth, link_bandwidth; 1232 u32 average_bytes_per_tu, average_bytes_per_tu_frac; 1233 u32 ts, hblank_interval; 1234 u32 value; 1235 int ret; 1236 1237 ret = dw_dp_video_set_pixel_mode(dp, pixel_mode); 1238 if (ret) 1239 return ret; 1240 1241 ret = dw_dp_video_set_msa(dp, color_format, bpc, vstart, hstart); 1242 if (ret) 1243 return ret; 1244 1245 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_MAPPING, 1246 FIELD_PREP(VIDEO_MAPPING, video->video_mapping)); 1247 1248 /* Configure DPTX_VINPUT_POLARITY_CTRL register */ 1249 value = 0; 1250 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1251 value |= FIELD_PREP(HSYNC_IN_POLARITY, 1); 1252 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1253 value |= FIELD_PREP(VSYNC_IN_POLARITY, 1); 1254 regmap_write(dp->regmap, DPTX_VINPUT_POLARITY_CTRL, value); 1255 1256 /* Configure DPTX_VIDEO_CONFIG1 register */ 1257 hactive = mode->hdisplay; 1258 hblank = mode->htotal - mode->hdisplay; 1259 value = FIELD_PREP(HACTIVE, hactive) | FIELD_PREP(HBLANK, hblank); 1260 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1261 value |= FIELD_PREP(I_P, 1); 1262 vic = drm_match_cea_mode(mode); 1263 if (vic == 5 || vic == 6 || vic == 7 || 1264 vic == 10 || vic == 11 || vic == 20 || 1265 vic == 21 || vic == 22 || vic == 39 || 1266 vic == 25 || vic == 26 || vic == 40 || 1267 vic == 44 || vic == 45 || vic == 46 || 1268 vic == 50 || vic == 51 || vic == 54 || 1269 vic == 55 || vic == 58 || vic == 59) 1270 value |= R_V_BLANK_IN_OSC; 1271 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG1, value); 1272 1273 /* Configure DPTX_VIDEO_CONFIG2 register */ 1274 vblank = mode->vtotal - mode->vdisplay; 1275 vactive = mode->vdisplay; 1276 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG2, 1277 FIELD_PREP(VBLANK, vblank) | FIELD_PREP(VACTIVE, vactive)); 1278 1279 /* Configure DPTX_VIDEO_CONFIG3 register */ 1280 h_sync_width = mode->hsync_end - mode->hsync_start; 1281 h_front_porch = mode->hsync_start - mode->hdisplay; 1282 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG3, 1283 FIELD_PREP(H_SYNC_WIDTH, h_sync_width) | 1284 FIELD_PREP(H_FRONT_PORCH, h_front_porch)); 1285 1286 /* Configure DPTX_VIDEO_CONFIG4 register */ 1287 v_sync_width = mode->vsync_end - mode->vsync_start; 1288 v_front_porch = mode->vsync_start - mode->vdisplay; 1289 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG4, 1290 FIELD_PREP(V_SYNC_WIDTH, v_sync_width) | 1291 FIELD_PREP(V_FRONT_PORCH, v_front_porch)); 1292 1293 /* Configure DPTX_VIDEO_CONFIG5 register */ 1294 peak_stream_bandwidth = mode->clock * bpp / 8; 1295 link_bandwidth = (link->rate / 1000) * link->lanes; 1296 ts = peak_stream_bandwidth * 64 / link_bandwidth; 1297 average_bytes_per_tu = ts / 1000; 1298 average_bytes_per_tu_frac = ts / 100 - average_bytes_per_tu * 10; 1299 if (pixel_mode == DPTX_MP_SINGLE_PIXEL) { 1300 if (average_bytes_per_tu < 6) 1301 init_threshold = 32; 1302 else if (hblank <= 80 && 1303 color_format != DRM_COLOR_FORMAT_YCRCB420) 1304 init_threshold = 12; 1305 else if (hblank <= 40 && 1306 color_format == DRM_COLOR_FORMAT_YCRCB420) 1307 init_threshold = 3; 1308 else 1309 init_threshold = 16; 1310 } else { 1311 u32 t1 = 0, t2 = 0, t3 = 0; 1312 1313 switch (bpc) { 1314 case 6: 1315 t1 = (4 * 1000 / 9) * link->lanes; 1316 break; 1317 case 8: 1318 if (color_format == DRM_COLOR_FORMAT_YCRCB422) { 1319 t1 = (1000 / 2) * link->lanes; 1320 } else { 1321 if (pixel_mode == DPTX_MP_DUAL_PIXEL) 1322 t1 = (1000 / 3) * link->lanes; 1323 else 1324 t1 = (3000 / 16) * link->lanes; 1325 } 1326 break; 1327 case 10: 1328 if (color_format == DRM_COLOR_FORMAT_YCRCB422) 1329 t1 = (2000 / 5) * link->lanes; 1330 else 1331 t1 = (4000 / 15) * link->lanes; 1332 break; 1333 case 12: 1334 if (color_format == DRM_COLOR_FORMAT_YCRCB422) { 1335 if (pixel_mode == DPTX_MP_DUAL_PIXEL) 1336 t1 = (1000 / 6) * link->lanes; 1337 else 1338 t1 = (1000 / 3) * link->lanes; 1339 } else { 1340 t1 = (2000 / 9) * link->lanes; 1341 } 1342 break; 1343 case 16: 1344 if (color_format != DRM_COLOR_FORMAT_YCRCB422 && 1345 pixel_mode == DPTX_MP_DUAL_PIXEL) 1346 t1 = (1000 / 6) * link->lanes; 1347 else 1348 t1 = (1000 / 4) * link->lanes; 1349 break; 1350 default: 1351 return -EINVAL; 1352 } 1353 1354 if (color_format == DRM_COLOR_FORMAT_YCRCB420) 1355 t2 = (link->rate / 4) * 1000 / (mode->clock / 2); 1356 else 1357 t2 = (link->rate / 4) * 1000 / mode->clock; 1358 1359 if (average_bytes_per_tu_frac) 1360 t3 = average_bytes_per_tu + 1; 1361 else 1362 t3 = average_bytes_per_tu; 1363 init_threshold = t1 * t2 * t3 / (1000 * 1000); 1364 if (init_threshold <= 16 || average_bytes_per_tu < 10) 1365 init_threshold = 40; 1366 } 1367 1368 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG5, 1369 FIELD_PREP(INIT_THRESHOLD_HI, init_threshold >> 6) | 1370 FIELD_PREP(AVERAGE_BYTES_PER_TU_FRAC, 1371 average_bytes_per_tu_frac) | 1372 FIELD_PREP(INIT_THRESHOLD, init_threshold) | 1373 FIELD_PREP(AVERAGE_BYTES_PER_TU, average_bytes_per_tu)); 1374 1375 /* Configure DPTX_VIDEO_HBLANK_INTERVAL register */ 1376 hblank_interval = hblank * (link->rate / 4) / mode->clock; 1377 regmap_write(dp->regmap, DPTX_VIDEO_HBLANK_INTERVAL, 1378 FIELD_PREP(HBLANK_INTERVAL_EN, 1) | 1379 FIELD_PREP(HBLANK_INTERVAL, hblank_interval)); 1380 1381 /* Video stream enable */ 1382 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_STREAM_ENABLE, 1383 FIELD_PREP(VIDEO_STREAM_ENABLE, 1)); 1384 1385 if (link->vsc_sdp_extension_for_colorimetry_supported) 1386 dw_dp_send_vsc_sdp(dp); 1387 1388 return 0; 1389 } 1390 1391 static bool dw_dp_detect(struct dw_dp *dp) 1392 { 1393 u32 value; 1394 1395 if (dm_gpio_is_valid(&dp->hpd_gpio)) 1396 return dm_gpio_get_value(&dp->hpd_gpio); 1397 1398 regmap_read(dp->regmap, DPTX_HPD_STATUS, &value); 1399 if (FIELD_GET(HPD_STATE, value) == SOURCE_STATE_PLUG) { 1400 regmap_write(dp->regmap, DPTX_HPD_STATUS, HPD_HOT_PLUG); 1401 return true; 1402 } 1403 1404 return false; 1405 } 1406 1407 static int dw_dp_connector_pre_init(struct display_state *state) 1408 { 1409 struct connector_state *conn_state = &state->conn_state; 1410 1411 conn_state->type = DRM_MODE_CONNECTOR_DisplayPort; 1412 1413 return 0; 1414 } 1415 1416 static int dw_dp_connector_init(struct display_state *state) 1417 { 1418 struct connector_state *conn_state = &state->conn_state; 1419 struct dw_dp *dp = dev_get_priv(conn_state->dev); 1420 int ret; 1421 1422 conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_DP1 : VOP_OUTPUT_IF_DP0; 1423 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1424 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 1425 1426 clk_set_defaults(dp->dev); 1427 1428 reset_assert(&dp->reset); 1429 udelay(20); 1430 reset_deassert(&dp->reset); 1431 1432 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, 1433 dp->id); 1434 dw_dp_init(dp); 1435 ret = generic_phy_power_on(&dp->phy); 1436 1437 return ret; 1438 } 1439 1440 static int dw_dp_connector_get_edid(struct display_state *state) 1441 { 1442 int ret; 1443 struct connector_state *conn_state = &state->conn_state; 1444 struct dw_dp *dp = dev_get_priv(conn_state->dev); 1445 1446 ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); 1447 1448 return ret; 1449 } 1450 1451 static int dw_dp_get_output_fmts_index(u32 bus_format) 1452 { 1453 int i; 1454 1455 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 1456 const struct dw_dp_output_format *fmt = &possible_output_fmts[i]; 1457 1458 if (fmt->bus_format == bus_format) 1459 break; 1460 } 1461 1462 if (i == ARRAY_SIZE(possible_output_fmts)) 1463 return 1; 1464 1465 return i; 1466 } 1467 1468 static int dw_dp_connector_prepare(struct display_state *state) 1469 { 1470 struct connector_state *conn_state = &state->conn_state; 1471 struct dw_dp *dp = dev_get_priv(conn_state->dev); 1472 struct dw_dp_video *video = &dp->video; 1473 int bus_fmt; 1474 1475 bus_fmt = dw_dp_get_output_fmts_index(conn_state->bus_format); 1476 video->video_mapping = possible_output_fmts[bus_fmt].video_mapping; 1477 video->color_format = possible_output_fmts[bus_fmt].color_format; 1478 video->bus_format = possible_output_fmts[bus_fmt].bus_format; 1479 video->bpc = possible_output_fmts[bus_fmt].bpc; 1480 video->bpp = possible_output_fmts[bus_fmt].bpp; 1481 1482 return 0; 1483 } 1484 1485 static int dw_dp_connector_enable(struct display_state *state) 1486 { 1487 struct connector_state *conn_state = &state->conn_state; 1488 struct drm_display_mode *mode = &conn_state->mode; 1489 struct dw_dp *dp = dev_get_priv(conn_state->dev); 1490 struct dw_dp_video *video = &dp->video; 1491 int ret; 1492 1493 memcpy(&video->mode, mode, sizeof(video->mode)); 1494 video->pixel_mode = DPTX_MP_QUAD_PIXEL; 1495 1496 if (dp->force_output) { 1497 ret = dw_dp_set_phy_default_config(dp); 1498 if (ret < 0) 1499 printf("failed to set phy_default config: %d\n", ret); 1500 } else { 1501 ret = dw_dp_link_enable(dp); 1502 if (ret < 0) { 1503 printf("failed to enable link: %d\n", ret); 1504 return ret; 1505 } 1506 } 1507 1508 ret = dw_dp_video_enable(dp); 1509 if (ret < 0) { 1510 printf("failed to enable video: %d\n", ret); 1511 return ret; 1512 } 1513 1514 return 0; 1515 } 1516 1517 static int dw_dp_connector_disable(struct display_state *state) 1518 { 1519 /* TODO */ 1520 1521 return 0; 1522 } 1523 1524 static int dw_dp_connector_detect(struct display_state *state) 1525 { 1526 struct connector_state *conn_state = &state->conn_state; 1527 struct dw_dp *dp = dev_get_priv(conn_state->dev); 1528 int status, tries, ret; 1529 1530 for (tries = 0; tries < 200; tries++) { 1531 status = dw_dp_detect(dp); 1532 if (status) 1533 break; 1534 mdelay(2); 1535 } 1536 1537 if (state->force_output && !status) 1538 dp->force_output = true; 1539 1540 if (!status && !dp->force_output) 1541 generic_phy_power_off(&dp->phy); 1542 1543 if (status && !dp->force_output) { 1544 ret = dw_dp_link_probe(dp); 1545 if (ret) 1546 printf("failed to probe DP link: %d\n", ret); 1547 } 1548 1549 return status; 1550 } 1551 1552 static int dw_dp_mode_valid(struct dw_dp *dp, struct hdmi_edid_data *edid_data) 1553 { 1554 struct dw_dp_link *link = &dp->link; 1555 struct drm_display_info *di = &edid_data->display_info; 1556 u32 min_bpp; 1557 int i; 1558 1559 if (di->color_formats & DRM_COLOR_FORMAT_YCRCB420 && 1560 link->vsc_sdp_extension_for_colorimetry_supported) 1561 min_bpp = 12; 1562 else if (di->color_formats & DRM_COLOR_FORMAT_YCRCB422) 1563 min_bpp = 16; 1564 else if (di->color_formats & DRM_COLOR_FORMAT_RGB444) 1565 min_bpp = 18; 1566 else 1567 min_bpp = 24; 1568 1569 for (i = 0; i < edid_data->modes; i++) { 1570 if (!dw_dp_bandwidth_ok(dp, &edid_data->mode_buf[i], min_bpp, link->lanes, 1571 link->rate)) 1572 edid_data->mode_buf[i].invalid = true; 1573 } 1574 1575 return 0; 1576 } 1577 1578 static u32 dw_dp_get_output_bus_fmts(struct dw_dp *dp, struct hdmi_edid_data *edid_data) 1579 { 1580 struct dw_dp_link *link = &dp->link; 1581 unsigned int i; 1582 1583 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 1584 const struct dw_dp_output_format *fmt = &possible_output_fmts[i]; 1585 1586 if (fmt->bpc > edid_data->display_info.bpc) 1587 continue; 1588 1589 if (!(edid_data->display_info.color_formats & fmt->color_format)) 1590 continue; 1591 1592 if (fmt->color_format == DRM_COLOR_FORMAT_YCRCB420 && 1593 !link->vsc_sdp_extension_for_colorimetry_supported) 1594 continue; 1595 1596 if (drm_mode_is_420(&edid_data->display_info, edid_data->preferred_mode) && 1597 fmt->color_format != DRM_COLOR_FORMAT_YCRCB420) 1598 continue; 1599 1600 if (!dw_dp_bandwidth_ok(dp, edid_data->preferred_mode, fmt->bpp, link->lanes, 1601 link->rate)) 1602 continue; 1603 1604 break; 1605 } 1606 1607 if (i == ARRAY_SIZE(possible_output_fmts)) 1608 return 1; 1609 1610 return i; 1611 } 1612 1613 static int dw_dp_connector_get_timing(struct display_state *state) 1614 { 1615 int ret, i; 1616 struct connector_state *conn_state = &state->conn_state; 1617 struct dw_dp *dp = dev_get_priv(conn_state->dev); 1618 struct drm_display_mode *mode = &conn_state->mode; 1619 struct hdmi_edid_data edid_data; 1620 struct drm_display_mode *mode_buf; 1621 u32 bus_fmt; 1622 1623 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 1624 if (!mode_buf) 1625 return -ENOMEM; 1626 1627 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 1628 memset(&edid_data, 0, sizeof(struct hdmi_edid_data)); 1629 edid_data.mode_buf = mode_buf; 1630 1631 if (!dp->force_output) { 1632 ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); 1633 if (!ret) 1634 ret = drm_add_edid_modes(&edid_data, conn_state->edid); 1635 1636 if (ret < 0) { 1637 printf("failed to get edid\n"); 1638 goto err; 1639 } 1640 1641 drm_rk_filter_whitelist(&edid_data); 1642 drm_mode_max_resolution_filter(&edid_data, 1643 &state->crtc_state.max_output); 1644 dw_dp_mode_valid(dp, &edid_data); 1645 1646 if (!drm_mode_prune_invalid(&edid_data)) { 1647 printf("can't find valid hdmi mode\n"); 1648 ret = -EINVAL; 1649 goto err; 1650 } 1651 1652 for (i = 0; i < edid_data.modes; i++) 1653 edid_data.mode_buf[i].vrefresh = 1654 drm_mode_vrefresh(&edid_data.mode_buf[i]); 1655 1656 drm_mode_sort(&edid_data); 1657 memcpy(mode, edid_data.preferred_mode, sizeof(struct drm_display_mode)); 1658 } 1659 1660 if (state->force_output) 1661 bus_fmt = dw_dp_get_output_fmts_index(state->force_bus_format); 1662 else 1663 bus_fmt = dw_dp_get_output_bus_fmts(dp, &edid_data); 1664 1665 conn_state->bus_format = possible_output_fmts[bus_fmt].bus_format; 1666 1667 switch (possible_output_fmts[bus_fmt].color_format) { 1668 case DRM_COLOR_FORMAT_YCRCB420: 1669 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420; 1670 break; 1671 case DRM_COLOR_FORMAT_YCRCB422: 1672 conn_state->output_mode = ROCKCHIP_OUT_MODE_S888_DUMMY; 1673 break; 1674 case DRM_COLOR_FORMAT_RGB444: 1675 case DRM_COLOR_FORMAT_YCRCB444: 1676 default: 1677 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1678 break; 1679 } 1680 1681 err: 1682 free(mode_buf); 1683 1684 return 0; 1685 } 1686 1687 static const struct rockchip_connector_funcs dw_dp_connector_funcs = { 1688 .pre_init = dw_dp_connector_pre_init, 1689 .init = dw_dp_connector_init, 1690 .get_edid = dw_dp_connector_get_edid, 1691 .prepare = dw_dp_connector_prepare, 1692 .enable = dw_dp_connector_enable, 1693 .disable = dw_dp_connector_disable, 1694 .detect = dw_dp_connector_detect, 1695 .get_timing = dw_dp_connector_get_timing, 1696 }; 1697 1698 static int dw_dp_ddc_init(struct dw_dp *dp) 1699 { 1700 dp->aux.name = "dw-dp"; 1701 dp->aux.dev = dp->dev; 1702 dp->aux.transfer = dw_dp_aux_transfer; 1703 dp->aux.ddc.ddc_xfer = drm_dp_i2c_xfer; 1704 1705 return 0; 1706 } 1707 1708 static int dw_dp_probe(struct udevice *dev) 1709 { 1710 struct dw_dp *dp = dev_get_priv(dev); 1711 int ret; 1712 1713 ret = regmap_init_mem(dev, &dp->regmap); 1714 if (ret) 1715 return ret; 1716 1717 dp->id = of_alias_get_id(ofnode_to_np(dev->node), "dp"); 1718 if (dp->id < 0) 1719 dp->id = 0; 1720 1721 ret = reset_get_by_index(dev, 0, &dp->reset); 1722 if (ret) { 1723 dev_err(dev, "failed to get reset control: %d\n", ret); 1724 return ret; 1725 } 1726 1727 dp->force_hpd = dev_read_bool(dev, "force-hpd"); 1728 1729 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 1730 GPIOD_IS_IN); 1731 if (ret && ret != -ENOENT) { 1732 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 1733 return ret; 1734 } 1735 1736 generic_phy_get_by_index(dev, 0, &dp->phy); 1737 1738 dp->dev = dev; 1739 1740 dw_dp_ddc_init(dp); 1741 1742 return 0; 1743 } 1744 1745 static const struct rockchip_connector rk3588_dp_driver_data = { 1746 .funcs = &dw_dp_connector_funcs, 1747 }; 1748 1749 static const struct udevice_id dw_dp_ids[] = { 1750 { 1751 .compatible = "rockchip,rk3588-dp", 1752 .data = (ulong)&rk3588_dp_driver_data 1753 }, 1754 {} 1755 }; 1756 1757 U_BOOT_DRIVER(dw_dp) = { 1758 .name = "dw_dp", 1759 .id = UCLASS_DISPLAY, 1760 .of_match = dw_dp_ids, 1761 .probe = dw_dp_probe, 1762 .priv_auto_alloc_size = sizeof(struct dw_dp), 1763 }; 1764 1765