1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Rockchip USBDP Combo PHY with Samsung IP block driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd 6 */ 7 8 #include <config.h> 9 #include <common.h> 10 #include <errno.h> 11 #include <malloc.h> 12 #include <asm/unaligned.h> 13 #include <asm/io.h> 14 #include <clk.h> 15 #include <dm/device.h> 16 #include <dm/of_access.h> 17 #include <dm/read.h> 18 #include <generic-phy.h> 19 #include <linux/bitfield.h> 20 #include <linux/hdmi.h> 21 #include <linux/media-bus-format.h> 22 #include <linux/list.h> 23 #include <asm/gpio.h> 24 #include <generic-phy.h> 25 #include <regmap.h> 26 #include <reset.h> 27 #include <drm/drm_dp_helper.h> 28 29 #include "rockchip_display.h" 30 #include "rockchip_crtc.h" 31 #include "rockchip_connector.h" 32 33 #define DPTX_VERSION_NUMBER 0x0000 34 #define DPTX_VERSION_TYPE 0x0004 35 #define DPTX_ID 0x0008 36 37 #define DPTX_CONFIG_REG1 0x0100 38 #define DPTX_CONFIG_REG2 0x0104 39 #define DPTX_CONFIG_REG3 0x0108 40 41 #define DPTX_CCTL 0x0200 42 #define FORCE_HPD BIT(4) 43 #define DEFAULT_FAST_LINK_TRAIN_EN BIT(2) 44 #define ENHANCE_FRAMING_EN BIT(1) 45 #define SCRAMBLE_DIS BIT(0) 46 #define DPTX_SOFT_RESET_CTRL 0x0204 47 #define VIDEO_RESET BIT(5) 48 #define AUX_RESET BIT(4) 49 #define AUDIO_SAMPLER_RESET BIT(3) 50 #define PHY_SOFT_RESET BIT(1) 51 #define CONTROLLER_RESET BIT(0) 52 53 #define DPTX_VSAMPLE_CTRL 0x0300 54 #define PIXEL_MODE_SELECT GENMASK(22, 21) 55 #define VIDEO_MAPPING GENMASK(20, 16) 56 #define VIDEO_STREAM_ENABLE BIT(5) 57 #define DPTX_VSAMPLE_STUFF_CTRL1 0x0304 58 #define DPTX_VSAMPLE_STUFF_CTRL2 0x0308 59 #define DPTX_VINPUT_POLARITY_CTRL 0x030c 60 #define DE_IN_POLARITY BIT(2) 61 #define HSYNC_IN_POLARITY BIT(1) 62 #define VSYNC_IN_POLARITY BIT(0) 63 #define DPTX_VIDEO_CONFIG1 0x0310 64 #define HACTIVE GENMASK(31, 16) 65 #define HBLANK GENMASK(15, 2) 66 #define I_P BIT(1) 67 #define R_V_BLANK_IN_OSC BIT(0) 68 #define DPTX_VIDEO_CONFIG2 0x0314 69 #define VBLANK GENMASK(31, 16) 70 #define VACTIVE GENMASK(15, 0) 71 #define DPTX_VIDEO_CONFIG3 0x0318 72 #define H_SYNC_WIDTH GENMASK(31, 16) 73 #define H_FRONT_PORCH GENMASK(15, 0) 74 #define DPTX_VIDEO_CONFIG4 0x031c 75 #define V_SYNC_WIDTH GENMASK(31, 16) 76 #define V_FRONT_PORCH GENMASK(15, 0) 77 #define DPTX_VIDEO_CONFIG5 0x0320 78 #define INIT_THRESHOLD_HI GENMASK(22, 21) 79 #define AVERAGE_BYTES_PER_TU_FRAC GENMASK(19, 16) 80 #define INIT_THRESHOLD GENMASK(13, 7) 81 #define AVERAGE_BYTES_PER_TU GENMASK(6, 0) 82 #define DPTX_VIDEO_MSA1 0x0324 83 #define VSTART GENMASK(31, 16) 84 #define HSTART GENMASK(15, 0) 85 #define DPTX_VIDEO_MSA2 0x0328 86 #define MISC0 GENMASK(31, 24) 87 #define DPTX_VIDEO_MSA3 0x032c 88 #define MISC1 GENMASK(31, 24) 89 #define DPTX_VIDEO_HBLANK_INTERVAL 0x0330 90 #define HBLANK_INTERVAL_EN BIT(16) 91 #define HBLANK_INTERVAL GENMASK(15, 0) 92 93 #define DPTX_AUD_CONFIG1 0x0400 94 #define AUDIO_TIMESTAMP_VERSION_NUM GENMASK(29, 24) 95 #define AUDIO_PACKET_ID GENMASK(23, 16) 96 #define AUDIO_MUTE BIT(15) 97 #define NUM_CHANNELS GENMASK(14, 12) 98 #define HBR_MODE_ENABLE BIT(10) 99 #define AUDIO_DATA_WIDTH GENMASK(9, 5) 100 #define AUDIO_DATA_IN_EN GENMASK(4, 1) 101 #define AUDIO_INF_SELECT BIT(0) 102 103 #define DPTX_SDP_VERTICAL_CTRL 0x0500 104 #define EN_VERTICAL_SDP BIT(2) 105 #define EN_AUDIO_STREAM_SDP BIT(1) 106 #define EN_AUDIO_TIMESTAMP_SDP BIT(0) 107 #define DPTX_SDP_HORIZONTAL_CTRL 0x0504 108 #define EN_HORIZONTAL_SDP BIT(2) 109 #define DPTX_SDP_STATUS_REGISTER 0x0508 110 #define DPTX_SDP_MANUAL_CTRL 0x050c 111 #define DPTX_SDP_STATUS_EN 0x0510 112 113 #define DPTX_SDP_REGISTER_BANK 0x0600 114 #define SDP_REGS GENMASK(31, 0) 115 116 #define DPTX_PHYIF_CTRL 0x0a00 117 #define PHY_WIDTH BIT(25) 118 #define PHY_POWERDOWN GENMASK(20, 17) 119 #define PHY_BUSY GENMASK(15, 12) 120 #define SSC_DIS BIT(16) 121 #define XMIT_ENABLE GENMASK(11, 8) 122 #define PHY_LANES GENMASK(7, 6) 123 #define PHY_RATE GENMASK(5, 4) 124 #define TPS_SEL GENMASK(3, 0) 125 #define DPTX_PHY_TX_EQ 0x0a04 126 #define DPTX_CUSTOMPAT0 0x0a08 127 #define DPTX_CUSTOMPAT1 0x0a0c 128 #define DPTX_CUSTOMPAT2 0x0a10 129 #define DPTX_HBR2_COMPLIANCE_SCRAMBLER_RESET 0x0a14 130 #define DPTX_PHYIF_PWRDOWN_CTRL 0x0a18 131 132 #define DPTX_AUX_CMD 0x0b00 133 #define AUX_CMD_TYPE GENMASK(31, 28) 134 #define AUX_ADDR GENMASK(27, 8) 135 #define I2C_ADDR_ONLY BIT(4) 136 #define AUX_LEN_REQ GENMASK(3, 0) 137 #define DPTX_AUX_STATUS 0x0b04 138 #define AUX_TIMEOUT BIT(17) 139 #define AUX_BYTES_READ GENMASK(23, 19) 140 #define AUX_STATUS GENMASK(7, 4) 141 #define DPTX_AUX_DATA0 0x0b08 142 #define DPTX_AUX_DATA1 0x0b0c 143 #define DPTX_AUX_DATA2 0x0b10 144 #define DPTX_AUX_DATA3 0x0b14 145 146 #define DPTX_GENERAL_INTERRUPT 0x0d00 147 #define VIDEO_FIFO_OVERFLOW_STREAM0 BIT(6) 148 #define AUDIO_FIFO_OVERFLOW_STREAM0 BIT(5) 149 #define SDP_EVENT_STREAM0 BIT(4) 150 #define AUX_CMD_INVALID BIT(3) 151 #define AUX_REPLY_EVENT BIT(1) 152 #define HPD_EVENT BIT(0) 153 #define DPTX_GENERAL_INTERRUPT_ENABLE 0x0d04 154 #define AUX_REPLY_EVENT_EN BIT(1) 155 #define HPD_EVENT_EN BIT(0) 156 #define DPTX_HPD_STATUS 0x0d08 157 #define HPD_STATE GENMASK(11, 9) 158 #define HPD_STATUS BIT(8) 159 #define HPD_HOT_UNPLUG BIT(2) 160 #define HPD_HOT_PLUG BIT(1) 161 #define HPD_IRQ BIT(0) 162 #define DPTX_HPD_INTERRUPT_ENABLE 0x0d0c 163 #define HPD_UNPLUG_ERR_EN BIT(3) 164 #define HPD_UNPLUG_EN BIT(2) 165 #define HPD_PLUG_EN BIT(1) 166 #define HPD_IRQ_EN BIT(0) 167 168 #define DPTX_MAX_REGISTER DPTX_HPD_INTERRUPT_ENABLE 169 170 #define SDP_REG_BANK_SIZE 16 171 172 struct drm_dp_link_caps { 173 bool enhanced_framing; 174 bool tps3_supported; 175 bool tps4_supported; 176 bool channel_coding; 177 bool ssc; 178 }; 179 180 struct drm_dp_link_train_set { 181 unsigned int voltage_swing[4]; 182 unsigned int pre_emphasis[4]; 183 }; 184 185 struct drm_dp_link_train { 186 struct drm_dp_link_train_set request; 187 struct drm_dp_link_train_set adjust; 188 bool clock_recovered; 189 bool channel_equalized; 190 }; 191 192 struct dw_dp_link { 193 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 194 unsigned char revision; 195 unsigned int rate; 196 unsigned int lanes; 197 struct drm_dp_link_caps caps; 198 struct drm_dp_link_train train; 199 u8 sink_count; 200 u8 vsc_sdp_extension_for_colorimetry_supported; 201 }; 202 203 struct dw_dp_video { 204 struct drm_display_mode mode; 205 u32 bus_format; 206 u8 video_mapping; 207 u8 pixel_mode; 208 u8 color_format; 209 u8 bpc; 210 u8 bpp; 211 }; 212 213 struct dw_dp_sdp { 214 struct dp_sdp_header header; 215 u8 db[32]; 216 unsigned long flags; 217 }; 218 219 struct dw_dp { 220 struct udevice *dev; 221 struct regmap *regmap; 222 struct phy phy; 223 struct reset_ctl reset; 224 int id; 225 226 struct gpio_desc hpd_gpio; 227 struct drm_dp_aux aux; 228 struct dw_dp_link link; 229 struct dw_dp_video video; 230 }; 231 232 enum { 233 SOURCE_STATE_IDLE, 234 SOURCE_STATE_UNPLUG, 235 SOURCE_STATE_HPD_TIMEOUT = 4, 236 SOURCE_STATE_PLUG = 7 237 }; 238 239 enum { 240 DPTX_VM_RGB_6BIT, 241 DPTX_VM_RGB_8BIT, 242 DPTX_VM_RGB_10BIT, 243 DPTX_VM_RGB_12BIT, 244 DPTX_VM_RGB_16BIT, 245 DPTX_VM_YCBCR444_8BIT, 246 DPTX_VM_YCBCR444_10BIT, 247 DPTX_VM_YCBCR444_12BIT, 248 DPTX_VM_YCBCR444_16BIT, 249 DPTX_VM_YCBCR422_8BIT, 250 DPTX_VM_YCBCR422_10BIT, 251 DPTX_VM_YCBCR422_12BIT, 252 DPTX_VM_YCBCR422_16BIT, 253 DPTX_VM_YCBCR420_8BIT, 254 DPTX_VM_YCBCR420_10BIT, 255 DPTX_VM_YCBCR420_12BIT, 256 DPTX_VM_YCBCR420_16BIT, 257 }; 258 259 enum { 260 DPTX_MP_SINGLE_PIXEL, 261 DPTX_MP_DUAL_PIXEL, 262 DPTX_MP_QUAD_PIXEL, 263 }; 264 265 enum { 266 DPTX_SDP_VERTICAL_INTERVAL = BIT(0), 267 DPTX_SDP_HORIZONTAL_INTERVAL = BIT(1), 268 }; 269 270 enum { 271 DPTX_PHY_PATTERN_NONE, 272 DPTX_PHY_PATTERN_TPS_1, 273 DPTX_PHY_PATTERN_TPS_2, 274 DPTX_PHY_PATTERN_TPS_3, 275 DPTX_PHY_PATTERN_TPS_4, 276 DPTX_PHY_PATTERN_SERM, 277 DPTX_PHY_PATTERN_PBRS7, 278 DPTX_PHY_PATTERN_CUSTOM_80BIT, 279 DPTX_PHY_PATTERN_CP2520_1, 280 DPTX_PHY_PATTERN_CP2520_2, 281 }; 282 283 struct dw_dp_output_format { 284 u32 bus_format; 285 u32 color_format; 286 u8 video_mapping; 287 u8 bpc; 288 u8 bpp; 289 }; 290 291 static const struct dw_dp_output_format possible_output_fmts[] = { 292 { MEDIA_BUS_FMT_RGB101010_1X30, DRM_COLOR_FORMAT_RGB444, 293 DPTX_VM_RGB_10BIT, 10, 30 }, 294 { MEDIA_BUS_FMT_RGB888_1X24, DRM_COLOR_FORMAT_RGB444, 295 DPTX_VM_RGB_8BIT, 8, 24 }, 296 { MEDIA_BUS_FMT_YUV10_1X30, DRM_COLOR_FORMAT_YCRCB444, 297 DPTX_VM_YCBCR444_10BIT, 10, 30 }, 298 { MEDIA_BUS_FMT_YUV8_1X24, DRM_COLOR_FORMAT_YCRCB444, 299 DPTX_VM_YCBCR444_8BIT, 8, 24}, 300 { MEDIA_BUS_FMT_YUYV10_1X20, DRM_COLOR_FORMAT_YCRCB422, 301 DPTX_VM_YCBCR422_10BIT, 10, 20 }, 302 { MEDIA_BUS_FMT_YUYV8_1X16, DRM_COLOR_FORMAT_YCRCB422, 303 DPTX_VM_YCBCR422_8BIT, 8, 16 }, 304 { MEDIA_BUS_FMT_UYYVYY10_0_5X30, DRM_COLOR_FORMAT_YCRCB420, 305 DPTX_VM_YCBCR420_10BIT, 10, 15 }, 306 { MEDIA_BUS_FMT_UYYVYY8_0_5X24, DRM_COLOR_FORMAT_YCRCB420, 307 DPTX_VM_YCBCR420_8BIT, 8, 12 }, 308 { MEDIA_BUS_FMT_RGB666_1X24_CPADHI, DRM_COLOR_FORMAT_RGB444, 309 DPTX_VM_RGB_6BIT, 6, 18 }, 310 }; 311 312 static int dw_dp_aux_write_data(struct dw_dp *dp, const u8 *buffer, size_t size) 313 { 314 size_t i, j; 315 316 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 317 size_t num = min_t(size_t, size - i * 4, 4); 318 u32 value = 0; 319 320 for (j = 0; j < num; j++) 321 value |= buffer[i * 4 + j] << (j * 8); 322 323 regmap_write(dp->regmap, DPTX_AUX_DATA0 + i * 4, value); 324 } 325 326 return size; 327 } 328 329 static int dw_dp_aux_read_data(struct dw_dp *dp, u8 *buffer, size_t size) 330 { 331 size_t i, j; 332 333 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 334 size_t num = min_t(size_t, size - i * 4, 4); 335 u32 value; 336 337 regmap_read(dp->regmap, DPTX_AUX_DATA0 + i * 4, &value); 338 339 for (j = 0; j < num; j++) 340 buffer[i * 4 + j] = value >> (j * 8); 341 } 342 343 return size; 344 } 345 346 static ssize_t dw_dp_aux_transfer(struct drm_dp_aux *aux, 347 struct drm_dp_aux_msg *msg) 348 { 349 u32 status, value; 350 ssize_t ret = 0; 351 int timeout = 0; 352 struct dw_dp *dp = dev_get_priv(aux->dev); 353 354 if (WARN_ON(msg->size > 16)) 355 return -E2BIG; 356 357 switch (msg->request & ~DP_AUX_I2C_MOT) { 358 case DP_AUX_NATIVE_WRITE: 359 case DP_AUX_I2C_WRITE: 360 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 361 ret = dw_dp_aux_write_data(dp, msg->buffer, msg->size); 362 if (ret < 0) 363 return ret; 364 break; 365 case DP_AUX_NATIVE_READ: 366 case DP_AUX_I2C_READ: 367 break; 368 default: 369 return -EINVAL; 370 } 371 372 if (msg->size > 0) 373 value = FIELD_PREP(AUX_LEN_REQ, msg->size - 1); 374 else 375 value = FIELD_PREP(I2C_ADDR_ONLY, 1); 376 377 value |= FIELD_PREP(AUX_CMD_TYPE, msg->request); 378 value |= FIELD_PREP(AUX_ADDR, msg->address); 379 regmap_write(dp->regmap, DPTX_AUX_CMD, value); 380 381 timeout = regmap_read_poll_timeout(dp->regmap, DPTX_GENERAL_INTERRUPT, 382 status, status & AUX_REPLY_EVENT, 383 200, 10); 384 385 if (timeout) { 386 printf("timeout waiting for AUX reply\n"); 387 return -ETIMEDOUT; 388 } 389 regmap_write(dp->regmap, DPTX_GENERAL_INTERRUPT, AUX_REPLY_EVENT); 390 391 regmap_read(dp->regmap, DPTX_AUX_STATUS, &value); 392 if (value & AUX_TIMEOUT) { 393 printf("aux timeout\n"); 394 return -ETIMEDOUT; 395 } 396 397 msg->reply = FIELD_GET(AUX_STATUS, value); 398 399 if (msg->size > 0 && msg->reply == DP_AUX_NATIVE_REPLY_ACK) { 400 if (msg->request & DP_AUX_I2C_READ) { 401 size_t count = FIELD_GET(AUX_BYTES_READ, value) - 1; 402 403 if (count != msg->size) { 404 printf("aux fail to read %lu bytes\n", count); 405 return -EBUSY; 406 } 407 408 ret = dw_dp_aux_read_data(dp, msg->buffer, count); 409 if (ret < 0) 410 return ret; 411 } 412 } 413 414 return ret; 415 } 416 417 static bool dw_dp_bandwidth_ok(struct dw_dp *dp, 418 const struct drm_display_mode *mode, u32 bpp, 419 unsigned int lanes, unsigned int rate) 420 { 421 u32 max_bw, req_bw; 422 423 req_bw = mode->clock * bpp / 8; 424 max_bw = lanes * rate; 425 if (req_bw > max_bw) 426 return false; 427 428 return true; 429 } 430 431 static void dw_dp_hpd_init(struct dw_dp *dp) 432 { 433 if (dm_gpio_is_valid(&dp->hpd_gpio)) { 434 regmap_update_bits(dp->regmap, DPTX_CCTL, FORCE_HPD, 435 FIELD_PREP(FORCE_HPD, 1)); 436 return; 437 } 438 439 /* Enable all HPD interrupts */ 440 regmap_update_bits(dp->regmap, DPTX_HPD_INTERRUPT_ENABLE, 441 HPD_UNPLUG_EN | HPD_PLUG_EN | HPD_IRQ_EN, 442 FIELD_PREP(HPD_UNPLUG_EN, 1) | 443 FIELD_PREP(HPD_PLUG_EN, 1) | 444 FIELD_PREP(HPD_IRQ_EN, 1)); 445 446 /* Enable all top-level interrupts */ 447 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, 448 HPD_EVENT_EN, FIELD_PREP(HPD_EVENT_EN, 1)); 449 } 450 451 static void dw_dp_aux_init(struct dw_dp *dp) 452 { 453 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, 454 FIELD_PREP(AUX_RESET, 1)); 455 udelay(10); 456 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, 457 FIELD_PREP(AUX_RESET, 0)); 458 459 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, 460 AUX_REPLY_EVENT_EN, 461 FIELD_PREP(AUX_REPLY_EVENT_EN, 1)); 462 } 463 464 static void dw_dp_init(struct dw_dp *dp) 465 { 466 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, 467 FIELD_PREP(CONTROLLER_RESET, 1)); 468 udelay(10); 469 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, 470 FIELD_PREP(CONTROLLER_RESET, 0)); 471 472 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, 473 FIELD_PREP(PHY_SOFT_RESET, 1)); 474 udelay(10); 475 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, 476 FIELD_PREP(PHY_SOFT_RESET, 0)); 477 478 regmap_update_bits(dp->regmap, DPTX_CCTL, DEFAULT_FAST_LINK_TRAIN_EN, 479 FIELD_PREP(DEFAULT_FAST_LINK_TRAIN_EN, 0)); 480 481 dw_dp_hpd_init(dp); 482 dw_dp_aux_init(dp); 483 } 484 485 static void dw_dp_phy_set_pattern(struct dw_dp *dp, u32 pattern) 486 { 487 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, TPS_SEL, 488 FIELD_PREP(TPS_SEL, pattern)); 489 } 490 491 static void dw_dp_phy_xmit_enable(struct dw_dp *dp, u32 lanes) 492 { 493 u32 xmit_enable; 494 495 switch (lanes) { 496 case 4: 497 case 2: 498 case 1: 499 xmit_enable = GENMASK(lanes - 1, 0); 500 break; 501 case 0: 502 default: 503 xmit_enable = 0; 504 break; 505 } 506 507 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, XMIT_ENABLE, 508 FIELD_PREP(XMIT_ENABLE, xmit_enable)); 509 } 510 511 static int dw_dp_link_power_up(struct dw_dp *dp) 512 { 513 struct dw_dp_link *link = &dp->link; 514 u8 value; 515 int ret; 516 517 if (link->revision < 0x11) 518 return 0; 519 520 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value); 521 if (ret < 0) 522 return ret; 523 524 value &= ~DP_SET_POWER_MASK; 525 value |= DP_SET_POWER_D0; 526 527 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value); 528 if (ret < 0) 529 return ret; 530 531 udelay(1000); 532 return 0; 533 } 534 535 static int dw_dp_link_probe(struct dw_dp *dp) 536 { 537 struct dw_dp_link *link = &dp->link; 538 u8 dpcd; 539 int ret; 540 541 ret = drm_dp_read_dpcd_caps(&dp->aux, link->dpcd); 542 if (ret < 0) 543 return ret; 544 545 ret = drm_dp_dpcd_readb(&dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, 546 &dpcd); 547 if (ret < 0) 548 return ret; 549 550 link->vsc_sdp_extension_for_colorimetry_supported = 551 !!(dpcd & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED); 552 553 link->revision = link->dpcd[DP_DPCD_REV]; 554 link->rate = drm_dp_max_link_rate(link->dpcd); 555 link->lanes = min_t(u8, dp->phy.attrs.bus_width, 556 drm_dp_max_lane_count(link->dpcd)); 557 558 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(link->dpcd); 559 link->caps.tps3_supported = drm_dp_tps3_supported(link->dpcd); 560 link->caps.tps4_supported = drm_dp_tps4_supported(link->dpcd); 561 link->caps.channel_coding = drm_dp_channel_coding_supported(link->dpcd); 562 link->caps.ssc = !!(link->dpcd[DP_MAX_DOWNSPREAD] & 563 DP_MAX_DOWNSPREAD_0_5); 564 565 return 0; 566 } 567 568 static int dw_dp_link_train_update_vs_emph(struct dw_dp *dp) 569 { 570 struct dw_dp_link *link = &dp->link; 571 struct drm_dp_link_train_set *request = &link->train.request; 572 union phy_configure_opts phy_cfg; 573 unsigned int lanes = link->lanes, *vs, *pe; 574 u8 buf[4]; 575 int i, ret; 576 577 vs = request->voltage_swing; 578 pe = request->pre_emphasis; 579 580 for (i = 0; i < lanes; i++) { 581 phy_cfg.dp.voltage[i] = vs[i]; 582 phy_cfg.dp.pre[i] = pe[i]; 583 } 584 phy_cfg.dp.lanes = lanes; 585 phy_cfg.dp.link_rate = link->rate / 100; 586 phy_cfg.dp.set_lanes = false; 587 phy_cfg.dp.set_rate = false; 588 phy_cfg.dp.set_voltages = true; 589 ret = generic_phy_configure(&dp->phy, &phy_cfg); 590 if (ret) 591 return ret; 592 593 for (i = 0; i < lanes; i++) 594 buf[i] = (vs[i] << DP_TRAIN_VOLTAGE_SWING_SHIFT) | 595 (pe[i] << DP_TRAIN_PRE_EMPHASIS_SHIFT); 596 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, lanes); 597 if (ret < 0) 598 return ret; 599 600 return 0; 601 } 602 603 static int dw_dp_link_configure(struct dw_dp *dp) 604 { 605 struct dw_dp_link *link = &dp->link; 606 union phy_configure_opts phy_cfg; 607 u8 buf[2]; 608 int ret; 609 610 /* Move PHY to P3 */ 611 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 612 FIELD_PREP(PHY_POWERDOWN, 0x3)); 613 614 phy_cfg.dp.lanes = link->lanes; 615 phy_cfg.dp.link_rate = link->rate / 100; 616 phy_cfg.dp.ssc = link->caps.ssc; 617 phy_cfg.dp.set_lanes = true; 618 phy_cfg.dp.set_rate = true; 619 phy_cfg.dp.set_voltages = false; 620 ret = generic_phy_configure(&dp->phy, &phy_cfg); 621 if (ret) 622 return ret; 623 624 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, 625 FIELD_PREP(PHY_LANES, link->lanes / 2)); 626 627 /* Move PHY to P0 */ 628 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 629 FIELD_PREP(PHY_POWERDOWN, 0x0)); 630 631 dw_dp_phy_xmit_enable(dp, link->lanes); 632 633 buf[0] = drm_dp_link_rate_to_bw_code(link->rate); 634 buf[1] = link->lanes; 635 636 if (link->caps.enhanced_framing) { 637 buf[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 638 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 639 FIELD_PREP(ENHANCE_FRAMING_EN, 1)); 640 } else { 641 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 642 FIELD_PREP(ENHANCE_FRAMING_EN, 0)); 643 } 644 645 ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, sizeof(buf)); 646 if (ret < 0) 647 return ret; 648 649 buf[0] = link->caps.ssc ? DP_SPREAD_AMP_0_5 : 0; 650 buf[1] = link->caps.channel_coding ? DP_SET_ANSI_8B10B : 0; 651 652 ret = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, 653 sizeof(buf)); 654 if (ret < 0) 655 return ret; 656 657 return 0; 658 } 659 660 static void dw_dp_link_train_init(struct drm_dp_link_train *train) 661 { 662 struct drm_dp_link_train_set *request = &train->request; 663 struct drm_dp_link_train_set *adjust = &train->adjust; 664 unsigned int i; 665 666 for (i = 0; i < 4; i++) { 667 request->voltage_swing[i] = 0; 668 adjust->voltage_swing[i] = 0; 669 670 request->pre_emphasis[i] = 0; 671 adjust->pre_emphasis[i] = 0; 672 } 673 674 train->clock_recovered = false; 675 train->channel_equalized = false; 676 } 677 678 static int dw_dp_link_train_set_pattern(struct dw_dp *dp, u32 pattern) 679 { 680 u8 buf = 0; 681 int ret; 682 683 if (pattern && pattern != DP_TRAINING_PATTERN_4) { 684 buf |= DP_LINK_SCRAMBLING_DISABLE; 685 686 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, 687 FIELD_PREP(SCRAMBLE_DIS, 1)); 688 } else { 689 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, 690 FIELD_PREP(SCRAMBLE_DIS, 0)); 691 } 692 693 switch (pattern) { 694 case DP_TRAINING_PATTERN_DISABLE: 695 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE); 696 break; 697 case DP_TRAINING_PATTERN_1: 698 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_1); 699 break; 700 case DP_TRAINING_PATTERN_2: 701 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_2); 702 break; 703 case DP_TRAINING_PATTERN_3: 704 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_3); 705 break; 706 case DP_TRAINING_PATTERN_4: 707 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_4); 708 break; 709 default: 710 return -EINVAL; 711 } 712 713 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 714 buf | pattern); 715 if (ret < 0) 716 return ret; 717 718 return 0; 719 } 720 721 static void dw_dp_link_get_adjustments(struct dw_dp_link *link, 722 u8 status[DP_LINK_STATUS_SIZE]) 723 { 724 struct drm_dp_link_train_set *adjust = &link->train.adjust; 725 unsigned int i; 726 727 for (i = 0; i < link->lanes; i++) { 728 adjust->voltage_swing[i] = 729 drm_dp_get_adjust_request_voltage(status, i) >> 730 DP_TRAIN_VOLTAGE_SWING_SHIFT; 731 732 adjust->pre_emphasis[i] = 733 drm_dp_get_adjust_request_pre_emphasis(status, i) >> 734 DP_TRAIN_PRE_EMPHASIS_SHIFT; 735 } 736 } 737 738 static void dw_dp_link_train_adjust(struct drm_dp_link_train *train) 739 { 740 struct drm_dp_link_train_set *request = &train->request; 741 struct drm_dp_link_train_set *adjust = &train->adjust; 742 unsigned int i; 743 744 for (i = 0; i < 4; i++) 745 if (request->voltage_swing[i] != adjust->voltage_swing[i]) 746 request->voltage_swing[i] = adjust->voltage_swing[i]; 747 748 for (i = 0; i < 4; i++) 749 if (request->pre_emphasis[i] != adjust->pre_emphasis[i]) 750 request->pre_emphasis[i] = adjust->pre_emphasis[i]; 751 } 752 753 static int dw_dp_link_clock_recovery(struct dw_dp *dp) 754 { 755 struct dw_dp_link *link = &dp->link; 756 u8 status[DP_LINK_STATUS_SIZE]; 757 unsigned int tries = 0; 758 int ret; 759 760 ret = dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_1); 761 if (ret) 762 return ret; 763 764 for (;;) { 765 ret = dw_dp_link_train_update_vs_emph(dp); 766 if (ret) 767 return ret; 768 769 drm_dp_link_train_clock_recovery_delay(link->dpcd); 770 771 ret = drm_dp_dpcd_read_link_status(&dp->aux, status); 772 if (ret < 0) { 773 dev_err(dp->dev, "failed to read link status: %d\n", 774 ret); 775 return ret; 776 } 777 778 if (drm_dp_clock_recovery_ok(status, link->lanes)) { 779 link->train.clock_recovered = true; 780 break; 781 } 782 783 dw_dp_link_get_adjustments(link, status); 784 785 if (link->train.request.voltage_swing[0] == 786 link->train.adjust.voltage_swing[0]) 787 tries++; 788 else 789 tries = 0; 790 791 if (tries == 5) 792 break; 793 794 dw_dp_link_train_adjust(&link->train); 795 } 796 797 return 0; 798 } 799 800 static int dw_dp_link_channel_equalization(struct dw_dp *dp) 801 { 802 struct dw_dp_link *link = &dp->link; 803 u8 status[DP_LINK_STATUS_SIZE], pattern; 804 unsigned int tries; 805 int ret; 806 807 if (link->caps.tps4_supported) 808 pattern = DP_TRAINING_PATTERN_4; 809 else if (link->caps.tps3_supported) 810 pattern = DP_TRAINING_PATTERN_3; 811 else 812 pattern = DP_TRAINING_PATTERN_2; 813 ret = dw_dp_link_train_set_pattern(dp, pattern); 814 if (ret) 815 return ret; 816 817 for (tries = 1; tries < 5; tries++) { 818 ret = dw_dp_link_train_update_vs_emph(dp); 819 if (ret) 820 return ret; 821 822 drm_dp_link_train_channel_eq_delay(link->dpcd); 823 824 ret = drm_dp_dpcd_read_link_status(&dp->aux, status); 825 if (ret < 0) 826 return ret; 827 828 if (!drm_dp_clock_recovery_ok(status, link->lanes)) { 829 dev_err(dp->dev, 830 "clock recovery lost while eq\n"); 831 link->train.clock_recovered = false; 832 break; 833 } 834 835 if (drm_dp_channel_eq_ok(status, link->lanes)) { 836 link->train.channel_equalized = true; 837 break; 838 } 839 840 dw_dp_link_get_adjustments(link, status); 841 dw_dp_link_train_adjust(&link->train); 842 } 843 844 return 0; 845 } 846 847 static int dw_dp_link_downgrade(struct dw_dp *dp) 848 { 849 struct dw_dp_link *link = &dp->link; 850 struct dw_dp_video *video = &dp->video; 851 852 switch (link->rate) { 853 case 162000: 854 return -EINVAL; 855 case 270000: 856 link->rate = 162000; 857 break; 858 case 540000: 859 link->rate = 270000; 860 break; 861 case 810000: 862 link->rate = 540000; 863 break; 864 } 865 866 if (!dw_dp_bandwidth_ok(dp, &video->mode, video->bpp, link->lanes, 867 link->rate)) 868 return -E2BIG; 869 870 return 0; 871 } 872 873 static int dw_dp_link_train(struct dw_dp *dp) 874 { 875 struct dw_dp_link *link = &dp->link; 876 int ret; 877 878 retry: 879 dw_dp_link_train_init(&link->train); 880 881 printf("training link: %u lane%s at %u MHz\n", 882 link->lanes, (link->lanes > 1) ? "s" : "", link->rate / 100); 883 884 ret = dw_dp_link_configure(dp); 885 if (ret < 0) { 886 dev_err(dp->dev, "failed to configure DP link: %d\n", ret); 887 return ret; 888 } 889 890 ret = dw_dp_link_clock_recovery(dp); 891 if (ret < 0) { 892 dev_err(dp->dev, "clock recovery failed: %d\n", ret); 893 goto out; 894 } 895 896 if (!link->train.clock_recovered) { 897 dev_err(dp->dev, "clock recovery failed, downgrading link\n"); 898 899 ret = dw_dp_link_downgrade(dp); 900 if (ret < 0) 901 goto out; 902 else 903 goto retry; 904 } 905 906 printf("clock recovery succeeded\n"); 907 908 ret = dw_dp_link_channel_equalization(dp); 909 if (ret < 0) { 910 dev_err(dp->dev, "channel equalization failed: %d\n", ret); 911 goto out; 912 } 913 914 if (!link->train.channel_equalized) { 915 dev_err(dp->dev, 916 "channel equalization failed, downgrading link\n"); 917 918 ret = dw_dp_link_downgrade(dp); 919 if (ret < 0) 920 goto out; 921 else 922 goto retry; 923 } 924 925 printf("channel equalization succeeded\n"); 926 927 out: 928 dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE); 929 return ret; 930 } 931 932 static int dw_dp_link_enable(struct dw_dp *dp) 933 { 934 int ret; 935 936 ret = dw_dp_link_power_up(dp); 937 if (ret < 0) 938 return ret; 939 940 ret = dw_dp_link_train(dp); 941 if (ret < 0) { 942 dev_err(dp->dev, "link training failed: %d\n", ret); 943 return ret; 944 } 945 946 return 0; 947 } 948 949 static int dw_dp_send_sdp(struct dw_dp *dp, struct dw_dp_sdp *sdp) 950 { 951 const u8 *payload = sdp->db; 952 u32 reg; 953 int i, nr = 0; 954 955 reg = DPTX_SDP_REGISTER_BANK + nr * 9 * 4; 956 957 /* SDP header */ 958 regmap_write(dp->regmap, reg, get_unaligned_le32(&sdp->header)); 959 960 /* SDP data payload */ 961 for (i = 1; i < 9; i++, payload += 4) 962 regmap_write(dp->regmap, reg + i * 4, 963 FIELD_PREP(SDP_REGS, get_unaligned_le32(payload))); 964 965 if (sdp->flags & DPTX_SDP_VERTICAL_INTERVAL) 966 regmap_update_bits(dp->regmap, DPTX_SDP_VERTICAL_CTRL, 967 EN_VERTICAL_SDP << nr, 968 EN_VERTICAL_SDP << nr); 969 970 if (sdp->flags & DPTX_SDP_HORIZONTAL_INTERVAL) 971 regmap_update_bits(dp->regmap, DPTX_SDP_HORIZONTAL_CTRL, 972 EN_HORIZONTAL_SDP << nr, 973 EN_HORIZONTAL_SDP << nr); 974 975 return 0; 976 } 977 978 static void dw_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, 979 struct dw_dp_sdp *sdp) 980 { 981 sdp->header.HB0 = 0; 982 sdp->header.HB1 = DP_SDP_VSC; 983 sdp->header.HB2 = vsc->revision; 984 sdp->header.HB3 = vsc->length; 985 986 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; 987 sdp->db[16] |= vsc->colorimetry & 0xf; 988 989 switch (vsc->bpc) { 990 case 8: 991 sdp->db[17] = 0x1; 992 break; 993 case 10: 994 sdp->db[17] = 0x2; 995 break; 996 case 12: 997 sdp->db[17] = 0x3; 998 break; 999 case 16: 1000 sdp->db[17] = 0x4; 1001 break; 1002 case 6: 1003 default: 1004 break; 1005 } 1006 1007 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) 1008 sdp->db[17] |= 0x80; 1009 1010 sdp->db[18] = vsc->content_type & 0x7; 1011 1012 sdp->flags |= DPTX_SDP_VERTICAL_INTERVAL; 1013 } 1014 1015 static int dw_dp_send_vsc_sdp(struct dw_dp *dp) 1016 { 1017 struct dw_dp_video *video = &dp->video; 1018 struct drm_dp_vsc_sdp vsc = {}; 1019 struct dw_dp_sdp sdp = {}; 1020 1021 vsc.revision = 0x5; 1022 vsc.length = 0x13; 1023 1024 switch (video->color_format) { 1025 case DRM_COLOR_FORMAT_YCRCB444: 1026 vsc.pixelformat = DP_PIXELFORMAT_YUV444; 1027 break; 1028 case DRM_COLOR_FORMAT_YCRCB420: 1029 vsc.pixelformat = DP_PIXELFORMAT_YUV420; 1030 break; 1031 case DRM_COLOR_FORMAT_YCRCB422: 1032 vsc.pixelformat = DP_PIXELFORMAT_YUV422; 1033 break; 1034 case DRM_COLOR_FORMAT_RGB444: 1035 default: 1036 vsc.pixelformat = DP_PIXELFORMAT_RGB; 1037 break; 1038 } 1039 1040 if (video->color_format == DRM_COLOR_FORMAT_RGB444) 1041 vsc.colorimetry = DP_COLORIMETRY_DEFAULT; 1042 else 1043 vsc.colorimetry = DP_COLORIMETRY_BT709_YCC; 1044 1045 vsc.bpc = video->bpc; 1046 vsc.dynamic_range = DP_DYNAMIC_RANGE_CTA; 1047 vsc.content_type = DP_CONTENT_TYPE_NOT_DEFINED; 1048 1049 dw_dp_vsc_sdp_pack(&vsc, &sdp); 1050 1051 return dw_dp_send_sdp(dp, &sdp); 1052 } 1053 1054 static int dw_dp_video_set_pixel_mode(struct dw_dp *dp, u8 pixel_mode) 1055 { 1056 switch (pixel_mode) { 1057 case DPTX_MP_SINGLE_PIXEL: 1058 case DPTX_MP_DUAL_PIXEL: 1059 case DPTX_MP_QUAD_PIXEL: 1060 break; 1061 default: 1062 return -EINVAL; 1063 } 1064 1065 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, PIXEL_MODE_SELECT, 1066 FIELD_PREP(PIXEL_MODE_SELECT, pixel_mode)); 1067 1068 return 0; 1069 } 1070 1071 static int dw_dp_video_set_msa(struct dw_dp *dp, u8 color_format, u8 bpc, 1072 u16 vstart, u16 hstart) 1073 { 1074 struct dw_dp_link *link = &dp->link; 1075 u16 misc = 0; 1076 1077 if (link->vsc_sdp_extension_for_colorimetry_supported) 1078 misc |= DP_MSA_MISC_COLOR_VSC_SDP; 1079 1080 switch (color_format) { 1081 case DRM_COLOR_FORMAT_RGB444: 1082 misc |= DP_MSA_MISC_COLOR_RGB; 1083 break; 1084 case DRM_COLOR_FORMAT_YCRCB444: 1085 misc |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 1086 break; 1087 case DRM_COLOR_FORMAT_YCRCB422: 1088 misc |= DP_MSA_MISC_COLOR_YCBCR_422_BT709; 1089 break; 1090 case DRM_COLOR_FORMAT_YCRCB420: 1091 break; 1092 default: 1093 return -EINVAL; 1094 } 1095 1096 switch (bpc) { 1097 case 6: 1098 misc |= DP_MSA_MISC_6_BPC; 1099 break; 1100 case 8: 1101 misc |= DP_MSA_MISC_8_BPC; 1102 break; 1103 case 10: 1104 misc |= DP_MSA_MISC_10_BPC; 1105 break; 1106 case 12: 1107 misc |= DP_MSA_MISC_12_BPC; 1108 break; 1109 case 16: 1110 misc |= DP_MSA_MISC_16_BPC; 1111 break; 1112 default: 1113 return -EINVAL; 1114 } 1115 1116 regmap_write(dp->regmap, DPTX_VIDEO_MSA1, 1117 FIELD_PREP(VSTART, vstart) | FIELD_PREP(HSTART, hstart)); 1118 regmap_write(dp->regmap, DPTX_VIDEO_MSA2, FIELD_PREP(MISC0, misc)); 1119 regmap_write(dp->regmap, DPTX_VIDEO_MSA3, FIELD_PREP(MISC1, misc >> 8)); 1120 1121 return 0; 1122 } 1123 1124 static int dw_dp_video_enable(struct dw_dp *dp) 1125 { 1126 struct dw_dp_video *video = &dp->video; 1127 struct dw_dp_link *link = &dp->link; 1128 struct drm_display_mode *mode = &video->mode; 1129 u8 color_format = video->color_format; 1130 u8 bpc = video->bpc; 1131 u8 pixel_mode = video->pixel_mode; 1132 u8 bpp = video->bpp, init_threshold, vic; 1133 u32 hactive, hblank, h_sync_width, h_front_porch; 1134 u32 vactive, vblank, v_sync_width, v_front_porch; 1135 u32 vstart = mode->vtotal - mode->vsync_start; 1136 u32 hstart = mode->htotal - mode->hsync_start; 1137 u32 peak_stream_bandwidth, link_bandwidth; 1138 u32 average_bytes_per_tu, average_bytes_per_tu_frac; 1139 u32 ts, hblank_interval; 1140 u32 value; 1141 int ret; 1142 1143 ret = dw_dp_video_set_pixel_mode(dp, pixel_mode); 1144 if (ret) 1145 return ret; 1146 1147 ret = dw_dp_video_set_msa(dp, color_format, bpc, vstart, hstart); 1148 if (ret) 1149 return ret; 1150 1151 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_MAPPING, 1152 FIELD_PREP(VIDEO_MAPPING, video->video_mapping)); 1153 1154 /* Configure DPTX_VINPUT_POLARITY_CTRL register */ 1155 value = 0; 1156 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1157 value |= FIELD_PREP(HSYNC_IN_POLARITY, 1); 1158 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1159 value |= FIELD_PREP(VSYNC_IN_POLARITY, 1); 1160 regmap_write(dp->regmap, DPTX_VINPUT_POLARITY_CTRL, value); 1161 1162 /* Configure DPTX_VIDEO_CONFIG1 register */ 1163 hactive = mode->hdisplay; 1164 hblank = mode->htotal - mode->hdisplay; 1165 value = FIELD_PREP(HACTIVE, hactive) | FIELD_PREP(HBLANK, hblank); 1166 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1167 value |= FIELD_PREP(I_P, 1); 1168 vic = drm_match_cea_mode(mode); 1169 if (vic == 5 || vic == 6 || vic == 7 || 1170 vic == 10 || vic == 11 || vic == 20 || 1171 vic == 21 || vic == 22 || vic == 39 || 1172 vic == 25 || vic == 26 || vic == 40 || 1173 vic == 44 || vic == 45 || vic == 46 || 1174 vic == 50 || vic == 51 || vic == 54 || 1175 vic == 55 || vic == 58 || vic == 59) 1176 value |= R_V_BLANK_IN_OSC; 1177 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG1, value); 1178 1179 /* Configure DPTX_VIDEO_CONFIG2 register */ 1180 vblank = mode->vtotal - mode->vdisplay; 1181 vactive = mode->vdisplay; 1182 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG2, 1183 FIELD_PREP(VBLANK, vblank) | FIELD_PREP(VACTIVE, vactive)); 1184 1185 /* Configure DPTX_VIDEO_CONFIG3 register */ 1186 h_sync_width = mode->hsync_end - mode->hsync_start; 1187 h_front_porch = mode->hsync_start - mode->hdisplay; 1188 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG3, 1189 FIELD_PREP(H_SYNC_WIDTH, h_sync_width) | 1190 FIELD_PREP(H_FRONT_PORCH, h_front_porch)); 1191 1192 /* Configure DPTX_VIDEO_CONFIG4 register */ 1193 v_sync_width = mode->vsync_end - mode->vsync_start; 1194 v_front_porch = mode->vsync_start - mode->vdisplay; 1195 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG4, 1196 FIELD_PREP(V_SYNC_WIDTH, v_sync_width) | 1197 FIELD_PREP(V_FRONT_PORCH, v_front_porch)); 1198 1199 /* Configure DPTX_VIDEO_CONFIG5 register */ 1200 peak_stream_bandwidth = mode->clock * bpp / 8; 1201 link_bandwidth = (link->rate / 1000) * link->lanes; 1202 ts = peak_stream_bandwidth * 64 / link_bandwidth; 1203 average_bytes_per_tu = ts / 1000; 1204 average_bytes_per_tu_frac = ts / 100 - average_bytes_per_tu * 10; 1205 if (pixel_mode == DPTX_MP_SINGLE_PIXEL) { 1206 if (average_bytes_per_tu < 6) 1207 init_threshold = 32; 1208 else if (hblank <= 80 && 1209 color_format != DRM_COLOR_FORMAT_YCRCB420) 1210 init_threshold = 12; 1211 else if (hblank <= 40 && 1212 color_format == DRM_COLOR_FORMAT_YCRCB420) 1213 init_threshold = 3; 1214 else 1215 init_threshold = 16; 1216 } else { 1217 u32 t1 = 0, t2 = 0, t3 = 0; 1218 1219 switch (bpc) { 1220 case 6: 1221 t1 = (4 * 1000 / 9) * link->lanes; 1222 break; 1223 case 8: 1224 if (color_format == DRM_COLOR_FORMAT_YCRCB422) { 1225 t1 = (1000 / 2) * link->lanes; 1226 } else { 1227 if (pixel_mode == DPTX_MP_DUAL_PIXEL) 1228 t1 = (1000 / 3) * link->lanes; 1229 else 1230 t1 = (3000 / 16) * link->lanes; 1231 } 1232 break; 1233 case 10: 1234 if (color_format == DRM_COLOR_FORMAT_YCRCB422) 1235 t1 = (2000 / 5) * link->lanes; 1236 else 1237 t1 = (4000 / 15) * link->lanes; 1238 break; 1239 case 12: 1240 if (color_format == DRM_COLOR_FORMAT_YCRCB422) { 1241 if (pixel_mode == DPTX_MP_DUAL_PIXEL) 1242 t1 = (1000 / 6) * link->lanes; 1243 else 1244 t1 = (1000 / 3) * link->lanes; 1245 } else { 1246 t1 = (2000 / 9) * link->lanes; 1247 } 1248 break; 1249 case 16: 1250 if (color_format != DRM_COLOR_FORMAT_YCRCB422 && 1251 pixel_mode == DPTX_MP_DUAL_PIXEL) 1252 t1 = (1000 / 6) * link->lanes; 1253 else 1254 t1 = (1000 / 4) * link->lanes; 1255 break; 1256 default: 1257 return -EINVAL; 1258 } 1259 1260 if (color_format == DRM_COLOR_FORMAT_YCRCB420) 1261 t2 = (link->rate / 4) * 1000 / (mode->clock / 2); 1262 else 1263 t2 = (link->rate / 4) * 1000 / mode->clock; 1264 1265 if (average_bytes_per_tu_frac) 1266 t3 = average_bytes_per_tu + 1; 1267 else 1268 t3 = average_bytes_per_tu; 1269 init_threshold = t1 * t2 * t3 / (1000 * 1000); 1270 if (init_threshold <= 16 || average_bytes_per_tu < 10) 1271 init_threshold = 40; 1272 } 1273 1274 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG5, 1275 FIELD_PREP(INIT_THRESHOLD_HI, init_threshold >> 6) | 1276 FIELD_PREP(AVERAGE_BYTES_PER_TU_FRAC, 1277 average_bytes_per_tu_frac) | 1278 FIELD_PREP(INIT_THRESHOLD, init_threshold) | 1279 FIELD_PREP(AVERAGE_BYTES_PER_TU, average_bytes_per_tu)); 1280 1281 /* Configure DPTX_VIDEO_HBLANK_INTERVAL register */ 1282 hblank_interval = hblank * (link->rate / 4) / mode->clock; 1283 regmap_write(dp->regmap, DPTX_VIDEO_HBLANK_INTERVAL, 1284 FIELD_PREP(HBLANK_INTERVAL_EN, 1) | 1285 FIELD_PREP(HBLANK_INTERVAL, hblank_interval)); 1286 1287 /* Video stream enable */ 1288 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_STREAM_ENABLE, 1289 FIELD_PREP(VIDEO_STREAM_ENABLE, 1)); 1290 1291 if (link->vsc_sdp_extension_for_colorimetry_supported) 1292 dw_dp_send_vsc_sdp(dp); 1293 1294 return 0; 1295 } 1296 1297 static bool dw_dp_detect(struct dw_dp *dp) 1298 { 1299 u32 value; 1300 1301 if (dm_gpio_is_valid(&dp->hpd_gpio)) 1302 return dm_gpio_get_value(&dp->hpd_gpio); 1303 1304 regmap_read(dp->regmap, DPTX_GENERAL_INTERRUPT, &value); 1305 if (value & HPD_EVENT) { 1306 regmap_read(dp->regmap, DPTX_HPD_STATUS, &value); 1307 if ((value & HPD_HOT_PLUG) && 1308 (FIELD_GET(HPD_STATE, value) == SOURCE_STATE_PLUG)) { 1309 regmap_write(dp->regmap, DPTX_HPD_STATUS, HPD_HOT_PLUG); 1310 return true; 1311 } 1312 } 1313 1314 return false; 1315 } 1316 1317 static int dw_dp_connector_pre_init(struct display_state *state) 1318 { 1319 struct connector_state *conn_state = &state->conn_state; 1320 1321 conn_state->type = DRM_MODE_CONNECTOR_DisplayPort; 1322 1323 return 0; 1324 } 1325 1326 static int dw_dp_connector_init(struct display_state *state) 1327 { 1328 struct connector_state *conn_state = &state->conn_state; 1329 struct dw_dp *dp = dev_get_priv(conn_state->dev); 1330 int ret; 1331 1332 conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_DP1 : VOP_OUTPUT_IF_DP0; 1333 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1334 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 1335 1336 clk_set_defaults(dp->dev); 1337 1338 reset_assert(&dp->reset); 1339 udelay(20); 1340 reset_deassert(&dp->reset); 1341 1342 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, 1343 dp->id); 1344 dw_dp_init(dp); 1345 ret = generic_phy_power_on(&dp->phy); 1346 1347 return ret; 1348 } 1349 1350 static int dw_dp_connector_get_edid(struct display_state *state) 1351 { 1352 int ret; 1353 struct connector_state *conn_state = &state->conn_state; 1354 struct dw_dp *dp = dev_get_priv(conn_state->dev); 1355 1356 ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); 1357 1358 return ret; 1359 } 1360 1361 static int dw_dp_connector_enable(struct display_state *state) 1362 { 1363 struct connector_state *conn_state = &state->conn_state; 1364 struct drm_display_mode *mode = &conn_state->mode; 1365 struct dw_dp *dp = dev_get_priv(conn_state->dev); 1366 struct dw_dp_video *video = &dp->video; 1367 int ret; 1368 1369 memcpy(&video->mode, mode, sizeof(video->mode)); 1370 video->pixel_mode = DPTX_MP_QUAD_PIXEL; 1371 1372 ret = dw_dp_link_enable(dp); 1373 if (ret < 0) { 1374 dev_err(dp->dev, "failed to enable link: %d\n", ret); 1375 return ret; 1376 } 1377 1378 ret = dw_dp_video_enable(dp); 1379 if (ret < 0) { 1380 dev_err(dp->dev, "failed to enable video: %d\n", ret); 1381 return ret; 1382 } 1383 1384 return 0; 1385 } 1386 1387 static int dw_dp_connector_disable(struct display_state *state) 1388 { 1389 /* TODO */ 1390 1391 return 0; 1392 } 1393 1394 static int dw_dp_connector_detect(struct display_state *state) 1395 { 1396 struct connector_state *conn_state = &state->conn_state; 1397 struct dw_dp *dp = dev_get_priv(conn_state->dev); 1398 int status, tries; 1399 1400 for (tries = 0; tries < 100; tries++) { 1401 status = dw_dp_detect(dp); 1402 if (status) 1403 break; 1404 mdelay(2); 1405 } 1406 1407 if (!status) 1408 generic_phy_power_off(&dp->phy); 1409 1410 return status; 1411 } 1412 1413 static int dw_dp_mode_valid(struct dw_dp *dp, struct hdmi_edid_data *edid_data) 1414 { 1415 struct dw_dp_link *link = &dp->link; 1416 struct drm_display_info *di = &edid_data->display_info; 1417 u32 min_bpp; 1418 int i; 1419 1420 if (di->color_formats & DRM_COLOR_FORMAT_YCRCB420 && 1421 link->vsc_sdp_extension_for_colorimetry_supported) 1422 min_bpp = 12; 1423 else if (di->color_formats & DRM_COLOR_FORMAT_YCRCB422) 1424 min_bpp = 16; 1425 else if (di->color_formats & DRM_COLOR_FORMAT_RGB444) 1426 min_bpp = 18; 1427 else 1428 min_bpp = 24; 1429 1430 for (i = 0; i < edid_data->modes; i++) { 1431 if (!dw_dp_bandwidth_ok(dp, &edid_data->mode_buf[i], min_bpp, link->lanes, 1432 link->rate)) 1433 edid_data->mode_buf[i].invalid = true; 1434 } 1435 1436 return 0; 1437 } 1438 1439 static u32 dw_dp_get_output_bus_fmts(struct dw_dp *dp, struct hdmi_edid_data *edid_data) 1440 { 1441 struct dw_dp_link *link = &dp->link; 1442 unsigned int i; 1443 1444 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 1445 const struct dw_dp_output_format *fmt = &possible_output_fmts[i]; 1446 1447 if (fmt->bpc > edid_data->display_info.bpc) 1448 continue; 1449 1450 if (!(edid_data->display_info.color_formats & fmt->color_format)) 1451 continue; 1452 1453 if (fmt->color_format == DRM_COLOR_FORMAT_YCRCB420 && 1454 !link->vsc_sdp_extension_for_colorimetry_supported) 1455 continue; 1456 1457 if (drm_mode_is_420(&edid_data->display_info, edid_data->preferred_mode) && 1458 fmt->color_format != DRM_COLOR_FORMAT_YCRCB420) 1459 continue; 1460 1461 if (!dw_dp_bandwidth_ok(dp, edid_data->preferred_mode, fmt->bpp, link->lanes, 1462 link->rate)) 1463 continue; 1464 1465 break; 1466 } 1467 1468 if (i == ARRAY_SIZE(possible_output_fmts)) 1469 return 1; 1470 1471 return i; 1472 } 1473 1474 static int dw_dp_get_force_output_fmts(struct display_state *state) 1475 { 1476 int i; 1477 1478 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 1479 const struct dw_dp_output_format *fmt = &possible_output_fmts[i]; 1480 1481 if (fmt->bus_format == state->force_bus_format) 1482 break; 1483 } 1484 1485 if (i == ARRAY_SIZE(possible_output_fmts)) 1486 return 1; 1487 1488 return i; 1489 } 1490 1491 static int dw_dp_connector_get_timing(struct display_state *state) 1492 { 1493 int ret, i; 1494 struct connector_state *conn_state = &state->conn_state; 1495 struct dw_dp *dp = dev_get_priv(conn_state->dev); 1496 struct dw_dp_video *video = &dp->video; 1497 struct drm_display_mode *mode = &conn_state->mode; 1498 struct hdmi_edid_data edid_data; 1499 struct drm_display_mode *mode_buf; 1500 u32 bus_fmt; 1501 1502 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 1503 if (!mode_buf) 1504 return -ENOMEM; 1505 1506 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 1507 memset(&edid_data, 0, sizeof(struct hdmi_edid_data)); 1508 edid_data.mode_buf = mode_buf; 1509 1510 ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); 1511 if (!ret) 1512 ret = drm_add_edid_modes(&edid_data, conn_state->edid); 1513 1514 if (ret < 0) { 1515 printf("failed to get edid\n"); 1516 goto err; 1517 } 1518 1519 ret = dw_dp_link_probe(dp); 1520 if (ret) { 1521 printf("failed to probe DP link: %d\n", ret); 1522 ret = -EINVAL; 1523 goto err; 1524 } 1525 1526 drm_rk_filter_whitelist(&edid_data); 1527 drm_mode_max_resolution_filter(&edid_data, 1528 &state->crtc_state.max_output); 1529 dw_dp_mode_valid(dp, &edid_data); 1530 1531 if (!drm_mode_prune_invalid(&edid_data)) { 1532 printf("can't find valid hdmi mode\n"); 1533 ret = -EINVAL; 1534 goto err; 1535 } 1536 1537 for (i = 0; i < edid_data.modes; i++) 1538 edid_data.mode_buf[i].vrefresh = 1539 drm_mode_vrefresh(&edid_data.mode_buf[i]); 1540 1541 drm_mode_sort(&edid_data); 1542 memcpy(mode, edid_data.preferred_mode, sizeof(struct drm_display_mode)); 1543 1544 if (state->force_output) 1545 bus_fmt = dw_dp_get_force_output_fmts(state); 1546 else 1547 bus_fmt = dw_dp_get_output_bus_fmts(dp, &edid_data); 1548 1549 video->video_mapping = possible_output_fmts[bus_fmt].video_mapping; 1550 video->color_format = possible_output_fmts[bus_fmt].color_format; 1551 video->bus_format = possible_output_fmts[bus_fmt].bus_format; 1552 video->bpc = possible_output_fmts[bus_fmt].bpc; 1553 video->bpp = possible_output_fmts[bus_fmt].bpp; 1554 1555 switch (video->color_format) { 1556 case DRM_COLOR_FORMAT_YCRCB420: 1557 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420; 1558 break; 1559 case DRM_COLOR_FORMAT_YCRCB422: 1560 conn_state->output_mode = ROCKCHIP_OUT_MODE_S888_DUMMY; 1561 break; 1562 case DRM_COLOR_FORMAT_RGB444: 1563 case DRM_COLOR_FORMAT_YCRCB444: 1564 default: 1565 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1566 break; 1567 } 1568 1569 conn_state->bus_format = video->bus_format; 1570 err: 1571 free(mode_buf); 1572 1573 return 0; 1574 } 1575 1576 static const struct rockchip_connector_funcs dw_dp_connector_funcs = { 1577 .pre_init = dw_dp_connector_pre_init, 1578 .init = dw_dp_connector_init, 1579 .get_edid = dw_dp_connector_get_edid, 1580 .enable = dw_dp_connector_enable, 1581 .disable = dw_dp_connector_disable, 1582 .detect = dw_dp_connector_detect, 1583 .get_timing = dw_dp_connector_get_timing, 1584 }; 1585 1586 static int dw_dp_ddc_init(struct dw_dp *dp) 1587 { 1588 dp->aux.name = "dw-dp"; 1589 dp->aux.dev = dp->dev; 1590 dp->aux.transfer = dw_dp_aux_transfer; 1591 dp->aux.ddc.ddc_xfer = drm_dp_i2c_xfer; 1592 1593 return 0; 1594 } 1595 1596 static int dw_dp_probe(struct udevice *dev) 1597 { 1598 struct dw_dp *dp = dev_get_priv(dev); 1599 int ret; 1600 1601 ret = regmap_init_mem(dev, &dp->regmap); 1602 if (ret) 1603 return ret; 1604 1605 dp->id = of_alias_get_id(ofnode_to_np(dev->node), "dp"); 1606 if (dp->id < 0) 1607 dp->id = 0; 1608 1609 ret = reset_get_by_index(dev, 0, &dp->reset); 1610 if (ret) { 1611 dev_err(dev, "failed to get reset control: %d\n", ret); 1612 return ret; 1613 } 1614 1615 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 1616 GPIOD_IS_IN); 1617 if (ret && ret != -ENOENT) { 1618 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 1619 return ret; 1620 } 1621 1622 generic_phy_get_by_index(dev, 0, &dp->phy); 1623 1624 dp->dev = dev; 1625 1626 dw_dp_ddc_init(dp); 1627 1628 return 0; 1629 } 1630 1631 static const struct rockchip_connector rk3588_dp_driver_data = { 1632 .funcs = &dw_dp_connector_funcs, 1633 }; 1634 1635 static const struct udevice_id dw_dp_ids[] = { 1636 { 1637 .compatible = "rockchip,rk3588-dp", 1638 .data = (ulong)&rk3588_dp_driver_data 1639 }, 1640 {} 1641 }; 1642 1643 U_BOOT_DRIVER(dw_dp) = { 1644 .name = "dw_dp", 1645 .id = UCLASS_DISPLAY, 1646 .of_match = dw_dp_ids, 1647 .probe = dw_dp_probe, 1648 .priv_auto_alloc_size = sizeof(struct dw_dp), 1649 }; 1650 1651