1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Rockchip USBDP Combo PHY with Samsung IP block driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd 6 */ 7 8 #include <config.h> 9 #include <common.h> 10 #include <errno.h> 11 #include <malloc.h> 12 #include <asm/unaligned.h> 13 #include <asm/io.h> 14 #include <clk.h> 15 #include <dm/device.h> 16 #include <dm/of_access.h> 17 #include <dm/read.h> 18 #include <generic-phy.h> 19 #include <linux/bitfield.h> 20 #include <linux/hdmi.h> 21 #include <linux/media-bus-format.h> 22 #include <linux/list.h> 23 #include <asm/gpio.h> 24 #include <generic-phy.h> 25 #include <regmap.h> 26 #include <reset.h> 27 #include <drm/drm_dp_helper.h> 28 29 #include "rockchip_display.h" 30 #include "rockchip_crtc.h" 31 #include "rockchip_connector.h" 32 33 #define DPTX_VERSION_NUMBER 0x0000 34 #define DPTX_VERSION_TYPE 0x0004 35 #define DPTX_ID 0x0008 36 37 #define DPTX_CONFIG_REG1 0x0100 38 #define DPTX_CONFIG_REG2 0x0104 39 #define DPTX_CONFIG_REG3 0x0108 40 41 #define DPTX_CCTL 0x0200 42 #define FORCE_HPD BIT(4) 43 #define DEFAULT_FAST_LINK_TRAIN_EN BIT(2) 44 #define ENHANCE_FRAMING_EN BIT(1) 45 #define SCRAMBLE_DIS BIT(0) 46 #define DPTX_SOFT_RESET_CTRL 0x0204 47 #define VIDEO_RESET BIT(5) 48 #define AUX_RESET BIT(4) 49 #define AUDIO_SAMPLER_RESET BIT(3) 50 #define PHY_SOFT_RESET BIT(1) 51 #define CONTROLLER_RESET BIT(0) 52 53 #define DPTX_VSAMPLE_CTRL 0x0300 54 #define PIXEL_MODE_SELECT GENMASK(22, 21) 55 #define VIDEO_MAPPING GENMASK(20, 16) 56 #define VIDEO_STREAM_ENABLE BIT(5) 57 #define DPTX_VSAMPLE_STUFF_CTRL1 0x0304 58 #define DPTX_VSAMPLE_STUFF_CTRL2 0x0308 59 #define DPTX_VINPUT_POLARITY_CTRL 0x030c 60 #define DE_IN_POLARITY BIT(2) 61 #define HSYNC_IN_POLARITY BIT(1) 62 #define VSYNC_IN_POLARITY BIT(0) 63 #define DPTX_VIDEO_CONFIG1 0x0310 64 #define HACTIVE GENMASK(31, 16) 65 #define HBLANK GENMASK(15, 2) 66 #define I_P BIT(1) 67 #define R_V_BLANK_IN_OSC BIT(0) 68 #define DPTX_VIDEO_CONFIG2 0x0314 69 #define VBLANK GENMASK(31, 16) 70 #define VACTIVE GENMASK(15, 0) 71 #define DPTX_VIDEO_CONFIG3 0x0318 72 #define H_SYNC_WIDTH GENMASK(31, 16) 73 #define H_FRONT_PORCH GENMASK(15, 0) 74 #define DPTX_VIDEO_CONFIG4 0x031c 75 #define V_SYNC_WIDTH GENMASK(31, 16) 76 #define V_FRONT_PORCH GENMASK(15, 0) 77 #define DPTX_VIDEO_CONFIG5 0x0320 78 #define INIT_THRESHOLD_HI GENMASK(22, 21) 79 #define AVERAGE_BYTES_PER_TU_FRAC GENMASK(19, 16) 80 #define INIT_THRESHOLD GENMASK(13, 7) 81 #define AVERAGE_BYTES_PER_TU GENMASK(6, 0) 82 #define DPTX_VIDEO_MSA1 0x0324 83 #define VSTART GENMASK(31, 16) 84 #define HSTART GENMASK(15, 0) 85 #define DPTX_VIDEO_MSA2 0x0328 86 #define MISC0 GENMASK(31, 24) 87 #define DPTX_VIDEO_MSA3 0x032c 88 #define MISC1 GENMASK(31, 24) 89 #define DPTX_VIDEO_HBLANK_INTERVAL 0x0330 90 #define HBLANK_INTERVAL_EN BIT(16) 91 #define HBLANK_INTERVAL GENMASK(15, 0) 92 93 #define DPTX_AUD_CONFIG1 0x0400 94 #define AUDIO_TIMESTAMP_VERSION_NUM GENMASK(29, 24) 95 #define AUDIO_PACKET_ID GENMASK(23, 16) 96 #define AUDIO_MUTE BIT(15) 97 #define NUM_CHANNELS GENMASK(14, 12) 98 #define HBR_MODE_ENABLE BIT(10) 99 #define AUDIO_DATA_WIDTH GENMASK(9, 5) 100 #define AUDIO_DATA_IN_EN GENMASK(4, 1) 101 #define AUDIO_INF_SELECT BIT(0) 102 103 #define DPTX_SDP_VERTICAL_CTRL 0x0500 104 #define EN_VERTICAL_SDP BIT(2) 105 #define EN_AUDIO_STREAM_SDP BIT(1) 106 #define EN_AUDIO_TIMESTAMP_SDP BIT(0) 107 #define DPTX_SDP_HORIZONTAL_CTRL 0x0504 108 #define EN_HORIZONTAL_SDP BIT(2) 109 #define DPTX_SDP_STATUS_REGISTER 0x0508 110 #define DPTX_SDP_MANUAL_CTRL 0x050c 111 #define DPTX_SDP_STATUS_EN 0x0510 112 113 #define DPTX_SDP_REGISTER_BANK 0x0600 114 #define SDP_REGS GENMASK(31, 0) 115 116 #define DPTX_PHYIF_CTRL 0x0a00 117 #define PHY_WIDTH BIT(25) 118 #define PHY_POWERDOWN GENMASK(20, 17) 119 #define PHY_BUSY GENMASK(15, 12) 120 #define SSC_DIS BIT(16) 121 #define XMIT_ENABLE GENMASK(11, 8) 122 #define PHY_LANES GENMASK(7, 6) 123 #define PHY_RATE GENMASK(5, 4) 124 #define TPS_SEL GENMASK(3, 0) 125 #define DPTX_PHY_TX_EQ 0x0a04 126 #define DPTX_CUSTOMPAT0 0x0a08 127 #define DPTX_CUSTOMPAT1 0x0a0c 128 #define DPTX_CUSTOMPAT2 0x0a10 129 #define DPTX_HBR2_COMPLIANCE_SCRAMBLER_RESET 0x0a14 130 #define DPTX_PHYIF_PWRDOWN_CTRL 0x0a18 131 132 #define DPTX_AUX_CMD 0x0b00 133 #define AUX_CMD_TYPE GENMASK(31, 28) 134 #define AUX_ADDR GENMASK(27, 8) 135 #define I2C_ADDR_ONLY BIT(4) 136 #define AUX_LEN_REQ GENMASK(3, 0) 137 #define DPTX_AUX_STATUS 0x0b04 138 #define AUX_TIMEOUT BIT(17) 139 #define AUX_BYTES_READ GENMASK(23, 19) 140 #define AUX_STATUS GENMASK(7, 4) 141 #define DPTX_AUX_DATA0 0x0b08 142 #define DPTX_AUX_DATA1 0x0b0c 143 #define DPTX_AUX_DATA2 0x0b10 144 #define DPTX_AUX_DATA3 0x0b14 145 146 #define DPTX_GENERAL_INTERRUPT 0x0d00 147 #define VIDEO_FIFO_OVERFLOW_STREAM0 BIT(6) 148 #define AUDIO_FIFO_OVERFLOW_STREAM0 BIT(5) 149 #define SDP_EVENT_STREAM0 BIT(4) 150 #define AUX_CMD_INVALID BIT(3) 151 #define AUX_REPLY_EVENT BIT(1) 152 #define HPD_EVENT BIT(0) 153 #define DPTX_GENERAL_INTERRUPT_ENABLE 0x0d04 154 #define AUX_REPLY_EVENT_EN BIT(1) 155 #define HPD_EVENT_EN BIT(0) 156 #define DPTX_HPD_STATUS 0x0d08 157 #define HPD_STATE GENMASK(11, 9) 158 #define HPD_STATUS BIT(8) 159 #define HPD_HOT_UNPLUG BIT(2) 160 #define HPD_HOT_PLUG BIT(1) 161 #define HPD_IRQ BIT(0) 162 #define DPTX_HPD_INTERRUPT_ENABLE 0x0d0c 163 #define HPD_UNPLUG_ERR_EN BIT(3) 164 #define HPD_UNPLUG_EN BIT(2) 165 #define HPD_PLUG_EN BIT(1) 166 #define HPD_IRQ_EN BIT(0) 167 168 #define DPTX_MAX_REGISTER DPTX_HPD_INTERRUPT_ENABLE 169 170 #define SDP_REG_BANK_SIZE 16 171 172 struct drm_dp_link_caps { 173 bool enhanced_framing; 174 bool tps3_supported; 175 bool tps4_supported; 176 bool channel_coding; 177 bool ssc; 178 }; 179 180 struct drm_dp_link_train_set { 181 unsigned int voltage_swing[4]; 182 unsigned int pre_emphasis[4]; 183 }; 184 185 struct drm_dp_link_train { 186 struct drm_dp_link_train_set request; 187 struct drm_dp_link_train_set adjust; 188 bool clock_recovered; 189 bool channel_equalized; 190 }; 191 192 struct dw_dp_link { 193 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 194 unsigned char revision; 195 unsigned int rate; 196 unsigned int lanes; 197 struct drm_dp_link_caps caps; 198 struct drm_dp_link_train train; 199 u8 sink_count; 200 u8 vsc_sdp_extension_for_colorimetry_supported; 201 }; 202 203 struct dw_dp_video { 204 struct drm_display_mode mode; 205 u32 bus_format; 206 u8 video_mapping; 207 u8 pixel_mode; 208 u8 color_format; 209 u8 bpc; 210 u8 bpp; 211 }; 212 213 struct dw_dp_sdp { 214 struct dp_sdp_header header; 215 u8 db[32]; 216 unsigned long flags; 217 }; 218 219 struct dw_dp_chip_data { 220 int pixel_mode; 221 }; 222 223 struct dw_dp { 224 struct rockchip_connector connector; 225 struct udevice *dev; 226 struct regmap *regmap; 227 struct phy phy; 228 struct reset_ctl reset; 229 int id; 230 231 struct gpio_desc hpd_gpio; 232 struct drm_dp_aux aux; 233 struct dw_dp_link link; 234 struct dw_dp_video video; 235 236 bool force_hpd; 237 bool force_output; 238 u32 max_link_rate; 239 }; 240 241 enum { 242 SOURCE_STATE_IDLE, 243 SOURCE_STATE_UNPLUG, 244 SOURCE_STATE_HPD_TIMEOUT = 4, 245 SOURCE_STATE_PLUG = 7 246 }; 247 248 enum { 249 DPTX_VM_RGB_6BIT, 250 DPTX_VM_RGB_8BIT, 251 DPTX_VM_RGB_10BIT, 252 DPTX_VM_RGB_12BIT, 253 DPTX_VM_RGB_16BIT, 254 DPTX_VM_YCBCR444_8BIT, 255 DPTX_VM_YCBCR444_10BIT, 256 DPTX_VM_YCBCR444_12BIT, 257 DPTX_VM_YCBCR444_16BIT, 258 DPTX_VM_YCBCR422_8BIT, 259 DPTX_VM_YCBCR422_10BIT, 260 DPTX_VM_YCBCR422_12BIT, 261 DPTX_VM_YCBCR422_16BIT, 262 DPTX_VM_YCBCR420_8BIT, 263 DPTX_VM_YCBCR420_10BIT, 264 DPTX_VM_YCBCR420_12BIT, 265 DPTX_VM_YCBCR420_16BIT, 266 }; 267 268 enum { 269 DPTX_MP_SINGLE_PIXEL, 270 DPTX_MP_DUAL_PIXEL, 271 DPTX_MP_QUAD_PIXEL, 272 }; 273 274 enum { 275 DPTX_SDP_VERTICAL_INTERVAL = BIT(0), 276 DPTX_SDP_HORIZONTAL_INTERVAL = BIT(1), 277 }; 278 279 enum { 280 DPTX_PHY_PATTERN_NONE, 281 DPTX_PHY_PATTERN_TPS_1, 282 DPTX_PHY_PATTERN_TPS_2, 283 DPTX_PHY_PATTERN_TPS_3, 284 DPTX_PHY_PATTERN_TPS_4, 285 DPTX_PHY_PATTERN_SERM, 286 DPTX_PHY_PATTERN_PBRS7, 287 DPTX_PHY_PATTERN_CUSTOM_80BIT, 288 DPTX_PHY_PATTERN_CP2520_1, 289 DPTX_PHY_PATTERN_CP2520_2, 290 }; 291 292 enum { 293 DPTX_PHYRATE_RBR, 294 DPTX_PHYRATE_HBR, 295 DPTX_PHYRATE_HBR2, 296 DPTX_PHYRATE_HBR3, 297 }; 298 299 struct dw_dp_output_format { 300 u32 bus_format; 301 u32 color_format; 302 u8 video_mapping; 303 u8 bpc; 304 u8 bpp; 305 }; 306 307 static const struct dw_dp_output_format possible_output_fmts[] = { 308 { MEDIA_BUS_FMT_RGB101010_1X30, DRM_COLOR_FORMAT_RGB444, 309 DPTX_VM_RGB_10BIT, 10, 30 }, 310 { MEDIA_BUS_FMT_RGB888_1X24, DRM_COLOR_FORMAT_RGB444, 311 DPTX_VM_RGB_8BIT, 8, 24 }, 312 { MEDIA_BUS_FMT_YUV10_1X30, DRM_COLOR_FORMAT_YCRCB444, 313 DPTX_VM_YCBCR444_10BIT, 10, 30 }, 314 { MEDIA_BUS_FMT_YUV8_1X24, DRM_COLOR_FORMAT_YCRCB444, 315 DPTX_VM_YCBCR444_8BIT, 8, 24}, 316 { MEDIA_BUS_FMT_YUYV10_1X20, DRM_COLOR_FORMAT_YCRCB422, 317 DPTX_VM_YCBCR422_10BIT, 10, 20 }, 318 { MEDIA_BUS_FMT_YUYV8_1X16, DRM_COLOR_FORMAT_YCRCB422, 319 DPTX_VM_YCBCR422_8BIT, 8, 16 }, 320 { MEDIA_BUS_FMT_UYYVYY10_0_5X30, DRM_COLOR_FORMAT_YCRCB420, 321 DPTX_VM_YCBCR420_10BIT, 10, 15 }, 322 { MEDIA_BUS_FMT_UYYVYY8_0_5X24, DRM_COLOR_FORMAT_YCRCB420, 323 DPTX_VM_YCBCR420_8BIT, 8, 12 }, 324 { MEDIA_BUS_FMT_RGB666_1X24_CPADHI, DRM_COLOR_FORMAT_RGB444, 325 DPTX_VM_RGB_6BIT, 6, 18 }, 326 }; 327 328 static int dw_dp_aux_write_data(struct dw_dp *dp, const u8 *buffer, size_t size) 329 { 330 size_t i, j; 331 332 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 333 size_t num = min_t(size_t, size - i * 4, 4); 334 u32 value = 0; 335 336 for (j = 0; j < num; j++) 337 value |= buffer[i * 4 + j] << (j * 8); 338 339 regmap_write(dp->regmap, DPTX_AUX_DATA0 + i * 4, value); 340 } 341 342 return size; 343 } 344 345 static int dw_dp_aux_read_data(struct dw_dp *dp, u8 *buffer, size_t size) 346 { 347 size_t i, j; 348 349 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 350 size_t num = min_t(size_t, size - i * 4, 4); 351 u32 value; 352 353 regmap_read(dp->regmap, DPTX_AUX_DATA0 + i * 4, &value); 354 355 for (j = 0; j < num; j++) 356 buffer[i * 4 + j] = value >> (j * 8); 357 } 358 359 return size; 360 } 361 362 static ssize_t dw_dp_aux_transfer(struct drm_dp_aux *aux, 363 struct drm_dp_aux_msg *msg) 364 { 365 u32 status, value; 366 ssize_t ret = 0; 367 int timeout = 0; 368 struct dw_dp *dp = dev_get_priv(aux->dev); 369 370 if (WARN_ON(msg->size > 16)) 371 return -E2BIG; 372 373 switch (msg->request & ~DP_AUX_I2C_MOT) { 374 case DP_AUX_NATIVE_WRITE: 375 case DP_AUX_I2C_WRITE: 376 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 377 ret = dw_dp_aux_write_data(dp, msg->buffer, msg->size); 378 if (ret < 0) 379 return ret; 380 break; 381 case DP_AUX_NATIVE_READ: 382 case DP_AUX_I2C_READ: 383 break; 384 default: 385 return -EINVAL; 386 } 387 388 if (msg->size > 0) 389 value = FIELD_PREP(AUX_LEN_REQ, msg->size - 1); 390 else 391 value = FIELD_PREP(I2C_ADDR_ONLY, 1); 392 393 value |= FIELD_PREP(AUX_CMD_TYPE, msg->request); 394 value |= FIELD_PREP(AUX_ADDR, msg->address); 395 regmap_write(dp->regmap, DPTX_AUX_CMD, value); 396 397 timeout = regmap_read_poll_timeout(dp->regmap, DPTX_GENERAL_INTERRUPT, 398 status, status & AUX_REPLY_EVENT, 399 200, 10); 400 401 if (timeout) { 402 printf("timeout waiting for AUX reply\n"); 403 return -ETIMEDOUT; 404 } 405 regmap_write(dp->regmap, DPTX_GENERAL_INTERRUPT, AUX_REPLY_EVENT); 406 407 regmap_read(dp->regmap, DPTX_AUX_STATUS, &value); 408 if (value & AUX_TIMEOUT) { 409 printf("aux timeout\n"); 410 return -ETIMEDOUT; 411 } 412 413 msg->reply = FIELD_GET(AUX_STATUS, value); 414 415 if (msg->size > 0 && msg->reply == DP_AUX_NATIVE_REPLY_ACK) { 416 if (msg->request & DP_AUX_I2C_READ) { 417 size_t count = FIELD_GET(AUX_BYTES_READ, value) - 1; 418 419 if (count != msg->size) { 420 printf("aux fail to read %lu bytes\n", count); 421 return -EBUSY; 422 } 423 424 ret = dw_dp_aux_read_data(dp, msg->buffer, count); 425 if (ret < 0) 426 return ret; 427 } 428 } 429 430 return ret; 431 } 432 433 static bool dw_dp_bandwidth_ok(struct dw_dp *dp, 434 const struct drm_display_mode *mode, u32 bpp, 435 unsigned int lanes, unsigned int rate) 436 { 437 u32 max_bw, req_bw; 438 439 req_bw = mode->clock * bpp / 8; 440 max_bw = lanes * rate; 441 if (req_bw > max_bw) 442 return false; 443 444 return true; 445 } 446 447 static void dw_dp_hpd_init(struct dw_dp *dp) 448 { 449 if (dm_gpio_is_valid(&dp->hpd_gpio) || dp->force_hpd) { 450 regmap_update_bits(dp->regmap, DPTX_CCTL, FORCE_HPD, 451 FIELD_PREP(FORCE_HPD, 1)); 452 return; 453 } 454 455 /* Enable all HPD interrupts */ 456 regmap_update_bits(dp->regmap, DPTX_HPD_INTERRUPT_ENABLE, 457 HPD_UNPLUG_EN | HPD_PLUG_EN | HPD_IRQ_EN, 458 FIELD_PREP(HPD_UNPLUG_EN, 1) | 459 FIELD_PREP(HPD_PLUG_EN, 1) | 460 FIELD_PREP(HPD_IRQ_EN, 1)); 461 462 /* Enable all top-level interrupts */ 463 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, 464 HPD_EVENT_EN, FIELD_PREP(HPD_EVENT_EN, 1)); 465 } 466 467 static void dw_dp_aux_init(struct dw_dp *dp) 468 { 469 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, 470 FIELD_PREP(AUX_RESET, 1)); 471 udelay(10); 472 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, 473 FIELD_PREP(AUX_RESET, 0)); 474 475 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, 476 AUX_REPLY_EVENT_EN, 477 FIELD_PREP(AUX_REPLY_EVENT_EN, 1)); 478 } 479 480 static void dw_dp_init(struct dw_dp *dp) 481 { 482 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, 483 FIELD_PREP(CONTROLLER_RESET, 1)); 484 udelay(10); 485 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, 486 FIELD_PREP(CONTROLLER_RESET, 0)); 487 488 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, 489 FIELD_PREP(PHY_SOFT_RESET, 1)); 490 udelay(10); 491 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, 492 FIELD_PREP(PHY_SOFT_RESET, 0)); 493 494 regmap_update_bits(dp->regmap, DPTX_CCTL, DEFAULT_FAST_LINK_TRAIN_EN, 495 FIELD_PREP(DEFAULT_FAST_LINK_TRAIN_EN, 0)); 496 497 dw_dp_hpd_init(dp); 498 dw_dp_aux_init(dp); 499 } 500 501 static void dw_dp_phy_set_pattern(struct dw_dp *dp, u32 pattern) 502 { 503 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, TPS_SEL, 504 FIELD_PREP(TPS_SEL, pattern)); 505 } 506 507 static void dw_dp_phy_xmit_enable(struct dw_dp *dp, u32 lanes) 508 { 509 u32 xmit_enable; 510 511 switch (lanes) { 512 case 4: 513 case 2: 514 case 1: 515 xmit_enable = GENMASK(lanes - 1, 0); 516 break; 517 case 0: 518 default: 519 xmit_enable = 0; 520 break; 521 } 522 523 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, XMIT_ENABLE, 524 FIELD_PREP(XMIT_ENABLE, xmit_enable)); 525 } 526 527 static int dw_dp_link_power_up(struct dw_dp *dp) 528 { 529 struct dw_dp_link *link = &dp->link; 530 u8 value; 531 int ret; 532 533 if (link->revision < 0x11) 534 return 0; 535 536 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value); 537 if (ret < 0) 538 return ret; 539 540 value &= ~DP_SET_POWER_MASK; 541 value |= DP_SET_POWER_D0; 542 543 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value); 544 if (ret < 0) 545 return ret; 546 547 udelay(1000); 548 return 0; 549 } 550 551 static int dw_dp_link_probe(struct dw_dp *dp) 552 { 553 struct dw_dp_link *link = &dp->link; 554 u8 dpcd; 555 int ret; 556 557 drm_dp_dpcd_writeb(&dp->aux, DP_MSTM_CTRL, 0); 558 ret = drm_dp_read_dpcd_caps(&dp->aux, link->dpcd); 559 if (ret < 0) 560 return ret; 561 562 ret = drm_dp_dpcd_readb(&dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, 563 &dpcd); 564 if (ret < 0) 565 return ret; 566 567 link->vsc_sdp_extension_for_colorimetry_supported = 568 !!(dpcd & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED); 569 570 link->revision = link->dpcd[DP_DPCD_REV]; 571 link->rate = min_t(u32, min(dp->max_link_rate, dp->phy.attrs.max_link_rate * 100), 572 drm_dp_max_link_rate(link->dpcd)); 573 link->lanes = min_t(u8, dp->phy.attrs.bus_width, 574 drm_dp_max_lane_count(link->dpcd)); 575 576 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(link->dpcd); 577 link->caps.tps3_supported = drm_dp_tps3_supported(link->dpcd); 578 link->caps.tps4_supported = drm_dp_tps4_supported(link->dpcd); 579 link->caps.channel_coding = drm_dp_channel_coding_supported(link->dpcd); 580 link->caps.ssc = !!(link->dpcd[DP_MAX_DOWNSPREAD] & 581 DP_MAX_DOWNSPREAD_0_5); 582 583 return 0; 584 } 585 586 static int dw_dp_link_train_update_vs_emph(struct dw_dp *dp) 587 { 588 struct dw_dp_link *link = &dp->link; 589 struct drm_dp_link_train_set *request = &link->train.request; 590 union phy_configure_opts phy_cfg; 591 unsigned int lanes = link->lanes, *vs, *pe; 592 u8 buf[4]; 593 int i, ret; 594 595 vs = request->voltage_swing; 596 pe = request->pre_emphasis; 597 598 for (i = 0; i < lanes; i++) { 599 phy_cfg.dp.voltage[i] = vs[i]; 600 phy_cfg.dp.pre[i] = pe[i]; 601 } 602 phy_cfg.dp.lanes = lanes; 603 phy_cfg.dp.link_rate = link->rate / 100; 604 phy_cfg.dp.set_lanes = false; 605 phy_cfg.dp.set_rate = false; 606 phy_cfg.dp.set_voltages = true; 607 ret = generic_phy_configure(&dp->phy, &phy_cfg); 608 if (ret) 609 return ret; 610 611 for (i = 0; i < lanes; i++) 612 buf[i] = (vs[i] << DP_TRAIN_VOLTAGE_SWING_SHIFT) | 613 (pe[i] << DP_TRAIN_PRE_EMPHASIS_SHIFT); 614 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, lanes); 615 if (ret < 0) 616 return ret; 617 618 return 0; 619 } 620 621 static int dw_dp_link_configure(struct dw_dp *dp) 622 { 623 struct dw_dp_link *link = &dp->link; 624 union phy_configure_opts phy_cfg; 625 u8 buf[2]; 626 int ret, phy_rate; 627 628 /* Move PHY to P3 */ 629 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 630 FIELD_PREP(PHY_POWERDOWN, 0x3)); 631 632 phy_cfg.dp.lanes = link->lanes; 633 phy_cfg.dp.link_rate = link->rate / 100; 634 phy_cfg.dp.ssc = link->caps.ssc; 635 phy_cfg.dp.set_lanes = true; 636 phy_cfg.dp.set_rate = true; 637 phy_cfg.dp.set_voltages = false; 638 ret = generic_phy_configure(&dp->phy, &phy_cfg); 639 if (ret) 640 return ret; 641 642 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, 643 FIELD_PREP(PHY_LANES, link->lanes / 2)); 644 645 switch (link->rate) { 646 case 810000: 647 phy_rate = DPTX_PHYRATE_HBR3; 648 break; 649 case 540000: 650 phy_rate = DPTX_PHYRATE_HBR2; 651 break; 652 case 270000: 653 phy_rate = DPTX_PHYRATE_HBR; 654 break; 655 case 162000: 656 default: 657 phy_rate = DPTX_PHYRATE_RBR; 658 break; 659 } 660 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_RATE, 661 FIELD_PREP(PHY_RATE, phy_rate)); 662 663 /* Move PHY to P0 */ 664 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 665 FIELD_PREP(PHY_POWERDOWN, 0x0)); 666 667 dw_dp_phy_xmit_enable(dp, link->lanes); 668 669 buf[0] = drm_dp_link_rate_to_bw_code(link->rate); 670 buf[1] = link->lanes; 671 672 if (link->caps.enhanced_framing) { 673 buf[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 674 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 675 FIELD_PREP(ENHANCE_FRAMING_EN, 1)); 676 } else { 677 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 678 FIELD_PREP(ENHANCE_FRAMING_EN, 0)); 679 } 680 681 ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, sizeof(buf)); 682 if (ret < 0) 683 return ret; 684 685 buf[0] = link->caps.ssc ? DP_SPREAD_AMP_0_5 : 0; 686 buf[1] = link->caps.channel_coding ? DP_SET_ANSI_8B10B : 0; 687 688 ret = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, 689 sizeof(buf)); 690 if (ret < 0) 691 return ret; 692 693 return 0; 694 } 695 696 static void dw_dp_link_train_init(struct drm_dp_link_train *train) 697 { 698 struct drm_dp_link_train_set *request = &train->request; 699 struct drm_dp_link_train_set *adjust = &train->adjust; 700 unsigned int i; 701 702 for (i = 0; i < 4; i++) { 703 request->voltage_swing[i] = 0; 704 adjust->voltage_swing[i] = 0; 705 706 request->pre_emphasis[i] = 0; 707 adjust->pre_emphasis[i] = 0; 708 } 709 710 train->clock_recovered = false; 711 train->channel_equalized = false; 712 } 713 714 static int dw_dp_link_train_set_pattern(struct dw_dp *dp, u32 pattern) 715 { 716 u8 buf = 0; 717 int ret; 718 719 if (pattern && pattern != DP_TRAINING_PATTERN_4) { 720 buf |= DP_LINK_SCRAMBLING_DISABLE; 721 722 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, 723 FIELD_PREP(SCRAMBLE_DIS, 1)); 724 } else { 725 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, 726 FIELD_PREP(SCRAMBLE_DIS, 0)); 727 } 728 729 switch (pattern) { 730 case DP_TRAINING_PATTERN_DISABLE: 731 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE); 732 break; 733 case DP_TRAINING_PATTERN_1: 734 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_1); 735 break; 736 case DP_TRAINING_PATTERN_2: 737 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_2); 738 break; 739 case DP_TRAINING_PATTERN_3: 740 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_3); 741 break; 742 case DP_TRAINING_PATTERN_4: 743 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_4); 744 break; 745 default: 746 return -EINVAL; 747 } 748 749 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 750 buf | pattern); 751 if (ret < 0) 752 return ret; 753 754 return 0; 755 } 756 757 static void dw_dp_link_get_adjustments(struct dw_dp_link *link, 758 u8 status[DP_LINK_STATUS_SIZE]) 759 { 760 struct drm_dp_link_train_set *adjust = &link->train.adjust; 761 unsigned int i; 762 763 for (i = 0; i < link->lanes; i++) { 764 adjust->voltage_swing[i] = 765 drm_dp_get_adjust_request_voltage(status, i) >> 766 DP_TRAIN_VOLTAGE_SWING_SHIFT; 767 768 adjust->pre_emphasis[i] = 769 drm_dp_get_adjust_request_pre_emphasis(status, i) >> 770 DP_TRAIN_PRE_EMPHASIS_SHIFT; 771 } 772 } 773 774 static void dw_dp_link_train_adjust(struct drm_dp_link_train *train) 775 { 776 struct drm_dp_link_train_set *request = &train->request; 777 struct drm_dp_link_train_set *adjust = &train->adjust; 778 unsigned int i; 779 780 for (i = 0; i < 4; i++) 781 if (request->voltage_swing[i] != adjust->voltage_swing[i]) 782 request->voltage_swing[i] = adjust->voltage_swing[i]; 783 784 for (i = 0; i < 4; i++) 785 if (request->pre_emphasis[i] != adjust->pre_emphasis[i]) 786 request->pre_emphasis[i] = adjust->pre_emphasis[i]; 787 } 788 789 static int dw_dp_link_clock_recovery(struct dw_dp *dp) 790 { 791 struct dw_dp_link *link = &dp->link; 792 u8 status[DP_LINK_STATUS_SIZE]; 793 unsigned int tries = 0; 794 int ret; 795 796 ret = dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_1); 797 if (ret) 798 return ret; 799 800 for (;;) { 801 ret = dw_dp_link_train_update_vs_emph(dp); 802 if (ret) 803 return ret; 804 805 drm_dp_link_train_clock_recovery_delay(link->dpcd); 806 807 ret = drm_dp_dpcd_read_link_status(&dp->aux, status); 808 if (ret < 0) { 809 dev_err(dp->dev, "failed to read link status: %d\n", 810 ret); 811 return ret; 812 } 813 814 if (drm_dp_clock_recovery_ok(status, link->lanes)) { 815 link->train.clock_recovered = true; 816 break; 817 } 818 819 dw_dp_link_get_adjustments(link, status); 820 821 if (link->train.request.voltage_swing[0] == 822 link->train.adjust.voltage_swing[0]) 823 tries++; 824 else 825 tries = 0; 826 827 if (tries == 5) 828 break; 829 830 dw_dp_link_train_adjust(&link->train); 831 } 832 833 return 0; 834 } 835 836 static int dw_dp_link_channel_equalization(struct dw_dp *dp) 837 { 838 struct dw_dp_link *link = &dp->link; 839 u8 status[DP_LINK_STATUS_SIZE], pattern; 840 unsigned int tries; 841 int ret; 842 843 if (link->caps.tps4_supported) 844 pattern = DP_TRAINING_PATTERN_4; 845 else if (link->caps.tps3_supported) 846 pattern = DP_TRAINING_PATTERN_3; 847 else 848 pattern = DP_TRAINING_PATTERN_2; 849 ret = dw_dp_link_train_set_pattern(dp, pattern); 850 if (ret) 851 return ret; 852 853 for (tries = 1; tries < 5; tries++) { 854 ret = dw_dp_link_train_update_vs_emph(dp); 855 if (ret) 856 return ret; 857 858 drm_dp_link_train_channel_eq_delay(link->dpcd); 859 860 ret = drm_dp_dpcd_read_link_status(&dp->aux, status); 861 if (ret < 0) 862 return ret; 863 864 if (!drm_dp_clock_recovery_ok(status, link->lanes)) { 865 dev_err(dp->dev, 866 "clock recovery lost while eq\n"); 867 link->train.clock_recovered = false; 868 break; 869 } 870 871 if (drm_dp_channel_eq_ok(status, link->lanes)) { 872 link->train.channel_equalized = true; 873 break; 874 } 875 876 dw_dp_link_get_adjustments(link, status); 877 dw_dp_link_train_adjust(&link->train); 878 } 879 880 return 0; 881 } 882 883 static int dw_dp_link_downgrade(struct dw_dp *dp) 884 { 885 struct dw_dp_link *link = &dp->link; 886 struct dw_dp_video *video = &dp->video; 887 888 switch (link->rate) { 889 case 162000: 890 return -EINVAL; 891 case 270000: 892 link->rate = 162000; 893 break; 894 case 540000: 895 link->rate = 270000; 896 break; 897 case 810000: 898 link->rate = 540000; 899 break; 900 } 901 902 if (!dw_dp_bandwidth_ok(dp, &video->mode, video->bpp, link->lanes, 903 link->rate)) 904 return -E2BIG; 905 906 return 0; 907 } 908 909 static int dw_dp_link_train(struct dw_dp *dp) 910 { 911 struct dw_dp_link *link = &dp->link; 912 int ret; 913 914 retry: 915 dw_dp_link_train_init(&link->train); 916 917 printf("training link: %u lane%s at %u MHz\n", 918 link->lanes, (link->lanes > 1) ? "s" : "", link->rate / 100); 919 920 ret = dw_dp_link_configure(dp); 921 if (ret < 0) { 922 dev_err(dp->dev, "failed to configure DP link: %d\n", ret); 923 return ret; 924 } 925 926 ret = dw_dp_link_clock_recovery(dp); 927 if (ret < 0) { 928 dev_err(dp->dev, "clock recovery failed: %d\n", ret); 929 goto out; 930 } 931 932 if (!link->train.clock_recovered) { 933 dev_err(dp->dev, "clock recovery failed, downgrading link\n"); 934 935 ret = dw_dp_link_downgrade(dp); 936 if (ret < 0) 937 goto out; 938 else 939 goto retry; 940 } 941 942 printf("clock recovery succeeded\n"); 943 944 ret = dw_dp_link_channel_equalization(dp); 945 if (ret < 0) { 946 dev_err(dp->dev, "channel equalization failed: %d\n", ret); 947 goto out; 948 } 949 950 if (!link->train.channel_equalized) { 951 dev_err(dp->dev, 952 "channel equalization failed, downgrading link\n"); 953 954 ret = dw_dp_link_downgrade(dp); 955 if (ret < 0) 956 goto out; 957 else 958 goto retry; 959 } 960 961 printf("channel equalization succeeded\n"); 962 963 out: 964 dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE); 965 return ret; 966 } 967 968 static int dw_dp_link_enable(struct dw_dp *dp) 969 { 970 int ret; 971 972 ret = dw_dp_link_power_up(dp); 973 if (ret < 0) 974 return ret; 975 976 ret = dw_dp_link_train(dp); 977 if (ret < 0) { 978 dev_err(dp->dev, "link training failed: %d\n", ret); 979 return ret; 980 } 981 982 return 0; 983 } 984 985 static int dw_dp_set_phy_default_config(struct dw_dp *dp) 986 { 987 struct dw_dp_link *link = &dp->link; 988 union phy_configure_opts phy_cfg; 989 int ret, i, phy_rate; 990 991 link->vsc_sdp_extension_for_colorimetry_supported = false; 992 link->rate = 270000; 993 link->lanes = dp->phy.attrs.bus_width; 994 995 link->caps.enhanced_framing = true; 996 link->caps.channel_coding = true; 997 link->caps.ssc = true; 998 999 /* Move PHY to P3 */ 1000 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 1001 FIELD_PREP(PHY_POWERDOWN, 0x3)); 1002 1003 for (i = 0; i < link->lanes; i++) { 1004 phy_cfg.dp.voltage[i] = 3; 1005 phy_cfg.dp.pre[i] = 0; 1006 } 1007 phy_cfg.dp.lanes = link->lanes; 1008 phy_cfg.dp.link_rate = link->rate / 100; 1009 phy_cfg.dp.ssc = link->caps.ssc; 1010 phy_cfg.dp.set_lanes = true; 1011 phy_cfg.dp.set_rate = true; 1012 phy_cfg.dp.set_voltages = true; 1013 ret = generic_phy_configure(&dp->phy, &phy_cfg); 1014 if (ret) 1015 return ret; 1016 1017 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, 1018 FIELD_PREP(PHY_LANES, link->lanes / 2)); 1019 1020 switch (link->rate) { 1021 case 810000: 1022 phy_rate = DPTX_PHYRATE_HBR3; 1023 break; 1024 case 540000: 1025 phy_rate = DPTX_PHYRATE_HBR2; 1026 break; 1027 case 270000: 1028 phy_rate = DPTX_PHYRATE_HBR; 1029 break; 1030 case 162000: 1031 default: 1032 phy_rate = DPTX_PHYRATE_RBR; 1033 break; 1034 } 1035 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_RATE, 1036 FIELD_PREP(PHY_RATE, phy_rate)); 1037 1038 /* Move PHY to P0 */ 1039 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 1040 FIELD_PREP(PHY_POWERDOWN, 0x0)); 1041 1042 dw_dp_phy_xmit_enable(dp, link->lanes); 1043 1044 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 1045 FIELD_PREP(ENHANCE_FRAMING_EN, 1)); 1046 1047 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE); 1048 return 0; 1049 } 1050 1051 static int dw_dp_send_sdp(struct dw_dp *dp, struct dw_dp_sdp *sdp) 1052 { 1053 const u8 *payload = sdp->db; 1054 u32 reg; 1055 int i, nr = 0; 1056 1057 reg = DPTX_SDP_REGISTER_BANK + nr * 9 * 4; 1058 1059 /* SDP header */ 1060 regmap_write(dp->regmap, reg, get_unaligned_le32(&sdp->header)); 1061 1062 /* SDP data payload */ 1063 for (i = 1; i < 9; i++, payload += 4) 1064 regmap_write(dp->regmap, reg + i * 4, 1065 FIELD_PREP(SDP_REGS, get_unaligned_le32(payload))); 1066 1067 if (sdp->flags & DPTX_SDP_VERTICAL_INTERVAL) 1068 regmap_update_bits(dp->regmap, DPTX_SDP_VERTICAL_CTRL, 1069 EN_VERTICAL_SDP << nr, 1070 EN_VERTICAL_SDP << nr); 1071 1072 if (sdp->flags & DPTX_SDP_HORIZONTAL_INTERVAL) 1073 regmap_update_bits(dp->regmap, DPTX_SDP_HORIZONTAL_CTRL, 1074 EN_HORIZONTAL_SDP << nr, 1075 EN_HORIZONTAL_SDP << nr); 1076 1077 return 0; 1078 } 1079 1080 static void dw_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, 1081 struct dw_dp_sdp *sdp) 1082 { 1083 sdp->header.HB0 = 0; 1084 sdp->header.HB1 = DP_SDP_VSC; 1085 sdp->header.HB2 = vsc->revision; 1086 sdp->header.HB3 = vsc->length; 1087 1088 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; 1089 sdp->db[16] |= vsc->colorimetry & 0xf; 1090 1091 switch (vsc->bpc) { 1092 case 8: 1093 sdp->db[17] = 0x1; 1094 break; 1095 case 10: 1096 sdp->db[17] = 0x2; 1097 break; 1098 case 12: 1099 sdp->db[17] = 0x3; 1100 break; 1101 case 16: 1102 sdp->db[17] = 0x4; 1103 break; 1104 case 6: 1105 default: 1106 break; 1107 } 1108 1109 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) 1110 sdp->db[17] |= 0x80; 1111 1112 sdp->db[18] = vsc->content_type & 0x7; 1113 1114 sdp->flags |= DPTX_SDP_VERTICAL_INTERVAL; 1115 } 1116 1117 static int dw_dp_send_vsc_sdp(struct dw_dp *dp) 1118 { 1119 struct dw_dp_video *video = &dp->video; 1120 struct drm_dp_vsc_sdp vsc = {}; 1121 struct dw_dp_sdp sdp = {}; 1122 1123 vsc.revision = 0x5; 1124 vsc.length = 0x13; 1125 1126 switch (video->color_format) { 1127 case DRM_COLOR_FORMAT_YCRCB444: 1128 vsc.pixelformat = DP_PIXELFORMAT_YUV444; 1129 break; 1130 case DRM_COLOR_FORMAT_YCRCB420: 1131 vsc.pixelformat = DP_PIXELFORMAT_YUV420; 1132 break; 1133 case DRM_COLOR_FORMAT_YCRCB422: 1134 vsc.pixelformat = DP_PIXELFORMAT_YUV422; 1135 break; 1136 case DRM_COLOR_FORMAT_RGB444: 1137 default: 1138 vsc.pixelformat = DP_PIXELFORMAT_RGB; 1139 break; 1140 } 1141 1142 if (video->color_format == DRM_COLOR_FORMAT_RGB444) 1143 vsc.colorimetry = DP_COLORIMETRY_DEFAULT; 1144 else 1145 vsc.colorimetry = DP_COLORIMETRY_BT709_YCC; 1146 1147 vsc.bpc = video->bpc; 1148 vsc.dynamic_range = DP_DYNAMIC_RANGE_CTA; 1149 vsc.content_type = DP_CONTENT_TYPE_NOT_DEFINED; 1150 1151 dw_dp_vsc_sdp_pack(&vsc, &sdp); 1152 1153 return dw_dp_send_sdp(dp, &sdp); 1154 } 1155 1156 static int dw_dp_video_set_pixel_mode(struct dw_dp *dp, u8 pixel_mode) 1157 { 1158 switch (pixel_mode) { 1159 case DPTX_MP_SINGLE_PIXEL: 1160 case DPTX_MP_DUAL_PIXEL: 1161 case DPTX_MP_QUAD_PIXEL: 1162 break; 1163 default: 1164 return -EINVAL; 1165 } 1166 1167 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, PIXEL_MODE_SELECT, 1168 FIELD_PREP(PIXEL_MODE_SELECT, pixel_mode)); 1169 1170 return 0; 1171 } 1172 1173 static int dw_dp_video_set_msa(struct dw_dp *dp, u8 color_format, u8 bpc, 1174 u16 vstart, u16 hstart) 1175 { 1176 struct dw_dp_link *link = &dp->link; 1177 u16 misc = 0; 1178 1179 if (link->vsc_sdp_extension_for_colorimetry_supported) 1180 misc |= DP_MSA_MISC_COLOR_VSC_SDP; 1181 1182 switch (color_format) { 1183 case DRM_COLOR_FORMAT_RGB444: 1184 misc |= DP_MSA_MISC_COLOR_RGB; 1185 break; 1186 case DRM_COLOR_FORMAT_YCRCB444: 1187 misc |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 1188 break; 1189 case DRM_COLOR_FORMAT_YCRCB422: 1190 misc |= DP_MSA_MISC_COLOR_YCBCR_422_BT709; 1191 break; 1192 case DRM_COLOR_FORMAT_YCRCB420: 1193 break; 1194 default: 1195 return -EINVAL; 1196 } 1197 1198 switch (bpc) { 1199 case 6: 1200 misc |= DP_MSA_MISC_6_BPC; 1201 break; 1202 case 8: 1203 misc |= DP_MSA_MISC_8_BPC; 1204 break; 1205 case 10: 1206 misc |= DP_MSA_MISC_10_BPC; 1207 break; 1208 case 12: 1209 misc |= DP_MSA_MISC_12_BPC; 1210 break; 1211 case 16: 1212 misc |= DP_MSA_MISC_16_BPC; 1213 break; 1214 default: 1215 return -EINVAL; 1216 } 1217 1218 regmap_write(dp->regmap, DPTX_VIDEO_MSA1, 1219 FIELD_PREP(VSTART, vstart) | FIELD_PREP(HSTART, hstart)); 1220 regmap_write(dp->regmap, DPTX_VIDEO_MSA2, FIELD_PREP(MISC0, misc)); 1221 regmap_write(dp->regmap, DPTX_VIDEO_MSA3, FIELD_PREP(MISC1, misc >> 8)); 1222 1223 return 0; 1224 } 1225 1226 static int dw_dp_video_enable(struct dw_dp *dp) 1227 { 1228 struct dw_dp_video *video = &dp->video; 1229 struct dw_dp_link *link = &dp->link; 1230 struct drm_display_mode *mode = &video->mode; 1231 u8 color_format = video->color_format; 1232 u8 bpc = video->bpc; 1233 u8 pixel_mode = video->pixel_mode; 1234 u8 bpp = video->bpp, init_threshold, vic; 1235 u32 hactive, hblank, h_sync_width, h_front_porch; 1236 u32 vactive, vblank, v_sync_width, v_front_porch; 1237 u32 vstart = mode->vtotal - mode->vsync_start; 1238 u32 hstart = mode->htotal - mode->hsync_start; 1239 u32 peak_stream_bandwidth, link_bandwidth; 1240 u32 average_bytes_per_tu, average_bytes_per_tu_frac; 1241 u32 ts, hblank_interval; 1242 u32 value; 1243 int ret; 1244 1245 ret = dw_dp_video_set_pixel_mode(dp, pixel_mode); 1246 if (ret) 1247 return ret; 1248 1249 ret = dw_dp_video_set_msa(dp, color_format, bpc, vstart, hstart); 1250 if (ret) 1251 return ret; 1252 1253 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_MAPPING, 1254 FIELD_PREP(VIDEO_MAPPING, video->video_mapping)); 1255 1256 /* Configure DPTX_VINPUT_POLARITY_CTRL register */ 1257 value = 0; 1258 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1259 value |= FIELD_PREP(HSYNC_IN_POLARITY, 1); 1260 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1261 value |= FIELD_PREP(VSYNC_IN_POLARITY, 1); 1262 regmap_write(dp->regmap, DPTX_VINPUT_POLARITY_CTRL, value); 1263 1264 /* Configure DPTX_VIDEO_CONFIG1 register */ 1265 hactive = mode->hdisplay; 1266 hblank = mode->htotal - mode->hdisplay; 1267 value = FIELD_PREP(HACTIVE, hactive) | FIELD_PREP(HBLANK, hblank); 1268 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1269 value |= FIELD_PREP(I_P, 1); 1270 vic = drm_match_cea_mode(mode); 1271 if (vic == 5 || vic == 6 || vic == 7 || 1272 vic == 10 || vic == 11 || vic == 20 || 1273 vic == 21 || vic == 22 || vic == 39 || 1274 vic == 25 || vic == 26 || vic == 40 || 1275 vic == 44 || vic == 45 || vic == 46 || 1276 vic == 50 || vic == 51 || vic == 54 || 1277 vic == 55 || vic == 58 || vic == 59) 1278 value |= R_V_BLANK_IN_OSC; 1279 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG1, value); 1280 1281 /* Configure DPTX_VIDEO_CONFIG2 register */ 1282 vblank = mode->vtotal - mode->vdisplay; 1283 vactive = mode->vdisplay; 1284 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG2, 1285 FIELD_PREP(VBLANK, vblank) | FIELD_PREP(VACTIVE, vactive)); 1286 1287 /* Configure DPTX_VIDEO_CONFIG3 register */ 1288 h_sync_width = mode->hsync_end - mode->hsync_start; 1289 h_front_porch = mode->hsync_start - mode->hdisplay; 1290 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG3, 1291 FIELD_PREP(H_SYNC_WIDTH, h_sync_width) | 1292 FIELD_PREP(H_FRONT_PORCH, h_front_porch)); 1293 1294 /* Configure DPTX_VIDEO_CONFIG4 register */ 1295 v_sync_width = mode->vsync_end - mode->vsync_start; 1296 v_front_porch = mode->vsync_start - mode->vdisplay; 1297 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG4, 1298 FIELD_PREP(V_SYNC_WIDTH, v_sync_width) | 1299 FIELD_PREP(V_FRONT_PORCH, v_front_porch)); 1300 1301 /* Configure DPTX_VIDEO_CONFIG5 register */ 1302 peak_stream_bandwidth = mode->clock * bpp / 8; 1303 link_bandwidth = (link->rate / 1000) * link->lanes; 1304 ts = peak_stream_bandwidth * 64 / link_bandwidth; 1305 average_bytes_per_tu = ts / 1000; 1306 average_bytes_per_tu_frac = ts / 100 - average_bytes_per_tu * 10; 1307 if (pixel_mode == DPTX_MP_SINGLE_PIXEL) { 1308 if (average_bytes_per_tu < 6) 1309 init_threshold = 32; 1310 else if (hblank <= 80 && 1311 color_format != DRM_COLOR_FORMAT_YCRCB420) 1312 init_threshold = 12; 1313 else if (hblank <= 40 && 1314 color_format == DRM_COLOR_FORMAT_YCRCB420) 1315 init_threshold = 3; 1316 else 1317 init_threshold = 16; 1318 } else { 1319 u32 t1 = 0, t2 = 0, t3 = 0; 1320 1321 switch (bpc) { 1322 case 6: 1323 t1 = (4 * 1000 / 9) * link->lanes; 1324 break; 1325 case 8: 1326 if (color_format == DRM_COLOR_FORMAT_YCRCB422) { 1327 t1 = (1000 / 2) * link->lanes; 1328 } else { 1329 if (pixel_mode == DPTX_MP_DUAL_PIXEL) 1330 t1 = (1000 / 3) * link->lanes; 1331 else 1332 t1 = (3000 / 16) * link->lanes; 1333 } 1334 break; 1335 case 10: 1336 if (color_format == DRM_COLOR_FORMAT_YCRCB422) 1337 t1 = (2000 / 5) * link->lanes; 1338 else 1339 t1 = (4000 / 15) * link->lanes; 1340 break; 1341 case 12: 1342 if (color_format == DRM_COLOR_FORMAT_YCRCB422) { 1343 if (pixel_mode == DPTX_MP_DUAL_PIXEL) 1344 t1 = (1000 / 6) * link->lanes; 1345 else 1346 t1 = (1000 / 3) * link->lanes; 1347 } else { 1348 t1 = (2000 / 9) * link->lanes; 1349 } 1350 break; 1351 case 16: 1352 if (color_format != DRM_COLOR_FORMAT_YCRCB422 && 1353 pixel_mode == DPTX_MP_DUAL_PIXEL) 1354 t1 = (1000 / 6) * link->lanes; 1355 else 1356 t1 = (1000 / 4) * link->lanes; 1357 break; 1358 default: 1359 return -EINVAL; 1360 } 1361 1362 if (color_format == DRM_COLOR_FORMAT_YCRCB420) 1363 t2 = (link->rate / 4) * 1000 / (mode->clock / 2); 1364 else 1365 t2 = (link->rate / 4) * 1000 / mode->clock; 1366 1367 if (average_bytes_per_tu_frac) 1368 t3 = average_bytes_per_tu + 1; 1369 else 1370 t3 = average_bytes_per_tu; 1371 init_threshold = t1 * t2 * t3 / (1000 * 1000); 1372 if (init_threshold <= 16 || average_bytes_per_tu < 10) 1373 init_threshold = 40; 1374 } 1375 1376 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG5, 1377 FIELD_PREP(INIT_THRESHOLD_HI, init_threshold >> 6) | 1378 FIELD_PREP(AVERAGE_BYTES_PER_TU_FRAC, 1379 average_bytes_per_tu_frac) | 1380 FIELD_PREP(INIT_THRESHOLD, init_threshold) | 1381 FIELD_PREP(AVERAGE_BYTES_PER_TU, average_bytes_per_tu)); 1382 1383 /* Configure DPTX_VIDEO_HBLANK_INTERVAL register */ 1384 hblank_interval = hblank * (link->rate / 4) / mode->clock; 1385 regmap_write(dp->regmap, DPTX_VIDEO_HBLANK_INTERVAL, 1386 FIELD_PREP(HBLANK_INTERVAL_EN, 1) | 1387 FIELD_PREP(HBLANK_INTERVAL, hblank_interval)); 1388 1389 /* Video stream enable */ 1390 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_STREAM_ENABLE, 1391 FIELD_PREP(VIDEO_STREAM_ENABLE, 1)); 1392 1393 if (link->vsc_sdp_extension_for_colorimetry_supported) 1394 dw_dp_send_vsc_sdp(dp); 1395 1396 return 0; 1397 } 1398 1399 static bool dw_dp_detect(struct dw_dp *dp) 1400 { 1401 u32 value; 1402 1403 if (dm_gpio_is_valid(&dp->hpd_gpio)) 1404 return dm_gpio_get_value(&dp->hpd_gpio); 1405 1406 regmap_read(dp->regmap, DPTX_HPD_STATUS, &value); 1407 if (FIELD_GET(HPD_STATE, value) == SOURCE_STATE_PLUG) { 1408 regmap_write(dp->regmap, DPTX_HPD_STATUS, HPD_HOT_PLUG); 1409 return true; 1410 } 1411 1412 return false; 1413 } 1414 1415 static int dw_dp_connector_init(struct rockchip_connector *conn, struct display_state *state) 1416 { 1417 struct connector_state *conn_state = &state->conn_state; 1418 struct dw_dp *dp = dev_get_priv(conn->dev); 1419 int ret; 1420 1421 conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_DP1 : VOP_OUTPUT_IF_DP0; 1422 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1423 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709; 1424 1425 clk_set_defaults(dp->dev); 1426 1427 reset_assert(&dp->reset); 1428 udelay(20); 1429 reset_deassert(&dp->reset); 1430 1431 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, 1432 dp->id); 1433 dw_dp_init(dp); 1434 ret = generic_phy_power_on(&dp->phy); 1435 1436 return ret; 1437 } 1438 1439 static int dw_dp_connector_get_edid(struct rockchip_connector *conn, struct display_state *state) 1440 { 1441 int ret; 1442 struct connector_state *conn_state = &state->conn_state; 1443 struct dw_dp *dp = dev_get_priv(conn->dev); 1444 1445 ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); 1446 1447 return ret; 1448 } 1449 1450 static int dw_dp_get_output_fmts_index(u32 bus_format) 1451 { 1452 int i; 1453 1454 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 1455 const struct dw_dp_output_format *fmt = &possible_output_fmts[i]; 1456 1457 if (fmt->bus_format == bus_format) 1458 break; 1459 } 1460 1461 if (i == ARRAY_SIZE(possible_output_fmts)) 1462 return 1; 1463 1464 return i; 1465 } 1466 1467 static int dw_dp_connector_prepare(struct rockchip_connector *conn, struct display_state *state) 1468 { 1469 struct connector_state *conn_state = &state->conn_state; 1470 struct dw_dp *dp = dev_get_priv(conn->dev); 1471 struct dw_dp_video *video = &dp->video; 1472 int bus_fmt; 1473 1474 bus_fmt = dw_dp_get_output_fmts_index(conn_state->bus_format); 1475 video->video_mapping = possible_output_fmts[bus_fmt].video_mapping; 1476 video->color_format = possible_output_fmts[bus_fmt].color_format; 1477 video->bus_format = possible_output_fmts[bus_fmt].bus_format; 1478 video->bpc = possible_output_fmts[bus_fmt].bpc; 1479 video->bpp = possible_output_fmts[bus_fmt].bpp; 1480 1481 return 0; 1482 } 1483 1484 static int dw_dp_connector_enable(struct rockchip_connector *conn, struct display_state *state) 1485 { 1486 struct connector_state *conn_state = &state->conn_state; 1487 struct drm_display_mode *mode = &conn_state->mode; 1488 struct dw_dp *dp = dev_get_priv(conn->dev); 1489 struct dw_dp_video *video = &dp->video; 1490 int ret; 1491 1492 memcpy(&video->mode, mode, sizeof(video->mode)); 1493 1494 if (dp->force_output) { 1495 ret = dw_dp_set_phy_default_config(dp); 1496 if (ret < 0) 1497 printf("failed to set phy_default config: %d\n", ret); 1498 } else { 1499 ret = dw_dp_link_enable(dp); 1500 if (ret < 0) { 1501 printf("failed to enable link: %d\n", ret); 1502 return ret; 1503 } 1504 } 1505 1506 ret = dw_dp_video_enable(dp); 1507 if (ret < 0) { 1508 printf("failed to enable video: %d\n", ret); 1509 return ret; 1510 } 1511 1512 return 0; 1513 } 1514 1515 static int dw_dp_connector_disable(struct rockchip_connector *conn, struct display_state *state) 1516 { 1517 /* TODO */ 1518 1519 return 0; 1520 } 1521 1522 static int dw_dp_connector_detect(struct rockchip_connector *conn, struct display_state *state) 1523 { 1524 struct dw_dp *dp = dev_get_priv(conn->dev); 1525 int status, tries, ret; 1526 1527 for (tries = 0; tries < 200; tries++) { 1528 status = dw_dp_detect(dp); 1529 if (status) 1530 break; 1531 mdelay(2); 1532 } 1533 1534 if (state->force_output && !status) 1535 dp->force_output = true; 1536 1537 if (!status && !dp->force_output) 1538 generic_phy_power_off(&dp->phy); 1539 1540 if (status && !dp->force_output) { 1541 ret = dw_dp_link_probe(dp); 1542 if (ret) 1543 printf("failed to probe DP link: %d\n", ret); 1544 } 1545 1546 return status; 1547 } 1548 1549 static int dw_dp_mode_valid(struct dw_dp *dp, struct hdmi_edid_data *edid_data) 1550 { 1551 struct dw_dp_link *link = &dp->link; 1552 struct drm_display_info *di = &edid_data->display_info; 1553 u32 min_bpp; 1554 int i; 1555 1556 if (di->color_formats & DRM_COLOR_FORMAT_YCRCB420 && 1557 link->vsc_sdp_extension_for_colorimetry_supported) 1558 min_bpp = 12; 1559 else if (di->color_formats & DRM_COLOR_FORMAT_YCRCB422) 1560 min_bpp = 16; 1561 else if (di->color_formats & DRM_COLOR_FORMAT_RGB444) 1562 min_bpp = 18; 1563 else 1564 min_bpp = 24; 1565 1566 for (i = 0; i < edid_data->modes; i++) { 1567 if (!dw_dp_bandwidth_ok(dp, &edid_data->mode_buf[i], min_bpp, link->lanes, 1568 link->rate)) 1569 edid_data->mode_buf[i].invalid = true; 1570 } 1571 1572 return 0; 1573 } 1574 1575 static u32 dw_dp_get_output_bus_fmts(struct dw_dp *dp, struct hdmi_edid_data *edid_data) 1576 { 1577 struct dw_dp_link *link = &dp->link; 1578 unsigned int i; 1579 1580 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 1581 const struct dw_dp_output_format *fmt = &possible_output_fmts[i]; 1582 1583 if (fmt->bpc > edid_data->display_info.bpc) 1584 continue; 1585 1586 if (!(edid_data->display_info.color_formats & fmt->color_format)) 1587 continue; 1588 1589 if (fmt->color_format == DRM_COLOR_FORMAT_YCRCB420 && 1590 !link->vsc_sdp_extension_for_colorimetry_supported) 1591 continue; 1592 1593 if (drm_mode_is_420(&edid_data->display_info, edid_data->preferred_mode) && 1594 fmt->color_format != DRM_COLOR_FORMAT_YCRCB420) 1595 continue; 1596 1597 if (!dw_dp_bandwidth_ok(dp, edid_data->preferred_mode, fmt->bpp, link->lanes, 1598 link->rate)) 1599 continue; 1600 1601 break; 1602 } 1603 1604 if (i == ARRAY_SIZE(possible_output_fmts)) 1605 return 1; 1606 1607 return i; 1608 } 1609 1610 static int dw_dp_connector_get_timing(struct rockchip_connector *conn, struct display_state *state) 1611 { 1612 int ret, i; 1613 struct connector_state *conn_state = &state->conn_state; 1614 struct dw_dp *dp = dev_get_priv(conn->dev); 1615 struct drm_display_mode *mode = &conn_state->mode; 1616 struct hdmi_edid_data edid_data; 1617 struct drm_display_mode *mode_buf; 1618 struct vop_rect rect; 1619 u32 bus_fmt; 1620 1621 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 1622 if (!mode_buf) 1623 return -ENOMEM; 1624 1625 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 1626 memset(&edid_data, 0, sizeof(struct hdmi_edid_data)); 1627 edid_data.mode_buf = mode_buf; 1628 1629 if (!dp->force_output) { 1630 ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); 1631 if (!ret) 1632 ret = drm_add_edid_modes(&edid_data, conn_state->edid); 1633 1634 if (ret < 0) { 1635 printf("failed to get edid\n"); 1636 goto err; 1637 } 1638 1639 drm_rk_filter_whitelist(&edid_data); 1640 if (state->conn_state.secondary) { 1641 rect.width = state->crtc_state.max_output.width / 2; 1642 rect.height = state->crtc_state.max_output.height / 2; 1643 } else { 1644 rect.width = state->crtc_state.max_output.width; 1645 rect.height = state->crtc_state.max_output.height; 1646 } 1647 1648 drm_mode_max_resolution_filter(&edid_data, &rect); 1649 dw_dp_mode_valid(dp, &edid_data); 1650 1651 if (!drm_mode_prune_invalid(&edid_data)) { 1652 printf("can't find valid dp mode\n"); 1653 ret = -EINVAL; 1654 goto err; 1655 } 1656 1657 for (i = 0; i < edid_data.modes; i++) 1658 edid_data.mode_buf[i].vrefresh = 1659 drm_mode_vrefresh(&edid_data.mode_buf[i]); 1660 1661 drm_mode_sort(&edid_data); 1662 memcpy(mode, edid_data.preferred_mode, sizeof(struct drm_display_mode)); 1663 } 1664 1665 if (state->force_output) 1666 bus_fmt = dw_dp_get_output_fmts_index(state->force_bus_format); 1667 else 1668 bus_fmt = dw_dp_get_output_bus_fmts(dp, &edid_data); 1669 1670 conn_state->bus_format = possible_output_fmts[bus_fmt].bus_format; 1671 1672 switch (possible_output_fmts[bus_fmt].color_format) { 1673 case DRM_COLOR_FORMAT_YCRCB420: 1674 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420; 1675 break; 1676 case DRM_COLOR_FORMAT_YCRCB422: 1677 conn_state->output_mode = ROCKCHIP_OUT_MODE_S888_DUMMY; 1678 break; 1679 case DRM_COLOR_FORMAT_RGB444: 1680 case DRM_COLOR_FORMAT_YCRCB444: 1681 default: 1682 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1683 break; 1684 } 1685 1686 err: 1687 free(mode_buf); 1688 1689 return 0; 1690 } 1691 1692 static const struct rockchip_connector_funcs dw_dp_connector_funcs = { 1693 .init = dw_dp_connector_init, 1694 .get_edid = dw_dp_connector_get_edid, 1695 .prepare = dw_dp_connector_prepare, 1696 .enable = dw_dp_connector_enable, 1697 .disable = dw_dp_connector_disable, 1698 .detect = dw_dp_connector_detect, 1699 .get_timing = dw_dp_connector_get_timing, 1700 }; 1701 1702 static int dw_dp_ddc_init(struct dw_dp *dp) 1703 { 1704 dp->aux.name = "dw-dp"; 1705 dp->aux.dev = dp->dev; 1706 dp->aux.transfer = dw_dp_aux_transfer; 1707 dp->aux.ddc.ddc_xfer = drm_dp_i2c_xfer; 1708 1709 return 0; 1710 } 1711 1712 static u32 dw_dp_parse_link_frequencies(struct dw_dp *dp) 1713 { 1714 struct udevice *dev = dp->dev; 1715 const struct device_node *endpoint; 1716 u64 frequency = 0; 1717 1718 endpoint = rockchip_of_graph_get_endpoint_by_regs(dev->node, 1, 0); 1719 if (!endpoint) 1720 return 0; 1721 1722 if (of_property_read_u64(endpoint, "link-frequencies", &frequency) < 0) 1723 return 0; 1724 1725 if (!frequency) 1726 return 0; 1727 1728 do_div(frequency, 10 * 1000); /* symbol rate kbytes */ 1729 1730 switch (frequency) { 1731 case 162000: 1732 case 270000: 1733 case 540000: 1734 case 810000: 1735 break; 1736 default: 1737 dev_err(dev, "invalid link frequency value: %llu\n", frequency); 1738 return 0; 1739 } 1740 1741 return frequency; 1742 } 1743 1744 static int dw_dp_parse_dt(struct dw_dp *dp) 1745 { 1746 dp->force_hpd = dev_read_bool(dp->dev, "force-hpd"); 1747 1748 dp->max_link_rate = dw_dp_parse_link_frequencies(dp); 1749 if (!dp->max_link_rate) 1750 dp->max_link_rate = 810000; 1751 1752 return 0; 1753 } 1754 1755 static int dw_dp_probe(struct udevice *dev) 1756 { 1757 struct dw_dp *dp = dev_get_priv(dev); 1758 const struct dw_dp_chip_data *pdata = 1759 (const struct dw_dp_chip_data *)dev_get_driver_data(dev); 1760 int ret; 1761 1762 ret = regmap_init_mem(dev, &dp->regmap); 1763 if (ret) 1764 return ret; 1765 1766 dp->id = of_alias_get_id(ofnode_to_np(dev->node), "dp"); 1767 if (dp->id < 0) 1768 dp->id = 0; 1769 1770 dp->video.pixel_mode = pdata->pixel_mode; 1771 1772 ret = reset_get_by_index(dev, 0, &dp->reset); 1773 if (ret) { 1774 dev_err(dev, "failed to get reset control: %d\n", ret); 1775 return ret; 1776 } 1777 1778 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 1779 GPIOD_IS_IN); 1780 if (ret && ret != -ENOENT) { 1781 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 1782 return ret; 1783 } 1784 1785 generic_phy_get_by_index(dev, 0, &dp->phy); 1786 1787 dp->dev = dev; 1788 1789 ret = dw_dp_parse_dt(dp); 1790 if (ret) { 1791 dev_err(dev, "failed to parse DT\n"); 1792 return ret; 1793 } 1794 1795 dw_dp_ddc_init(dp); 1796 1797 rockchip_connector_bind(&dp->connector, dev, dp->id, &dw_dp_connector_funcs, NULL, 1798 DRM_MODE_CONNECTOR_DisplayPort); 1799 1800 return 0; 1801 } 1802 1803 static const struct dw_dp_chip_data rk3588_dp = { 1804 .pixel_mode = DPTX_MP_QUAD_PIXEL, 1805 }; 1806 1807 static const struct dw_dp_chip_data rk3576_dp = { 1808 .pixel_mode = DPTX_MP_DUAL_PIXEL, 1809 }; 1810 1811 static const struct udevice_id dw_dp_ids[] = { 1812 { 1813 .compatible = "rockchip,rk3576-dp", 1814 .data = (ulong)&rk3576_dp, 1815 }, 1816 { 1817 .compatible = "rockchip,rk3588-dp", 1818 .data = (ulong)&rk3588_dp, 1819 }, 1820 {} 1821 }; 1822 1823 U_BOOT_DRIVER(dw_dp) = { 1824 .name = "dw_dp", 1825 .id = UCLASS_DISPLAY, 1826 .of_match = dw_dp_ids, 1827 .probe = dw_dp_probe, 1828 .priv_auto_alloc_size = sizeof(struct dw_dp), 1829 }; 1830 1831