1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Rockchip USBDP Combo PHY with Samsung IP block driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd 6 */ 7 8 #include <config.h> 9 #include <common.h> 10 #include <errno.h> 11 #include <malloc.h> 12 #include <asm/unaligned.h> 13 #include <asm/io.h> 14 #include <clk.h> 15 #include <dm/device.h> 16 #include <dm/of_access.h> 17 #include <dm/read.h> 18 #include <generic-phy.h> 19 #include <linux/bitfield.h> 20 #include <linux/hdmi.h> 21 #include <linux/media-bus-format.h> 22 #include <linux/list.h> 23 #include <asm/gpio.h> 24 #include <generic-phy.h> 25 #include <regmap.h> 26 #include <reset.h> 27 #include <drm/drm_dp_helper.h> 28 29 #include "rockchip_display.h" 30 #include "rockchip_crtc.h" 31 #include "rockchip_connector.h" 32 33 #define DPTX_VERSION_NUMBER 0x0000 34 #define DPTX_VERSION_TYPE 0x0004 35 #define DPTX_ID 0x0008 36 37 #define DPTX_CONFIG_REG1 0x0100 38 #define DPTX_CONFIG_REG2 0x0104 39 #define DPTX_CONFIG_REG3 0x0108 40 41 #define DPTX_CCTL 0x0200 42 #define FORCE_HPD BIT(4) 43 #define DEFAULT_FAST_LINK_TRAIN_EN BIT(2) 44 #define ENHANCE_FRAMING_EN BIT(1) 45 #define SCRAMBLE_DIS BIT(0) 46 #define DPTX_SOFT_RESET_CTRL 0x0204 47 #define VIDEO_RESET BIT(5) 48 #define AUX_RESET BIT(4) 49 #define AUDIO_SAMPLER_RESET BIT(3) 50 #define PHY_SOFT_RESET BIT(1) 51 #define CONTROLLER_RESET BIT(0) 52 53 #define DPTX_VSAMPLE_CTRL 0x0300 54 #define PIXEL_MODE_SELECT GENMASK(22, 21) 55 #define VIDEO_MAPPING GENMASK(20, 16) 56 #define VIDEO_STREAM_ENABLE BIT(5) 57 #define DPTX_VSAMPLE_STUFF_CTRL1 0x0304 58 #define DPTX_VSAMPLE_STUFF_CTRL2 0x0308 59 #define DPTX_VINPUT_POLARITY_CTRL 0x030c 60 #define DE_IN_POLARITY BIT(2) 61 #define HSYNC_IN_POLARITY BIT(1) 62 #define VSYNC_IN_POLARITY BIT(0) 63 #define DPTX_VIDEO_CONFIG1 0x0310 64 #define HACTIVE GENMASK(31, 16) 65 #define HBLANK GENMASK(15, 2) 66 #define I_P BIT(1) 67 #define R_V_BLANK_IN_OSC BIT(0) 68 #define DPTX_VIDEO_CONFIG2 0x0314 69 #define VBLANK GENMASK(31, 16) 70 #define VACTIVE GENMASK(15, 0) 71 #define DPTX_VIDEO_CONFIG3 0x0318 72 #define H_SYNC_WIDTH GENMASK(31, 16) 73 #define H_FRONT_PORCH GENMASK(15, 0) 74 #define DPTX_VIDEO_CONFIG4 0x031c 75 #define V_SYNC_WIDTH GENMASK(31, 16) 76 #define V_FRONT_PORCH GENMASK(15, 0) 77 #define DPTX_VIDEO_CONFIG5 0x0320 78 #define INIT_THRESHOLD_HI GENMASK(22, 21) 79 #define AVERAGE_BYTES_PER_TU_FRAC GENMASK(19, 16) 80 #define INIT_THRESHOLD GENMASK(13, 7) 81 #define AVERAGE_BYTES_PER_TU GENMASK(6, 0) 82 #define DPTX_VIDEO_MSA1 0x0324 83 #define VSTART GENMASK(31, 16) 84 #define HSTART GENMASK(15, 0) 85 #define DPTX_VIDEO_MSA2 0x0328 86 #define MISC0 GENMASK(31, 24) 87 #define DPTX_VIDEO_MSA3 0x032c 88 #define MISC1 GENMASK(31, 24) 89 #define DPTX_VIDEO_HBLANK_INTERVAL 0x0330 90 #define HBLANK_INTERVAL_EN BIT(16) 91 #define HBLANK_INTERVAL GENMASK(15, 0) 92 93 #define DPTX_AUD_CONFIG1 0x0400 94 #define AUDIO_TIMESTAMP_VERSION_NUM GENMASK(29, 24) 95 #define AUDIO_PACKET_ID GENMASK(23, 16) 96 #define AUDIO_MUTE BIT(15) 97 #define NUM_CHANNELS GENMASK(14, 12) 98 #define HBR_MODE_ENABLE BIT(10) 99 #define AUDIO_DATA_WIDTH GENMASK(9, 5) 100 #define AUDIO_DATA_IN_EN GENMASK(4, 1) 101 #define AUDIO_INF_SELECT BIT(0) 102 103 #define DPTX_SDP_VERTICAL_CTRL 0x0500 104 #define EN_VERTICAL_SDP BIT(2) 105 #define EN_AUDIO_STREAM_SDP BIT(1) 106 #define EN_AUDIO_TIMESTAMP_SDP BIT(0) 107 #define DPTX_SDP_HORIZONTAL_CTRL 0x0504 108 #define EN_HORIZONTAL_SDP BIT(2) 109 #define DPTX_SDP_STATUS_REGISTER 0x0508 110 #define DPTX_SDP_MANUAL_CTRL 0x050c 111 #define DPTX_SDP_STATUS_EN 0x0510 112 113 #define DPTX_SDP_REGISTER_BANK 0x0600 114 #define SDP_REGS GENMASK(31, 0) 115 116 #define DPTX_PHYIF_CTRL 0x0a00 117 #define PHY_WIDTH BIT(25) 118 #define PHY_POWERDOWN GENMASK(20, 17) 119 #define PHY_BUSY GENMASK(15, 12) 120 #define SSC_DIS BIT(16) 121 #define XMIT_ENABLE GENMASK(11, 8) 122 #define PHY_LANES GENMASK(7, 6) 123 #define PHY_RATE GENMASK(5, 4) 124 #define TPS_SEL GENMASK(3, 0) 125 #define DPTX_PHY_TX_EQ 0x0a04 126 #define DPTX_CUSTOMPAT0 0x0a08 127 #define DPTX_CUSTOMPAT1 0x0a0c 128 #define DPTX_CUSTOMPAT2 0x0a10 129 #define DPTX_HBR2_COMPLIANCE_SCRAMBLER_RESET 0x0a14 130 #define DPTX_PHYIF_PWRDOWN_CTRL 0x0a18 131 132 #define DPTX_AUX_CMD 0x0b00 133 #define AUX_CMD_TYPE GENMASK(31, 28) 134 #define AUX_ADDR GENMASK(27, 8) 135 #define I2C_ADDR_ONLY BIT(4) 136 #define AUX_LEN_REQ GENMASK(3, 0) 137 #define DPTX_AUX_STATUS 0x0b04 138 #define AUX_TIMEOUT BIT(17) 139 #define AUX_BYTES_READ GENMASK(23, 19) 140 #define AUX_STATUS GENMASK(7, 4) 141 #define DPTX_AUX_DATA0 0x0b08 142 #define DPTX_AUX_DATA1 0x0b0c 143 #define DPTX_AUX_DATA2 0x0b10 144 #define DPTX_AUX_DATA3 0x0b14 145 146 #define DPTX_GENERAL_INTERRUPT 0x0d00 147 #define VIDEO_FIFO_OVERFLOW_STREAM0 BIT(6) 148 #define AUDIO_FIFO_OVERFLOW_STREAM0 BIT(5) 149 #define SDP_EVENT_STREAM0 BIT(4) 150 #define AUX_CMD_INVALID BIT(3) 151 #define AUX_REPLY_EVENT BIT(1) 152 #define HPD_EVENT BIT(0) 153 #define DPTX_GENERAL_INTERRUPT_ENABLE 0x0d04 154 #define AUX_REPLY_EVENT_EN BIT(1) 155 #define HPD_EVENT_EN BIT(0) 156 #define DPTX_HPD_STATUS 0x0d08 157 #define HPD_STATE GENMASK(11, 9) 158 #define HPD_STATUS BIT(8) 159 #define HPD_HOT_UNPLUG BIT(2) 160 #define HPD_HOT_PLUG BIT(1) 161 #define HPD_IRQ BIT(0) 162 #define DPTX_HPD_INTERRUPT_ENABLE 0x0d0c 163 #define HPD_UNPLUG_ERR_EN BIT(3) 164 #define HPD_UNPLUG_EN BIT(2) 165 #define HPD_PLUG_EN BIT(1) 166 #define HPD_IRQ_EN BIT(0) 167 168 #define DPTX_MAX_REGISTER DPTX_HPD_INTERRUPT_ENABLE 169 170 #define SDP_REG_BANK_SIZE 16 171 172 struct drm_dp_link_caps { 173 bool enhanced_framing; 174 bool tps3_supported; 175 bool tps4_supported; 176 bool channel_coding; 177 bool ssc; 178 }; 179 180 struct drm_dp_link_train_set { 181 unsigned int voltage_swing[4]; 182 unsigned int pre_emphasis[4]; 183 }; 184 185 struct drm_dp_link_train { 186 struct drm_dp_link_train_set request; 187 struct drm_dp_link_train_set adjust; 188 bool clock_recovered; 189 bool channel_equalized; 190 }; 191 192 struct dw_dp_link { 193 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 194 unsigned char revision; 195 unsigned int rate; 196 unsigned int lanes; 197 struct drm_dp_link_caps caps; 198 struct drm_dp_link_train train; 199 u8 sink_count; 200 u8 vsc_sdp_extension_for_colorimetry_supported; 201 }; 202 203 struct dw_dp_video { 204 struct drm_display_mode mode; 205 u32 bus_format; 206 u8 video_mapping; 207 u8 pixel_mode; 208 u8 color_format; 209 u8 bpc; 210 u8 bpp; 211 }; 212 213 struct dw_dp_sdp { 214 struct dp_sdp_header header; 215 u8 db[32]; 216 unsigned long flags; 217 }; 218 219 struct dw_dp { 220 struct rockchip_connector connector; 221 struct udevice *dev; 222 struct regmap *regmap; 223 struct phy phy; 224 struct reset_ctl reset; 225 int id; 226 227 struct gpio_desc hpd_gpio; 228 struct drm_dp_aux aux; 229 struct dw_dp_link link; 230 struct dw_dp_video video; 231 232 bool force_hpd; 233 bool force_output; 234 u32 max_link_rate; 235 }; 236 237 enum { 238 SOURCE_STATE_IDLE, 239 SOURCE_STATE_UNPLUG, 240 SOURCE_STATE_HPD_TIMEOUT = 4, 241 SOURCE_STATE_PLUG = 7 242 }; 243 244 enum { 245 DPTX_VM_RGB_6BIT, 246 DPTX_VM_RGB_8BIT, 247 DPTX_VM_RGB_10BIT, 248 DPTX_VM_RGB_12BIT, 249 DPTX_VM_RGB_16BIT, 250 DPTX_VM_YCBCR444_8BIT, 251 DPTX_VM_YCBCR444_10BIT, 252 DPTX_VM_YCBCR444_12BIT, 253 DPTX_VM_YCBCR444_16BIT, 254 DPTX_VM_YCBCR422_8BIT, 255 DPTX_VM_YCBCR422_10BIT, 256 DPTX_VM_YCBCR422_12BIT, 257 DPTX_VM_YCBCR422_16BIT, 258 DPTX_VM_YCBCR420_8BIT, 259 DPTX_VM_YCBCR420_10BIT, 260 DPTX_VM_YCBCR420_12BIT, 261 DPTX_VM_YCBCR420_16BIT, 262 }; 263 264 enum { 265 DPTX_MP_SINGLE_PIXEL, 266 DPTX_MP_DUAL_PIXEL, 267 DPTX_MP_QUAD_PIXEL, 268 }; 269 270 enum { 271 DPTX_SDP_VERTICAL_INTERVAL = BIT(0), 272 DPTX_SDP_HORIZONTAL_INTERVAL = BIT(1), 273 }; 274 275 enum { 276 DPTX_PHY_PATTERN_NONE, 277 DPTX_PHY_PATTERN_TPS_1, 278 DPTX_PHY_PATTERN_TPS_2, 279 DPTX_PHY_PATTERN_TPS_3, 280 DPTX_PHY_PATTERN_TPS_4, 281 DPTX_PHY_PATTERN_SERM, 282 DPTX_PHY_PATTERN_PBRS7, 283 DPTX_PHY_PATTERN_CUSTOM_80BIT, 284 DPTX_PHY_PATTERN_CP2520_1, 285 DPTX_PHY_PATTERN_CP2520_2, 286 }; 287 288 enum { 289 DPTX_PHYRATE_RBR, 290 DPTX_PHYRATE_HBR, 291 DPTX_PHYRATE_HBR2, 292 DPTX_PHYRATE_HBR3, 293 }; 294 295 struct dw_dp_output_format { 296 u32 bus_format; 297 u32 color_format; 298 u8 video_mapping; 299 u8 bpc; 300 u8 bpp; 301 }; 302 303 static const struct dw_dp_output_format possible_output_fmts[] = { 304 { MEDIA_BUS_FMT_RGB101010_1X30, DRM_COLOR_FORMAT_RGB444, 305 DPTX_VM_RGB_10BIT, 10, 30 }, 306 { MEDIA_BUS_FMT_RGB888_1X24, DRM_COLOR_FORMAT_RGB444, 307 DPTX_VM_RGB_8BIT, 8, 24 }, 308 { MEDIA_BUS_FMT_YUV10_1X30, DRM_COLOR_FORMAT_YCRCB444, 309 DPTX_VM_YCBCR444_10BIT, 10, 30 }, 310 { MEDIA_BUS_FMT_YUV8_1X24, DRM_COLOR_FORMAT_YCRCB444, 311 DPTX_VM_YCBCR444_8BIT, 8, 24}, 312 { MEDIA_BUS_FMT_YUYV10_1X20, DRM_COLOR_FORMAT_YCRCB422, 313 DPTX_VM_YCBCR422_10BIT, 10, 20 }, 314 { MEDIA_BUS_FMT_YUYV8_1X16, DRM_COLOR_FORMAT_YCRCB422, 315 DPTX_VM_YCBCR422_8BIT, 8, 16 }, 316 { MEDIA_BUS_FMT_UYYVYY10_0_5X30, DRM_COLOR_FORMAT_YCRCB420, 317 DPTX_VM_YCBCR420_10BIT, 10, 15 }, 318 { MEDIA_BUS_FMT_UYYVYY8_0_5X24, DRM_COLOR_FORMAT_YCRCB420, 319 DPTX_VM_YCBCR420_8BIT, 8, 12 }, 320 { MEDIA_BUS_FMT_RGB666_1X24_CPADHI, DRM_COLOR_FORMAT_RGB444, 321 DPTX_VM_RGB_6BIT, 6, 18 }, 322 }; 323 324 static int dw_dp_aux_write_data(struct dw_dp *dp, const u8 *buffer, size_t size) 325 { 326 size_t i, j; 327 328 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 329 size_t num = min_t(size_t, size - i * 4, 4); 330 u32 value = 0; 331 332 for (j = 0; j < num; j++) 333 value |= buffer[i * 4 + j] << (j * 8); 334 335 regmap_write(dp->regmap, DPTX_AUX_DATA0 + i * 4, value); 336 } 337 338 return size; 339 } 340 341 static int dw_dp_aux_read_data(struct dw_dp *dp, u8 *buffer, size_t size) 342 { 343 size_t i, j; 344 345 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 346 size_t num = min_t(size_t, size - i * 4, 4); 347 u32 value; 348 349 regmap_read(dp->regmap, DPTX_AUX_DATA0 + i * 4, &value); 350 351 for (j = 0; j < num; j++) 352 buffer[i * 4 + j] = value >> (j * 8); 353 } 354 355 return size; 356 } 357 358 static ssize_t dw_dp_aux_transfer(struct drm_dp_aux *aux, 359 struct drm_dp_aux_msg *msg) 360 { 361 u32 status, value; 362 ssize_t ret = 0; 363 int timeout = 0; 364 struct dw_dp *dp = dev_get_priv(aux->dev); 365 366 if (WARN_ON(msg->size > 16)) 367 return -E2BIG; 368 369 switch (msg->request & ~DP_AUX_I2C_MOT) { 370 case DP_AUX_NATIVE_WRITE: 371 case DP_AUX_I2C_WRITE: 372 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 373 ret = dw_dp_aux_write_data(dp, msg->buffer, msg->size); 374 if (ret < 0) 375 return ret; 376 break; 377 case DP_AUX_NATIVE_READ: 378 case DP_AUX_I2C_READ: 379 break; 380 default: 381 return -EINVAL; 382 } 383 384 if (msg->size > 0) 385 value = FIELD_PREP(AUX_LEN_REQ, msg->size - 1); 386 else 387 value = FIELD_PREP(I2C_ADDR_ONLY, 1); 388 389 value |= FIELD_PREP(AUX_CMD_TYPE, msg->request); 390 value |= FIELD_PREP(AUX_ADDR, msg->address); 391 regmap_write(dp->regmap, DPTX_AUX_CMD, value); 392 393 timeout = regmap_read_poll_timeout(dp->regmap, DPTX_GENERAL_INTERRUPT, 394 status, status & AUX_REPLY_EVENT, 395 200, 10); 396 397 if (timeout) { 398 printf("timeout waiting for AUX reply\n"); 399 return -ETIMEDOUT; 400 } 401 regmap_write(dp->regmap, DPTX_GENERAL_INTERRUPT, AUX_REPLY_EVENT); 402 403 regmap_read(dp->regmap, DPTX_AUX_STATUS, &value); 404 if (value & AUX_TIMEOUT) { 405 printf("aux timeout\n"); 406 return -ETIMEDOUT; 407 } 408 409 msg->reply = FIELD_GET(AUX_STATUS, value); 410 411 if (msg->size > 0 && msg->reply == DP_AUX_NATIVE_REPLY_ACK) { 412 if (msg->request & DP_AUX_I2C_READ) { 413 size_t count = FIELD_GET(AUX_BYTES_READ, value) - 1; 414 415 if (count != msg->size) { 416 printf("aux fail to read %lu bytes\n", count); 417 return -EBUSY; 418 } 419 420 ret = dw_dp_aux_read_data(dp, msg->buffer, count); 421 if (ret < 0) 422 return ret; 423 } 424 } 425 426 return ret; 427 } 428 429 static bool dw_dp_bandwidth_ok(struct dw_dp *dp, 430 const struct drm_display_mode *mode, u32 bpp, 431 unsigned int lanes, unsigned int rate) 432 { 433 u32 max_bw, req_bw; 434 435 req_bw = mode->clock * bpp / 8; 436 max_bw = lanes * rate; 437 if (req_bw > max_bw) 438 return false; 439 440 return true; 441 } 442 443 static void dw_dp_hpd_init(struct dw_dp *dp) 444 { 445 if (dm_gpio_is_valid(&dp->hpd_gpio) || dp->force_hpd) { 446 regmap_update_bits(dp->regmap, DPTX_CCTL, FORCE_HPD, 447 FIELD_PREP(FORCE_HPD, 1)); 448 return; 449 } 450 451 /* Enable all HPD interrupts */ 452 regmap_update_bits(dp->regmap, DPTX_HPD_INTERRUPT_ENABLE, 453 HPD_UNPLUG_EN | HPD_PLUG_EN | HPD_IRQ_EN, 454 FIELD_PREP(HPD_UNPLUG_EN, 1) | 455 FIELD_PREP(HPD_PLUG_EN, 1) | 456 FIELD_PREP(HPD_IRQ_EN, 1)); 457 458 /* Enable all top-level interrupts */ 459 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, 460 HPD_EVENT_EN, FIELD_PREP(HPD_EVENT_EN, 1)); 461 } 462 463 static void dw_dp_aux_init(struct dw_dp *dp) 464 { 465 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, 466 FIELD_PREP(AUX_RESET, 1)); 467 udelay(10); 468 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, 469 FIELD_PREP(AUX_RESET, 0)); 470 471 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, 472 AUX_REPLY_EVENT_EN, 473 FIELD_PREP(AUX_REPLY_EVENT_EN, 1)); 474 } 475 476 static void dw_dp_init(struct dw_dp *dp) 477 { 478 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, 479 FIELD_PREP(CONTROLLER_RESET, 1)); 480 udelay(10); 481 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, 482 FIELD_PREP(CONTROLLER_RESET, 0)); 483 484 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, 485 FIELD_PREP(PHY_SOFT_RESET, 1)); 486 udelay(10); 487 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, 488 FIELD_PREP(PHY_SOFT_RESET, 0)); 489 490 regmap_update_bits(dp->regmap, DPTX_CCTL, DEFAULT_FAST_LINK_TRAIN_EN, 491 FIELD_PREP(DEFAULT_FAST_LINK_TRAIN_EN, 0)); 492 493 dw_dp_hpd_init(dp); 494 dw_dp_aux_init(dp); 495 } 496 497 static void dw_dp_phy_set_pattern(struct dw_dp *dp, u32 pattern) 498 { 499 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, TPS_SEL, 500 FIELD_PREP(TPS_SEL, pattern)); 501 } 502 503 static void dw_dp_phy_xmit_enable(struct dw_dp *dp, u32 lanes) 504 { 505 u32 xmit_enable; 506 507 switch (lanes) { 508 case 4: 509 case 2: 510 case 1: 511 xmit_enable = GENMASK(lanes - 1, 0); 512 break; 513 case 0: 514 default: 515 xmit_enable = 0; 516 break; 517 } 518 519 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, XMIT_ENABLE, 520 FIELD_PREP(XMIT_ENABLE, xmit_enable)); 521 } 522 523 static int dw_dp_link_power_up(struct dw_dp *dp) 524 { 525 struct dw_dp_link *link = &dp->link; 526 u8 value; 527 int ret; 528 529 if (link->revision < 0x11) 530 return 0; 531 532 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value); 533 if (ret < 0) 534 return ret; 535 536 value &= ~DP_SET_POWER_MASK; 537 value |= DP_SET_POWER_D0; 538 539 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value); 540 if (ret < 0) 541 return ret; 542 543 udelay(1000); 544 return 0; 545 } 546 547 static int dw_dp_link_probe(struct dw_dp *dp) 548 { 549 struct dw_dp_link *link = &dp->link; 550 u8 dpcd; 551 int ret; 552 553 ret = drm_dp_read_dpcd_caps(&dp->aux, link->dpcd); 554 if (ret < 0) 555 return ret; 556 557 ret = drm_dp_dpcd_readb(&dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, 558 &dpcd); 559 if (ret < 0) 560 return ret; 561 562 link->vsc_sdp_extension_for_colorimetry_supported = 563 !!(dpcd & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED); 564 565 link->revision = link->dpcd[DP_DPCD_REV]; 566 link->rate = min_t(u32, min(dp->max_link_rate, dp->phy.attrs.max_link_rate * 100), 567 drm_dp_max_link_rate(link->dpcd)); 568 link->lanes = min_t(u8, dp->phy.attrs.bus_width, 569 drm_dp_max_lane_count(link->dpcd)); 570 571 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(link->dpcd); 572 link->caps.tps3_supported = drm_dp_tps3_supported(link->dpcd); 573 link->caps.tps4_supported = drm_dp_tps4_supported(link->dpcd); 574 link->caps.channel_coding = drm_dp_channel_coding_supported(link->dpcd); 575 link->caps.ssc = !!(link->dpcd[DP_MAX_DOWNSPREAD] & 576 DP_MAX_DOWNSPREAD_0_5); 577 578 return 0; 579 } 580 581 static int dw_dp_link_train_update_vs_emph(struct dw_dp *dp) 582 { 583 struct dw_dp_link *link = &dp->link; 584 struct drm_dp_link_train_set *request = &link->train.request; 585 union phy_configure_opts phy_cfg; 586 unsigned int lanes = link->lanes, *vs, *pe; 587 u8 buf[4]; 588 int i, ret; 589 590 vs = request->voltage_swing; 591 pe = request->pre_emphasis; 592 593 for (i = 0; i < lanes; i++) { 594 phy_cfg.dp.voltage[i] = vs[i]; 595 phy_cfg.dp.pre[i] = pe[i]; 596 } 597 phy_cfg.dp.lanes = lanes; 598 phy_cfg.dp.link_rate = link->rate / 100; 599 phy_cfg.dp.set_lanes = false; 600 phy_cfg.dp.set_rate = false; 601 phy_cfg.dp.set_voltages = true; 602 ret = generic_phy_configure(&dp->phy, &phy_cfg); 603 if (ret) 604 return ret; 605 606 for (i = 0; i < lanes; i++) 607 buf[i] = (vs[i] << DP_TRAIN_VOLTAGE_SWING_SHIFT) | 608 (pe[i] << DP_TRAIN_PRE_EMPHASIS_SHIFT); 609 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, lanes); 610 if (ret < 0) 611 return ret; 612 613 return 0; 614 } 615 616 static int dw_dp_link_configure(struct dw_dp *dp) 617 { 618 struct dw_dp_link *link = &dp->link; 619 union phy_configure_opts phy_cfg; 620 u8 buf[2]; 621 int ret, phy_rate; 622 623 /* Move PHY to P3 */ 624 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 625 FIELD_PREP(PHY_POWERDOWN, 0x3)); 626 627 phy_cfg.dp.lanes = link->lanes; 628 phy_cfg.dp.link_rate = link->rate / 100; 629 phy_cfg.dp.ssc = link->caps.ssc; 630 phy_cfg.dp.set_lanes = true; 631 phy_cfg.dp.set_rate = true; 632 phy_cfg.dp.set_voltages = false; 633 ret = generic_phy_configure(&dp->phy, &phy_cfg); 634 if (ret) 635 return ret; 636 637 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, 638 FIELD_PREP(PHY_LANES, link->lanes / 2)); 639 640 switch (link->rate) { 641 case 810000: 642 phy_rate = DPTX_PHYRATE_HBR3; 643 break; 644 case 540000: 645 phy_rate = DPTX_PHYRATE_HBR2; 646 break; 647 case 270000: 648 phy_rate = DPTX_PHYRATE_HBR; 649 break; 650 case 162000: 651 default: 652 phy_rate = DPTX_PHYRATE_RBR; 653 break; 654 } 655 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_RATE, 656 FIELD_PREP(PHY_RATE, phy_rate)); 657 658 /* Move PHY to P0 */ 659 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 660 FIELD_PREP(PHY_POWERDOWN, 0x0)); 661 662 dw_dp_phy_xmit_enable(dp, link->lanes); 663 664 buf[0] = drm_dp_link_rate_to_bw_code(link->rate); 665 buf[1] = link->lanes; 666 667 if (link->caps.enhanced_framing) { 668 buf[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 669 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 670 FIELD_PREP(ENHANCE_FRAMING_EN, 1)); 671 } else { 672 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 673 FIELD_PREP(ENHANCE_FRAMING_EN, 0)); 674 } 675 676 ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, sizeof(buf)); 677 if (ret < 0) 678 return ret; 679 680 buf[0] = link->caps.ssc ? DP_SPREAD_AMP_0_5 : 0; 681 buf[1] = link->caps.channel_coding ? DP_SET_ANSI_8B10B : 0; 682 683 ret = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, 684 sizeof(buf)); 685 if (ret < 0) 686 return ret; 687 688 return 0; 689 } 690 691 static void dw_dp_link_train_init(struct drm_dp_link_train *train) 692 { 693 struct drm_dp_link_train_set *request = &train->request; 694 struct drm_dp_link_train_set *adjust = &train->adjust; 695 unsigned int i; 696 697 for (i = 0; i < 4; i++) { 698 request->voltage_swing[i] = 0; 699 adjust->voltage_swing[i] = 0; 700 701 request->pre_emphasis[i] = 0; 702 adjust->pre_emphasis[i] = 0; 703 } 704 705 train->clock_recovered = false; 706 train->channel_equalized = false; 707 } 708 709 static int dw_dp_link_train_set_pattern(struct dw_dp *dp, u32 pattern) 710 { 711 u8 buf = 0; 712 int ret; 713 714 if (pattern && pattern != DP_TRAINING_PATTERN_4) { 715 buf |= DP_LINK_SCRAMBLING_DISABLE; 716 717 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, 718 FIELD_PREP(SCRAMBLE_DIS, 1)); 719 } else { 720 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, 721 FIELD_PREP(SCRAMBLE_DIS, 0)); 722 } 723 724 switch (pattern) { 725 case DP_TRAINING_PATTERN_DISABLE: 726 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE); 727 break; 728 case DP_TRAINING_PATTERN_1: 729 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_1); 730 break; 731 case DP_TRAINING_PATTERN_2: 732 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_2); 733 break; 734 case DP_TRAINING_PATTERN_3: 735 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_3); 736 break; 737 case DP_TRAINING_PATTERN_4: 738 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_4); 739 break; 740 default: 741 return -EINVAL; 742 } 743 744 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 745 buf | pattern); 746 if (ret < 0) 747 return ret; 748 749 return 0; 750 } 751 752 static void dw_dp_link_get_adjustments(struct dw_dp_link *link, 753 u8 status[DP_LINK_STATUS_SIZE]) 754 { 755 struct drm_dp_link_train_set *adjust = &link->train.adjust; 756 unsigned int i; 757 758 for (i = 0; i < link->lanes; i++) { 759 adjust->voltage_swing[i] = 760 drm_dp_get_adjust_request_voltage(status, i) >> 761 DP_TRAIN_VOLTAGE_SWING_SHIFT; 762 763 adjust->pre_emphasis[i] = 764 drm_dp_get_adjust_request_pre_emphasis(status, i) >> 765 DP_TRAIN_PRE_EMPHASIS_SHIFT; 766 } 767 } 768 769 static void dw_dp_link_train_adjust(struct drm_dp_link_train *train) 770 { 771 struct drm_dp_link_train_set *request = &train->request; 772 struct drm_dp_link_train_set *adjust = &train->adjust; 773 unsigned int i; 774 775 for (i = 0; i < 4; i++) 776 if (request->voltage_swing[i] != adjust->voltage_swing[i]) 777 request->voltage_swing[i] = adjust->voltage_swing[i]; 778 779 for (i = 0; i < 4; i++) 780 if (request->pre_emphasis[i] != adjust->pre_emphasis[i]) 781 request->pre_emphasis[i] = adjust->pre_emphasis[i]; 782 } 783 784 static int dw_dp_link_clock_recovery(struct dw_dp *dp) 785 { 786 struct dw_dp_link *link = &dp->link; 787 u8 status[DP_LINK_STATUS_SIZE]; 788 unsigned int tries = 0; 789 int ret; 790 791 ret = dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_1); 792 if (ret) 793 return ret; 794 795 for (;;) { 796 ret = dw_dp_link_train_update_vs_emph(dp); 797 if (ret) 798 return ret; 799 800 drm_dp_link_train_clock_recovery_delay(link->dpcd); 801 802 ret = drm_dp_dpcd_read_link_status(&dp->aux, status); 803 if (ret < 0) { 804 dev_err(dp->dev, "failed to read link status: %d\n", 805 ret); 806 return ret; 807 } 808 809 if (drm_dp_clock_recovery_ok(status, link->lanes)) { 810 link->train.clock_recovered = true; 811 break; 812 } 813 814 dw_dp_link_get_adjustments(link, status); 815 816 if (link->train.request.voltage_swing[0] == 817 link->train.adjust.voltage_swing[0]) 818 tries++; 819 else 820 tries = 0; 821 822 if (tries == 5) 823 break; 824 825 dw_dp_link_train_adjust(&link->train); 826 } 827 828 return 0; 829 } 830 831 static int dw_dp_link_channel_equalization(struct dw_dp *dp) 832 { 833 struct dw_dp_link *link = &dp->link; 834 u8 status[DP_LINK_STATUS_SIZE], pattern; 835 unsigned int tries; 836 int ret; 837 838 if (link->caps.tps4_supported) 839 pattern = DP_TRAINING_PATTERN_4; 840 else if (link->caps.tps3_supported) 841 pattern = DP_TRAINING_PATTERN_3; 842 else 843 pattern = DP_TRAINING_PATTERN_2; 844 ret = dw_dp_link_train_set_pattern(dp, pattern); 845 if (ret) 846 return ret; 847 848 for (tries = 1; tries < 5; tries++) { 849 ret = dw_dp_link_train_update_vs_emph(dp); 850 if (ret) 851 return ret; 852 853 drm_dp_link_train_channel_eq_delay(link->dpcd); 854 855 ret = drm_dp_dpcd_read_link_status(&dp->aux, status); 856 if (ret < 0) 857 return ret; 858 859 if (!drm_dp_clock_recovery_ok(status, link->lanes)) { 860 dev_err(dp->dev, 861 "clock recovery lost while eq\n"); 862 link->train.clock_recovered = false; 863 break; 864 } 865 866 if (drm_dp_channel_eq_ok(status, link->lanes)) { 867 link->train.channel_equalized = true; 868 break; 869 } 870 871 dw_dp_link_get_adjustments(link, status); 872 dw_dp_link_train_adjust(&link->train); 873 } 874 875 return 0; 876 } 877 878 static int dw_dp_link_downgrade(struct dw_dp *dp) 879 { 880 struct dw_dp_link *link = &dp->link; 881 struct dw_dp_video *video = &dp->video; 882 883 switch (link->rate) { 884 case 162000: 885 return -EINVAL; 886 case 270000: 887 link->rate = 162000; 888 break; 889 case 540000: 890 link->rate = 270000; 891 break; 892 case 810000: 893 link->rate = 540000; 894 break; 895 } 896 897 if (!dw_dp_bandwidth_ok(dp, &video->mode, video->bpp, link->lanes, 898 link->rate)) 899 return -E2BIG; 900 901 return 0; 902 } 903 904 static int dw_dp_link_train(struct dw_dp *dp) 905 { 906 struct dw_dp_link *link = &dp->link; 907 int ret; 908 909 retry: 910 dw_dp_link_train_init(&link->train); 911 912 printf("training link: %u lane%s at %u MHz\n", 913 link->lanes, (link->lanes > 1) ? "s" : "", link->rate / 100); 914 915 ret = dw_dp_link_configure(dp); 916 if (ret < 0) { 917 dev_err(dp->dev, "failed to configure DP link: %d\n", ret); 918 return ret; 919 } 920 921 ret = dw_dp_link_clock_recovery(dp); 922 if (ret < 0) { 923 dev_err(dp->dev, "clock recovery failed: %d\n", ret); 924 goto out; 925 } 926 927 if (!link->train.clock_recovered) { 928 dev_err(dp->dev, "clock recovery failed, downgrading link\n"); 929 930 ret = dw_dp_link_downgrade(dp); 931 if (ret < 0) 932 goto out; 933 else 934 goto retry; 935 } 936 937 printf("clock recovery succeeded\n"); 938 939 ret = dw_dp_link_channel_equalization(dp); 940 if (ret < 0) { 941 dev_err(dp->dev, "channel equalization failed: %d\n", ret); 942 goto out; 943 } 944 945 if (!link->train.channel_equalized) { 946 dev_err(dp->dev, 947 "channel equalization failed, downgrading link\n"); 948 949 ret = dw_dp_link_downgrade(dp); 950 if (ret < 0) 951 goto out; 952 else 953 goto retry; 954 } 955 956 printf("channel equalization succeeded\n"); 957 958 out: 959 dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE); 960 return ret; 961 } 962 963 static int dw_dp_link_enable(struct dw_dp *dp) 964 { 965 int ret; 966 967 ret = dw_dp_link_power_up(dp); 968 if (ret < 0) 969 return ret; 970 971 ret = dw_dp_link_train(dp); 972 if (ret < 0) { 973 dev_err(dp->dev, "link training failed: %d\n", ret); 974 return ret; 975 } 976 977 return 0; 978 } 979 980 static int dw_dp_set_phy_default_config(struct dw_dp *dp) 981 { 982 struct dw_dp_link *link = &dp->link; 983 union phy_configure_opts phy_cfg; 984 int ret, i, phy_rate; 985 986 link->vsc_sdp_extension_for_colorimetry_supported = false; 987 link->rate = 270000; 988 link->lanes = dp->phy.attrs.bus_width; 989 990 link->caps.enhanced_framing = true; 991 link->caps.channel_coding = true; 992 link->caps.ssc = true; 993 994 /* Move PHY to P3 */ 995 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 996 FIELD_PREP(PHY_POWERDOWN, 0x3)); 997 998 for (i = 0; i < link->lanes; i++) { 999 phy_cfg.dp.voltage[i] = 3; 1000 phy_cfg.dp.pre[i] = 0; 1001 } 1002 phy_cfg.dp.lanes = link->lanes; 1003 phy_cfg.dp.link_rate = link->rate / 100; 1004 phy_cfg.dp.ssc = link->caps.ssc; 1005 phy_cfg.dp.set_lanes = true; 1006 phy_cfg.dp.set_rate = true; 1007 phy_cfg.dp.set_voltages = true; 1008 ret = generic_phy_configure(&dp->phy, &phy_cfg); 1009 if (ret) 1010 return ret; 1011 1012 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, 1013 FIELD_PREP(PHY_LANES, link->lanes / 2)); 1014 1015 switch (link->rate) { 1016 case 810000: 1017 phy_rate = DPTX_PHYRATE_HBR3; 1018 break; 1019 case 540000: 1020 phy_rate = DPTX_PHYRATE_HBR2; 1021 break; 1022 case 270000: 1023 phy_rate = DPTX_PHYRATE_HBR; 1024 break; 1025 case 162000: 1026 default: 1027 phy_rate = DPTX_PHYRATE_RBR; 1028 break; 1029 } 1030 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_RATE, 1031 FIELD_PREP(PHY_RATE, phy_rate)); 1032 1033 /* Move PHY to P0 */ 1034 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 1035 FIELD_PREP(PHY_POWERDOWN, 0x0)); 1036 1037 dw_dp_phy_xmit_enable(dp, link->lanes); 1038 1039 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 1040 FIELD_PREP(ENHANCE_FRAMING_EN, 1)); 1041 1042 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE); 1043 return 0; 1044 } 1045 1046 static int dw_dp_send_sdp(struct dw_dp *dp, struct dw_dp_sdp *sdp) 1047 { 1048 const u8 *payload = sdp->db; 1049 u32 reg; 1050 int i, nr = 0; 1051 1052 reg = DPTX_SDP_REGISTER_BANK + nr * 9 * 4; 1053 1054 /* SDP header */ 1055 regmap_write(dp->regmap, reg, get_unaligned_le32(&sdp->header)); 1056 1057 /* SDP data payload */ 1058 for (i = 1; i < 9; i++, payload += 4) 1059 regmap_write(dp->regmap, reg + i * 4, 1060 FIELD_PREP(SDP_REGS, get_unaligned_le32(payload))); 1061 1062 if (sdp->flags & DPTX_SDP_VERTICAL_INTERVAL) 1063 regmap_update_bits(dp->regmap, DPTX_SDP_VERTICAL_CTRL, 1064 EN_VERTICAL_SDP << nr, 1065 EN_VERTICAL_SDP << nr); 1066 1067 if (sdp->flags & DPTX_SDP_HORIZONTAL_INTERVAL) 1068 regmap_update_bits(dp->regmap, DPTX_SDP_HORIZONTAL_CTRL, 1069 EN_HORIZONTAL_SDP << nr, 1070 EN_HORIZONTAL_SDP << nr); 1071 1072 return 0; 1073 } 1074 1075 static void dw_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, 1076 struct dw_dp_sdp *sdp) 1077 { 1078 sdp->header.HB0 = 0; 1079 sdp->header.HB1 = DP_SDP_VSC; 1080 sdp->header.HB2 = vsc->revision; 1081 sdp->header.HB3 = vsc->length; 1082 1083 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; 1084 sdp->db[16] |= vsc->colorimetry & 0xf; 1085 1086 switch (vsc->bpc) { 1087 case 8: 1088 sdp->db[17] = 0x1; 1089 break; 1090 case 10: 1091 sdp->db[17] = 0x2; 1092 break; 1093 case 12: 1094 sdp->db[17] = 0x3; 1095 break; 1096 case 16: 1097 sdp->db[17] = 0x4; 1098 break; 1099 case 6: 1100 default: 1101 break; 1102 } 1103 1104 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) 1105 sdp->db[17] |= 0x80; 1106 1107 sdp->db[18] = vsc->content_type & 0x7; 1108 1109 sdp->flags |= DPTX_SDP_VERTICAL_INTERVAL; 1110 } 1111 1112 static int dw_dp_send_vsc_sdp(struct dw_dp *dp) 1113 { 1114 struct dw_dp_video *video = &dp->video; 1115 struct drm_dp_vsc_sdp vsc = {}; 1116 struct dw_dp_sdp sdp = {}; 1117 1118 vsc.revision = 0x5; 1119 vsc.length = 0x13; 1120 1121 switch (video->color_format) { 1122 case DRM_COLOR_FORMAT_YCRCB444: 1123 vsc.pixelformat = DP_PIXELFORMAT_YUV444; 1124 break; 1125 case DRM_COLOR_FORMAT_YCRCB420: 1126 vsc.pixelformat = DP_PIXELFORMAT_YUV420; 1127 break; 1128 case DRM_COLOR_FORMAT_YCRCB422: 1129 vsc.pixelformat = DP_PIXELFORMAT_YUV422; 1130 break; 1131 case DRM_COLOR_FORMAT_RGB444: 1132 default: 1133 vsc.pixelformat = DP_PIXELFORMAT_RGB; 1134 break; 1135 } 1136 1137 if (video->color_format == DRM_COLOR_FORMAT_RGB444) 1138 vsc.colorimetry = DP_COLORIMETRY_DEFAULT; 1139 else 1140 vsc.colorimetry = DP_COLORIMETRY_BT709_YCC; 1141 1142 vsc.bpc = video->bpc; 1143 vsc.dynamic_range = DP_DYNAMIC_RANGE_CTA; 1144 vsc.content_type = DP_CONTENT_TYPE_NOT_DEFINED; 1145 1146 dw_dp_vsc_sdp_pack(&vsc, &sdp); 1147 1148 return dw_dp_send_sdp(dp, &sdp); 1149 } 1150 1151 static int dw_dp_video_set_pixel_mode(struct dw_dp *dp, u8 pixel_mode) 1152 { 1153 switch (pixel_mode) { 1154 case DPTX_MP_SINGLE_PIXEL: 1155 case DPTX_MP_DUAL_PIXEL: 1156 case DPTX_MP_QUAD_PIXEL: 1157 break; 1158 default: 1159 return -EINVAL; 1160 } 1161 1162 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, PIXEL_MODE_SELECT, 1163 FIELD_PREP(PIXEL_MODE_SELECT, pixel_mode)); 1164 1165 return 0; 1166 } 1167 1168 static int dw_dp_video_set_msa(struct dw_dp *dp, u8 color_format, u8 bpc, 1169 u16 vstart, u16 hstart) 1170 { 1171 struct dw_dp_link *link = &dp->link; 1172 u16 misc = 0; 1173 1174 if (link->vsc_sdp_extension_for_colorimetry_supported) 1175 misc |= DP_MSA_MISC_COLOR_VSC_SDP; 1176 1177 switch (color_format) { 1178 case DRM_COLOR_FORMAT_RGB444: 1179 misc |= DP_MSA_MISC_COLOR_RGB; 1180 break; 1181 case DRM_COLOR_FORMAT_YCRCB444: 1182 misc |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 1183 break; 1184 case DRM_COLOR_FORMAT_YCRCB422: 1185 misc |= DP_MSA_MISC_COLOR_YCBCR_422_BT709; 1186 break; 1187 case DRM_COLOR_FORMAT_YCRCB420: 1188 break; 1189 default: 1190 return -EINVAL; 1191 } 1192 1193 switch (bpc) { 1194 case 6: 1195 misc |= DP_MSA_MISC_6_BPC; 1196 break; 1197 case 8: 1198 misc |= DP_MSA_MISC_8_BPC; 1199 break; 1200 case 10: 1201 misc |= DP_MSA_MISC_10_BPC; 1202 break; 1203 case 12: 1204 misc |= DP_MSA_MISC_12_BPC; 1205 break; 1206 case 16: 1207 misc |= DP_MSA_MISC_16_BPC; 1208 break; 1209 default: 1210 return -EINVAL; 1211 } 1212 1213 regmap_write(dp->regmap, DPTX_VIDEO_MSA1, 1214 FIELD_PREP(VSTART, vstart) | FIELD_PREP(HSTART, hstart)); 1215 regmap_write(dp->regmap, DPTX_VIDEO_MSA2, FIELD_PREP(MISC0, misc)); 1216 regmap_write(dp->regmap, DPTX_VIDEO_MSA3, FIELD_PREP(MISC1, misc >> 8)); 1217 1218 return 0; 1219 } 1220 1221 static int dw_dp_video_enable(struct dw_dp *dp) 1222 { 1223 struct dw_dp_video *video = &dp->video; 1224 struct dw_dp_link *link = &dp->link; 1225 struct drm_display_mode *mode = &video->mode; 1226 u8 color_format = video->color_format; 1227 u8 bpc = video->bpc; 1228 u8 pixel_mode = video->pixel_mode; 1229 u8 bpp = video->bpp, init_threshold, vic; 1230 u32 hactive, hblank, h_sync_width, h_front_porch; 1231 u32 vactive, vblank, v_sync_width, v_front_porch; 1232 u32 vstart = mode->vtotal - mode->vsync_start; 1233 u32 hstart = mode->htotal - mode->hsync_start; 1234 u32 peak_stream_bandwidth, link_bandwidth; 1235 u32 average_bytes_per_tu, average_bytes_per_tu_frac; 1236 u32 ts, hblank_interval; 1237 u32 value; 1238 int ret; 1239 1240 ret = dw_dp_video_set_pixel_mode(dp, pixel_mode); 1241 if (ret) 1242 return ret; 1243 1244 ret = dw_dp_video_set_msa(dp, color_format, bpc, vstart, hstart); 1245 if (ret) 1246 return ret; 1247 1248 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_MAPPING, 1249 FIELD_PREP(VIDEO_MAPPING, video->video_mapping)); 1250 1251 /* Configure DPTX_VINPUT_POLARITY_CTRL register */ 1252 value = 0; 1253 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1254 value |= FIELD_PREP(HSYNC_IN_POLARITY, 1); 1255 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1256 value |= FIELD_PREP(VSYNC_IN_POLARITY, 1); 1257 regmap_write(dp->regmap, DPTX_VINPUT_POLARITY_CTRL, value); 1258 1259 /* Configure DPTX_VIDEO_CONFIG1 register */ 1260 hactive = mode->hdisplay; 1261 hblank = mode->htotal - mode->hdisplay; 1262 value = FIELD_PREP(HACTIVE, hactive) | FIELD_PREP(HBLANK, hblank); 1263 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1264 value |= FIELD_PREP(I_P, 1); 1265 vic = drm_match_cea_mode(mode); 1266 if (vic == 5 || vic == 6 || vic == 7 || 1267 vic == 10 || vic == 11 || vic == 20 || 1268 vic == 21 || vic == 22 || vic == 39 || 1269 vic == 25 || vic == 26 || vic == 40 || 1270 vic == 44 || vic == 45 || vic == 46 || 1271 vic == 50 || vic == 51 || vic == 54 || 1272 vic == 55 || vic == 58 || vic == 59) 1273 value |= R_V_BLANK_IN_OSC; 1274 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG1, value); 1275 1276 /* Configure DPTX_VIDEO_CONFIG2 register */ 1277 vblank = mode->vtotal - mode->vdisplay; 1278 vactive = mode->vdisplay; 1279 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG2, 1280 FIELD_PREP(VBLANK, vblank) | FIELD_PREP(VACTIVE, vactive)); 1281 1282 /* Configure DPTX_VIDEO_CONFIG3 register */ 1283 h_sync_width = mode->hsync_end - mode->hsync_start; 1284 h_front_porch = mode->hsync_start - mode->hdisplay; 1285 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG3, 1286 FIELD_PREP(H_SYNC_WIDTH, h_sync_width) | 1287 FIELD_PREP(H_FRONT_PORCH, h_front_porch)); 1288 1289 /* Configure DPTX_VIDEO_CONFIG4 register */ 1290 v_sync_width = mode->vsync_end - mode->vsync_start; 1291 v_front_porch = mode->vsync_start - mode->vdisplay; 1292 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG4, 1293 FIELD_PREP(V_SYNC_WIDTH, v_sync_width) | 1294 FIELD_PREP(V_FRONT_PORCH, v_front_porch)); 1295 1296 /* Configure DPTX_VIDEO_CONFIG5 register */ 1297 peak_stream_bandwidth = mode->clock * bpp / 8; 1298 link_bandwidth = (link->rate / 1000) * link->lanes; 1299 ts = peak_stream_bandwidth * 64 / link_bandwidth; 1300 average_bytes_per_tu = ts / 1000; 1301 average_bytes_per_tu_frac = ts / 100 - average_bytes_per_tu * 10; 1302 if (pixel_mode == DPTX_MP_SINGLE_PIXEL) { 1303 if (average_bytes_per_tu < 6) 1304 init_threshold = 32; 1305 else if (hblank <= 80 && 1306 color_format != DRM_COLOR_FORMAT_YCRCB420) 1307 init_threshold = 12; 1308 else if (hblank <= 40 && 1309 color_format == DRM_COLOR_FORMAT_YCRCB420) 1310 init_threshold = 3; 1311 else 1312 init_threshold = 16; 1313 } else { 1314 u32 t1 = 0, t2 = 0, t3 = 0; 1315 1316 switch (bpc) { 1317 case 6: 1318 t1 = (4 * 1000 / 9) * link->lanes; 1319 break; 1320 case 8: 1321 if (color_format == DRM_COLOR_FORMAT_YCRCB422) { 1322 t1 = (1000 / 2) * link->lanes; 1323 } else { 1324 if (pixel_mode == DPTX_MP_DUAL_PIXEL) 1325 t1 = (1000 / 3) * link->lanes; 1326 else 1327 t1 = (3000 / 16) * link->lanes; 1328 } 1329 break; 1330 case 10: 1331 if (color_format == DRM_COLOR_FORMAT_YCRCB422) 1332 t1 = (2000 / 5) * link->lanes; 1333 else 1334 t1 = (4000 / 15) * link->lanes; 1335 break; 1336 case 12: 1337 if (color_format == DRM_COLOR_FORMAT_YCRCB422) { 1338 if (pixel_mode == DPTX_MP_DUAL_PIXEL) 1339 t1 = (1000 / 6) * link->lanes; 1340 else 1341 t1 = (1000 / 3) * link->lanes; 1342 } else { 1343 t1 = (2000 / 9) * link->lanes; 1344 } 1345 break; 1346 case 16: 1347 if (color_format != DRM_COLOR_FORMAT_YCRCB422 && 1348 pixel_mode == DPTX_MP_DUAL_PIXEL) 1349 t1 = (1000 / 6) * link->lanes; 1350 else 1351 t1 = (1000 / 4) * link->lanes; 1352 break; 1353 default: 1354 return -EINVAL; 1355 } 1356 1357 if (color_format == DRM_COLOR_FORMAT_YCRCB420) 1358 t2 = (link->rate / 4) * 1000 / (mode->clock / 2); 1359 else 1360 t2 = (link->rate / 4) * 1000 / mode->clock; 1361 1362 if (average_bytes_per_tu_frac) 1363 t3 = average_bytes_per_tu + 1; 1364 else 1365 t3 = average_bytes_per_tu; 1366 init_threshold = t1 * t2 * t3 / (1000 * 1000); 1367 if (init_threshold <= 16 || average_bytes_per_tu < 10) 1368 init_threshold = 40; 1369 } 1370 1371 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG5, 1372 FIELD_PREP(INIT_THRESHOLD_HI, init_threshold >> 6) | 1373 FIELD_PREP(AVERAGE_BYTES_PER_TU_FRAC, 1374 average_bytes_per_tu_frac) | 1375 FIELD_PREP(INIT_THRESHOLD, init_threshold) | 1376 FIELD_PREP(AVERAGE_BYTES_PER_TU, average_bytes_per_tu)); 1377 1378 /* Configure DPTX_VIDEO_HBLANK_INTERVAL register */ 1379 hblank_interval = hblank * (link->rate / 4) / mode->clock; 1380 regmap_write(dp->regmap, DPTX_VIDEO_HBLANK_INTERVAL, 1381 FIELD_PREP(HBLANK_INTERVAL_EN, 1) | 1382 FIELD_PREP(HBLANK_INTERVAL, hblank_interval)); 1383 1384 /* Video stream enable */ 1385 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_STREAM_ENABLE, 1386 FIELD_PREP(VIDEO_STREAM_ENABLE, 1)); 1387 1388 if (link->vsc_sdp_extension_for_colorimetry_supported) 1389 dw_dp_send_vsc_sdp(dp); 1390 1391 return 0; 1392 } 1393 1394 static bool dw_dp_detect(struct dw_dp *dp) 1395 { 1396 u32 value; 1397 1398 if (dm_gpio_is_valid(&dp->hpd_gpio)) 1399 return dm_gpio_get_value(&dp->hpd_gpio); 1400 1401 regmap_read(dp->regmap, DPTX_HPD_STATUS, &value); 1402 if (FIELD_GET(HPD_STATE, value) == SOURCE_STATE_PLUG) { 1403 regmap_write(dp->regmap, DPTX_HPD_STATUS, HPD_HOT_PLUG); 1404 return true; 1405 } 1406 1407 return false; 1408 } 1409 1410 static int dw_dp_connector_init(struct rockchip_connector *conn, struct display_state *state) 1411 { 1412 struct connector_state *conn_state = &state->conn_state; 1413 struct dw_dp *dp = dev_get_priv(conn->dev); 1414 int ret; 1415 1416 conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_DP1 : VOP_OUTPUT_IF_DP0; 1417 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1418 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 1419 1420 clk_set_defaults(dp->dev); 1421 1422 reset_assert(&dp->reset); 1423 udelay(20); 1424 reset_deassert(&dp->reset); 1425 1426 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, 1427 dp->id); 1428 dw_dp_init(dp); 1429 ret = generic_phy_power_on(&dp->phy); 1430 1431 return ret; 1432 } 1433 1434 static int dw_dp_connector_get_edid(struct rockchip_connector *conn, struct display_state *state) 1435 { 1436 int ret; 1437 struct connector_state *conn_state = &state->conn_state; 1438 struct dw_dp *dp = dev_get_priv(conn->dev); 1439 1440 ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); 1441 1442 return ret; 1443 } 1444 1445 static int dw_dp_get_output_fmts_index(u32 bus_format) 1446 { 1447 int i; 1448 1449 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 1450 const struct dw_dp_output_format *fmt = &possible_output_fmts[i]; 1451 1452 if (fmt->bus_format == bus_format) 1453 break; 1454 } 1455 1456 if (i == ARRAY_SIZE(possible_output_fmts)) 1457 return 1; 1458 1459 return i; 1460 } 1461 1462 static int dw_dp_connector_prepare(struct rockchip_connector *conn, struct display_state *state) 1463 { 1464 struct connector_state *conn_state = &state->conn_state; 1465 struct dw_dp *dp = dev_get_priv(conn->dev); 1466 struct dw_dp_video *video = &dp->video; 1467 int bus_fmt; 1468 1469 bus_fmt = dw_dp_get_output_fmts_index(conn_state->bus_format); 1470 video->video_mapping = possible_output_fmts[bus_fmt].video_mapping; 1471 video->color_format = possible_output_fmts[bus_fmt].color_format; 1472 video->bus_format = possible_output_fmts[bus_fmt].bus_format; 1473 video->bpc = possible_output_fmts[bus_fmt].bpc; 1474 video->bpp = possible_output_fmts[bus_fmt].bpp; 1475 1476 return 0; 1477 } 1478 1479 static int dw_dp_connector_enable(struct rockchip_connector *conn, struct display_state *state) 1480 { 1481 struct connector_state *conn_state = &state->conn_state; 1482 struct drm_display_mode *mode = &conn_state->mode; 1483 struct dw_dp *dp = dev_get_priv(conn->dev); 1484 struct dw_dp_video *video = &dp->video; 1485 int ret; 1486 1487 memcpy(&video->mode, mode, sizeof(video->mode)); 1488 video->pixel_mode = DPTX_MP_QUAD_PIXEL; 1489 1490 if (dp->force_output) { 1491 ret = dw_dp_set_phy_default_config(dp); 1492 if (ret < 0) 1493 printf("failed to set phy_default config: %d\n", ret); 1494 } else { 1495 ret = dw_dp_link_enable(dp); 1496 if (ret < 0) { 1497 printf("failed to enable link: %d\n", ret); 1498 return ret; 1499 } 1500 } 1501 1502 ret = dw_dp_video_enable(dp); 1503 if (ret < 0) { 1504 printf("failed to enable video: %d\n", ret); 1505 return ret; 1506 } 1507 1508 return 0; 1509 } 1510 1511 static int dw_dp_connector_disable(struct rockchip_connector *conn, struct display_state *state) 1512 { 1513 /* TODO */ 1514 1515 return 0; 1516 } 1517 1518 static int dw_dp_connector_detect(struct rockchip_connector *conn, struct display_state *state) 1519 { 1520 struct dw_dp *dp = dev_get_priv(conn->dev); 1521 int status, tries, ret; 1522 1523 for (tries = 0; tries < 200; tries++) { 1524 status = dw_dp_detect(dp); 1525 if (status) 1526 break; 1527 mdelay(2); 1528 } 1529 1530 if (state->force_output && !status) 1531 dp->force_output = true; 1532 1533 if (!status && !dp->force_output) 1534 generic_phy_power_off(&dp->phy); 1535 1536 if (status && !dp->force_output) { 1537 ret = dw_dp_link_probe(dp); 1538 if (ret) 1539 printf("failed to probe DP link: %d\n", ret); 1540 } 1541 1542 return status; 1543 } 1544 1545 static int dw_dp_mode_valid(struct dw_dp *dp, struct hdmi_edid_data *edid_data) 1546 { 1547 struct dw_dp_link *link = &dp->link; 1548 struct drm_display_info *di = &edid_data->display_info; 1549 u32 min_bpp; 1550 int i; 1551 1552 if (di->color_formats & DRM_COLOR_FORMAT_YCRCB420 && 1553 link->vsc_sdp_extension_for_colorimetry_supported) 1554 min_bpp = 12; 1555 else if (di->color_formats & DRM_COLOR_FORMAT_YCRCB422) 1556 min_bpp = 16; 1557 else if (di->color_formats & DRM_COLOR_FORMAT_RGB444) 1558 min_bpp = 18; 1559 else 1560 min_bpp = 24; 1561 1562 for (i = 0; i < edid_data->modes; i++) { 1563 if (!dw_dp_bandwidth_ok(dp, &edid_data->mode_buf[i], min_bpp, link->lanes, 1564 link->rate)) 1565 edid_data->mode_buf[i].invalid = true; 1566 } 1567 1568 return 0; 1569 } 1570 1571 static u32 dw_dp_get_output_bus_fmts(struct dw_dp *dp, struct hdmi_edid_data *edid_data) 1572 { 1573 struct dw_dp_link *link = &dp->link; 1574 unsigned int i; 1575 1576 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 1577 const struct dw_dp_output_format *fmt = &possible_output_fmts[i]; 1578 1579 if (fmt->bpc > edid_data->display_info.bpc) 1580 continue; 1581 1582 if (!(edid_data->display_info.color_formats & fmt->color_format)) 1583 continue; 1584 1585 if (fmt->color_format == DRM_COLOR_FORMAT_YCRCB420 && 1586 !link->vsc_sdp_extension_for_colorimetry_supported) 1587 continue; 1588 1589 if (drm_mode_is_420(&edid_data->display_info, edid_data->preferred_mode) && 1590 fmt->color_format != DRM_COLOR_FORMAT_YCRCB420) 1591 continue; 1592 1593 if (!dw_dp_bandwidth_ok(dp, edid_data->preferred_mode, fmt->bpp, link->lanes, 1594 link->rate)) 1595 continue; 1596 1597 break; 1598 } 1599 1600 if (i == ARRAY_SIZE(possible_output_fmts)) 1601 return 1; 1602 1603 return i; 1604 } 1605 1606 static int dw_dp_connector_get_timing(struct rockchip_connector *conn, struct display_state *state) 1607 { 1608 int ret, i; 1609 struct connector_state *conn_state = &state->conn_state; 1610 struct dw_dp *dp = dev_get_priv(conn->dev); 1611 struct drm_display_mode *mode = &conn_state->mode; 1612 struct hdmi_edid_data edid_data; 1613 struct drm_display_mode *mode_buf; 1614 struct vop_rect rect; 1615 u32 bus_fmt; 1616 1617 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 1618 if (!mode_buf) 1619 return -ENOMEM; 1620 1621 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 1622 memset(&edid_data, 0, sizeof(struct hdmi_edid_data)); 1623 edid_data.mode_buf = mode_buf; 1624 1625 if (!dp->force_output) { 1626 ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); 1627 if (!ret) 1628 ret = drm_add_edid_modes(&edid_data, conn_state->edid); 1629 1630 if (ret < 0) { 1631 printf("failed to get edid\n"); 1632 goto err; 1633 } 1634 1635 drm_rk_filter_whitelist(&edid_data); 1636 if (state->conn_state.secondary) { 1637 rect.width = state->crtc_state.max_output.width / 2; 1638 rect.height = state->crtc_state.max_output.height / 2; 1639 } else { 1640 rect.width = state->crtc_state.max_output.width; 1641 rect.height = state->crtc_state.max_output.height; 1642 } 1643 1644 drm_mode_max_resolution_filter(&edid_data, &rect); 1645 dw_dp_mode_valid(dp, &edid_data); 1646 1647 if (!drm_mode_prune_invalid(&edid_data)) { 1648 printf("can't find valid hdmi mode\n"); 1649 ret = -EINVAL; 1650 goto err; 1651 } 1652 1653 for (i = 0; i < edid_data.modes; i++) 1654 edid_data.mode_buf[i].vrefresh = 1655 drm_mode_vrefresh(&edid_data.mode_buf[i]); 1656 1657 drm_mode_sort(&edid_data); 1658 memcpy(mode, edid_data.preferred_mode, sizeof(struct drm_display_mode)); 1659 } 1660 1661 if (state->force_output) 1662 bus_fmt = dw_dp_get_output_fmts_index(state->force_bus_format); 1663 else 1664 bus_fmt = dw_dp_get_output_bus_fmts(dp, &edid_data); 1665 1666 conn_state->bus_format = possible_output_fmts[bus_fmt].bus_format; 1667 1668 switch (possible_output_fmts[bus_fmt].color_format) { 1669 case DRM_COLOR_FORMAT_YCRCB420: 1670 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420; 1671 break; 1672 case DRM_COLOR_FORMAT_YCRCB422: 1673 conn_state->output_mode = ROCKCHIP_OUT_MODE_S888_DUMMY; 1674 break; 1675 case DRM_COLOR_FORMAT_RGB444: 1676 case DRM_COLOR_FORMAT_YCRCB444: 1677 default: 1678 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1679 break; 1680 } 1681 1682 err: 1683 free(mode_buf); 1684 1685 return 0; 1686 } 1687 1688 static const struct rockchip_connector_funcs dw_dp_connector_funcs = { 1689 .init = dw_dp_connector_init, 1690 .get_edid = dw_dp_connector_get_edid, 1691 .prepare = dw_dp_connector_prepare, 1692 .enable = dw_dp_connector_enable, 1693 .disable = dw_dp_connector_disable, 1694 .detect = dw_dp_connector_detect, 1695 .get_timing = dw_dp_connector_get_timing, 1696 }; 1697 1698 static int dw_dp_ddc_init(struct dw_dp *dp) 1699 { 1700 dp->aux.name = "dw-dp"; 1701 dp->aux.dev = dp->dev; 1702 dp->aux.transfer = dw_dp_aux_transfer; 1703 dp->aux.ddc.ddc_xfer = drm_dp_i2c_xfer; 1704 1705 return 0; 1706 } 1707 1708 static u32 dw_dp_parse_link_frequencies(struct dw_dp *dp) 1709 { 1710 struct udevice *dev = dp->dev; 1711 const struct device_node *endpoint; 1712 u64 frequency = 0; 1713 1714 endpoint = rockchip_of_graph_get_endpoint_by_regs(dev->node, 1, 0); 1715 if (!endpoint) 1716 return 0; 1717 1718 if (of_property_read_u64(endpoint, "link-frequencies", &frequency) < 0) 1719 return 0; 1720 1721 if (!frequency) 1722 return 0; 1723 1724 do_div(frequency, 10 * 1000); /* symbol rate kbytes */ 1725 1726 switch (frequency) { 1727 case 162000: 1728 case 270000: 1729 case 540000: 1730 case 810000: 1731 break; 1732 default: 1733 dev_err(dev, "invalid link frequency value: %llu\n", frequency); 1734 return 0; 1735 } 1736 1737 return frequency; 1738 } 1739 1740 static int dw_dp_parse_dt(struct dw_dp *dp) 1741 { 1742 dp->force_hpd = dev_read_bool(dp->dev, "force-hpd"); 1743 1744 dp->max_link_rate = dw_dp_parse_link_frequencies(dp); 1745 if (!dp->max_link_rate) 1746 dp->max_link_rate = 810000; 1747 1748 return 0; 1749 } 1750 1751 static int dw_dp_probe(struct udevice *dev) 1752 { 1753 struct dw_dp *dp = dev_get_priv(dev); 1754 int ret; 1755 1756 ret = regmap_init_mem(dev, &dp->regmap); 1757 if (ret) 1758 return ret; 1759 1760 dp->id = of_alias_get_id(ofnode_to_np(dev->node), "dp"); 1761 if (dp->id < 0) 1762 dp->id = 0; 1763 1764 ret = reset_get_by_index(dev, 0, &dp->reset); 1765 if (ret) { 1766 dev_err(dev, "failed to get reset control: %d\n", ret); 1767 return ret; 1768 } 1769 1770 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 1771 GPIOD_IS_IN); 1772 if (ret && ret != -ENOENT) { 1773 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 1774 return ret; 1775 } 1776 1777 generic_phy_get_by_index(dev, 0, &dp->phy); 1778 1779 dp->dev = dev; 1780 1781 ret = dw_dp_parse_dt(dp); 1782 if (ret) { 1783 dev_err(dev, "failed to parse DT\n"); 1784 return ret; 1785 } 1786 1787 dw_dp_ddc_init(dp); 1788 1789 rockchip_connector_bind(&dp->connector, dev, dp->id, &dw_dp_connector_funcs, NULL, 1790 DRM_MODE_CONNECTOR_DisplayPort); 1791 1792 return 0; 1793 } 1794 1795 static const struct udevice_id dw_dp_ids[] = { 1796 { 1797 .compatible = "rockchip,rk3588-dp", 1798 }, 1799 {} 1800 }; 1801 1802 U_BOOT_DRIVER(dw_dp) = { 1803 .name = "dw_dp", 1804 .id = UCLASS_DISPLAY, 1805 .of_match = dw_dp_ids, 1806 .probe = dw_dp_probe, 1807 .priv_auto_alloc_size = sizeof(struct dw_dp), 1808 }; 1809 1810