1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Rockchip USBDP Combo PHY with Samsung IP block driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd 6 */ 7 8 #include <config.h> 9 #include <common.h> 10 #include <errno.h> 11 #include <malloc.h> 12 #include <asm/unaligned.h> 13 #include <asm/io.h> 14 #include <clk.h> 15 #include <dm/device.h> 16 #include <dm/of_access.h> 17 #include <dm/read.h> 18 #include <generic-phy.h> 19 #include <linux/bitfield.h> 20 #include <linux/hdmi.h> 21 #include <linux/media-bus-format.h> 22 #include <linux/list.h> 23 #include <asm/gpio.h> 24 #include <generic-phy.h> 25 #include <regmap.h> 26 #include <reset.h> 27 #include <drm/drm_dp_helper.h> 28 29 #include "rockchip_display.h" 30 #include "rockchip_crtc.h" 31 #include "rockchip_connector.h" 32 33 #define DPTX_VERSION_NUMBER 0x0000 34 #define DPTX_VERSION_TYPE 0x0004 35 #define DPTX_ID 0x0008 36 37 #define DPTX_CONFIG_REG1 0x0100 38 #define DPTX_CONFIG_REG2 0x0104 39 #define DPTX_CONFIG_REG3 0x0108 40 41 #define DPTX_CCTL 0x0200 42 #define FORCE_HPD BIT(4) 43 #define DEFAULT_FAST_LINK_TRAIN_EN BIT(2) 44 #define ENHANCE_FRAMING_EN BIT(1) 45 #define SCRAMBLE_DIS BIT(0) 46 #define DPTX_SOFT_RESET_CTRL 0x0204 47 #define VIDEO_RESET BIT(5) 48 #define AUX_RESET BIT(4) 49 #define AUDIO_SAMPLER_RESET BIT(3) 50 #define PHY_SOFT_RESET BIT(1) 51 #define CONTROLLER_RESET BIT(0) 52 53 #define DPTX_VSAMPLE_CTRL 0x0300 54 #define PIXEL_MODE_SELECT GENMASK(22, 21) 55 #define VIDEO_MAPPING GENMASK(20, 16) 56 #define VIDEO_STREAM_ENABLE BIT(5) 57 #define DPTX_VSAMPLE_STUFF_CTRL1 0x0304 58 #define DPTX_VSAMPLE_STUFF_CTRL2 0x0308 59 #define DPTX_VINPUT_POLARITY_CTRL 0x030c 60 #define DE_IN_POLARITY BIT(2) 61 #define HSYNC_IN_POLARITY BIT(1) 62 #define VSYNC_IN_POLARITY BIT(0) 63 #define DPTX_VIDEO_CONFIG1 0x0310 64 #define HACTIVE GENMASK(31, 16) 65 #define HBLANK GENMASK(15, 2) 66 #define I_P BIT(1) 67 #define R_V_BLANK_IN_OSC BIT(0) 68 #define DPTX_VIDEO_CONFIG2 0x0314 69 #define VBLANK GENMASK(31, 16) 70 #define VACTIVE GENMASK(15, 0) 71 #define DPTX_VIDEO_CONFIG3 0x0318 72 #define H_SYNC_WIDTH GENMASK(31, 16) 73 #define H_FRONT_PORCH GENMASK(15, 0) 74 #define DPTX_VIDEO_CONFIG4 0x031c 75 #define V_SYNC_WIDTH GENMASK(31, 16) 76 #define V_FRONT_PORCH GENMASK(15, 0) 77 #define DPTX_VIDEO_CONFIG5 0x0320 78 #define INIT_THRESHOLD_HI GENMASK(22, 21) 79 #define AVERAGE_BYTES_PER_TU_FRAC GENMASK(19, 16) 80 #define INIT_THRESHOLD GENMASK(13, 7) 81 #define AVERAGE_BYTES_PER_TU GENMASK(6, 0) 82 #define DPTX_VIDEO_MSA1 0x0324 83 #define VSTART GENMASK(31, 16) 84 #define HSTART GENMASK(15, 0) 85 #define DPTX_VIDEO_MSA2 0x0328 86 #define MISC0 GENMASK(31, 24) 87 #define DPTX_VIDEO_MSA3 0x032c 88 #define MISC1 GENMASK(31, 24) 89 #define DPTX_VIDEO_HBLANK_INTERVAL 0x0330 90 #define HBLANK_INTERVAL_EN BIT(16) 91 #define HBLANK_INTERVAL GENMASK(15, 0) 92 93 #define DPTX_AUD_CONFIG1 0x0400 94 #define AUDIO_TIMESTAMP_VERSION_NUM GENMASK(29, 24) 95 #define AUDIO_PACKET_ID GENMASK(23, 16) 96 #define AUDIO_MUTE BIT(15) 97 #define NUM_CHANNELS GENMASK(14, 12) 98 #define HBR_MODE_ENABLE BIT(10) 99 #define AUDIO_DATA_WIDTH GENMASK(9, 5) 100 #define AUDIO_DATA_IN_EN GENMASK(4, 1) 101 #define AUDIO_INF_SELECT BIT(0) 102 103 #define DPTX_SDP_VERTICAL_CTRL 0x0500 104 #define EN_VERTICAL_SDP BIT(2) 105 #define EN_AUDIO_STREAM_SDP BIT(1) 106 #define EN_AUDIO_TIMESTAMP_SDP BIT(0) 107 #define DPTX_SDP_HORIZONTAL_CTRL 0x0504 108 #define EN_HORIZONTAL_SDP BIT(2) 109 #define DPTX_SDP_STATUS_REGISTER 0x0508 110 #define DPTX_SDP_MANUAL_CTRL 0x050c 111 #define DPTX_SDP_STATUS_EN 0x0510 112 113 #define DPTX_SDP_REGISTER_BANK 0x0600 114 #define SDP_REGS GENMASK(31, 0) 115 116 #define DPTX_PHYIF_CTRL 0x0a00 117 #define PHY_WIDTH BIT(25) 118 #define PHY_POWERDOWN GENMASK(20, 17) 119 #define PHY_BUSY GENMASK(15, 12) 120 #define SSC_DIS BIT(16) 121 #define XMIT_ENABLE GENMASK(11, 8) 122 #define PHY_LANES GENMASK(7, 6) 123 #define PHY_RATE GENMASK(5, 4) 124 #define TPS_SEL GENMASK(3, 0) 125 #define DPTX_PHY_TX_EQ 0x0a04 126 #define DPTX_CUSTOMPAT0 0x0a08 127 #define DPTX_CUSTOMPAT1 0x0a0c 128 #define DPTX_CUSTOMPAT2 0x0a10 129 #define DPTX_HBR2_COMPLIANCE_SCRAMBLER_RESET 0x0a14 130 #define DPTX_PHYIF_PWRDOWN_CTRL 0x0a18 131 132 #define DPTX_AUX_CMD 0x0b00 133 #define AUX_CMD_TYPE GENMASK(31, 28) 134 #define AUX_ADDR GENMASK(27, 8) 135 #define I2C_ADDR_ONLY BIT(4) 136 #define AUX_LEN_REQ GENMASK(3, 0) 137 #define DPTX_AUX_STATUS 0x0b04 138 #define AUX_TIMEOUT BIT(17) 139 #define AUX_BYTES_READ GENMASK(23, 19) 140 #define AUX_STATUS GENMASK(7, 4) 141 #define DPTX_AUX_DATA0 0x0b08 142 #define DPTX_AUX_DATA1 0x0b0c 143 #define DPTX_AUX_DATA2 0x0b10 144 #define DPTX_AUX_DATA3 0x0b14 145 146 #define DPTX_GENERAL_INTERRUPT 0x0d00 147 #define VIDEO_FIFO_OVERFLOW_STREAM0 BIT(6) 148 #define AUDIO_FIFO_OVERFLOW_STREAM0 BIT(5) 149 #define SDP_EVENT_STREAM0 BIT(4) 150 #define AUX_CMD_INVALID BIT(3) 151 #define AUX_REPLY_EVENT BIT(1) 152 #define HPD_EVENT BIT(0) 153 #define DPTX_GENERAL_INTERRUPT_ENABLE 0x0d04 154 #define AUX_REPLY_EVENT_EN BIT(1) 155 #define HPD_EVENT_EN BIT(0) 156 #define DPTX_HPD_STATUS 0x0d08 157 #define HPD_STATE GENMASK(11, 9) 158 #define HPD_STATUS BIT(8) 159 #define HPD_HOT_UNPLUG BIT(2) 160 #define HPD_HOT_PLUG BIT(1) 161 #define HPD_IRQ BIT(0) 162 #define DPTX_HPD_INTERRUPT_ENABLE 0x0d0c 163 #define HPD_UNPLUG_ERR_EN BIT(3) 164 #define HPD_UNPLUG_EN BIT(2) 165 #define HPD_PLUG_EN BIT(1) 166 #define HPD_IRQ_EN BIT(0) 167 168 #define DPTX_MAX_REGISTER DPTX_HPD_INTERRUPT_ENABLE 169 170 #define SDP_REG_BANK_SIZE 16 171 172 struct drm_dp_link_caps { 173 bool enhanced_framing; 174 bool tps3_supported; 175 bool tps4_supported; 176 bool channel_coding; 177 bool ssc; 178 }; 179 180 struct drm_dp_link_train_set { 181 unsigned int voltage_swing[4]; 182 unsigned int pre_emphasis[4]; 183 }; 184 185 struct drm_dp_link_train { 186 struct drm_dp_link_train_set request; 187 struct drm_dp_link_train_set adjust; 188 bool clock_recovered; 189 bool channel_equalized; 190 }; 191 192 struct dw_dp_link { 193 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 194 unsigned char revision; 195 unsigned int rate; 196 unsigned int lanes; 197 struct drm_dp_link_caps caps; 198 struct drm_dp_link_train train; 199 u8 sink_count; 200 u8 vsc_sdp_extension_for_colorimetry_supported; 201 }; 202 203 struct dw_dp_video { 204 struct drm_display_mode mode; 205 u32 bus_format; 206 u8 video_mapping; 207 u8 pixel_mode; 208 u8 color_format; 209 u8 bpc; 210 u8 bpp; 211 }; 212 213 struct dw_dp_sdp { 214 struct dp_sdp_header header; 215 u8 db[32]; 216 unsigned long flags; 217 }; 218 219 struct dw_dp { 220 struct rockchip_connector connector; 221 struct udevice *dev; 222 struct regmap *regmap; 223 struct phy phy; 224 struct reset_ctl reset; 225 int id; 226 227 struct gpio_desc hpd_gpio; 228 struct drm_dp_aux aux; 229 struct dw_dp_link link; 230 struct dw_dp_video video; 231 232 bool force_hpd; 233 bool force_output; 234 }; 235 236 enum { 237 SOURCE_STATE_IDLE, 238 SOURCE_STATE_UNPLUG, 239 SOURCE_STATE_HPD_TIMEOUT = 4, 240 SOURCE_STATE_PLUG = 7 241 }; 242 243 enum { 244 DPTX_VM_RGB_6BIT, 245 DPTX_VM_RGB_8BIT, 246 DPTX_VM_RGB_10BIT, 247 DPTX_VM_RGB_12BIT, 248 DPTX_VM_RGB_16BIT, 249 DPTX_VM_YCBCR444_8BIT, 250 DPTX_VM_YCBCR444_10BIT, 251 DPTX_VM_YCBCR444_12BIT, 252 DPTX_VM_YCBCR444_16BIT, 253 DPTX_VM_YCBCR422_8BIT, 254 DPTX_VM_YCBCR422_10BIT, 255 DPTX_VM_YCBCR422_12BIT, 256 DPTX_VM_YCBCR422_16BIT, 257 DPTX_VM_YCBCR420_8BIT, 258 DPTX_VM_YCBCR420_10BIT, 259 DPTX_VM_YCBCR420_12BIT, 260 DPTX_VM_YCBCR420_16BIT, 261 }; 262 263 enum { 264 DPTX_MP_SINGLE_PIXEL, 265 DPTX_MP_DUAL_PIXEL, 266 DPTX_MP_QUAD_PIXEL, 267 }; 268 269 enum { 270 DPTX_SDP_VERTICAL_INTERVAL = BIT(0), 271 DPTX_SDP_HORIZONTAL_INTERVAL = BIT(1), 272 }; 273 274 enum { 275 DPTX_PHY_PATTERN_NONE, 276 DPTX_PHY_PATTERN_TPS_1, 277 DPTX_PHY_PATTERN_TPS_2, 278 DPTX_PHY_PATTERN_TPS_3, 279 DPTX_PHY_PATTERN_TPS_4, 280 DPTX_PHY_PATTERN_SERM, 281 DPTX_PHY_PATTERN_PBRS7, 282 DPTX_PHY_PATTERN_CUSTOM_80BIT, 283 DPTX_PHY_PATTERN_CP2520_1, 284 DPTX_PHY_PATTERN_CP2520_2, 285 }; 286 287 enum { 288 DPTX_PHYRATE_RBR, 289 DPTX_PHYRATE_HBR, 290 DPTX_PHYRATE_HBR2, 291 DPTX_PHYRATE_HBR3, 292 }; 293 294 struct dw_dp_output_format { 295 u32 bus_format; 296 u32 color_format; 297 u8 video_mapping; 298 u8 bpc; 299 u8 bpp; 300 }; 301 302 static const struct dw_dp_output_format possible_output_fmts[] = { 303 { MEDIA_BUS_FMT_RGB101010_1X30, DRM_COLOR_FORMAT_RGB444, 304 DPTX_VM_RGB_10BIT, 10, 30 }, 305 { MEDIA_BUS_FMT_RGB888_1X24, DRM_COLOR_FORMAT_RGB444, 306 DPTX_VM_RGB_8BIT, 8, 24 }, 307 { MEDIA_BUS_FMT_YUV10_1X30, DRM_COLOR_FORMAT_YCRCB444, 308 DPTX_VM_YCBCR444_10BIT, 10, 30 }, 309 { MEDIA_BUS_FMT_YUV8_1X24, DRM_COLOR_FORMAT_YCRCB444, 310 DPTX_VM_YCBCR444_8BIT, 8, 24}, 311 { MEDIA_BUS_FMT_YUYV10_1X20, DRM_COLOR_FORMAT_YCRCB422, 312 DPTX_VM_YCBCR422_10BIT, 10, 20 }, 313 { MEDIA_BUS_FMT_YUYV8_1X16, DRM_COLOR_FORMAT_YCRCB422, 314 DPTX_VM_YCBCR422_8BIT, 8, 16 }, 315 { MEDIA_BUS_FMT_UYYVYY10_0_5X30, DRM_COLOR_FORMAT_YCRCB420, 316 DPTX_VM_YCBCR420_10BIT, 10, 15 }, 317 { MEDIA_BUS_FMT_UYYVYY8_0_5X24, DRM_COLOR_FORMAT_YCRCB420, 318 DPTX_VM_YCBCR420_8BIT, 8, 12 }, 319 { MEDIA_BUS_FMT_RGB666_1X24_CPADHI, DRM_COLOR_FORMAT_RGB444, 320 DPTX_VM_RGB_6BIT, 6, 18 }, 321 }; 322 323 static int dw_dp_aux_write_data(struct dw_dp *dp, const u8 *buffer, size_t size) 324 { 325 size_t i, j; 326 327 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 328 size_t num = min_t(size_t, size - i * 4, 4); 329 u32 value = 0; 330 331 for (j = 0; j < num; j++) 332 value |= buffer[i * 4 + j] << (j * 8); 333 334 regmap_write(dp->regmap, DPTX_AUX_DATA0 + i * 4, value); 335 } 336 337 return size; 338 } 339 340 static int dw_dp_aux_read_data(struct dw_dp *dp, u8 *buffer, size_t size) 341 { 342 size_t i, j; 343 344 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 345 size_t num = min_t(size_t, size - i * 4, 4); 346 u32 value; 347 348 regmap_read(dp->regmap, DPTX_AUX_DATA0 + i * 4, &value); 349 350 for (j = 0; j < num; j++) 351 buffer[i * 4 + j] = value >> (j * 8); 352 } 353 354 return size; 355 } 356 357 static ssize_t dw_dp_aux_transfer(struct drm_dp_aux *aux, 358 struct drm_dp_aux_msg *msg) 359 { 360 u32 status, value; 361 ssize_t ret = 0; 362 int timeout = 0; 363 struct dw_dp *dp = dev_get_priv(aux->dev); 364 365 if (WARN_ON(msg->size > 16)) 366 return -E2BIG; 367 368 switch (msg->request & ~DP_AUX_I2C_MOT) { 369 case DP_AUX_NATIVE_WRITE: 370 case DP_AUX_I2C_WRITE: 371 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 372 ret = dw_dp_aux_write_data(dp, msg->buffer, msg->size); 373 if (ret < 0) 374 return ret; 375 break; 376 case DP_AUX_NATIVE_READ: 377 case DP_AUX_I2C_READ: 378 break; 379 default: 380 return -EINVAL; 381 } 382 383 if (msg->size > 0) 384 value = FIELD_PREP(AUX_LEN_REQ, msg->size - 1); 385 else 386 value = FIELD_PREP(I2C_ADDR_ONLY, 1); 387 388 value |= FIELD_PREP(AUX_CMD_TYPE, msg->request); 389 value |= FIELD_PREP(AUX_ADDR, msg->address); 390 regmap_write(dp->regmap, DPTX_AUX_CMD, value); 391 392 timeout = regmap_read_poll_timeout(dp->regmap, DPTX_GENERAL_INTERRUPT, 393 status, status & AUX_REPLY_EVENT, 394 200, 10); 395 396 if (timeout) { 397 printf("timeout waiting for AUX reply\n"); 398 return -ETIMEDOUT; 399 } 400 regmap_write(dp->regmap, DPTX_GENERAL_INTERRUPT, AUX_REPLY_EVENT); 401 402 regmap_read(dp->regmap, DPTX_AUX_STATUS, &value); 403 if (value & AUX_TIMEOUT) { 404 printf("aux timeout\n"); 405 return -ETIMEDOUT; 406 } 407 408 msg->reply = FIELD_GET(AUX_STATUS, value); 409 410 if (msg->size > 0 && msg->reply == DP_AUX_NATIVE_REPLY_ACK) { 411 if (msg->request & DP_AUX_I2C_READ) { 412 size_t count = FIELD_GET(AUX_BYTES_READ, value) - 1; 413 414 if (count != msg->size) { 415 printf("aux fail to read %lu bytes\n", count); 416 return -EBUSY; 417 } 418 419 ret = dw_dp_aux_read_data(dp, msg->buffer, count); 420 if (ret < 0) 421 return ret; 422 } 423 } 424 425 return ret; 426 } 427 428 static bool dw_dp_bandwidth_ok(struct dw_dp *dp, 429 const struct drm_display_mode *mode, u32 bpp, 430 unsigned int lanes, unsigned int rate) 431 { 432 u32 max_bw, req_bw; 433 434 req_bw = mode->clock * bpp / 8; 435 max_bw = lanes * rate; 436 if (req_bw > max_bw) 437 return false; 438 439 return true; 440 } 441 442 static void dw_dp_hpd_init(struct dw_dp *dp) 443 { 444 if (dm_gpio_is_valid(&dp->hpd_gpio) || dp->force_hpd) { 445 regmap_update_bits(dp->regmap, DPTX_CCTL, FORCE_HPD, 446 FIELD_PREP(FORCE_HPD, 1)); 447 return; 448 } 449 450 /* Enable all HPD interrupts */ 451 regmap_update_bits(dp->regmap, DPTX_HPD_INTERRUPT_ENABLE, 452 HPD_UNPLUG_EN | HPD_PLUG_EN | HPD_IRQ_EN, 453 FIELD_PREP(HPD_UNPLUG_EN, 1) | 454 FIELD_PREP(HPD_PLUG_EN, 1) | 455 FIELD_PREP(HPD_IRQ_EN, 1)); 456 457 /* Enable all top-level interrupts */ 458 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, 459 HPD_EVENT_EN, FIELD_PREP(HPD_EVENT_EN, 1)); 460 } 461 462 static void dw_dp_aux_init(struct dw_dp *dp) 463 { 464 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, 465 FIELD_PREP(AUX_RESET, 1)); 466 udelay(10); 467 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, 468 FIELD_PREP(AUX_RESET, 0)); 469 470 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, 471 AUX_REPLY_EVENT_EN, 472 FIELD_PREP(AUX_REPLY_EVENT_EN, 1)); 473 } 474 475 static void dw_dp_init(struct dw_dp *dp) 476 { 477 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, 478 FIELD_PREP(CONTROLLER_RESET, 1)); 479 udelay(10); 480 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, 481 FIELD_PREP(CONTROLLER_RESET, 0)); 482 483 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, 484 FIELD_PREP(PHY_SOFT_RESET, 1)); 485 udelay(10); 486 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, 487 FIELD_PREP(PHY_SOFT_RESET, 0)); 488 489 regmap_update_bits(dp->regmap, DPTX_CCTL, DEFAULT_FAST_LINK_TRAIN_EN, 490 FIELD_PREP(DEFAULT_FAST_LINK_TRAIN_EN, 0)); 491 492 dw_dp_hpd_init(dp); 493 dw_dp_aux_init(dp); 494 } 495 496 static void dw_dp_phy_set_pattern(struct dw_dp *dp, u32 pattern) 497 { 498 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, TPS_SEL, 499 FIELD_PREP(TPS_SEL, pattern)); 500 } 501 502 static void dw_dp_phy_xmit_enable(struct dw_dp *dp, u32 lanes) 503 { 504 u32 xmit_enable; 505 506 switch (lanes) { 507 case 4: 508 case 2: 509 case 1: 510 xmit_enable = GENMASK(lanes - 1, 0); 511 break; 512 case 0: 513 default: 514 xmit_enable = 0; 515 break; 516 } 517 518 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, XMIT_ENABLE, 519 FIELD_PREP(XMIT_ENABLE, xmit_enable)); 520 } 521 522 static int dw_dp_link_power_up(struct dw_dp *dp) 523 { 524 struct dw_dp_link *link = &dp->link; 525 u8 value; 526 int ret; 527 528 if (link->revision < 0x11) 529 return 0; 530 531 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value); 532 if (ret < 0) 533 return ret; 534 535 value &= ~DP_SET_POWER_MASK; 536 value |= DP_SET_POWER_D0; 537 538 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value); 539 if (ret < 0) 540 return ret; 541 542 udelay(1000); 543 return 0; 544 } 545 546 static int dw_dp_link_probe(struct dw_dp *dp) 547 { 548 struct dw_dp_link *link = &dp->link; 549 u8 dpcd; 550 int ret; 551 552 ret = drm_dp_read_dpcd_caps(&dp->aux, link->dpcd); 553 if (ret < 0) 554 return ret; 555 556 ret = drm_dp_dpcd_readb(&dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, 557 &dpcd); 558 if (ret < 0) 559 return ret; 560 561 link->vsc_sdp_extension_for_colorimetry_supported = 562 !!(dpcd & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED); 563 564 link->revision = link->dpcd[DP_DPCD_REV]; 565 link->rate = min_t(u32, dp->phy.attrs.max_link_rate * 100, 566 drm_dp_max_link_rate(link->dpcd)); 567 link->lanes = min_t(u8, dp->phy.attrs.bus_width, 568 drm_dp_max_lane_count(link->dpcd)); 569 570 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(link->dpcd); 571 link->caps.tps3_supported = drm_dp_tps3_supported(link->dpcd); 572 link->caps.tps4_supported = drm_dp_tps4_supported(link->dpcd); 573 link->caps.channel_coding = drm_dp_channel_coding_supported(link->dpcd); 574 link->caps.ssc = !!(link->dpcd[DP_MAX_DOWNSPREAD] & 575 DP_MAX_DOWNSPREAD_0_5); 576 577 return 0; 578 } 579 580 static int dw_dp_link_train_update_vs_emph(struct dw_dp *dp) 581 { 582 struct dw_dp_link *link = &dp->link; 583 struct drm_dp_link_train_set *request = &link->train.request; 584 union phy_configure_opts phy_cfg; 585 unsigned int lanes = link->lanes, *vs, *pe; 586 u8 buf[4]; 587 int i, ret; 588 589 vs = request->voltage_swing; 590 pe = request->pre_emphasis; 591 592 for (i = 0; i < lanes; i++) { 593 phy_cfg.dp.voltage[i] = vs[i]; 594 phy_cfg.dp.pre[i] = pe[i]; 595 } 596 phy_cfg.dp.lanes = lanes; 597 phy_cfg.dp.link_rate = link->rate / 100; 598 phy_cfg.dp.set_lanes = false; 599 phy_cfg.dp.set_rate = false; 600 phy_cfg.dp.set_voltages = true; 601 ret = generic_phy_configure(&dp->phy, &phy_cfg); 602 if (ret) 603 return ret; 604 605 for (i = 0; i < lanes; i++) 606 buf[i] = (vs[i] << DP_TRAIN_VOLTAGE_SWING_SHIFT) | 607 (pe[i] << DP_TRAIN_PRE_EMPHASIS_SHIFT); 608 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, lanes); 609 if (ret < 0) 610 return ret; 611 612 return 0; 613 } 614 615 static int dw_dp_link_configure(struct dw_dp *dp) 616 { 617 struct dw_dp_link *link = &dp->link; 618 union phy_configure_opts phy_cfg; 619 u8 buf[2]; 620 int ret, phy_rate; 621 622 /* Move PHY to P3 */ 623 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 624 FIELD_PREP(PHY_POWERDOWN, 0x3)); 625 626 phy_cfg.dp.lanes = link->lanes; 627 phy_cfg.dp.link_rate = link->rate / 100; 628 phy_cfg.dp.ssc = link->caps.ssc; 629 phy_cfg.dp.set_lanes = true; 630 phy_cfg.dp.set_rate = true; 631 phy_cfg.dp.set_voltages = false; 632 ret = generic_phy_configure(&dp->phy, &phy_cfg); 633 if (ret) 634 return ret; 635 636 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, 637 FIELD_PREP(PHY_LANES, link->lanes / 2)); 638 639 switch (link->rate) { 640 case 810000: 641 phy_rate = DPTX_PHYRATE_HBR3; 642 break; 643 case 540000: 644 phy_rate = DPTX_PHYRATE_HBR2; 645 break; 646 case 270000: 647 phy_rate = DPTX_PHYRATE_HBR; 648 break; 649 case 162000: 650 default: 651 phy_rate = DPTX_PHYRATE_RBR; 652 break; 653 } 654 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_RATE, 655 FIELD_PREP(PHY_RATE, phy_rate)); 656 657 /* Move PHY to P0 */ 658 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 659 FIELD_PREP(PHY_POWERDOWN, 0x0)); 660 661 dw_dp_phy_xmit_enable(dp, link->lanes); 662 663 buf[0] = drm_dp_link_rate_to_bw_code(link->rate); 664 buf[1] = link->lanes; 665 666 if (link->caps.enhanced_framing) { 667 buf[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 668 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 669 FIELD_PREP(ENHANCE_FRAMING_EN, 1)); 670 } else { 671 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 672 FIELD_PREP(ENHANCE_FRAMING_EN, 0)); 673 } 674 675 ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, sizeof(buf)); 676 if (ret < 0) 677 return ret; 678 679 buf[0] = link->caps.ssc ? DP_SPREAD_AMP_0_5 : 0; 680 buf[1] = link->caps.channel_coding ? DP_SET_ANSI_8B10B : 0; 681 682 ret = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, 683 sizeof(buf)); 684 if (ret < 0) 685 return ret; 686 687 return 0; 688 } 689 690 static void dw_dp_link_train_init(struct drm_dp_link_train *train) 691 { 692 struct drm_dp_link_train_set *request = &train->request; 693 struct drm_dp_link_train_set *adjust = &train->adjust; 694 unsigned int i; 695 696 for (i = 0; i < 4; i++) { 697 request->voltage_swing[i] = 0; 698 adjust->voltage_swing[i] = 0; 699 700 request->pre_emphasis[i] = 0; 701 adjust->pre_emphasis[i] = 0; 702 } 703 704 train->clock_recovered = false; 705 train->channel_equalized = false; 706 } 707 708 static int dw_dp_link_train_set_pattern(struct dw_dp *dp, u32 pattern) 709 { 710 u8 buf = 0; 711 int ret; 712 713 if (pattern && pattern != DP_TRAINING_PATTERN_4) { 714 buf |= DP_LINK_SCRAMBLING_DISABLE; 715 716 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, 717 FIELD_PREP(SCRAMBLE_DIS, 1)); 718 } else { 719 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, 720 FIELD_PREP(SCRAMBLE_DIS, 0)); 721 } 722 723 switch (pattern) { 724 case DP_TRAINING_PATTERN_DISABLE: 725 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE); 726 break; 727 case DP_TRAINING_PATTERN_1: 728 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_1); 729 break; 730 case DP_TRAINING_PATTERN_2: 731 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_2); 732 break; 733 case DP_TRAINING_PATTERN_3: 734 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_3); 735 break; 736 case DP_TRAINING_PATTERN_4: 737 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_4); 738 break; 739 default: 740 return -EINVAL; 741 } 742 743 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 744 buf | pattern); 745 if (ret < 0) 746 return ret; 747 748 return 0; 749 } 750 751 static void dw_dp_link_get_adjustments(struct dw_dp_link *link, 752 u8 status[DP_LINK_STATUS_SIZE]) 753 { 754 struct drm_dp_link_train_set *adjust = &link->train.adjust; 755 unsigned int i; 756 757 for (i = 0; i < link->lanes; i++) { 758 adjust->voltage_swing[i] = 759 drm_dp_get_adjust_request_voltage(status, i) >> 760 DP_TRAIN_VOLTAGE_SWING_SHIFT; 761 762 adjust->pre_emphasis[i] = 763 drm_dp_get_adjust_request_pre_emphasis(status, i) >> 764 DP_TRAIN_PRE_EMPHASIS_SHIFT; 765 } 766 } 767 768 static void dw_dp_link_train_adjust(struct drm_dp_link_train *train) 769 { 770 struct drm_dp_link_train_set *request = &train->request; 771 struct drm_dp_link_train_set *adjust = &train->adjust; 772 unsigned int i; 773 774 for (i = 0; i < 4; i++) 775 if (request->voltage_swing[i] != adjust->voltage_swing[i]) 776 request->voltage_swing[i] = adjust->voltage_swing[i]; 777 778 for (i = 0; i < 4; i++) 779 if (request->pre_emphasis[i] != adjust->pre_emphasis[i]) 780 request->pre_emphasis[i] = adjust->pre_emphasis[i]; 781 } 782 783 static int dw_dp_link_clock_recovery(struct dw_dp *dp) 784 { 785 struct dw_dp_link *link = &dp->link; 786 u8 status[DP_LINK_STATUS_SIZE]; 787 unsigned int tries = 0; 788 int ret; 789 790 ret = dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_1); 791 if (ret) 792 return ret; 793 794 for (;;) { 795 ret = dw_dp_link_train_update_vs_emph(dp); 796 if (ret) 797 return ret; 798 799 drm_dp_link_train_clock_recovery_delay(link->dpcd); 800 801 ret = drm_dp_dpcd_read_link_status(&dp->aux, status); 802 if (ret < 0) { 803 dev_err(dp->dev, "failed to read link status: %d\n", 804 ret); 805 return ret; 806 } 807 808 if (drm_dp_clock_recovery_ok(status, link->lanes)) { 809 link->train.clock_recovered = true; 810 break; 811 } 812 813 dw_dp_link_get_adjustments(link, status); 814 815 if (link->train.request.voltage_swing[0] == 816 link->train.adjust.voltage_swing[0]) 817 tries++; 818 else 819 tries = 0; 820 821 if (tries == 5) 822 break; 823 824 dw_dp_link_train_adjust(&link->train); 825 } 826 827 return 0; 828 } 829 830 static int dw_dp_link_channel_equalization(struct dw_dp *dp) 831 { 832 struct dw_dp_link *link = &dp->link; 833 u8 status[DP_LINK_STATUS_SIZE], pattern; 834 unsigned int tries; 835 int ret; 836 837 if (link->caps.tps4_supported) 838 pattern = DP_TRAINING_PATTERN_4; 839 else if (link->caps.tps3_supported) 840 pattern = DP_TRAINING_PATTERN_3; 841 else 842 pattern = DP_TRAINING_PATTERN_2; 843 ret = dw_dp_link_train_set_pattern(dp, pattern); 844 if (ret) 845 return ret; 846 847 for (tries = 1; tries < 5; tries++) { 848 ret = dw_dp_link_train_update_vs_emph(dp); 849 if (ret) 850 return ret; 851 852 drm_dp_link_train_channel_eq_delay(link->dpcd); 853 854 ret = drm_dp_dpcd_read_link_status(&dp->aux, status); 855 if (ret < 0) 856 return ret; 857 858 if (!drm_dp_clock_recovery_ok(status, link->lanes)) { 859 dev_err(dp->dev, 860 "clock recovery lost while eq\n"); 861 link->train.clock_recovered = false; 862 break; 863 } 864 865 if (drm_dp_channel_eq_ok(status, link->lanes)) { 866 link->train.channel_equalized = true; 867 break; 868 } 869 870 dw_dp_link_get_adjustments(link, status); 871 dw_dp_link_train_adjust(&link->train); 872 } 873 874 return 0; 875 } 876 877 static int dw_dp_link_downgrade(struct dw_dp *dp) 878 { 879 struct dw_dp_link *link = &dp->link; 880 struct dw_dp_video *video = &dp->video; 881 882 switch (link->rate) { 883 case 162000: 884 return -EINVAL; 885 case 270000: 886 link->rate = 162000; 887 break; 888 case 540000: 889 link->rate = 270000; 890 break; 891 case 810000: 892 link->rate = 540000; 893 break; 894 } 895 896 if (!dw_dp_bandwidth_ok(dp, &video->mode, video->bpp, link->lanes, 897 link->rate)) 898 return -E2BIG; 899 900 return 0; 901 } 902 903 static int dw_dp_link_train(struct dw_dp *dp) 904 { 905 struct dw_dp_link *link = &dp->link; 906 int ret; 907 908 retry: 909 dw_dp_link_train_init(&link->train); 910 911 printf("training link: %u lane%s at %u MHz\n", 912 link->lanes, (link->lanes > 1) ? "s" : "", link->rate / 100); 913 914 ret = dw_dp_link_configure(dp); 915 if (ret < 0) { 916 dev_err(dp->dev, "failed to configure DP link: %d\n", ret); 917 return ret; 918 } 919 920 ret = dw_dp_link_clock_recovery(dp); 921 if (ret < 0) { 922 dev_err(dp->dev, "clock recovery failed: %d\n", ret); 923 goto out; 924 } 925 926 if (!link->train.clock_recovered) { 927 dev_err(dp->dev, "clock recovery failed, downgrading link\n"); 928 929 ret = dw_dp_link_downgrade(dp); 930 if (ret < 0) 931 goto out; 932 else 933 goto retry; 934 } 935 936 printf("clock recovery succeeded\n"); 937 938 ret = dw_dp_link_channel_equalization(dp); 939 if (ret < 0) { 940 dev_err(dp->dev, "channel equalization failed: %d\n", ret); 941 goto out; 942 } 943 944 if (!link->train.channel_equalized) { 945 dev_err(dp->dev, 946 "channel equalization failed, downgrading link\n"); 947 948 ret = dw_dp_link_downgrade(dp); 949 if (ret < 0) 950 goto out; 951 else 952 goto retry; 953 } 954 955 printf("channel equalization succeeded\n"); 956 957 out: 958 dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE); 959 return ret; 960 } 961 962 static int dw_dp_link_enable(struct dw_dp *dp) 963 { 964 int ret; 965 966 ret = dw_dp_link_power_up(dp); 967 if (ret < 0) 968 return ret; 969 970 ret = dw_dp_link_train(dp); 971 if (ret < 0) { 972 dev_err(dp->dev, "link training failed: %d\n", ret); 973 return ret; 974 } 975 976 return 0; 977 } 978 979 static int dw_dp_set_phy_default_config(struct dw_dp *dp) 980 { 981 struct dw_dp_link *link = &dp->link; 982 union phy_configure_opts phy_cfg; 983 int ret, i, phy_rate; 984 985 link->vsc_sdp_extension_for_colorimetry_supported = false; 986 link->rate = 270000; 987 link->lanes = dp->phy.attrs.bus_width; 988 989 link->caps.enhanced_framing = true; 990 link->caps.channel_coding = true; 991 link->caps.ssc = true; 992 993 /* Move PHY to P3 */ 994 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 995 FIELD_PREP(PHY_POWERDOWN, 0x3)); 996 997 for (i = 0; i < link->lanes; i++) { 998 phy_cfg.dp.voltage[i] = 3; 999 phy_cfg.dp.pre[i] = 0; 1000 } 1001 phy_cfg.dp.lanes = link->lanes; 1002 phy_cfg.dp.link_rate = link->rate / 100; 1003 phy_cfg.dp.ssc = link->caps.ssc; 1004 phy_cfg.dp.set_lanes = true; 1005 phy_cfg.dp.set_rate = true; 1006 phy_cfg.dp.set_voltages = true; 1007 ret = generic_phy_configure(&dp->phy, &phy_cfg); 1008 if (ret) 1009 return ret; 1010 1011 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, 1012 FIELD_PREP(PHY_LANES, link->lanes / 2)); 1013 1014 switch (link->rate) { 1015 case 810000: 1016 phy_rate = DPTX_PHYRATE_HBR3; 1017 break; 1018 case 540000: 1019 phy_rate = DPTX_PHYRATE_HBR2; 1020 break; 1021 case 270000: 1022 phy_rate = DPTX_PHYRATE_HBR; 1023 break; 1024 case 162000: 1025 default: 1026 phy_rate = DPTX_PHYRATE_RBR; 1027 break; 1028 } 1029 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_RATE, 1030 FIELD_PREP(PHY_RATE, phy_rate)); 1031 1032 /* Move PHY to P0 */ 1033 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, 1034 FIELD_PREP(PHY_POWERDOWN, 0x0)); 1035 1036 dw_dp_phy_xmit_enable(dp, link->lanes); 1037 1038 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, 1039 FIELD_PREP(ENHANCE_FRAMING_EN, 1)); 1040 1041 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE); 1042 return 0; 1043 } 1044 1045 static int dw_dp_send_sdp(struct dw_dp *dp, struct dw_dp_sdp *sdp) 1046 { 1047 const u8 *payload = sdp->db; 1048 u32 reg; 1049 int i, nr = 0; 1050 1051 reg = DPTX_SDP_REGISTER_BANK + nr * 9 * 4; 1052 1053 /* SDP header */ 1054 regmap_write(dp->regmap, reg, get_unaligned_le32(&sdp->header)); 1055 1056 /* SDP data payload */ 1057 for (i = 1; i < 9; i++, payload += 4) 1058 regmap_write(dp->regmap, reg + i * 4, 1059 FIELD_PREP(SDP_REGS, get_unaligned_le32(payload))); 1060 1061 if (sdp->flags & DPTX_SDP_VERTICAL_INTERVAL) 1062 regmap_update_bits(dp->regmap, DPTX_SDP_VERTICAL_CTRL, 1063 EN_VERTICAL_SDP << nr, 1064 EN_VERTICAL_SDP << nr); 1065 1066 if (sdp->flags & DPTX_SDP_HORIZONTAL_INTERVAL) 1067 regmap_update_bits(dp->regmap, DPTX_SDP_HORIZONTAL_CTRL, 1068 EN_HORIZONTAL_SDP << nr, 1069 EN_HORIZONTAL_SDP << nr); 1070 1071 return 0; 1072 } 1073 1074 static void dw_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, 1075 struct dw_dp_sdp *sdp) 1076 { 1077 sdp->header.HB0 = 0; 1078 sdp->header.HB1 = DP_SDP_VSC; 1079 sdp->header.HB2 = vsc->revision; 1080 sdp->header.HB3 = vsc->length; 1081 1082 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; 1083 sdp->db[16] |= vsc->colorimetry & 0xf; 1084 1085 switch (vsc->bpc) { 1086 case 8: 1087 sdp->db[17] = 0x1; 1088 break; 1089 case 10: 1090 sdp->db[17] = 0x2; 1091 break; 1092 case 12: 1093 sdp->db[17] = 0x3; 1094 break; 1095 case 16: 1096 sdp->db[17] = 0x4; 1097 break; 1098 case 6: 1099 default: 1100 break; 1101 } 1102 1103 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) 1104 sdp->db[17] |= 0x80; 1105 1106 sdp->db[18] = vsc->content_type & 0x7; 1107 1108 sdp->flags |= DPTX_SDP_VERTICAL_INTERVAL; 1109 } 1110 1111 static int dw_dp_send_vsc_sdp(struct dw_dp *dp) 1112 { 1113 struct dw_dp_video *video = &dp->video; 1114 struct drm_dp_vsc_sdp vsc = {}; 1115 struct dw_dp_sdp sdp = {}; 1116 1117 vsc.revision = 0x5; 1118 vsc.length = 0x13; 1119 1120 switch (video->color_format) { 1121 case DRM_COLOR_FORMAT_YCRCB444: 1122 vsc.pixelformat = DP_PIXELFORMAT_YUV444; 1123 break; 1124 case DRM_COLOR_FORMAT_YCRCB420: 1125 vsc.pixelformat = DP_PIXELFORMAT_YUV420; 1126 break; 1127 case DRM_COLOR_FORMAT_YCRCB422: 1128 vsc.pixelformat = DP_PIXELFORMAT_YUV422; 1129 break; 1130 case DRM_COLOR_FORMAT_RGB444: 1131 default: 1132 vsc.pixelformat = DP_PIXELFORMAT_RGB; 1133 break; 1134 } 1135 1136 if (video->color_format == DRM_COLOR_FORMAT_RGB444) 1137 vsc.colorimetry = DP_COLORIMETRY_DEFAULT; 1138 else 1139 vsc.colorimetry = DP_COLORIMETRY_BT709_YCC; 1140 1141 vsc.bpc = video->bpc; 1142 vsc.dynamic_range = DP_DYNAMIC_RANGE_CTA; 1143 vsc.content_type = DP_CONTENT_TYPE_NOT_DEFINED; 1144 1145 dw_dp_vsc_sdp_pack(&vsc, &sdp); 1146 1147 return dw_dp_send_sdp(dp, &sdp); 1148 } 1149 1150 static int dw_dp_video_set_pixel_mode(struct dw_dp *dp, u8 pixel_mode) 1151 { 1152 switch (pixel_mode) { 1153 case DPTX_MP_SINGLE_PIXEL: 1154 case DPTX_MP_DUAL_PIXEL: 1155 case DPTX_MP_QUAD_PIXEL: 1156 break; 1157 default: 1158 return -EINVAL; 1159 } 1160 1161 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, PIXEL_MODE_SELECT, 1162 FIELD_PREP(PIXEL_MODE_SELECT, pixel_mode)); 1163 1164 return 0; 1165 } 1166 1167 static int dw_dp_video_set_msa(struct dw_dp *dp, u8 color_format, u8 bpc, 1168 u16 vstart, u16 hstart) 1169 { 1170 struct dw_dp_link *link = &dp->link; 1171 u16 misc = 0; 1172 1173 if (link->vsc_sdp_extension_for_colorimetry_supported) 1174 misc |= DP_MSA_MISC_COLOR_VSC_SDP; 1175 1176 switch (color_format) { 1177 case DRM_COLOR_FORMAT_RGB444: 1178 misc |= DP_MSA_MISC_COLOR_RGB; 1179 break; 1180 case DRM_COLOR_FORMAT_YCRCB444: 1181 misc |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 1182 break; 1183 case DRM_COLOR_FORMAT_YCRCB422: 1184 misc |= DP_MSA_MISC_COLOR_YCBCR_422_BT709; 1185 break; 1186 case DRM_COLOR_FORMAT_YCRCB420: 1187 break; 1188 default: 1189 return -EINVAL; 1190 } 1191 1192 switch (bpc) { 1193 case 6: 1194 misc |= DP_MSA_MISC_6_BPC; 1195 break; 1196 case 8: 1197 misc |= DP_MSA_MISC_8_BPC; 1198 break; 1199 case 10: 1200 misc |= DP_MSA_MISC_10_BPC; 1201 break; 1202 case 12: 1203 misc |= DP_MSA_MISC_12_BPC; 1204 break; 1205 case 16: 1206 misc |= DP_MSA_MISC_16_BPC; 1207 break; 1208 default: 1209 return -EINVAL; 1210 } 1211 1212 regmap_write(dp->regmap, DPTX_VIDEO_MSA1, 1213 FIELD_PREP(VSTART, vstart) | FIELD_PREP(HSTART, hstart)); 1214 regmap_write(dp->regmap, DPTX_VIDEO_MSA2, FIELD_PREP(MISC0, misc)); 1215 regmap_write(dp->regmap, DPTX_VIDEO_MSA3, FIELD_PREP(MISC1, misc >> 8)); 1216 1217 return 0; 1218 } 1219 1220 static int dw_dp_video_enable(struct dw_dp *dp) 1221 { 1222 struct dw_dp_video *video = &dp->video; 1223 struct dw_dp_link *link = &dp->link; 1224 struct drm_display_mode *mode = &video->mode; 1225 u8 color_format = video->color_format; 1226 u8 bpc = video->bpc; 1227 u8 pixel_mode = video->pixel_mode; 1228 u8 bpp = video->bpp, init_threshold, vic; 1229 u32 hactive, hblank, h_sync_width, h_front_porch; 1230 u32 vactive, vblank, v_sync_width, v_front_porch; 1231 u32 vstart = mode->vtotal - mode->vsync_start; 1232 u32 hstart = mode->htotal - mode->hsync_start; 1233 u32 peak_stream_bandwidth, link_bandwidth; 1234 u32 average_bytes_per_tu, average_bytes_per_tu_frac; 1235 u32 ts, hblank_interval; 1236 u32 value; 1237 int ret; 1238 1239 ret = dw_dp_video_set_pixel_mode(dp, pixel_mode); 1240 if (ret) 1241 return ret; 1242 1243 ret = dw_dp_video_set_msa(dp, color_format, bpc, vstart, hstart); 1244 if (ret) 1245 return ret; 1246 1247 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_MAPPING, 1248 FIELD_PREP(VIDEO_MAPPING, video->video_mapping)); 1249 1250 /* Configure DPTX_VINPUT_POLARITY_CTRL register */ 1251 value = 0; 1252 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1253 value |= FIELD_PREP(HSYNC_IN_POLARITY, 1); 1254 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1255 value |= FIELD_PREP(VSYNC_IN_POLARITY, 1); 1256 regmap_write(dp->regmap, DPTX_VINPUT_POLARITY_CTRL, value); 1257 1258 /* Configure DPTX_VIDEO_CONFIG1 register */ 1259 hactive = mode->hdisplay; 1260 hblank = mode->htotal - mode->hdisplay; 1261 value = FIELD_PREP(HACTIVE, hactive) | FIELD_PREP(HBLANK, hblank); 1262 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1263 value |= FIELD_PREP(I_P, 1); 1264 vic = drm_match_cea_mode(mode); 1265 if (vic == 5 || vic == 6 || vic == 7 || 1266 vic == 10 || vic == 11 || vic == 20 || 1267 vic == 21 || vic == 22 || vic == 39 || 1268 vic == 25 || vic == 26 || vic == 40 || 1269 vic == 44 || vic == 45 || vic == 46 || 1270 vic == 50 || vic == 51 || vic == 54 || 1271 vic == 55 || vic == 58 || vic == 59) 1272 value |= R_V_BLANK_IN_OSC; 1273 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG1, value); 1274 1275 /* Configure DPTX_VIDEO_CONFIG2 register */ 1276 vblank = mode->vtotal - mode->vdisplay; 1277 vactive = mode->vdisplay; 1278 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG2, 1279 FIELD_PREP(VBLANK, vblank) | FIELD_PREP(VACTIVE, vactive)); 1280 1281 /* Configure DPTX_VIDEO_CONFIG3 register */ 1282 h_sync_width = mode->hsync_end - mode->hsync_start; 1283 h_front_porch = mode->hsync_start - mode->hdisplay; 1284 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG3, 1285 FIELD_PREP(H_SYNC_WIDTH, h_sync_width) | 1286 FIELD_PREP(H_FRONT_PORCH, h_front_porch)); 1287 1288 /* Configure DPTX_VIDEO_CONFIG4 register */ 1289 v_sync_width = mode->vsync_end - mode->vsync_start; 1290 v_front_porch = mode->vsync_start - mode->vdisplay; 1291 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG4, 1292 FIELD_PREP(V_SYNC_WIDTH, v_sync_width) | 1293 FIELD_PREP(V_FRONT_PORCH, v_front_porch)); 1294 1295 /* Configure DPTX_VIDEO_CONFIG5 register */ 1296 peak_stream_bandwidth = mode->clock * bpp / 8; 1297 link_bandwidth = (link->rate / 1000) * link->lanes; 1298 ts = peak_stream_bandwidth * 64 / link_bandwidth; 1299 average_bytes_per_tu = ts / 1000; 1300 average_bytes_per_tu_frac = ts / 100 - average_bytes_per_tu * 10; 1301 if (pixel_mode == DPTX_MP_SINGLE_PIXEL) { 1302 if (average_bytes_per_tu < 6) 1303 init_threshold = 32; 1304 else if (hblank <= 80 && 1305 color_format != DRM_COLOR_FORMAT_YCRCB420) 1306 init_threshold = 12; 1307 else if (hblank <= 40 && 1308 color_format == DRM_COLOR_FORMAT_YCRCB420) 1309 init_threshold = 3; 1310 else 1311 init_threshold = 16; 1312 } else { 1313 u32 t1 = 0, t2 = 0, t3 = 0; 1314 1315 switch (bpc) { 1316 case 6: 1317 t1 = (4 * 1000 / 9) * link->lanes; 1318 break; 1319 case 8: 1320 if (color_format == DRM_COLOR_FORMAT_YCRCB422) { 1321 t1 = (1000 / 2) * link->lanes; 1322 } else { 1323 if (pixel_mode == DPTX_MP_DUAL_PIXEL) 1324 t1 = (1000 / 3) * link->lanes; 1325 else 1326 t1 = (3000 / 16) * link->lanes; 1327 } 1328 break; 1329 case 10: 1330 if (color_format == DRM_COLOR_FORMAT_YCRCB422) 1331 t1 = (2000 / 5) * link->lanes; 1332 else 1333 t1 = (4000 / 15) * link->lanes; 1334 break; 1335 case 12: 1336 if (color_format == DRM_COLOR_FORMAT_YCRCB422) { 1337 if (pixel_mode == DPTX_MP_DUAL_PIXEL) 1338 t1 = (1000 / 6) * link->lanes; 1339 else 1340 t1 = (1000 / 3) * link->lanes; 1341 } else { 1342 t1 = (2000 / 9) * link->lanes; 1343 } 1344 break; 1345 case 16: 1346 if (color_format != DRM_COLOR_FORMAT_YCRCB422 && 1347 pixel_mode == DPTX_MP_DUAL_PIXEL) 1348 t1 = (1000 / 6) * link->lanes; 1349 else 1350 t1 = (1000 / 4) * link->lanes; 1351 break; 1352 default: 1353 return -EINVAL; 1354 } 1355 1356 if (color_format == DRM_COLOR_FORMAT_YCRCB420) 1357 t2 = (link->rate / 4) * 1000 / (mode->clock / 2); 1358 else 1359 t2 = (link->rate / 4) * 1000 / mode->clock; 1360 1361 if (average_bytes_per_tu_frac) 1362 t3 = average_bytes_per_tu + 1; 1363 else 1364 t3 = average_bytes_per_tu; 1365 init_threshold = t1 * t2 * t3 / (1000 * 1000); 1366 if (init_threshold <= 16 || average_bytes_per_tu < 10) 1367 init_threshold = 40; 1368 } 1369 1370 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG5, 1371 FIELD_PREP(INIT_THRESHOLD_HI, init_threshold >> 6) | 1372 FIELD_PREP(AVERAGE_BYTES_PER_TU_FRAC, 1373 average_bytes_per_tu_frac) | 1374 FIELD_PREP(INIT_THRESHOLD, init_threshold) | 1375 FIELD_PREP(AVERAGE_BYTES_PER_TU, average_bytes_per_tu)); 1376 1377 /* Configure DPTX_VIDEO_HBLANK_INTERVAL register */ 1378 hblank_interval = hblank * (link->rate / 4) / mode->clock; 1379 regmap_write(dp->regmap, DPTX_VIDEO_HBLANK_INTERVAL, 1380 FIELD_PREP(HBLANK_INTERVAL_EN, 1) | 1381 FIELD_PREP(HBLANK_INTERVAL, hblank_interval)); 1382 1383 /* Video stream enable */ 1384 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_STREAM_ENABLE, 1385 FIELD_PREP(VIDEO_STREAM_ENABLE, 1)); 1386 1387 if (link->vsc_sdp_extension_for_colorimetry_supported) 1388 dw_dp_send_vsc_sdp(dp); 1389 1390 return 0; 1391 } 1392 1393 static bool dw_dp_detect(struct dw_dp *dp) 1394 { 1395 u32 value; 1396 1397 if (dm_gpio_is_valid(&dp->hpd_gpio)) 1398 return dm_gpio_get_value(&dp->hpd_gpio); 1399 1400 regmap_read(dp->regmap, DPTX_HPD_STATUS, &value); 1401 if (FIELD_GET(HPD_STATE, value) == SOURCE_STATE_PLUG) { 1402 regmap_write(dp->regmap, DPTX_HPD_STATUS, HPD_HOT_PLUG); 1403 return true; 1404 } 1405 1406 return false; 1407 } 1408 1409 static int dw_dp_connector_init(struct rockchip_connector *conn, struct display_state *state) 1410 { 1411 struct connector_state *conn_state = &state->conn_state; 1412 struct dw_dp *dp = dev_get_priv(conn->dev); 1413 int ret; 1414 1415 conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_DP1 : VOP_OUTPUT_IF_DP0; 1416 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1417 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 1418 1419 clk_set_defaults(dp->dev); 1420 1421 reset_assert(&dp->reset); 1422 udelay(20); 1423 reset_deassert(&dp->reset); 1424 1425 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, 1426 dp->id); 1427 dw_dp_init(dp); 1428 ret = generic_phy_power_on(&dp->phy); 1429 1430 return ret; 1431 } 1432 1433 static int dw_dp_connector_get_edid(struct rockchip_connector *conn, struct display_state *state) 1434 { 1435 int ret; 1436 struct connector_state *conn_state = &state->conn_state; 1437 struct dw_dp *dp = dev_get_priv(conn->dev); 1438 1439 ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); 1440 1441 return ret; 1442 } 1443 1444 static int dw_dp_get_output_fmts_index(u32 bus_format) 1445 { 1446 int i; 1447 1448 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 1449 const struct dw_dp_output_format *fmt = &possible_output_fmts[i]; 1450 1451 if (fmt->bus_format == bus_format) 1452 break; 1453 } 1454 1455 if (i == ARRAY_SIZE(possible_output_fmts)) 1456 return 1; 1457 1458 return i; 1459 } 1460 1461 static int dw_dp_connector_prepare(struct rockchip_connector *conn, struct display_state *state) 1462 { 1463 struct connector_state *conn_state = &state->conn_state; 1464 struct dw_dp *dp = dev_get_priv(conn->dev); 1465 struct dw_dp_video *video = &dp->video; 1466 int bus_fmt; 1467 1468 bus_fmt = dw_dp_get_output_fmts_index(conn_state->bus_format); 1469 video->video_mapping = possible_output_fmts[bus_fmt].video_mapping; 1470 video->color_format = possible_output_fmts[bus_fmt].color_format; 1471 video->bus_format = possible_output_fmts[bus_fmt].bus_format; 1472 video->bpc = possible_output_fmts[bus_fmt].bpc; 1473 video->bpp = possible_output_fmts[bus_fmt].bpp; 1474 1475 return 0; 1476 } 1477 1478 static int dw_dp_connector_enable(struct rockchip_connector *conn, struct display_state *state) 1479 { 1480 struct connector_state *conn_state = &state->conn_state; 1481 struct drm_display_mode *mode = &conn_state->mode; 1482 struct dw_dp *dp = dev_get_priv(conn->dev); 1483 struct dw_dp_video *video = &dp->video; 1484 int ret; 1485 1486 memcpy(&video->mode, mode, sizeof(video->mode)); 1487 video->pixel_mode = DPTX_MP_QUAD_PIXEL; 1488 1489 if (dp->force_output) { 1490 ret = dw_dp_set_phy_default_config(dp); 1491 if (ret < 0) 1492 printf("failed to set phy_default config: %d\n", ret); 1493 } else { 1494 ret = dw_dp_link_enable(dp); 1495 if (ret < 0) { 1496 printf("failed to enable link: %d\n", ret); 1497 return ret; 1498 } 1499 } 1500 1501 ret = dw_dp_video_enable(dp); 1502 if (ret < 0) { 1503 printf("failed to enable video: %d\n", ret); 1504 return ret; 1505 } 1506 1507 return 0; 1508 } 1509 1510 static int dw_dp_connector_disable(struct rockchip_connector *conn, struct display_state *state) 1511 { 1512 /* TODO */ 1513 1514 return 0; 1515 } 1516 1517 static int dw_dp_connector_detect(struct rockchip_connector *conn, struct display_state *state) 1518 { 1519 struct dw_dp *dp = dev_get_priv(conn->dev); 1520 int status, tries, ret; 1521 1522 for (tries = 0; tries < 200; tries++) { 1523 status = dw_dp_detect(dp); 1524 if (status) 1525 break; 1526 mdelay(2); 1527 } 1528 1529 if (state->force_output && !status) 1530 dp->force_output = true; 1531 1532 if (!status && !dp->force_output) 1533 generic_phy_power_off(&dp->phy); 1534 1535 if (status && !dp->force_output) { 1536 ret = dw_dp_link_probe(dp); 1537 if (ret) 1538 printf("failed to probe DP link: %d\n", ret); 1539 } 1540 1541 return status; 1542 } 1543 1544 static int dw_dp_mode_valid(struct dw_dp *dp, struct hdmi_edid_data *edid_data) 1545 { 1546 struct dw_dp_link *link = &dp->link; 1547 struct drm_display_info *di = &edid_data->display_info; 1548 u32 min_bpp; 1549 int i; 1550 1551 if (di->color_formats & DRM_COLOR_FORMAT_YCRCB420 && 1552 link->vsc_sdp_extension_for_colorimetry_supported) 1553 min_bpp = 12; 1554 else if (di->color_formats & DRM_COLOR_FORMAT_YCRCB422) 1555 min_bpp = 16; 1556 else if (di->color_formats & DRM_COLOR_FORMAT_RGB444) 1557 min_bpp = 18; 1558 else 1559 min_bpp = 24; 1560 1561 for (i = 0; i < edid_data->modes; i++) { 1562 if (!dw_dp_bandwidth_ok(dp, &edid_data->mode_buf[i], min_bpp, link->lanes, 1563 link->rate)) 1564 edid_data->mode_buf[i].invalid = true; 1565 } 1566 1567 return 0; 1568 } 1569 1570 static u32 dw_dp_get_output_bus_fmts(struct dw_dp *dp, struct hdmi_edid_data *edid_data) 1571 { 1572 struct dw_dp_link *link = &dp->link; 1573 unsigned int i; 1574 1575 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 1576 const struct dw_dp_output_format *fmt = &possible_output_fmts[i]; 1577 1578 if (fmt->bpc > edid_data->display_info.bpc) 1579 continue; 1580 1581 if (!(edid_data->display_info.color_formats & fmt->color_format)) 1582 continue; 1583 1584 if (fmt->color_format == DRM_COLOR_FORMAT_YCRCB420 && 1585 !link->vsc_sdp_extension_for_colorimetry_supported) 1586 continue; 1587 1588 if (drm_mode_is_420(&edid_data->display_info, edid_data->preferred_mode) && 1589 fmt->color_format != DRM_COLOR_FORMAT_YCRCB420) 1590 continue; 1591 1592 if (!dw_dp_bandwidth_ok(dp, edid_data->preferred_mode, fmt->bpp, link->lanes, 1593 link->rate)) 1594 continue; 1595 1596 break; 1597 } 1598 1599 if (i == ARRAY_SIZE(possible_output_fmts)) 1600 return 1; 1601 1602 return i; 1603 } 1604 1605 static int dw_dp_connector_get_timing(struct rockchip_connector *conn, struct display_state *state) 1606 { 1607 int ret, i; 1608 struct connector_state *conn_state = &state->conn_state; 1609 struct dw_dp *dp = dev_get_priv(conn->dev); 1610 struct drm_display_mode *mode = &conn_state->mode; 1611 struct hdmi_edid_data edid_data; 1612 struct drm_display_mode *mode_buf; 1613 struct vop_rect rect; 1614 u32 bus_fmt; 1615 1616 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 1617 if (!mode_buf) 1618 return -ENOMEM; 1619 1620 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 1621 memset(&edid_data, 0, sizeof(struct hdmi_edid_data)); 1622 edid_data.mode_buf = mode_buf; 1623 1624 if (!dp->force_output) { 1625 ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); 1626 if (!ret) 1627 ret = drm_add_edid_modes(&edid_data, conn_state->edid); 1628 1629 if (ret < 0) { 1630 printf("failed to get edid\n"); 1631 goto err; 1632 } 1633 1634 drm_rk_filter_whitelist(&edid_data); 1635 if (state->conn_state.secondary) { 1636 rect.width = state->crtc_state.max_output.width / 2; 1637 rect.height = state->crtc_state.max_output.height / 2; 1638 } else { 1639 rect.width = state->crtc_state.max_output.width; 1640 rect.height = state->crtc_state.max_output.height; 1641 } 1642 1643 drm_mode_max_resolution_filter(&edid_data, &rect); 1644 dw_dp_mode_valid(dp, &edid_data); 1645 1646 if (!drm_mode_prune_invalid(&edid_data)) { 1647 printf("can't find valid hdmi mode\n"); 1648 ret = -EINVAL; 1649 goto err; 1650 } 1651 1652 for (i = 0; i < edid_data.modes; i++) 1653 edid_data.mode_buf[i].vrefresh = 1654 drm_mode_vrefresh(&edid_data.mode_buf[i]); 1655 1656 drm_mode_sort(&edid_data); 1657 memcpy(mode, edid_data.preferred_mode, sizeof(struct drm_display_mode)); 1658 } 1659 1660 if (state->force_output) 1661 bus_fmt = dw_dp_get_output_fmts_index(state->force_bus_format); 1662 else 1663 bus_fmt = dw_dp_get_output_bus_fmts(dp, &edid_data); 1664 1665 conn_state->bus_format = possible_output_fmts[bus_fmt].bus_format; 1666 1667 switch (possible_output_fmts[bus_fmt].color_format) { 1668 case DRM_COLOR_FORMAT_YCRCB420: 1669 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420; 1670 break; 1671 case DRM_COLOR_FORMAT_YCRCB422: 1672 conn_state->output_mode = ROCKCHIP_OUT_MODE_S888_DUMMY; 1673 break; 1674 case DRM_COLOR_FORMAT_RGB444: 1675 case DRM_COLOR_FORMAT_YCRCB444: 1676 default: 1677 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1678 break; 1679 } 1680 1681 err: 1682 free(mode_buf); 1683 1684 return 0; 1685 } 1686 1687 static const struct rockchip_connector_funcs dw_dp_connector_funcs = { 1688 .init = dw_dp_connector_init, 1689 .get_edid = dw_dp_connector_get_edid, 1690 .prepare = dw_dp_connector_prepare, 1691 .enable = dw_dp_connector_enable, 1692 .disable = dw_dp_connector_disable, 1693 .detect = dw_dp_connector_detect, 1694 .get_timing = dw_dp_connector_get_timing, 1695 }; 1696 1697 static int dw_dp_ddc_init(struct dw_dp *dp) 1698 { 1699 dp->aux.name = "dw-dp"; 1700 dp->aux.dev = dp->dev; 1701 dp->aux.transfer = dw_dp_aux_transfer; 1702 dp->aux.ddc.ddc_xfer = drm_dp_i2c_xfer; 1703 1704 return 0; 1705 } 1706 1707 static int dw_dp_probe(struct udevice *dev) 1708 { 1709 struct dw_dp *dp = dev_get_priv(dev); 1710 int ret; 1711 1712 ret = regmap_init_mem(dev, &dp->regmap); 1713 if (ret) 1714 return ret; 1715 1716 dp->id = of_alias_get_id(ofnode_to_np(dev->node), "dp"); 1717 if (dp->id < 0) 1718 dp->id = 0; 1719 1720 ret = reset_get_by_index(dev, 0, &dp->reset); 1721 if (ret) { 1722 dev_err(dev, "failed to get reset control: %d\n", ret); 1723 return ret; 1724 } 1725 1726 dp->force_hpd = dev_read_bool(dev, "force-hpd"); 1727 1728 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 1729 GPIOD_IS_IN); 1730 if (ret && ret != -ENOENT) { 1731 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 1732 return ret; 1733 } 1734 1735 generic_phy_get_by_index(dev, 0, &dp->phy); 1736 1737 dp->dev = dev; 1738 1739 dw_dp_ddc_init(dp); 1740 1741 rockchip_connector_bind(&dp->connector, dev, dp->id, &dw_dp_connector_funcs, NULL, 1742 DRM_MODE_CONNECTOR_DisplayPort); 1743 1744 return 0; 1745 } 1746 1747 static const struct udevice_id dw_dp_ids[] = { 1748 { 1749 .compatible = "rockchip,rk3588-dp", 1750 }, 1751 {} 1752 }; 1753 1754 U_BOOT_DRIVER(dw_dp) = { 1755 .name = "dw_dp", 1756 .id = UCLASS_DISPLAY, 1757 .of_match = dw_dp_ids, 1758 .probe = dw_dp_probe, 1759 .priv_auto_alloc_size = sizeof(struct dw_dp), 1760 }; 1761 1762