1*e60b0267SChaoyi Chen /* SPDX-License-Identifier: GPL-2.0+ */ 2*e60b0267SChaoyi Chen /* 3*e60b0267SChaoyi Chen * (C) Copyright 2023 Rockchip Electronics Co., Ltd 4*e60b0267SChaoyi Chen * 5*e60b0267SChaoyi Chen */ 6*e60b0267SChaoyi Chen #ifndef __DRM_OF_H__ 7*e60b0267SChaoyi Chen #define __DRM_OF_H__ 8*e60b0267SChaoyi Chen 9*e60b0267SChaoyi Chen #include <dm/ofnode.h> 10*e60b0267SChaoyi Chen #include <dm/of_access.h> 11*e60b0267SChaoyi Chen 12*e60b0267SChaoyi Chen /** 13*e60b0267SChaoyi Chen * enum drm_lvds_dual_link_pixels - Pixel order of an LVDS dual-link connection 14*e60b0267SChaoyi Chen * @DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS: Even pixels are expected to be 15*e60b0267SChaoyi Chen * generated from the first port, odd pixels from the second port 16*e60b0267SChaoyi Chen * @DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS: Odd pixels are expected to be 17*e60b0267SChaoyi Chen * generated from the first port, even pixels from the second port 18*e60b0267SChaoyi Chen * @DRM_LVDS_DUAL_LINK_LEFT_RIGHT_PIXELS: Left pixels are expected to be 19*e60b0267SChaoyi Chen * generated from the first port, right pixels from the second port 20*e60b0267SChaoyi Chen * @DRM_LVDS_DUAL_LINK_RIGHT_LEFT_PIXELS: Right pixels are expected to be 21*e60b0267SChaoyi Chen * generated from the first port, left pixels from the second port 22*e60b0267SChaoyi Chen */ 23*e60b0267SChaoyi Chen enum drm_lvds_dual_link_pixels { 24*e60b0267SChaoyi Chen DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS = 0, 25*e60b0267SChaoyi Chen DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS = 1, 26*e60b0267SChaoyi Chen DRM_LVDS_DUAL_LINK_LEFT_RIGHT_PIXELS = 2, 27*e60b0267SChaoyi Chen DRM_LVDS_DUAL_LINK_RIGHT_LEFT_PIXELS = 3, 28*e60b0267SChaoyi Chen }; 29*e60b0267SChaoyi Chen 30*e60b0267SChaoyi Chen int drm_of_lvds_get_dual_link_pixel_order(const struct device_node *port1, 31*e60b0267SChaoyi Chen const struct device_node *port2); 32*e60b0267SChaoyi Chen 33*e60b0267SChaoyi Chen #endif 34