1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2018 Intel Corp 4 * 5 * Author: 6 * Manasi Navare <manasi.d.navare@intel.com> 7 */ 8 9 #include <common.h> 10 #include <drm/drm_dp_helper.h> 11 #include <drm/drm_dsc.h> 12 13 /** 14 * DOC: dsc helpers 15 * 16 * VESA specification for DP 1.4 adds a new feature called Display Stream 17 * Compression (DSC) used to compress the pixel bits before sending it on 18 * DP/eDP/MIPI DSI interface. DSC is required to be enabled so that the existing 19 * display interfaces can support high resolutions at higher frames rates using 20 * the maximum available link capacity of these interfaces. 21 * 22 * These functions contain some common logic and helpers to deal with VESA 23 * Display Stream Compression standard required for DSC on Display Port/eDP or 24 * MIPI display interfaces. 25 */ 26 27 /** 28 * drm_dsc_dp_pps_header_init() - Initializes the PPS Header 29 * for DisplayPort as per the DP 1.4 spec. 30 * @pps_header: Secondary data packet header for DSC Picture 31 * Parameter Set as defined in &struct dp_sdp_header 32 * 33 * DP 1.4 spec defines the secondary data packet for sending the 34 * picture parameter infoframes from the source to the sink. 35 * This function populates the SDP header defined in 36 * &struct dp_sdp_header. 37 */ 38 void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header) 39 { 40 memset(pps_header, 0, sizeof(*pps_header)); 41 42 pps_header->HB1 = DP_SDP_PPS; 43 pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1; 44 } 45 46 /** 47 * drm_dsc_pps_payload_pack() - Populates the DSC PPS 48 * 49 * @pps_payload: 50 * Bitwise struct for DSC Picture Parameter Set. This is defined 51 * by &struct drm_dsc_picture_parameter_set 52 * @dsc_cfg: 53 * DSC Configuration data filled by driver as defined by 54 * &struct drm_dsc_config 55 * 56 * DSC source device sends a picture parameter set (PPS) containing the 57 * information required by the sink to decode the compressed frame. Driver 58 * populates the DSC PPS struct using the DSC configuration parameters in 59 * the order expected by the DSC Display Sink device. For the DSC, the sink 60 * device expects the PPS payload in big endian format for fields 61 * that span more than 1 byte. 62 */ 63 void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload, 64 const struct drm_dsc_config *dsc_cfg) 65 { 66 int i; 67 68 /* Protect against someone accidentally changing struct size */ 69 BUILD_BUG_ON(sizeof(*pps_payload) != 70 DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1); 71 72 memset(pps_payload, 0, sizeof(*pps_payload)); 73 74 /* PPS 0 */ 75 pps_payload->dsc_version = 76 dsc_cfg->dsc_version_minor | 77 dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; 78 79 /* PPS 1, 2 is 0 */ 80 81 /* PPS 3 */ 82 pps_payload->pps_3 = 83 dsc_cfg->line_buf_depth | 84 dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT; 85 86 /* PPS 4 */ 87 pps_payload->pps_4 = 88 ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >> 89 DSC_PPS_MSB_SHIFT) | 90 dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT | 91 dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT | 92 dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT | 93 dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT; 94 95 /* PPS 5 */ 96 pps_payload->bits_per_pixel_low = 97 (dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK); 98 99 /* 100 * The DSC panel expects the PPS packet to have big endian format 101 * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert 102 * to big endian format. If format is little endian, it will swap 103 * bytes to convert to Big endian else keep it unchanged. 104 */ 105 106 /* PPS 6, 7 */ 107 pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height); 108 109 /* PPS 8, 9 */ 110 pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width); 111 112 /* PPS 10, 11 */ 113 pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height); 114 115 /* PPS 12, 13 */ 116 pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width); 117 118 /* PPS 14, 15 */ 119 pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size); 120 121 /* PPS 16 */ 122 pps_payload->initial_xmit_delay_high = 123 ((dsc_cfg->initial_xmit_delay & 124 DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >> 125 DSC_PPS_MSB_SHIFT); 126 127 /* PPS 17 */ 128 pps_payload->initial_xmit_delay_low = 129 (dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK); 130 131 /* PPS 18, 19 */ 132 pps_payload->initial_dec_delay = 133 cpu_to_be16(dsc_cfg->initial_dec_delay); 134 135 /* PPS 20 is 0 */ 136 137 /* PPS 21 */ 138 pps_payload->initial_scale_value = 139 dsc_cfg->initial_scale_value; 140 141 /* PPS 22, 23 */ 142 pps_payload->scale_increment_interval = 143 cpu_to_be16(dsc_cfg->scale_increment_interval); 144 145 /* PPS 24 */ 146 pps_payload->scale_decrement_interval_high = 147 ((dsc_cfg->scale_decrement_interval & 148 DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >> 149 DSC_PPS_MSB_SHIFT); 150 151 /* PPS 25 */ 152 pps_payload->scale_decrement_interval_low = 153 (dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK); 154 155 /* PPS 26[7:0], PPS 27[7:5] RESERVED */ 156 157 /* PPS 27 */ 158 pps_payload->first_line_bpg_offset = 159 dsc_cfg->first_line_bpg_offset; 160 161 /* PPS 28, 29 */ 162 pps_payload->nfl_bpg_offset = 163 cpu_to_be16(dsc_cfg->nfl_bpg_offset); 164 165 /* PPS 30, 31 */ 166 pps_payload->slice_bpg_offset = 167 cpu_to_be16(dsc_cfg->slice_bpg_offset); 168 169 /* PPS 32, 33 */ 170 pps_payload->initial_offset = 171 cpu_to_be16(dsc_cfg->initial_offset); 172 173 /* PPS 34, 35 */ 174 pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset); 175 176 /* PPS 36 */ 177 pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp; 178 179 /* PPS 37 */ 180 pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp; 181 182 /* PPS 38, 39 */ 183 pps_payload->rc_model_size = 184 cpu_to_be16(DSC_RC_MODEL_SIZE_CONST); 185 186 /* PPS 40 */ 187 pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST; 188 189 /* PPS 41 */ 190 pps_payload->rc_quant_incr_limit0 = 191 dsc_cfg->rc_quant_incr_limit0; 192 193 /* PPS 42 */ 194 pps_payload->rc_quant_incr_limit1 = 195 dsc_cfg->rc_quant_incr_limit1; 196 197 /* PPS 43 */ 198 pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST | 199 DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT; 200 201 /* PPS 44 - 57 */ 202 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) 203 pps_payload->rc_buf_thresh[i] = 204 dsc_cfg->rc_buf_thresh[i]; 205 206 /* PPS 58 - 87 */ 207 /* 208 * For DSC sink programming the RC Range parameter fields 209 * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0] 210 */ 211 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 212 pps_payload->rc_range_parameters[i] = 213 cpu_to_be16((dsc_cfg->rc_range_params[i].range_min_qp << 214 DSC_PPS_RC_RANGE_MINQP_SHIFT) | 215 (dsc_cfg->rc_range_params[i].range_max_qp << 216 DSC_PPS_RC_RANGE_MAXQP_SHIFT) | 217 (dsc_cfg->rc_range_params[i].range_bpg_offset)); 218 } 219 220 /* PPS 88 */ 221 pps_payload->native_422_420 = dsc_cfg->native_422 | 222 dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT; 223 224 /* PPS 89 */ 225 pps_payload->second_line_bpg_offset = 226 dsc_cfg->second_line_bpg_offset; 227 228 /* PPS 90, 91 */ 229 pps_payload->nsl_bpg_offset = 230 cpu_to_be16(dsc_cfg->nsl_bpg_offset); 231 232 /* PPS 92, 93 */ 233 pps_payload->second_line_offset_adj = 234 cpu_to_be16(dsc_cfg->second_line_offset_adj); 235 236 /* PPS 94 - 127 are O */ 237 } 238 239 /** 240 * drm_dsc_compute_rc_parameters() - Write rate control 241 * parameters to the dsc configuration defined in 242 * &struct drm_dsc_config in accordance with the DSC 1.2 243 * specification. Some configuration fields must be present 244 * beforehand. 245 * 246 * @vdsc_cfg: 247 * DSC Configuration data partially filled by driver 248 */ 249 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) 250 { 251 unsigned long groups_per_line = 0; 252 unsigned long groups_total = 0; 253 unsigned long num_extra_mux_bits = 0; 254 unsigned long slice_bits = 0; 255 unsigned long hrd_delay = 0; 256 unsigned long final_scale = 0; 257 unsigned long rbs_min = 0; 258 259 if (vdsc_cfg->native_420 || vdsc_cfg->native_422) { 260 /* Number of groups used to code each line of a slice */ 261 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2, 262 DSC_RC_PIXELS_PER_GROUP); 263 264 /* chunksize in Bytes */ 265 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 * 266 vdsc_cfg->bits_per_pixel, 267 (8 * 16)); 268 } else { 269 /* Number of groups used to code each line of a slice */ 270 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, 271 DSC_RC_PIXELS_PER_GROUP); 272 273 /* chunksize in Bytes */ 274 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * 275 vdsc_cfg->bits_per_pixel, 276 (8 * 16)); 277 } 278 279 if (vdsc_cfg->convert_rgb) 280 num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size + 281 (4 * vdsc_cfg->bits_per_component + 4) 282 - 2); 283 else if (vdsc_cfg->native_422) 284 num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size + 285 (4 * vdsc_cfg->bits_per_component + 4) + 286 3 * (4 * vdsc_cfg->bits_per_component) - 2; 287 else 288 num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size + 289 (4 * vdsc_cfg->bits_per_component + 4) + 290 2 * (4 * vdsc_cfg->bits_per_component) - 2; 291 /* Number of bits in one Slice */ 292 slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; 293 294 while ((num_extra_mux_bits > 0) && 295 ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size)) 296 num_extra_mux_bits--; 297 298 if (groups_per_line < vdsc_cfg->initial_scale_value - 8) 299 vdsc_cfg->initial_scale_value = groups_per_line + 8; 300 301 /* scale_decrement_interval calculation according to DSC spec 1.11 */ 302 if (vdsc_cfg->initial_scale_value > 8) 303 vdsc_cfg->scale_decrement_interval = groups_per_line / 304 (vdsc_cfg->initial_scale_value - 8); 305 else 306 vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX; 307 308 vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - 309 (vdsc_cfg->initial_xmit_delay * 310 vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits; 311 312 if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { 313 printf("FinalOfs < RcModelSze for this InitialXmitDelay\n"); 314 return -ERANGE; 315 } 316 317 final_scale = (vdsc_cfg->rc_model_size * 8) / 318 (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); 319 if (vdsc_cfg->slice_height > 1) 320 /* 321 * NflBpgOffset is 16 bit value with 11 fractional bits 322 * hence we multiply by 2^11 for preserving the 323 * fractional part 324 */ 325 vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11), 326 (vdsc_cfg->slice_height - 1)); 327 else 328 vdsc_cfg->nfl_bpg_offset = 0; 329 330 /* Number of groups used to code the entire slice */ 331 groups_total = groups_per_line * vdsc_cfg->slice_height; 332 333 /* slice_bpg_offset is 16 bit value with 11 fractional bits */ 334 vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - 335 vdsc_cfg->initial_offset + 336 num_extra_mux_bits) << 11), 337 groups_total); 338 339 if (final_scale > 9) { 340 /* 341 * ScaleIncrementInterval = 342 * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125)) 343 * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value, 344 * we need divide by 2^11 from pstDscCfg values 345 */ 346 vdsc_cfg->scale_increment_interval = 347 (vdsc_cfg->final_offset * (1 << 11)) / 348 ((vdsc_cfg->nfl_bpg_offset + 349 vdsc_cfg->slice_bpg_offset) * 350 (final_scale - 9)); 351 } else { 352 /* 353 * If finalScaleValue is less than or equal to 9, a value of 0 should 354 * be used to disable the scale increment at the end of the slice 355 */ 356 vdsc_cfg->scale_increment_interval = 0; 357 } 358 359 /* 360 * DSC spec mentions that bits_per_pixel specifies the target 361 * bits/pixel (bpp) rate that is used by the encoder, 362 * in steps of 1/16 of a bit per pixel 363 */ 364 rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + 365 DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay * 366 vdsc_cfg->bits_per_pixel, 16) + 367 groups_per_line * vdsc_cfg->first_line_bpg_offset; 368 369 hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel); 370 vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; 371 vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay; 372 373 return 0; 374 } 375